FN4805 Rev.23.00 Page 1 of 36
Apr.26.19
ICL3221, ICL3222, ICL3223, ICL3232, ICL3241, ICL3243
One Microamp Supply-Current, +3V to +5.5V, 250kbps, RS-232
Transmitters/Receivers
Datasheet
The ICL3221, ICL3222, ICL3223, ICL3232, ICL3241,
ICL3243 (ISL32xx) devices are 3.0V to 5.5V powered
RS-232 transmitters/receivers that meet ElA/TIA-232
and V.28/V.24 specifications, even at VCC =3.0V.
Targeted applications are PDAs, notebook, and laptop
computers where the low operational power
consumption and even lower standby power
consumption are critical. Efficient on-chip charge
pumps, coupled with manual and automatic
power-down functions (except for the ICL3232),
reduce the standby supply current to a 1µA trickle.
Small footprint packaging, and the use of small, low
value capacitors ensure board space savings as well.
Data rates greater than 250kbps are ensured at worst
case load conditions. This family is fully compatible
with 3.3V only systems, mixed 3.3V and 5.0V
systems, and 5.0V only systems.
The ICL324x are 3-driver, 5-receiver devices that
provide a complete serial port suitable for laptop or
notebook computers. Both devices also include
noninverting always-active receivers for “wake-up”
capability.
The ICL3221, ICL3223 and ICL3243 feature an
automatic powerdown function that powers down the
on-chip power-supply and driver circuits. Power-down
occurs when an attached peripheral device is shut off
or the RS-232 cable is removed, conserving system
power automatically without changes to the hardware
or operating system. These devices power up again
when a valid RS-232 voltage is applied to any
receiver input.
Table 1 on page 6 summarizes the features of the
devices represented by this datasheet, while
Application Note AN9863 summarizes the features of
each device comprising the ICL32xx 3V family.
Related Literature
For a full list of related documents, visit our website:
•ICL3221, ICL3222, ICL3223, ICL3232, ICL3241,
and ICL3243 device pages
Features
• RoHS Compliant
• 15kV ESD protected (Human Body Model)
• Drop-in replacements for MAX3221, MAX3222,
MAX3223, MAX3232, MAX3241, MAX3243,
SP3243
• ICL3221 is a low-power, pin compatible upgrade for
5V MAX221
• ICL3222 is a low-power, pin compatible upgrade for
5V MAX242, and SP312A
• ICL3232 is a low-power upgrade for HIN232/ICL232
and pin compatible competitor devices
• RS-232 compatible with VCC = 2.7V
• Meets EIA/TIA-232 and V.28/V.24 specifications at
3V
• Latch-up free
• On-chip voltage converters require only four
external 0.1µF capacitors
• Manual and automatic powerdown features (except
ICL3232)
• Assured mouse driveability (ICL324x only)
• Receiver hysteresis for improved noise immunity
• Assured minimum data rate: 250kbps
• Assured minimum slew rate: 6V/μs
• Wide power supply range: single +3V to +5.5V
• Low supply current in powerdown state:1µA
Applications
• Any system requiring RS-232 communication ports
○ Battery powered, hand-held, and portable
equipment
○ Laptop computers, Notebooks
○ Modems, printers, and other peripherals
○ Digital cameras
○ Cellular/mobile phones
ICL3221, ICL3222, ICL3223, ICL3232, ICL3241, ICL3243
FN4805 Rev.23.00 Page 2 of 36
Apr.26.19
Contents
1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1 Typical Operating Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.3 Pin Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.4 Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2. Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.2 Thermal Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.3 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.4 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3. Typical Performance Curves. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4. Application Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.1 Charge Pump. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.1.1 Charge Pump Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.2 Transmitters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.3 Receivers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.4 Low Power Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.5 Powerdown Functionality (Except ICL3232) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.5.1 Software Controlled (Manual) Powerdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.5.2 INVALID Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.5.3 Automatic Powerdown (ICL3221/23/43 Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.6 Receiver ENABLE Control (ICL3221/22/23/41 Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.7 Capacitor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.8 Power Supply Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.9 Operation Down to 2.7V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.10 Transmitter Outputs when Exiting Powerdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.11 Mouse Driveability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.12 High Data Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.13 Interconnection with 3V and 5V Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.14 Pin Compatible Replacements For 5V Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5. Die Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6. Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7. Package Outline Drawings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
ICL3221, ICL3222, ICL3223, ICL3232, ICL3241, ICL3243 1. Overview
FN4805 Rev.23.00 Page 3 of 36
Apr.26.19
1. Overview
1.1 Typical Operating Circuits
ICL3221 ICL3222
ICL3223 ICL3232
15
VCC
T1OUT
T1IN
T1
0.1µF
+0.1µF
+
0.1µF
11 13
2
4
3
7
V+
V-
C1+
C1-
C2+
C2-
+
0.1µF
5
6
R1OUT R1IN
R1
89
5kΩ
C1
C2
+C3
C4
EN
1
GND
+3.3V +0.1µF
14
TTL/CMOS
Logic Levels
RS-232
Levels
FORCEON
FORCEOFF
12
16 VCC
10
INVALID To Power
Control
Logic
+
C3 (Optional Connection, Note)
NOTE: The negative terminal of C3 can be
connected to either VCC or GND
17
VCC
T1OUT
T2OUT
T1IN
T2IN
T1
T2
0.1µF
+0.1µF
+
0.1µF
12
11
15
8
2
4
3
7
V+
V-
C1+
C1-
C2+
C2-
+
0.1µF
5
6
R1OUT R1IN
14
5kΩ
R2OUT R2IN
9
10
5kΩ
13
C1
C2
+C3
C4
EN
SHDN
1
GND
18
+3.3V +0.1µF
16
VCC
TTL/CMOS
Logic Levels
RS-232
Levels
R1
R2
+
C3 (Optional Connection, Note)
NOTE: The negative terminal of C3 can be
connected to either VCC or GND
19
VCC
T1OUT
T2OUT
T1IN
T2IN
T1
T2
0.1µF
+
0.1µF
+
0.1µF
13
12
17
8
2
4
3
7
V+
V-
C1+
C1-
C2+
C2-
+
0.1µF
5
6
R1OUT R1IN
16
5kΩ
R2OUT R2IN
910
5kΩ
15
C1
C2
+C3
C4
EN
1
GND
+3.3V +0.1µF
18
TTL/CMOS
Logic Levels
RS-232
Levels
R1
R2
FORCEON
FORCEOFF
14
20 VCC
11
INVALID To Power
Control Logic
16
VCC
T1OUT
T2OUT
T1IN
T2IN
T1
T2
0.1µF
+
0.1µF
+
0.1µF
11
10
14
7
1
3
2
6
V+
V-
C1+
C1-
C2+
C2-
+
0.1µF
4
5
R1OUT R1IN
13
5kΩ
R2OUT R2IN
8
9
5kΩ
12
C1
C2
+C3
C4
GND
+3.3V +0.1μF
15
TTL/CMOS
Logic Levels
RS-232
Levels
R1
R2
+
C3 (Optional Connection, Note)
NOTE: The negative terminal of C3 can be
connected to either VCC or GND
ICL3221, ICL3222, ICL3223, ICL3232, ICL3241, ICL3243 1. Overview
FN4805 Rev.23.00 Page 4 of 36
Apr.26.19
1.2 Ordering Information
ICL3241 ICL3243
Part Number (Notes 2, 3)Part Marking Temp. Range (°c)
Tape and Reel
(Units) (Note 1)
Package
(RoHS Compliant) Pkg. Dwg. #
ICL3221CAZ ICL3221CAZ 0 to 70 - 16 Ld SSOP M16.209
ICL3221CAZ-T ICL3221CAZ 0 to 70 1k 16 Ld SSOP M16.209
ICL3221CVZ 3221CVZ 0 to 70 - 16 Ld TSSOP M16.173
ICL3221CVZ-T 3221CVZ 0 to 70 2.5k 16 Ld TSSOP M16.173
ICL3221IAZ ICL3221IAZ -40 to 85 - 16 Ld SSOP M16.209
ICL3221IAZ-T ICL3221IAZ -40 to 85 1k 16 Ld SSOP M16.209
ICL3221IAZ-T7A ICL3221IAZ -40 to 85 250 16 Ld SSOP M16.209
ICL3222CAZ (No longer available,
recommended replacement:
ICL3222ECAZ)
ICL3222CAZ 0 to 70 - 20 Ld SSOP M20.209
26
VCC
T1OUT
T2OUT
T3OUT
T1IN
T2IN
T3IN
T1
T2
T3
0.1µF
+0.1µF
+
0.1µF
14
13
9
10
12 11
28
24
27
3
V+
V-
C1+
C1-
C2+
C2-
+
0.1µF
1
2
R1OUT R1IN
4
5kΩ
R2OUT R2IN
518
5kΩ
R3OUT R3IN
617
5kΩ
R4OUT R4IN
716
5kΩ
R5OUT R5IN
R5
815
5kΩ
19
R2OUTB
C1
C2
+C3
C4
EN
SHDN
23
GND
22
+3.3V +0.1µF
20
25
VCC
TTL/CMOS
Logic Levels
RS-232
Levels
RS-232
Levels
R1OUTB
21
R1
R2
R3
R4
26
VCC
T1OUT
T2OUT
T3OUT
T1IN
T2IN
T3IN
T1
T2
T3
0.1µF
+0.1µF
+
0.1µF
14
13
9
10
12 11
28
24
27
3
V+
V-
C1+
C1-
C2+
C2-
+
0.1µF
1
2
R1OUT R1IN
4
5kΩ
R2OUT R2IN
518
5kΩ
R3OUT R3IN
617
5kΩ
R4OUT R4IN
716
5kΩ
R5OUT R5IN
R5
815
5kΩ
19
R2OUTB
C1
C2
+C3
C4
FORCEON
FORCEOFF
23
GND
22
+3.3V +0.1µF
20
25
VCC
TTL/CMOS
Logic Levels
RS-232
Levels
RS-232
Levels
R1
R2
R3
R4
21
INVALID
To Power
Control Logic
ICL3221, ICL3222, ICL3223, ICL3232, ICL3241, ICL3243 1. Overview
FN4805 Rev.23.00 Page 5 of 36
Apr.26.19
ICL3222CBZ (No longer available,
recommended replacement:
ICL3222EIBZ)
3222CBZ 0 to 70 - 18 Ld SOIC M18.3
ICL3222CVZ ICL3222CVZ 0 to 70 - 20 Ld TSSOP M20.173
ICL3222CVZ-T ICL3222CVZ 0 to 70 2.5k 20 Ld TSSOP M20.173
ICL3222IAZ (No longer available,
recommended replacement:
ICL3222EIAZ)
ICL3222IAZ -40 to 85 - 20 Ld SSOP M20.209
ICL3222IVZ (No longer available,
recommended replacement:
ICL3222EIVZ)
ICL3222IVZ -40 to 85 - 20 Ld TSSOP M20.173
ICL3223CAZ (No longer available,
recommended replacement:
ICL3223ECAZ)
ICL3223CAZ 0 to 70 - 20 Ld SSOP M20.209
ICL3223IAZ ICL3223IAZ -40 to 85 - 20 Ld SSOP M20.209
ICL3223IAZ-T ICL3223IAZ -40 to 85 1k 20 Ld SSOP M20.209
ICL3223IVZ ICL3223IVZ -40 to 85 - 20 Ld TSSOP M20.173
ICL3223IVZ-T ICL3223IVZ -40 to 85 2.5k 20 Ld TSSOP M20.173
ICL3232CAZ (No longer available,
recommended replacement:
ICL3232ECAZ)
3232CAZ 0 to 70 - 16 Ld SSOP M16.209
ICL3232CBZ (No longer available,
recommended replacement:
ICL3232ECBZ)
3232CBZ 0 to 70 - 16 Ld SOIC M16.3
ICL3232CBNZ 3232CBNZ 0 to 70 - 16 Ld SOIC (N) M16.15
ICL3232CBNZ-T 3232CBNZ 0 to 70 2.5k 16 Ld SOIC (N) M16.15
ICL3232CPZ ICL3232CPZ 0 to 70 - 16 Ld PDIP E16.3
ICL3232CVZ 3232CVZ 0 to 70 - 16 Ld TSSOP M16.173
ICL3232CVZ-T 3232CVZ 0 to 70 2.5k 16 Ld TSSOP M16.173
ICL3232IAZ (No longer available,
recommended replacement:
ICL3232EIAZ)
3232IAZ -40 to 85 - 16 Ld SSOP M16.209
ICL3232IBZ (No longer available,
recommended replacement:
ICL3232EIBZ)
3232IBZ -40 to 85 - 16 Ld SOIC M16.3
ICL3232IBNZ 3232IBNZ -40 to 85 - 16 Ld SOIC (N) M16.15
ICL3232IBNZ-T 3232IBNZ -40 to 85 2.5k 16 Ld SOIC (N) M16.15
ICL3232IBNZ-T7A 3232IBNZ -40 to 85 250 16 Ld SOIC (N) M16.15
ICL3232IVZ 3232IVZ -40 to 85 - 16 Ld TSSOP M16.173
ICL3232IVZ-T 3232IVZ -40 to 85 2.5k 16 Ld TSSOP M16.173
ICL3232IVZ-T7A 3232IVZ -40 to 85 250 16 Ld TSSOP M16.173
ICL3241CAZ (No longer available,
recommended replacement:
ICL3241ECAZ)
ICL3241CAZ 0 to 70 - 28 Ld SSOP M28.209
ICL3241CVZ (No longer available,
recommended replacement:
ICL3241ECVZ)
ICL3241CVZ 0 to 70 - 28 Ld TSSOP M28.173
ICL3241IAZ (No longer available,
recommended replacement:
ICL3241EIAZ)
ICL3241IAZ -40 to 85 - 28 Ld SSOP M28.209
Part Number (Notes 2, 3)Part Marking Temp. Range (°c)
Tape and Reel
(Units) (Note 1)
Package
(RoHS Compliant) Pkg. Dwg. #
ICL3221, ICL3222, ICL3223, ICL3232, ICL3241, ICL3243 1. Overview
FN4805 Rev.23.00 Page 6 of 36
Apr.26.19
1.3 Pin Configurations
ICL3243CAZ (No longer available,
recommended replacement:
ICL3243ECAZ)
ICL3243CAZ 0 to 70 - 28 Ld SSOP M28.209
ICL3243CBZ ICL3243CBZ 0 to 70 - 28 Ld SOIC M28.3
ICL3243CBZ-T ICL3243CBZ 0 to 70 1k 28 Ld SOIC M28.3
ICL3243CVZ (No longer available,
recommended replacement:
ICL3243ECVZ)
ICL3243CVZ 0 to 70 - 28 Ld TSSOP M28.173
ICL3243IAZ (No longer available,
recommended replacement:
ICL3243EIAZ)
ICL3243IAZ -40 to 85 - 28 Ld SSOP M28.209
Notes:
1. See TB347 for details about reel specifications.
2. Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J-STD-020.
3. For Moisture Sensitivity Level (MSL), see the ICL3221, ICL3222, ICL3223, ICL3232, ICL3241,and ICL3243 device pages. For more
information about MSL, see TB363.
Table 1. Summary of Features
Part Number No. of Tx. No. of Rx.
No. of Monitor
Rx. (ROUTB)
Data Rate
(kbps)
Rx. Enable
Function?
Ready
Output?
Manual
Power- Down?
Automatic
Powerdown
Function?
ICL3221 1 1 0 250 Yes No Yes Yes
ICL3222 2 2 0 250 Yes No Yes No
ICL3223 2 2 0 250 Yes No Yes Yes
ICL3232 2 2 0 250 No No No No
ICL3241 3 5 2 250 Yes No Yes No
ICL3243 3 5 1 250 No No Yes Yes
ICL3221 (SSOP, TSSOP)
Top View
ICL3222 (SOIC)
Top View
Part Number (Notes 2, 3)Part Marking Temp. Range (°c)
Tape and Reel
(Units) (Note 1)
Package
(RoHS Compliant) Pkg. Dwg. #
EN
C1+
V+
C1-
C2+
C2-
V-
R1IN
FORCEOFF
GND
T1OUT
FORCEON
T1IN
R1OUT
VCC
INVALID
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
EN
C1+
V+
C1-
C2+
C2-
V-
T2OUT
R2IN
SHDN
GND
T1OUT
R1IN
R1OUT
T2IN
VCC
T1IN
R2OUT
18
17
16
15
14
13
12
11
10
1
2
3
4
5
6
7
8
9
ICL3221, ICL3222, ICL3223, ICL3232, ICL3241, ICL3243 1. Overview
FN4805 Rev.23.00 Page 7 of 36
Apr.26.19
ICL3222 (SSOP, TSSOP)
Top View
ICL3223 (SSOP, TSSOP)
Top View
ICL3232 (PDIP, SOIC, SSOP, TSSOP)
Top View
ICL3241 (SSOP, TSSOP)
Top View
ICL3243 (SOIC, SSOP, TSSOP)
Top View
EN
C1+
V+
C1-
C2+
C2-
V-
T2OUT
R2IN
SHDN
GND
T1OUT
R1IN
R1OUT
T1IN
NC
VCC
NC
T2IN
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
R2OUT
EN
C1+
V+
C1-
C2+
C2-
V-
T2OUT
R2IN
FORCEOFF
GND
T1OUT
R1IN
R1OUT
T1IN
INVALID
VCC
FORCEON
T2IN
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
R2OUT
C1+
V+
C1-
C2+
C2-
V-
T2OUT
R2IN
VCC
T1OUT
R1IN
R1OUT
T1IN
R2OUT
GND
T2IN
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
C2+
C2-
V-
R1IN
R2IN
R3IN
R4IN
R5IN
T1OUT
T3OUT
T3IN
T2IN
T1IN
C1+
VCC
GND
C1-
EN
R1OUTB
R1OUT
R2OUT
R3OUT
R4OUT
R5OUT
V+
SHDN
R2OUTB
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
T2OUT
C2+
C2-
V-
R1IN
R2IN
R3IN
R4IN
R5IN
T1OUT
T3OUT
T3IN
T2IN
T1IN
C1+
VCC
GND
C1-
FORCEON
INVALID
R1OUT
R2OUT
R3OUT
R4OUT
R5OUT
V+
FORCEOFF
R2OUTB
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
T2OUT
ICL3221, ICL3222, ICL3223, ICL3232, ICL3241, ICL3243 1. Overview
FN4805 Rev.23.00 Page 8 of 36
Apr.26.19
1.4 Pin Descriptions
Pin Function
VCC System power supply input (3.0V to 5.5V).
V+ Internally generated positive transmitter supply (+5.5V).
V- Internally generated negative transmitter supply (-5.5V).
GND Ground connection.
C1+ External capacitor (voltage doubler) is connected to this lead.
C1- External capacitor (voltage doubler) is connected to this lead.
C2+ External capacitor (voltage inverter) is connected to this lead.
C2- External capacitor (voltage inverter) is connected to this lead.
TIN TTL/CMOS compatible transmitter Inputs.
TOUT RS-232 level (nominally ±5.5V) transmitter outputs.
RIN RS-232 compatible receiver inputs.
ROUT TTL/CMOS level receiver outputs.
ROUTB TTL/CMOS level, noninverting, always enabled receiver outputs.
INVALID Active low output that indicates if no valid RS-232 levels are present on any receiver input.
EN Active low receiver enable control; doesn’t disable ROUTB outputs.
SHDN Active low input to shut down transmitters and on-board power supply to place device in low power mode.
FORCEOFF Active low to shut down transmitters and on-chip power supply. This overrides any automatic circuitry and FORCEON (See
Table 5 on page 15).
FORCEON Active high input to override automatic powerdown circuitry thereby keeping transmitters active. (FORCEOFF must be high).
ICL3221, ICL3222, ICL3223, ICL3232, ICL3241, ICL3243 2. Specifications
FN4805 Rev.23.00 Page 9 of 36
Apr.26.19
2. Specifications
2.1 Absolute Maximum Ratings
2.2 Thermal Information
Parameter Minimum Maximum Unit
VCC to Ground -0.3 6 V
V+ to Ground -0.3 7 V
V- to Ground +0.3 -7 V
V+ to V- 14 V
Input Voltages
TIN, FORCEOFF, FORCEON, EN, SHDN -0.3 6 V
RIN ±25 V
Output Voltages
TOUT ±13.2 V
ROUT
, INVALID -0.3 VCC +0.3 V
Short-Circuit Duration
TOUT Continuous
ESD Rating (See ESD Performance)
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions can adversely
impact product reliability and result in failures not covered by warranty.
Thermal Resistance (Typical, Note 4)θJA (°C/W)
16 Ld PDIP Package (Note 5)90
16 Ld Wide SOIC Package 100
16 Ld Narrow SOIC Package 115
18 Ld SOIC Package 75
28 Ld SOIC Package 75
16 Ld SSOP Package 135
20 Ld SSOP Package 122
16 Ld TSSOP Package 145
20 Ld TSSOP Package 140
28 Ld SSOP and TSSOP Packages 100
Notes:
4. θJA is measured with the component mounted on a low-effective thermal conductivity test board in free air. See TB379.
5. Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing
applications.
Parameter Minimum Maximum Unit
Maximum Junction Temperature (Plastic Package) +150 °C
Maximum Storage Temperature Range -65 +150 °C
Pb-Free Reflow Profile (SOIC, SSOP, TSSOP Only) see TB493
ICL3221, ICL3222, ICL3223, ICL3232, ICL3241, ICL3243 2. Specifications
FN4805 Rev.23.00 Page 10 of 36
Apr.26.19
2.3 Recommended Operating Conditions
2.4 Electrical Specifications
Parameter Minimum Maximum Unit
Temperature Range
ICL32xxCx 0 +70 °C
ICL32xxIx -40 +85 °C
Test Conditions: VCC = 3V to 5.5V, C1 - C4 = 0.1µF; unless otherwise specified. Typicals are at TA = 25°C
Parameter Test Conditions
Tem
p
(°C) Min Typ Max
Uni
t
DC Characteristics
Supply Current, Automatic
Power-Down
All RIN open, FORCEON = GND, FORCEOFF =V
CC
(ICL3221, ICL3223, ICL3243 only)
25 - 1.0 10 µA
Supply Current, Powerdown FORCEOFF = SHDN = GND (except ICL3232) 25 - 1.0 10 µA
Supply Current, Automatic
Power-Down Disabled
All outputs unloaded,
FORCEON = FORCEOFF =
SHDN =V
CC
VCC = 3.15V,
ICL3221-32
25 - 0.3 1.0 mA
VCC = 3.0V, ICL3241-43 25 - 0.3 1.0 mA
Logic and Transmitter Inputs and Receiver Outputs
Input Logic Threshold Low TIN, FORCEON, FORCEOFF, EN, SHDN Full - - 0.8 V
Input Logic Threshold High TIN, FORCEON, FORCEOFF,
EN, SHDN
VCC = 3.3V Full 2.0 - - V
VCC = 5.0V Full 2.4 - - V
Input Leakage Current TIN, FORCEON, FORCEOFF, EN, SHDN Full - ±0.01 ±1.0 µA
Output Leakage Current
(Except ICL3232)
FORCEOFF = GND or EN =V
CC Full - ±0.05 ±10 µA
Output Voltage Low IOUT = 1.6mA Full - - 0.4 V
Output Voltage High IOUT = -1.0mA Full VCC -
0.6
VCC -
0.1
-V
Automatic Powerdown (ICL3221, ICL3223, ICL3243 only, FORCEON = GND, FORCEOFF = VCC)
Receiver Input Thresholds to Enable
Transmitters
ICL32xx powers up (See Figure 12) Full -2.7 - 2.7 V
Receiver Input Thresholds to Disable
Transmitters
ICL32xx powers down (See Figure 12) Full -0.3 - 0.3 V
INVALID Output Voltage Low IOUT = 1.6mA Full - - 0.4 V
INVALID Output Voltage High IOUT = -1.0mA Full VCC-0.6 - - V
Receiver Threshold to Transmitters
Enabled Delay (tWU)
25 - 100 - µs
Receiver Positive or Negative
Threshold to INVALID High Delay
(tINVH)
25 - 1 - µs
Receiver Positive or Negative
Threshold to INVALID Low Delay
(tINVL)
25 - 30 - µs
Receiver Inputs
Input Voltage Range Full -25 - 25 V
Input Threshold Low VCC = 3.3V 25 0.6 1.2 - V
VCC = 5.0V 25 0.8 1.5 - V
Input Threshold High VCC = 3.3V 25 - 1.5 2.4 V
VCC = 5.0V 25 - 1.8 2.4 V
Input Hysteresis 25 - 0.3 - V
ICL3221, ICL3222, ICL3223, ICL3232, ICL3241, ICL3243 2. Specifications
FN4805 Rev.23.00 Page 11 of 36
Apr.26.19
Input Resistance 25 3 5 7 kΩ
Transmitter Outputs
Output Voltage Swing All Transmitter Outputs Loaded with 3kΩ to Ground Full ±5.0 ±5.4 - V
Output Resistance VCC = V+ = V- = 0V, Transmitter Output = ±2V Full 300 10M - W
Output Short-Circuit Current Full - ±35 ±60 mA
Output Leakage Current VOUT = ±12V, VCC = 0V or 3V to 5.5V
Automatic Powerdown or FORCEOFF =SHDN=GND
Full - - ±25 µA
Mouse Driveability (ICL324X Only)
Transmitter Output Voltage
(See Figure 15)
T1IN =T2
IN = GND, T3IN =V
CC, T3OUT loaded with 3kΩ to
GND, T1OUT and T2OUT loaded with 2.5mA each
Full ±5 - - V
Timing Characteristics
Maximum Data Rate RL=3kΩ, CL= 1000pF, one transmitter switching Full 250 500 - kbp
s
Receiver Propagation Delay Receiver input to receiver output,
CL= 150pF
tPHL 25 - 0.3 - µs
tPLH 25 - 0.3 - µs
Receiver Output Enable Time Normal operation (except ICL3232) 25 - 200 - ns
Receiver Output Disable Time Normal operation (except ICL3232) 25 -200-ns
Transmitter Skew tPHL - tPLH Full - 200 100
0
ns
Receiver Skew tPHL - tPLH Full - 100 500 ns
Transition Region Slew Rate VCC =3.3V,
RL=3kΩ to 7kΩ,
Measured from 3V to -3V or -3V
to 3V
CL = 200pF to 2500pF 25 4 8.0 30 V/µ
s
CL = 200pF to 1000pF 25 6 - 30 V/µ
s
ESD Performance
RS-232 Pins (TOUT
, RIN) Human Body Model ICL3221 - ICL3243 25 - ±15 - kV
IEC61000-4-2 Contact Discharge ICL3221 - ICL3243 25 - ±8 - kV
IEC61000-4-2 Air Gap Discharge ICL3221 - ICL3232 25 - ±8 - kV
ICL3241 - ICL3243 25 - ±6 - kV
All Other Pins Human Body Model ICL3221 - ICL3243 25 - ±2 - kV
Test Conditions: VCC = 3V to 5.5V, C1 - C4 = 0.1µF; unless otherwise specified. Typicals are at TA = 25°C (Continued)
Parameter Test Conditions
Tem
p
(°C) Min Typ Max
Uni
t
ICL3221, ICL3222, ICL3223, ICL3232, ICL3241, ICL3243 3. Typical Performance Curves
FN4805 Rev.23.00 Page 12 of 36
Apr.26.19
3. Typical Performance Curves
VCC = 3.3V, TA = 25°C
Figure 1. Transmitter Output Voltage vs Load
Capacitance
Figure 2. Slew Rate vs Load Capacitance
Figure 3. Supply Current vs Load Capacitance when
Transmitting Data
Figure 4. Supply Current vs Load Capacitance when
Transmitting Data
Figure 5. Supply Current vs Load Capacitance when
Transmitting Data
Figure 6. Supply Current vs Supply Voltage
-6
-4
-2
0
2
4
6
1000 2000 3000 4000 50000
Load Capacitance (pF)
Transmitter Output Voltage (V)
1 Transmitter at 250kbps
VOUT+
VOUT -
1 or 2 Transmitters at 30kbps
Load Capacitance (pF)
Slew Rate (V/µs)
0 1000 2000 3000 4000 5000
5
10
15
20
25
+SLEW
-SLEW
0
5
10
15
20
25
30
45
35
40
0 1000 2000 3000 4000 5000
Load Capacitance (pF)
Supply Current (mA)
20kbps
250kbps
120kbps
ICL3221
0
5
10
15
20
25
30
45
35
40
0 1000 2000 3000 4000 5000
Load Capacitance (pF)
Supply Current (mA)
20kbps
250kbps
120kbps
ICL3222 - ICL3232
0
5
10
15
20
25
30
45
35
40
01000 2000 3000 4000 5000
Load Capacitance (pF)
Supply Current (mA)
20kbps
250kbps
120kbps
ICL324X
Supply Current (mA)
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
0
0.5
1.0
1.5
2.0
Supply Voltage (V)
2.5
3.0
3.5 No Load
All Outputs Static
ICL3221 - ICL3232
ICL324X
ICL324X
ICL3221, ICL3222, ICL3223, ICL3232, ICL3241, ICL3243 4. Application Information
FN4805 Rev.23.00 Page 13 of 36
Apr.26.19
4. Application Information
The ICL32xx interface ICs operate from a single +3V to +5.5V supply, ensure a 250kbps minimum data rate,
require only four small external 0.1µF capacitors, feature low-power consumption, and meet all ElA RS-232C and
V.28 specifications. The circuit is divided into three sections:
• Charge-pump
• Transmitters
• Receivers
4.1 Charge Pump
The ICL32xx family uses regulated on-chip dual charge pumps as voltage doublers, and voltage inverters to
generate ±5.5V transmitter supplies from a VCC supply as low as 3.0V, which allows these devices to maintain
RS-232 compliant output levels over the ±10% tolerance range of 3.3V powered systems. The efficient on-chip
power supplies require only four small, external 0.1µF capacitors for the voltage doubler and inverter functions at
VCC = 3.3V. See Capacitor Selection and Table 6 on page 19 for capacitor recommendations for other operating
conditions. The charge pumps operate discontinuously (for example, they turn off as soon as the V+ and V-
supplies are pumped up to the nominal values), resulting in significant power savings.
4.1.1 Charge Pump Absolute Maximum Ratings
These 3V to 5V RS-232 transceivers have been fully characterized for 3.0V to 3.6V operation, and at critical
points for 4.5V to 5.5V operation. Furthermore, load conditions were favorable using static logic states only.
The specified maximum values for V+ and V- are +7V and -7V, respectively. These limits apply for VCC values set
to 3.0V and 3.6V (see Tab le 2). For VCC values set to 4.5V and 5.5V, the maximum values for V+ and V- can
approach +9V and -7V respectively (see Tab le 3 ). The breakdown characteristics for V+ and V- were measured
with ±13V.
Table 2. V+ and V- Values for VCC = 3.0V to 3.6V
C1 (μF) C2, C3, C4 (μF) Load
T1IN (Logic
State)
V+ (V) V- (V)
VCC = 3.0V VCC = 3.6V VCC = 3.0V VCC = 3.6V
0.1 0.1 Open H 5.8 6.56 -5.6 -5.88
L 5.8 6.56 -5.6 -5.88
2.4kbps 5.8 6.56 -5.6 -5.88
3kΩ // 1000pF H 5.88 6.6 -5.56 -5.92
L 5.76 6.36 -5.56 -5.76
2.4kbps 6 6.64 -5.64 -5.96
0.047 0.33 Open H 5.68 6 -5.6 -5.6
L 5.68 6 -5.6 -5.6
2.4kbps 5.68 6 -5.6 -5.6
3kΩ // 1000pF H 5.76 6.08 -5.64 -5.64
L 5.68 6.04 -5.6 -5.6
2.4kbps 5.84 6.16 -5.64 -5.72
1 1 Open H 5.88 6.24 -5.6 -5.6
L 5.88 6.28 -5.6 -5.64
2.4kbps 5.8 6.2 -5.6 -5.6
3kΩ // 1000pF H 5.88 6.44 -5.64 -5.72
L 5.88 6.04 -5.64 -5.64
2.4kbps 5.92 6.4 -5.64 -5.64
ICL3221, ICL3222, ICL3223, ICL3232, ICL3241, ICL3243 4. Application Information
FN4805 Rev.23.00 Page 14 of 36
Apr.26.19
The resulting new maximum voltages at V+ and V- are listed in Tab le 4.
4.2 Transmitters
The transmitters are proprietary, low dropout, inverting drivers that translate TTL/CMOS inputs to EIA/TIA-232
output levels. These transmitters are coupled with the on-chip ± 5.5V supplies and deliver true RS-232 levels
across a wide range of single supply system voltages.
Except for the ICL3232, all transmitter outputs disable and assume a high impedance state when the device
enters the powerdown mode (See Table 5 on page 15). These outputs can be driven to ±12V when disabled.
All devices ensure a 250kbps data rate for full load conditions (3kΩ and 1000pF), VCC ≥ 3.0V, with one transmitter
operating at full speed. Under more typical conditions of VCC ≥3.3V, RL= 3kΩ, and CL= 250pF, one transmitter
easily operates at 900kbps.
Transmitter inputs float if left unconnected and may cause ICC increases. Connect unused inputs to GND for the
best performance.
4.3 Receivers
All the ICL32xx devices contain standard inverting receivers that three-state (except for the ICL3232) using the
EN or FORCEOFF control lines. Additionally, the two ICL324X products include noninverting (monitor) receivers
(denoted by the ROUTB label) that are always active, regardless of the state of any control lines. All the receivers
convert RS-232 signals to CMOS output levels and accept inputs up to ±25V while presenting the required 3kΩ to
7kΩ input impedance (see Figure 7) even if the power is off (VCC = 0V). The receivers’ Schmitt trigger input stage
uses hysteresis to increase noise immunity and decrease errors due to slow input signal transitions.
Table 3. V+ and V- Values for Vcc = 4.5V to 5.5V
C1 (μF) C2, C3, C4 (μF) Load
T1IN (Logic
State)
V+ (V) V- (V)
VCC = 4.5V VCC = 5.5V VCC = 4.5V VCC = 5.5V
0.1 0.1 Open H 7.44 8.48 -6.16 -6.4
L 7.44 8.48 -6.16 -6.44
2.4kbps 7.44 8.48 -6.17 -6.44
3kΩ // 1000pF H 7.76 8.88 -6.36 -6.72
L 7.08 8 -5.76 -5.76
2.4kbps 7.76 8.84 -6.4 -6.64
0.047 0.33 Open H 6.44 6.88 -5.8 -5.88
L 6.48 6.88 -5.84 -5.88
2.4kbps 6.44 6.88 -5.8 -5.88
3kΩ // 1000pF H 6.64 7.28 -5.92 -6.04
L 6.24 6.6 -5.52 -5.52
2.4kbps 6.72 7.16 -5.92 -5.96
1 1 Open H 6.84 7.6 -5.76 -5.76
L 6.88 7.6 -5.76 -5.76
2.4kbps 6.92 7.56 -5.72 -5.76
3kΩ // 1000pF H 7.28 8.16 -5.8 -5.92
L 6.44 6.84 -5.64 -6.84
2.4kbps 7.08 7.76 -5.8 -5.8
Table 4. New Measured Withstanding Voltages
V+, V- to Ground ±13V
V+ to V- 20V
ICL3221, ICL3222, ICL3223, ICL3232, ICL3241, ICL3243 4. Application Information
FN4805 Rev.23.00 Page 15 of 36
Apr.26.19
The ICL3221/22/23/41 inverting receivers disable only when EN is driven high. ICL3243 receivers disable during
forced (manual) powerdown, but not during automatic powerdown (See Tab le 5).
ICL324X monitor receivers remain active even during manual powerdown and forced receiver disable, making
them extremely useful for Ring Indicator monitoring. Standard receivers driving powered down peripherals must
be disabled to prevent current flow through the peripheral’s protection diodes (See Figures 8 and 9). When
disabled, the receivers cannot be used for wake up functions, but the corresponding monitor receiver can be
dedicated to this task as shown in Figure 9 on page 17.
4.4 Low Power Operation
The 3V devices require a nominal supply current of 0.3mA, even at VCC = 5.5V, during normal operation (not in
powerdown mode), which is considerably less than the 5mA to 11mA current required by comparable 5V RS-232
devices, allowing you to reduce system power simply by switching to this new family.
4.5 Powerdown Functionality (Except ICL3232)
The already low current requirement drops significantly when the device enters powerdown mode. In
power-down, supply current drops to 1µA, because the on-chip charge pump turns off (V+ collapses to VCC,
V- collapses to GND), and the transmitter outputs three-state. Inverting receiver outputs may disable in
power-down; see Tab le 5 for details. This micro-power mode makes these devices ideal for battery powered and
portable applications.
4.5.1 Software Controlled (Manual) Powerdown
Most devices in the ICL32xx family provide pins that allow you to force the IC into the low power, standby state.
On the ICL3222 and ICL3241, the powerdown control is using a simple shutdown (SHDN) pin. Driving this pin
high enables normal operation, and driving it low forces the IC into its powerdown state. Connect SHDN to VCC if
the powerdown function is not needed. Note that all the receiver outputs remain enabled during shutdown (See
Tab le 5 ). For the lowest power consumption during powerdown, the receivers should also be disabled by driving
the EN input high (See next section, and Figures 8 and 9).
The ICL3221, ICL3223, and ICL3243 use a two pin approach where the FORCEON and FORCEOFF inputs
determine the IC’s mode. For always enabled operation, FORCEON and FORCEOFF are both strapped high.
Under logic or software control, only the FORCEOFF input needs to be driven to switch between active and
powerdown modes. The FORCEON state is not critical because FORCEOFF overrides FORCEON. However, if
strictly manual control over powerdown is needed, you must strap FORCEON high to disable the automatic
power-down circuitry. ICL3243 inverting (standard) receiver outputs also disable when the device is in manual
powerdown, thereby eliminating the possible current path through a shutdown peripheral’s input protection diode
(See Figures 8 and 9).
Figure 7. Inverting Receiver Connections
Table 5. Powerdown and Enable Logic Truth Table
RS-232
Signal Present at
Receiver Input?
FORCEOFF
or SHDN
Input
FORCEON
Input
EN
Input
Transmitter
Outputs
Receiver
Outputs
ROUTB
Outputs
(Note 6)
INVALID
Output Mode of Operation
ICL3222, ICL3241
N.A. L N.A. L High-Z Active Active N.A. Manual Powerdown
N.A. L N.A. H High-Z High-Z Active N.A. Manual Powerdown w/Rcvr.
Disabled
N.A. H N.A. L Active Active Active N.A. Normal Operation
RXOUT
GND ≤ VROUT ≤ VCC
5kΩ
RXIN
-25V ≤ VRIN ≤ +25V
GND
VCC
ICL3221, ICL3222, ICL3223, ICL3232, ICL3241, ICL3243 4. Application Information
FN4805 Rev.23.00 Page 16 of 36
Apr.26.19
4.5.2 INVALID Output
The INVALID output always indicates whether a valid RS-232 signal is present at any of the receiver inputs (See
Tab le 5 ), giving you a way to determine when the interface block should power down. In the case of a
disconnected interface cable where all the receiver inputs are floating (but pulled to GND by the internal receiver
pull down resistors), the INVALID logic detects the invalid levels and drives the output low. The power
management logic then uses this indicator to power down the interface block. Reconnecting the cable restores
valid levels at the receiver inputs, INVALID switches high, and the power management logic wakes up the
interface block. INVALID can also be used to indicate the DTR or RING INDICATOR signal as long as the other
receiver inputs are floating or driven to GND (as in the case of a powered down driver). Connecting FORCEOFF
and FORCEON together disables the automatic powerdown feature, enabling them to function as a manual
SHUTDOWN input (See Figure 10).
N.A. H N.A. H Active High-Z Active N.A. Normal Operation w/Rcvr.
Disabled
ICL3221, ICL3223
No H H L Active Active N.A. L Normal Operation
(Auto Powerdown Disabled)
No H H H Active High-Z N.A. L
Yes H L L Active Active N.A. H Normal Operation
(Auto Powerdown Enabled)
Yes H L H Active High-Z N.A. H
No H L L High-Z Active N.A. L Powerdown Due to Auto
Power-Down Logic
No H L H High-Z High-Z N.A. L
Yes L X L High-Z Active N.A. H Manual Powerdown
Yes L X H High-Z High-Z N.A. H Manual Powerdown w/Rcvr.
Disabled
No L X L High-Z Active N.A. L Manual Powerdown
No L X H High-Z High-Z N.A. L Manual Powerdown w/Rcvr.
Disabled
ICL3243
No H H N.A. Active Active Active L Normal Operation
(Auto Powerdown Disabled)
Yes H L N.A. Active Active Active H Normal Operation
(Auto Powerdown Enabled)
No H L N.A. High-Z Active Active L Powerdown Due to Auto
Power-Down Logic
Yes L X N.A. High-Z High-Z Active H Manual Powerdown
No L X N.A. High-Z High-Z Active L Manual Powerdown
Note:
6. Applies only to the ICL3241 and ICL3243.
Table 5. Powerdown and Enable Logic Truth Table (Continued)
RS-232
Signal Present at
Receiver Input?
FORCEOFF
or SHDN
Input
FORCEON
Input
EN
Input
Transmitter
Outputs
Receiver
Outputs
ROUTB
Outputs
(Note 6)
INVALID
Output Mode of Operation
ICL3222, ICL3241
ICL3221, ICL3222, ICL3223, ICL3232, ICL3241, ICL3243 4. Application Information
FN4805 Rev.23.00 Page 17 of 36
Apr.26.19
With any of the above control schemes, the time required to exit powerdown and resume transmission is only
100µs. A mouse or other application may need more time to wake up from shutdown. If automatic powerdown is
being used, the RS-232 device reenters powerdown if valid receiver levels are not re-established within 30µs of
the ICL32xx powering up. Figure 11 on page 18 shows a circuit that keeps the ICL32xx from initiating automatic
Figure 8. Power Drain Through Powered Down Peripheral
Figure 9. Disabled Receivers Prevent Power Drain
Figure 10. Connections for Manual Powerdown when No Valid Receiver Signals are Present
Old
VCC
Powered
GND SHDN = GND
VCC
Rx
Tx
VCC
Current
VOUT = VCC
Flow
RS-232 Chip
Down
UART
ICL324X
Transition
RX
TX
R2OUTB
R2OUT
T1IN
FORCEOFF = GND
VCC
VCC
To
R2IN
T1OUT
VOUT = HI-Z
Powered
OR SHDN = GND, EN = VCC
Detector
Down
UART
Wake-Up
Logic
PWR
FORCEOFF
INVALID
CPU
I/O
FORCEON
ICL3221/23/43
MGT
Logic
UART
ICL3221, ICL3222, ICL3223, ICL3232, ICL3241, ICL3243 4. Application Information
FN4805 Rev.23.00 Page 18 of 36
Apr.26.19
power-down for 100ms after powering up, which gives the slow-to-wake peripheral circuit time to re-establish valid
RS-232 output levels.
4.5.3 Automatic Powerdown (ICL3221/23/43 Only)
Even greater power savings are available by using the ICL3221, ICL3223, or ICL3243's automatic powerdown
function. When no valid RS-232 voltages (See Figure 12) are sensed on any receiver input for 30μs, the
charge-pump and transmitters powerdown, thereby reducing supply current to 1µA. Invalid receiver levels occur
whenever the driving peripheral’s outputs are shut off (powered down) or when the RS-232 interface cable is
disconnected. The ICL32xx devices power back up whenever they detect a valid RS-232 voltage level on any
receiver input, which provides additional system power savings without changes to the existing operating system.
Automatic powerdown operates when the FORCEON input is low, and the FORCEOFF input is high. Tying
FORCEON high disables automatic powerdown, but manual powerdown is always available using the overriding
FORCEOFF input. Table 5 on page 15 summarizes the automatic powerdown functionality.
Devices with the automatic powerdown feature include an INVALID output signal, which switches low to indicate
that invalid levels have persisted on all of the receiver inputs for more than 30µs (See Figure 13). INVALID
switches high 1µs after detecting a valid RS-232 level on a receiver input. INVALID operates in all modes (forced
or automatic powerdown, or forced on), so it is also useful for systems employing manual powerdown circuitry.
When automatic powerdown is used, INVALID = 0 indicates that the ICL32xx is in powerdown mode.
Figure 11. Circuit to Prevent Auto Powerdown for 100ms After Forced Power-UP
Figure 12. Definition of Valid RS-232 Receiver Levels
ICL3221/23/43
FORCEOFF FORCEON
Power Master Powerdown Line
1MΩ
0.1µF
Management
Unit
0.3V
-0.3V
-2.7V
2.7V
Invalid Level - Powerdown Occurs After 30ms
Valid RS-232 Level - ICL32xx is Active
Valid RS-232 Level - ICL32xx is Active
Indeterminate - Powerdown May or
Indeterminate - Powerdown May or
May Not Occur
May Not Occur
ICL3221, ICL3222, ICL3223, ICL3232, ICL3241, ICL3243 4. Application Information
FN4805 Rev.23.00 Page 19 of 36
Apr.26.19
The time to recover from automatic powerdown mode is typically 100µs.
4.6 Receiver ENABLE Control (ICL3221/22/23/41 Only)
ICL3221, ICL3222, ICL3223, and ICL3241 also feature an EN input to control the receiver outputs. Driving EN
high disables all the inverting (standard) receiver outputs placing them in a high impedance state, which is useful
to eliminate supply current, due to a receiver output forward biasing the protection diode, when driving the input of
a powered down (VCC = GND) peripheral (See Figure 8 on page 17). The enable input has no effect on
transmitter nor monitor (ROUTB) outputs.
4.7 Capacitor Selection
The charge pumps require 0.1µF capacitors for 3.3V operation. For other supply voltages see Tab le 6 for
capacitor values. Do not use values smaller than those listed in Ta ble 6 . Increasing the capacitor values (by a
factor of 2) reduces ripple on the transmitter outputs and slightly reduces power consumption. C2, C3, and C4 can
be increased without increasing C1’s value; however, do not increase C1 without also increasing C2, C3, and C4 to
maintain the proper ratios (C1 to the other capacitors).
When using minimum required capacitor values, make sure that capacitor values do not degrade excessively with
temperature. If in doubt, use capacitors with a larger nominal value. The capacitor’s Equivalent Series Resistance
(ESR) usually rises at low temperatures and it influences the amount of ripple on V+ and V-.
4.8 Power Supply Decoupling
In most circumstances a 0.1µF bypass capacitor is adequate. In applications that are particularly sensitive to
power supply noise, decouple VCC to ground with a capacitor of the same value as the charge-pump capacitor C1.
Connect the bypass capacitor as close as possible to the IC.
4.9 Operation Down to 2.7V
ICL32xx transmitter outputs meet RS-562 levels (±3.7V), at full data rate, with VCC as low as 2.7V. RS-562 levels
typically ensure interoperability with RS-232 devices.
Figure 13. Automatic Powerdown and INVALID Timing Diagrams
Table 6. Required Capacitor Values
VCC (V) C1 (µF) C2, C3, C4 (µF)
3.0 to 3.6 0.1 0.1
4.5 to 5.5 0.047 0.33
3.0 to 5.5 0.1 0.47
Receiver
Inputs
Transmitter
Outputs
INVALID
Output
V+
VCC
0
V-
VCC
0
tINVL tINVH
Invalid
Region
}
AUTOPWDN PWR UP
ICL3221, ICL3222, ICL3223, ICL3232, ICL3241, ICL3243 4. Application Information
FN4805 Rev.23.00 Page 20 of 36
Apr.26.19
4.10 Transmitter Outputs when Exiting Powerdown
Figure 14 shows the response of two transmitter outputs when exiting powerdown mode. As they activate, the two
transmitter outputs properly go to opposite RS-232 levels, with no glitching, ringing, nor undesirable transients.
Each transmitter is loaded with 3kΩ in parallel with 2500pF. Note that the transmitters enable only when the
magnitude of the supplies exceed approximately 3V.
4.11 Mouse Driveability
The ICL324X have been specifically designed to power a serial mouse while operating from low voltage supplies.
Figure 15 shows the transmitter output voltages under increasing load current. The on-chip switching regulator
ensures the transmitters will supply at least ±5V during worst case conditions (15mA for paralleled V+
transmitters, 7.3mA for single V- transmitter). The Automatic Powerdown feature does not work with a mouse, so
FORCEOFF and FORCEON should be connected to VCC.
4.12 High Data Rates
The ICL32xx maintain the RS-232 ±5V minimum transmitter output voltages even at high data rates. Figure 16
details a transmitter loopback test circuit, and Figure 17 illustrates the loopback test result at 120kbps. For this
test, all transmitters were simultaneously driving RS-232 loads in parallel with 1000pF at 120kbps. Figure 18
shows the loopback results for a single transmitter driving 1000pF and an RS-232 load at 250kbps. The static
transmitters were also loaded with an RS-232 receiver.
Figure 14. Transmitter Outputs when Exiting Powerdown
Figure 15. Transmitter Output Voltage vs Load Current (per Transmitter, Such as, Double Current Axis for Total VOUT+
Current)
Time (20µs/Div)
T1
T2
2V/Div
5V/Div
VCC = +3.3V
FORCEOFF
C1 - C4 = 0.1µF
Transmitter Output Voltage (V)
Load Current per Transmitter (mA)
0246810
-6
-4
-2
0
2
4
6
-5
-3
-1
1
3
5
13579
VOUT+
VOUT -
VCC
VOUT+
VOUT -
T1
T2
T3
VCC = 3.0V
ICL3241/43
ICL3221, ICL3222, ICL3223, ICL3232, ICL3241, ICL3243 4. Application Information
FN4805 Rev.23.00 Page 21 of 36
Apr.26.19
4.13 Interconnection with 3V and 5V Logic
The ICL32xx directly interface with 5V CMOS and TTL logic families. With the ICL32xx at 3.3V, and the logic
supply at 5V, AC, HC, and CD4000 outputs can drive ICL32xx inputs, but ICL32xx outputs do not reach the
minimum VIH for these logic families. See Tab le 7 for more information.
Figure 16. Transmitter Loopback Test Circuit
Figure 17. Loopback Test at 120kbps Figure 18. Loopback Test at 250kbps
Table 7. Logic Family Compatibility with Various Supply Voltages
System Power-Supply
Voltage (V)
VCC Supply
Voltage (V) Compatibility
3.3 3.3 Compatible with all CMOS families.
5 5 Compatible with all TTL and CMOS logic families.
5 3.3 Compatible with ACT and HCT CMOS, and with TTL. ICL32xx outputs
are incompatible with AC, HC, and CD4000 CMOS inputs.
ICL32xx
VCC FORCEOFF
C1
C2C4
C3
+
+
+
+
1000pF
V+
V-
5k
TIN
ROUT
C1+
C1-
C2+
C2-
RIN
TOUT
+
VCC
0.1µF
VCC
EN
SHDN OR
T1IN
T1OUT
R1OUT
5µs/Div
VCC = +3.3V
5V/Div
C1 - C4 = 0.1µF
T1IN
T1OUT
R1OUT
2µs/Div
5V/Div
VCC = +3.3V
C1 - C4 = 0.1μF
ICL3221, ICL3222, ICL3223, ICL3232, ICL3241, ICL3243 4. Application Information
FN4805 Rev.23.00 Page 22 of 36
Apr.26.19
4.14 Pin Compatible Replacements For 5V Devices
The ICL3221/22/32 are pin compatible with existing 5V RS-232 transceivers (see the “Features” on page 1 for
details), which coupled with the low ICC and wide operating supply range, make the ICL32xx potential lower
power, higher performance, drop-in replacements for existing 5V applications. As long as the ±5V RS-232 output
swings are acceptable, and transmitter input pull-up resistors are not required, the ICL32xx should work in most
5V applications.
When replacing a device in an existing 5V application, it is acceptable to terminate C3 to VCC as shown on the
“Typical Operating Circuits” on page 3. Terminate C3 to GND if possible, as slightly better performance results
from this configuration.
ICL3221, ICL3222, ICL3223, ICL3232, ICL3241, ICL3243 5. Die Characteristics
FN4805 Rev.23.00 Page 23 of 36
Apr.26.19
5. Die Characteristics
Substrate Potential (Powered Up) GND
Transistor Count ICL3221: 286
ICL3222: 338
ICL3223: 357
ICL3232: 296
ICL324X: 464
Process Si Gate CMOS
ICL3221, ICL3222, ICL3223, ICL3232, ICL3241, ICL3243 6. Revision History
FN4805 Rev.23.00 Page 24 of 36
Apr.26.19
6. Revision History
Rev. Date Description
23 Apr 26, 2019 Updated to latest formatting.
Added Related Literature section.
Updated Ordering information table by adding active tape and reel information, updated notes, adding note 3,
removed retired parts, and stamped EOL parts.
Added “Charge Pump Absolute Maximum Ratings” on page 13.
Removed About Intersil section.
Updated M16.15 to the latest revision changes are as follows:
Update graphics to new standard layout, removing the dimension table.
Updated disclaimer.
22 Sep 1, 2015 - Ordering Information Table on page 2.
- Added Revision History.
- Added About Intersil Verbiage.
- Updated POD M16.173 to latest revision changes are as follow:
Convert to new POD format by moving dimensions from table onto drawing and adding land pattern. No
dimension changes.
- Updated POD M20.173 to most current version changes are as follow:
Convert to new POD format by moving dimensions from table onto drawing and adding land pattern. No
dimension changes.
- Updated POD M28.173 to most current version changes are as follow:
Convert to new POD format by moving dimensions from table onto drawing and adding land pattern. No
dimension changes.
-Updated POD M28.3 to most current version change is as follows:
Added land pattern.
ICL3221, ICL3222, ICL3223, ICL3232, ICL3241, ICL3243 7. Package Outline Drawings
FN4805 Rev.23.00 Page 25 of 36
Apr.26.19
7. Package Outline Drawings
Notes:
1. Controlling Dimensions: INCH. In case of conflict between English and
Metric dimensions, the inch dimensions control.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication No. 95.
4. Dimensions A, A1 and L are measured with the package seated in JE-
DEC seating plane gauge GS-3.
5. D, D1, and E1 dimensions do not include mold flash or protrusions.
Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).
6. E and are measured with the leads constrained to be perpendic-
ular to datum .
7. eB and eC are measured at the lead tips with the leads unconstrained.
eC must be zero or greater.
8. B1 maximum dimensions do not include dambar protrusions. Dambar
protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3,
E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).
eA
C
L
E
eA
C
eB
eC
-B-
E1
INDEX 12 3 N/2
N
AREA
SEATING
BASE
PLANE
PLANE
-C-
D1
B1
B
e
D
D1
A
A2
L
A1
-A-
0.010 (0.25) C AMBS
E16.3 (JEDEC MS-001-BB ISSUE D)
16 LEAD DUAL-IN-LINE PLASTIC PACKAGE (PDIP)
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A - 0.210 - 5.33 4
A1 0.015 - 0.39 - 4
A2 0.115 0.195 2.93 4.95 -
B 0.014 0.022 0.356 0.558 -
B1 0.045 0.070 1.15 1.77 8, 10
C 0.008 0.014 0.204 0.355 -
D 0.735 0.775 18.66 19.68 5
D1 0.005 - 0.13 - 5
E 0.300 0.325 7.62 8.25 6
E1 0.240 0.280 6.10 7.11 5
e 0.100 BSC 2.54 BSC -
eA0.300 BSC 7.62 BSC 6
eB- 0.430 - 10.92 7
L 0.115 0.150 2.93 3.81 4
N16 169
Rev. 0 12/93
For the most recent package outline drawing, see E16.3.
ICL3221, ICL3222, ICL3223, ICL3232, ICL3241, ICL3243 7. Package Outline Drawings
FN4805 Rev.23.00 Page 26 of 36
Apr.26.19
M16.15 (JEDEC MS-012-AC ISSUE C)
16 Lead Narrow Body Small Outline Plastic Package
Rev 2, 11/17
For the most recent package outline drawing, see M16.15.
ICL3221, ICL3222, ICL3223, ICL3232, ICL3241, ICL3243 7. Package Outline Drawings
FN4805 Rev.23.00 Page 27 of 36
Apr.26.19
M16.173
16 Lead Thin Shrink Small Outline Package (TSSOP)
Rev 2, 5/10
0.09-0.20
SEE DETAIL "X"
DETAIL "X"
TYPICAL RECOMMENDED LAND PATTERN
TOP VIEW
SIDE VIEW
END VIEW
Dimension does not include mold flash, protrusions or gate burrs.
Mold flash, protrusions or gate burrs shall not exceed 0.15 per side.
Dimension does not include interlead flash or protrusion. Interlead
flash or protrusion shall not exceed 0.25 per side.
Dimensions are measured at datum plane H.
Dimensioning and tolerancing per ASME Y14.5M-1994.
Dimension does not include dambar protrusion. Allowable protrusion
shall be 0.08mm total in excess of dimension at maximum material
condition. Minimum space between protrusion and adjacent lead
is 0.07mm.
Dimension in ( ) are for reference only.
Conforms to JEDEC MO-153.
6.
3.
5.
4.
2.
1.
NOTES:
7.
(0.65 TYP)
(5.65)
(0.35 TYP)
0.90 +0.15/-0.10
0.60 ±0.15
0.15 MAX
0.05 MIN
PLANE
GAUGE
0°-8°
0.25
1.00 REF
(1.45)
16
2
1
3
8
B
1 3
9
A
PIN #1
I.D. MARK
5.00 ±0.10
6.40
4.40 ±0.10
0.65
1.20 MAX
SEATING
PLANE
0.25 +0.05/-0.06 5
C
H
0.20 C B A
0.10 C
-
0.05
0.10 C B A
M
For the most recent package outline drawing, see M16.173.
ICL3221, ICL3222, ICL3223, ICL3232, ICL3241, ICL3243 7. Package Outline Drawings
FN4805 Rev.23.00 Page 28 of 36
Apr.26.19
Notes:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.20mm (0.0078
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.20mm (0.0078 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “B” does not include dambar protrusion. Allowable dambar
protrusion shall be 0.13mm (0.005 inch) total in excess of “B”
dimension at maximum material condition.
10. Controlling dimension: MILLIMETER. Converted inch dimensions are
not necessarily exact.
INDEX
AREA
E
D
N
123
-B-
0.25(0.010) C AMBS
e
-A-
L
B
M
-C-
A1
A
SEATING PLANE
0.10(0.004)
C
H0.25(0.010) BM M
α
0.25
0.010
GAUGE
PLANE
A2
M16.209 (JEDEC MO-150-AC ISSUE B)
16 Lead Shrink Small Outline Plastic Package (SSOP)
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A - 0.078 - 2.00 -
A1 0.002 - 0.05 - -
A2 0.065 0.072 1.65 1.85 -
B 0.009 0.014 0.22 0.38 9
C 0.004 0.009 0.09 0.25 -
D 0.233 0.255 5.90 6.50 3
E 0.197 0.220 5.00 5.60 4
e 0.026 BSC 0.65 BSC -
H 0.292 0.322 7.40 8.20 -
L 0.022 0.037 0.55 0.95 6
N16 167
α0° 8° 0° 8° -
Rev. 3 6/05
For the most recent package outline drawing, see M16.209.
ICL3221, ICL3222, ICL3223, ICL3232, ICL3241, ICL3243 7. Package Outline Drawings
FN4805 Rev.23.00 Page 29 of 36
Apr.26.19
Notes:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above
the seating plane, shall not exceed a maximum value of 0.61mm (0.024
inch)
10. Controlling dimension: MILLIMETER. Converted inch dimensions are
not necessarily exact.
INDEX
AREA
E
D
N
123
-B-
0.25(0.010) C AMBS
e
-A-
L
B
M
-C-
A1
A
SEATING PLANE
0.10(0.004)
h x 45°
C
H0.25(0.010) BM M
α
M16.3 (JEDEC MS-013-AA ISSUE C)
16 Lead Wide Body Small Outline Plastic Package (SOIC)
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A 0.0926 0.1043 2.35 2.65 -
A1 0.0040 0.0118 0.10 0.30 -
B 0.013 0.0200 0.33 0.51 9
C 0.0091 0.0125 0.23 0.32 -
D 0.3977 0.4133 10.10 10.50 3
E 0.2914 0.2992 7.40 7.60 4
e 0.050 BSC 1.27 BSC -
H 0.394 0.419 10.00 10.65 -
h 0.010 0.029 0.25 0.75 5
L 0.016 0.050 0.40 1.27 6
N16 167
α0° 8° 0° 8° -
Rev. 1 6/05
For the most recent package outline drawing, see M16.3.
ICL3221, ICL3222, ICL3223, ICL3232, ICL3241, ICL3243 7. Package Outline Drawings
FN4805 Rev.23.00 Page 30 of 36
Apr.26.19
Notes:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above
the seating plane, shall not exceed a maximum value of 0.61mm
(0.024 inch)
10. Controlling dimension: MILLIMETER. Converted inch dimensions are
not necessarily exact.
INDEX
AREA
E
D
N
123
-B-
0.25(0.010) C AMBS
e
-A-
L
B
M
-C-
A1
A
SEATING PLANE
0.10(0.004)
h x 45°
C
H0.25(0.010) BM M
α
M18.3 (JEDEC MS-013-AB ISSUE C)
18 Lead Wide Body Small Outline Plastic Package (SOIC)
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A 0.0926 0.1043 2.35 2.65 -
A1 0.0040 0.0118 0.10 0.30 -
B 0.013 0.0200 0.33 0.51 9
C 0.0091 0.0125 0.23 0.32 -
D 0.4469 0.4625 11.35 11.75 3
E 0.2914 0.2992 7.40 7.60 4
e 0.050 BSC 1.27 BSC -
H 0.394 0.419 10.00 10.65 -
h 0.010 0.029 0.25 0.75 5
L 0.016 0.050 0.40 1.27 6
N18 187
α0° 8° 0° 8° -
Rev. 1 6/05
For the most recent package outline drawing, see M18.3.
ICL3221, ICL3222, ICL3223, ICL3232, ICL3241, ICL3243 7. Package Outline Drawings
FN4805 Rev.23.00 Page 31 of 36
Apr.26.19
M20.173
20 Lead Thin Shrink Small Outline Package (TSSOP)
Rev 2, 5/10
DETAIL "X"
TYPICAL RECOMMENDED LAND PATTERN
TOP VIEW
SIDE VIEW
END VIEW
Dimension does not include mold flash, protrusions or gate burrs.
Mold flash, protrusions or gate burrs shall not exceed 0.15 per side.
Dimension does not include interlead flash or protrusion. Interlead
flash or protrusion shall not exceed 0.25 per side.
Dimensions are measured at datum plane H.
Dimensioning and tolerancing per ASME Y14.5M-1994.
Dimension does not include dambar protrusion. Allowable protrusion
shall be 0.08mm total in excess of dimension at maximum material
condition. Minimum space between protrusion and adjacent lead
is 0.07mm.
Dimension in ( ) are for reference only.
Conforms to JEDEC MO-153.
6.
3.
5.
4.
2.
1.
NOTES:
7.
0.09-0.20
SEE DETAIL "X"
(0.65 TYP)
(5.65)
(0.35 TYP)
0.90 +0.15/-0.10
0.60 ±0.15
0.15 MAX
0.05 MIN
PLANE
GAUGE
0°-8°
0.25
1.00 REF
(1.45)
20
0.20 C B A
2
1
3
9
B
1 3
10
A
PIN #1
I.D. MARK
6.50 ±0.10
6.40
4.40 ±0.10
0.65
0.10 C
SEATING
PLANE
0.25 +0.05/-0.06 5
C
H
-
0.05
1.20 MAX
0.10 C B A
M
For the most recent package outline drawing, see M20.173.
ICL3221, ICL3222, ICL3223, ICL3232, ICL3241, ICL3243 7. Package Outline Drawings
FN4805 Rev.23.00 Page 32 of 36
Apr.26.19
Notes:
1. Symbols are defined in the “MO Series Symbol List” in Section
2.2 of Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.20mm (0.0078 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions.
Interlead flash and protrusions shall not exceed 0.20mm (0.0078
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “B” does not include dambar protrusion. Allowable
dambar protrusion shall be 0.13mm (0.005 inch) total in excess
of “B” dimension at maximum material condition.
10. Controlling dimension: MILLIMETER. Converted inch
dimensions are not necessarily exact.
α
INDEX
AREA
E
D
N
123
-B-
0.25(0.010) C A
MBS
e
-A-
B
M
-C-
A1
A
SEATING PLANE
0.10(0.004)
C
H0.25(0.010) B
MM
L
0.25
0.010
GAUGE
PLANE
A2
M20.209 (JEDEC MO-150-AE ISSUE B)
20 Lead Shrink Small Outline Plastic Package (SSOP)
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A 0.068 0.078 1.73 1.99
A1 0.002 0.008’ 0.05 0.21
A2 0.066 0.070’ 1.68 1.78
B 0.010’ 0.015 0.25 0.38 9
C 0.004 0.008 0.09 0.20’
D 0.278 0.289 7.07 7.33 3
E 0.205 0.212 5.20’ 5.38 4
e 0.026 BSC 0.65 BSC
H 0.301 0.311 7.65 7.90’
L 0.025 0.037 0.63 0.95 6
N20 207
α0 deg. 8 deg. 0 deg. 8 deg.
Rev. 3 11/02
For the most recent package outline drawing, see M20.209.
ICL3221, ICL3222, ICL3223, ICL3232, ICL3241, ICL3243 7. Package Outline Drawings
FN4805 Rev.23.00 Page 33 of 36
Apr.26.19
M28.173
28 Lead Thin Shrink Small Outline Package (TSSOP)
Rev 1, 5/10
DETAIL "X"
TYPICAL RECOMMENDED LAND PATTERN
TOP VIEW
SIDE VIEW
END VIEW
Dimension does not include mold flash, protrusions or gate burrs.
Mold flash, protrusions or gate burrs shall not exceed 0.15 per side.
Dimension does not include interlead flash or protrusion. Interlead
flash or protrusion shall not exceed 0.25 per side.
Dimensions are measured at datum plane H.
Dimensioning and tolerancing per ASME Y14.5M-1994.
Dimension does not include dambar protrusion. Allowable protrusion
shall be 0.08mm total in excess of dimension at maximum material
condition. Minimum space between protrusion and adjacent lead
is 0.07mm.
Dimension in ( ) are for reference only.
Conforms to JEDEC MO-153.
6.
3.
5.
4.
2.
1.
NOTES:
7.
5
SEATING PLANE
C
H
32
1
28
B
14
1 3
15
A
PLANE
GAUGE
0.05 MIN
0.15 MAX
0°-8°
0.60 ±0.15
0.90
1.00 REF
0.25
SEE DETAIL "X"
0.25
(0.65 TYP)
(5.65)
(0.35 TYP)
(1.45)
6.40
4.40 ± 0.10
0.65
1.20 MAX
PIN #1
I.D. MARK
9.70± 0.10
-0.06
0.15 +0.05
-0.10
+0.15
-0.06
+0.05
0.20 C B A
0.10 C
-
0.05
0.10 C B A
M
For the most recent package outline drawing, see M28.173.
ICL3221, ICL3222, ICL3223, ICL3232, ICL3241, ICL3243 7. Package Outline Drawings
FN4805 Rev.23.00 Page 34 of 36
Apr.26.19
Notes:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2
of Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.20mm (0.0078 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions.
Interlead flash and protrusions shall not exceed 0.20mm (0.0078
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “B” does not include dambar protrusion. Allowable
dambar protrusion shall be 0.13mm (0.005 inch) total in excess of
“B” dimension at maximum material condition.
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
INDEX
AREA
E
D
N
123
-B-
0.25(0.010) C AMBS
e
-A-
L
B
M
-C-
A1
A
SEATING PLANE
0.10(0.004)
C
H0.25(0.010) BM M
α
0.25
0.010
GAUGE
PLANE
A2
M28.209 (JEDEC MO-150-AH ISSUE B)
28 Lead Shrink Small Outline Plastic Package (SSOP)
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A - 0.078 - 2.00 -
A1 0.002 - 0.05 - -
A2 0.065 0.072 1.65 1.85 -
B 0.009 0.014 0.22 0.38 9
C 0.004 0.009 0.09 0.25 -
D 0.390 0.413 9.90 10.50 3
E 0.197 0.220 5.00 5.60 4
e 0.026 BSC 0.65 BSC -
H 0.292 0.322 7.40 8.20 -
L 0.022 0.037 0.55 0.95 6
N28 287
α0° 8° 0° 8° -
Rev. 2 6/05
For the most recent package outline drawing, see M28.209.
ICL3221, ICL3222, ICL3223, ICL3232, ICL3241, ICL3243 7. Package Outline Drawings
FN4805 Rev.23.00 Page 35 of 36
Apr.26.19
a
INDEX
AREA
E
D
N
123
-B-
0.25(0.010) C AMBS
e
-A-
L
B
M
-C-
A1
A
SEATING PLANE
0.10(0.004)
h x 45o
C
H0.25(0.010) BM M
(1.50mm)
(9.38mm)
(1.27mm TYP) (0.51mm TYP)
TYPICAL RECOMMENDED LAND PATTERN
M28.3 (JEDEC MS-013-AE ISSUE C)
28 Lead Wide Body Small Outline Plastic Package (SOIC)
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A 0.0926 0.1043 2.35 2.65 -
A1 0.0040 0.0118 0.10 0.30 -
B 0.013 0.0200 0.33 0.51 9
C 0.0091 0.0125 0.23 0.32 -
D 0.6969 0.7125 17.70 18.10 3
E 0.2914 0.2992 7.40 7.60 4
e 0.05 BSC 1.27 BSC -
H 0.394 0.419 10.00 10.65 -
h 0.01 0.029 0.25 0.75 5
L 0.016 0.050 0.40 1.27 6
N28 287
α0o8o0o8o-
Rev. 1, 1/13
Notes:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above
the seating plane, shall not exceed a maximum value of 0.61mm
(0.024 inch)
10. Controlling dimension: MILLIMETER. Converted inch dimensions are
not necessarily exact.
For the most recent package outline drawing, see M28.3.
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