Features * High Performance, Low Power AVR(R) 8-Bit Microcontroller * Advanced RISC Architecture * * * * * * * * - 123 Powerful Instructions - Most Single Clock Cycle Execution - 32 x 8 General Purpose Working Registers - Fully Static Operation Non-volatile Program and Data Memories - 2/4/8K Byte of In-System Programmable Program Memory Flash * Endurance: 10,000 Write/Erase Cycles - 128/256/512 Bytes In-System Programmable EEPROM * Endurance: 100,000 Write/Erase Cycles - 128/256/512 Bytes Internal SRAM - Data retention: 20 years at 85C / 100 years at 25C - Programming Lock for Self-Programming Flash Program & EEPROM Data Security Peripheral Features - 8/16-bit Timer/Counter with Prescaler - 8/10-bit High Speed Timer/Counter with Separate Prescaler * 3 High Frequency PWM Outputs with Separate Output Compare Registers * Programmable Dead Time Generator - 10-bit ADC * 11 Single-Ended Channels * 16 Differential ADC Channel Pairs * 15 Differential ADC Channel Pairs with Programmable Gain (1x, 8x, 20x, 32x) - On-chip Analog Comparator - Programmable Watchdog Timer with Separate On-chip Oscillator - Universal Serial Interface with Start Condition Detector Special Microcontroller Features - debugWIRE On-chip Debug System - In-System Programmable via SPI Port - External and Internal Interrupt Sources - Low Power Idle, ADC Noise Reduction, Standby and Power-Down Modes - Enhanced Power-on Reset Circuit - Programmable Brown-out Detection Circuit - Internal Calibrated Oscillator - On-Chip Temperature Sensor I/O and Packages - 16 Programmable I/O Lines - Available in 20-pin PDIP, 20-pin SOIC and 32-pad MLF Operating Voltage: - 1.8 - 5.5V for ATtiny261V/461V/861V - 2.7 - 5.5V for ATtiny261/461/861 Speed Grade: - ATtiny261V/461V/861V: 0 - 4 MHz @ 1.8 - 5.5V, 0 - 10 MHz @ 2.7 - 5.5V - ATtiny261/461/861: 0 - 10 MHz @ 2.7 - 5.5V, 0 - 20 MHz @ 4.5 - 5.5V Industrial Temperature Range Low Power Consumption - Active Mode (1 MHz System Clock): 300 A @ 1.8V - Power-Down Mode: 0.1A at 1.8V 8-bit Microcontroller with 2/4/8K Bytes In-System Programmable Flash ATtiny261/V ATtiny461/V ATtiny861/V Preliminary Not recommended for new designs. Use: ATtiny261A ATtiny461A ATtiny861A 2588C-AVR-10/09 1. Pin Configurations Figure 1-1. Pinout ATtiny261/461/861 and ATtiny261V/461V/861V PDIP/SOIC 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 PA0 (ADC0/DI/SDA/PCINT0) PA1 (ADC1/DO/PCINT1) PA2 (ADC2/INT1/USCK/SCL/PCINT2) PA3 (AREF/PCINT3) AGND AVCC PA4 (ADC3/ICP0/PCINT4) PA5 (ADC4/AIN2/PCINT5) PA6 (ADC5/AIN0/PCINT6) PA7 (ADC6/AIN1/PCINT7) 32 31 30 29 28 27 26 25 PB2 (SCK/USCK/SCL/OC1B/PCINT10) PB1 (MISO/DO/OC1A/PCINT9) PB0 (MOSI/DI/SDA/OC1A/PCINT8) NC NC NC PA0 (ADC0/DI/SDA/PCINT0) PA1 (ADC1/DO/PCINT1) (MOSI/DI/SDA/OC1A/PCINT8) PB0 (MISO/DO/OC1A/PCINT9) PB1 (SCK/USCK/SCL/OC1B/PCINT10) PB2 (OC1B/PCINT11) PB3 VCC GND (ADC7/OC1D/CLKI/XTAL1/PCINT12) PB4 (ADC8/OC1D/CLKO/XTAL2/PCINT13) PB5 (ADC9/INT0/T0/PCINT14) PB6 (ADC10/RESET/PCINT15) PB7 1 2 3 4 5 6 7 8 QFN/MLF 24 23 22 21 20 19 18 17 NC PA2 (ADC2/INT1/USCK/SCL/PCINT2) PA3 (AREF/PCINT3) AGND NC NC AVCC PA4 (ADC3/ICP0/PCINT4) NC (ADC9/INT0/T0/PCINT14) PB6 (ADC10/RESET/PCINT15) PB7 NC (ADC6/AIN1/PCINT7) PA7 (ADC5/AIN0/PCINT6) PA6 (ADC4/AIN2/PCINT5) PA5 NC 9 10 11 12 13 14 15 16 NC (OC1B/PCINT11) PB3 NC VCC GND NC (ADC7/OC1D/CLKI/XTAL1/PCINT12) PB4 (ADC8/OC1D/CLKO/XTAL2/PCINT13) PB5 Note: 2 To ensure mechanical stability the center pad underneath the QFN/MLF package should be soldered to ground on the board. ATtiny261/461/861 2588C-AVR-10/09 ATtiny261/461/861 1.1 1.1.1 Pin Descriptions VCC Supply voltage. 1.1.2 GND Ground. 1.1.3 AVCC Analog supply voltage. This is the supply voltage pin for the Analog-to-digital Converter (ADC), the analog comparator, the Brown-Out Detector (BOD), the internal voltage reference and Port A. It should be externally connected to VCC, even if some peripherals such as the ADC are not used. If the ADC is used AVCC should be connected to VCC through a low-pass filter. 1.1.4 AGND Analog ground. 1.1.5 Port A (PA7:PA0) An 8-bit, bi-directional I/O port with internal pull-up resistors, individually selectable for each bit. Output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, port pins that are externally pulled low will source current if pull-up resistors have been activated. Port pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port A also serves the functions of various special features of the device, as listed on page 63. 1.1.6 Port B (PB7:PB0) An 8-bit, bi-directional I/O port with internal pull-up resistors, individually selectable for each bit. Output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, port pins that are externally pulled low will source current if pull-up resistors have been activated. Port pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port B also serves the functions of various special features of the device, as listed on page 66. 1.1.7 RESET Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running and provided the reset pin has not been disabled. The minimum pulse length is given in Table 19-4 on page 190. Shorter pulses are not guaranteed to generate a reset. The reset pin can also be used as a (weak) I/O pin. 3 2588C-AVR-10/09 2. Overview ATtiny261/461/861 are low-power CMOS 8-bit microcontrollers based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATtiny261/461/861 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. Block Diagram Block Diagram GND Figure 2-1. VCC 2.1 Watchdog Timer Watchdog Oscillator Oscillator Circuits / Clock Generation Power Supervision POR / BOD & RESET debugWIRE Flash SRAM PROGRAM LOGIC CPU EEPROM AVCC AGND AREF Timer/Counter1 A/D Conv. USI Analog Comp. Internal Bandgap DATABUS Timer/Counter0 3 PORT B (8) 11 PORT A (8) RESET XTAL[1..2] PB[0..7] PA[0..7] The AVR core combines a rich instruction set with 32 general purpose working registers. All 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers. 4 ATtiny261/461/861 2588C-AVR-10/09 ATtiny261/461/861 The ATtiny261/461/861 provides the following features: 2/4/8K byte of In-System Programmable Flash, 128/256/512 bytes EEPROM, 128/256/512 bytes SRAM, 16 general purpose I/O lines, 32 general purpose working registers, an 8-bit Timer/Counter with compare modes, an 8-bit high speed Timer/Counter, a Universal Serial Interface, Internal and External Interrupts, an 11-channel, 10-bit ADC, a programmable Watchdog Timer with internal oscillator, and four software selectable power saving modes. Idle mode stops the CPU while allowing the SRAM, Timer/Counter, ADC, Analog Comparator, and Interrupt system to continue functioning. Powerdown mode saves the register contents, disabling all chip functions until the next Interrupt or Hardware Reset. ADC Noise Reduction mode stops the CPU and all I/O modules except ADC, to minimize switching noise during ADC conversions. In Standby mode, the crystal/resonator oscillator is running while the rest of the device is sleeping, allowing very fast start-up combined with low power consumption. The device is manufactured using Atmel's high density non-volatile memory technology. The On-chip ISP Flash allows the Program memory to be re-programmed In-System through an SPI serial interface, by a conventional non-volatile memory programmer or by an On-chip boot code running on the AVR core. The ATtiny261/461/861 AVR is supported by a full suite of program and system development tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators, and Evaluation kits. 5 2588C-AVR-10/09 3. About 3.1 Resources A comprehensive set of drivers, application notes, data sheets and descriptions on development tools are available for download at http://www.atmel.com/avr. 3.2 Code Examples This documentation contains simple code examples that briefly show how to use various parts of the device. These code examples assume that the part specific header file is included before compilation. Be aware that not all C compiler vendors include bit definitions in the header files and interrupt handling in C is compiler dependent. Please confirm with the C compiler documentation for more details. For I/O Registers located in the extended I/O map, "IN", "OUT", "SBIS", "SBIC", "CBI", and "SBI" instructions must be replaced with instructions that allow access to extended I/O. Typically, this means "LDS" and "STS" combined with "SBRS", "SBRC", "SBR", and "CBR". Note that not all AVR devices include an extended I/O map. 3.3 Data Retention Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20 years at 85C or 100 years at 25C. 3.4 Disclaimer Typical values contained in this data sheet are based on simulations and characterization of other AVR microcontrollers manufactured on the same process technology. Min and Max values will be available after the device is characterized. 6 ATtiny261/461/861 2588C-AVR-10/09 ATtiny261/461/861 4. CPU Core This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts. 4.1 Architectural Overview Figure 4-1. Block Diagram of the AVR Architecture Data Bus 8-bit Flash Program Memory Program Counter Status and Control 32 x 8 General Purpose Registrers Control Lines Direct Addressing Instruction Decoder Indirect Addressing Instruction Register Interrupt Unit Watchdog Timer ALU Analog Comparator I/O Module1 Data SRAM I/O Module 2 I/O Module n EEPROM I/O Lines In order to maximize performance and parallelism, the AVR uses a Harvard architecture - with separate memories and buses for program and data. Instructions in the Program memory are executed with a single level pipelining. While one instruction is being executed, the next instruction is pre-fetched from the Program memory. This concept enables instructions to be executed in every clock cycle. The Program memory is In-System Reprogrammable Flash memory. 7 2588C-AVR-10/09 The fast-access Register File contains 32 x 8-bit general purpose working registers with a single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typical ALU operation, two operands are output from the Register File, the operation is executed, and the result is stored back in the Register File - in one clock cycle. Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing - enabling efficient address calculations. One of the these address pointers can also be used as an address pointer for look up tables in Flash Program memory. These added function registers are the 16-bit X-, Y-, and Z-register, described later in this section. The ALU supports arithmetic and logic operations between registers or between a constant and a register. Single register operations can also be executed in the ALU. After an arithmetic operation, the Status Register is updated to reflect information about the result of the operation. Program flow is provided by conditional and unconditional jump and call instructions, capable of directly addressing the whole address space. Most AVR instructions have a single 16-bit word format but 32-bit wide instructions also exist. The actual instruction set varies, as some devices only implement a part of the instruction set. During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the Stack. The Stack is effectively allocated in the general data SRAM, and consequently the Stack size is only limited by the total SRAM size and the usage of the SRAM. All user programs must initialize the SP in the Reset routine (before subroutines or interrupts are executed). The Stack Pointer (SP) is read/write accessible in the I/O space. The data SRAM can easily be accessed through the five different addressing modes supported in the AVR architecture. The memory spaces in the AVR architecture are all linear and regular memory maps. A flexible interrupt module has its control registers in the I/O space with an additional Global Interrupt Enable bit in the Status Register. All interrupts have a separate Interrupt Vector in the Interrupt Vector table. The interrupts have priority in accordance with their Interrupt Vector position. The lower the Interrupt Vector address, the higher the priority. The I/O memory space contains 64 addresses for CPU peripheral functions as Control Registers, SPI, and other I/O functions. The I/O memory can be accessed directly, or as the Data Space locations following those of the Register File, 0x20 - 0x5F. 4.2 ALU - Arithmetic Logic Unit The high-performance AVR ALU operates in direct connection with all the 32 general purpose working registers. Within a single clock cycle, arithmetic operations between general purpose registers or between a register and an immediate are executed. The ALU operations are divided into three main categories - arithmetic, logical, and bit-functions. Some implementations of the architecture also provide a powerful multiplier supporting both signed/unsigned multiplication and fractional format. See the "Instruction Set" section for a detailed description. 4.3 Status Register The Status Register contains information about the result of the most recently executed arithmetic instruction. This information can be used for altering program flow in order to perform conditional operations. Note that the Status Register is updated after all ALU operations, as specified in the Instruction Set Reference. This will in many cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code. 8 ATtiny261/461/861 2588C-AVR-10/09 ATtiny261/461/861 The Status Register is neither automatically stored when entering an interrupt routine, nor restored when returning from an interrupt. This must be handled by software. 4.3.1 SREG - AVR Status Register Bit 7 6 5 4 3 2 1 0 0x3F (0x5F) I T H S V N Z C Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 SREG * Bit 7 - I: Global Interrupt Enable The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers. If the Global Interrupt Enable Register is cleared, none of the interrupts are enabled independent of the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts. The I-bit can also be set and cleared by the application with the SEI and CLI instructions, as described in the instruction set reference. * Bit 6 - T: Bit Copy Storage The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or destination for the operated bit. A bit from a register in the Register File can be copied into T by the BST instruction, and a bit in T can be copied into a bit in a register in the Register File by the BLD instruction. * Bit 5 - H: Half Carry Flag The Half Carry Flag H indicates a Half Carry in some arithmetic operations. Half Carry is useful in BCD arithmetic. See the "Instruction Set Description" for detailed information. * Bit 4 - S: Sign Bit, S = N V The S-bit is always an exclusive or between the Negative Flag N and the Two's Complement Overflow Flag V. See the "Instruction Set Description" for detailed information. * Bit 3 - V: Two's Complement Overflow Flag The Two's Complement Overflow Flag V supports two's complement arithmetics. See the "Instruction Set Description" for detailed information. * Bit 2 - N: Negative Flag The Negative Flag N indicates a negative result in an arithmetic or logic operation. See the "Instruction Set Description" for detailed information. * Bit 1 - Z: Zero Flag The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the "Instruction Set Description" for detailed information. * Bit 0 - C: Carry Flag The Carry Flag C indicates a carry in an arithmetic or logic operation. See the "Instruction Set Description" for detailed information. 9 2588C-AVR-10/09 4.4 General Purpose Register File The Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve the required performance and flexibility, the following input/output schemes are supported by the Register File: * One 8-bit output operand and one 8-bit result input * Two 8-bit output operands and one 8-bit result input * Two 8-bit output operands and one 16-bit result input * One 16-bit output operand and one 16-bit result input Figure 4-2 below shows the structure of the 32 general purpose working registers in the CPU. Figure 4-2. AVR CPU General Purpose Working Registers 7 0 Addr. R0 0x00 R1 0x01 R2 0x02 ... R13 0x0D General R14 0x0E Purpose R15 0x0F Working R16 0x10 Registers R17 0x11 ... R26 0x1A R27 0x1B X-register Low Byte X-register High Byte R28 0x1C Y-register Low Byte R29 0x1D Y-register High Byte R30 0x1E Z-register Low Byte R31 0x1F Z-register High Byte Most of the instructions operating on the Register File have direct access to all registers, and most of them are single cycle instructions. As shown in Figure 4-2, each register is also assigned a Data memory address, mapping them directly into the first 32 locations of the user Data Space. Although not being physically implemented as SRAM locations, this memory organization provides great flexibility in access of the registers, as the X-, Y- and Z-pointer registers can be set to index any register in the file. 4.4.1 The X-register, Y-register, and Z-register The registers R26:R31 have some added functions to their general purpose usage. These registers are 16-bit address pointers for indirect addressing of the data space. The three indirect address registers X, Y, and Z are defined as described in Figure 4-3. Figure 4-3. The X-, Y-, and Z-registers 15 X-register 7 R27 (0x1B) 10 XH XL 0 7 0 0 R26 (0x1A) ATtiny261/461/861 2588C-AVR-10/09 ATtiny261/461/861 15 YH YL 7 Y-register 0 R29 (0x1D) Z-register 0 7 0 R28 (0x1C) 15 ZH 7 0 ZL 7 R31 (0x1F) 0 0 R30 (0x1E) In different addressing modes these address registers function as automatic increment and automatic decrement (see the instruction set reference for details). 4.5 Stack Pointer The Stack is mainly used for storing temporary data, for storing local variables and for storing return addresses after interrupts and subroutine calls. The Stack Pointer Register always points to the top of the Stack. Note that the Stack is implemented as growing from higher memory locations to lower memory locations. This implies that a Stack PUSH command decreases the Stack Pointer. The Stack Pointer points to the data SRAM Stack area where the Subroutine and Interrupt Stacks are located. This Stack space in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts are enabled. The Stack Pointer must be set to point above 0x60. The Stack Pointer is decremented by one when data is pushed onto the Stack with the PUSH instruction, and it is decremented by two when the return address is pushed onto the Stack with subroutine call or interrupt. The Stack Pointer is incremented by one when data is popped from the Stack with the POP instruction, and it is incremented by two when data is popped from the Stack with return from subroutine RET or return from interrupt RETI. The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of bits actually used is implementation dependent. Note that the data space in some implementations of the AVR architecture is so small that only SPL is needed. In this case, the SPH Register will not be present 4.5.1 SPH and SPL -- Stack Pointer Register Bit 15 14 13 12 11 10 9 8 0x3E (0x5E) SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SPH 0x3D (0x5D) SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 SPL 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Read/Write Initial Value 4.6 RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND Instruction Execution Timing This section describes the general access timing concepts for instruction execution. The AVR CPU is driven by the CPU clock clkCPU, directly generated from the selected clock source for the chip. No internal clock division is used. Figure 4-4 shows the parallel instruction fetches and instruction executions enabled by the Harvard architecture and the fast access Register File concept. This is the basic pipelining concept to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost, functions per clocks, and functions per power-unit. 11 2588C-AVR-10/09 Figure 4-4. The Parallel Instruction Fetches and Instruction Executions T1 T2 T3 T4 clkCPU 1st Instruction Fetch 1st Instruction Execute 2nd Instruction Fetch 2nd Instruction Execute 3rd Instruction Fetch 3rd Instruction Execute 4th Instruction Fetch Figure 4-5 shows the internal timing concept for the Register File. In a single clock cycle an ALU operation using two register operands is executed, and the result is stored back to the destination register. Figure 4-5. Single Cycle ALU Operation T1 T2 T3 T4 clkCPU Total Execution Time Register Operands Fetch ALU Operation Execute Result Write Back 4.7 Reset and Interrupt Handling The AVR provides several different interrupt sources. These interrupts and the separate Reset Vector each have a separate Program Vector in the Program memory space. All interrupts are assigned individual enable bits which must be written logic one together with the Global Interrupt Enable bit in the Status Register in order to enable the interrupt. The lowest addresses in the Program memory space are by default defined as the Reset and Interrupt Vectors. The complete list of vectors is shown in "Interrupts" on page 50. The list also determines the priority levels of the different interrupts. The lower the address the higher is the priority level. RESET has the highest priority, and next is INT0 - the External Interrupt Request 0. When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are disabled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then interrupt the current interrupt routine. The I-bit is automatically set when a Return from Interrupt instruction - RETI - is executed. There are basically two types of interrupts. The first type is triggered by an event that sets the Interrupt Flag. For these interrupts, the Program Counter is vectored to the actual Interrupt Vector in order to execute the interrupt handling routine, and hardware clears the corresponding Interrupt Flag. Interrupt Flags can also be cleared by writing a logic one to the flag bit position(s) 12 ATtiny261/461/861 2588C-AVR-10/09 ATtiny261/461/861 to be cleared. If an interrupt condition occurs while the corresponding interrupt enable bit is cleared, the Interrupt Flag will be set and remembered until the interrupt is enabled, or the flag is cleared by software. Similarly, if one or more interrupt conditions occur while the Global Interrupt Enable bit is cleared, the corresponding Interrupt Flag(s) will be set and remembered until the Global Interrupt Enable bit is set, and will then be executed by order of priority. The second type of interrupts will trigger as long as the interrupt condition is present. These interrupts do not necessarily have Interrupt Flags. If the interrupt condition disappears before the interrupt is enabled, the interrupt will not be triggered. When the AVR exits from an interrupt, it will always return to the main program and execute one more instruction before any pending interrupt is served. Note that the Status Register is not automatically stored when entering an interrupt routine, nor restored when returning from an interrupt routine. This must be handled by software. When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled. No interrupt will be executed after the CLI instruction, even if it occurs simultaneously with the CLI instruction. The following example shows how this can be used to avoid interrupts during the timed EEPROM write sequence. Assembly Code Example in r16, SREG cli ; store SREG value ; disable interrupts during timed sequence sbi EECR, EEMPE ; start EEPROM write sbi EECR, EEPE out SREG, r16 ; restore SREG value (I-bit) C Code Example char cSREG; cSREG = SREG; /* store SREG value */ /* disable interrupts during timed sequence */ _CLI(); EECR |= (1< ... ... ; Enable interrupts External Interrupts The External Interrupts are triggered by the INT0 or INT1 pin or any of the PCINT15:0 pins. Observe that, if enabled, the interrupts will trigger even if the INT0, INT1 or PCINT15:0 pins are configured as outputs. This feature provides a way of generating a software interrupt. Pin change interrupts PCI will trigger if any enabled PCINT15:0 pin toggles. The PCMSK Register control which pins contribute to the pin change interrupts. Pin change interrupts on PCINT15:0 are detected asynchronously. This implies that these interrupts can be used for waking the part also from sleep modes other than Idle mode. The INT0 and INT1 interrupts can be triggered by a falling or rising edge or a low level. This is set up as indicated in the specification for the MCU Control Register - MCUCR. When the INT0 interrupt is enabled and is configured as level triggered, the interrupt will trigger as long as the pin is held low. Note that recognition of falling or rising edge interrupts on INT0 or INT1 requires the presence of an I/O clock, described in "Clock Subsystems" on page 24. 9.2.1 Low Level Interrupt A low level interrupt on INT0 is detected asynchronously. This means that the interrupt source can be used for waking the part also from sleep modes other than Idle (the I/O clock is halted in all sleep modes except Idle). Note that if a level triggered interrupt is used for wake-up from Power-down, the required level must be held long enough for the MCU to complete the wake-up to trigger the level interrupt. If the level disappears before the end of the Start-up Time, the MCU will still wake up, but no inter- 51 2588C-AVR-10/09 rupt will be generated. The start-up time is defined by the SUT and CKSEL Fuses as described in "Clock System" on page 24. If the low level on the interrupt pin is removed before the device has woken up then program execution will not be diverted to the interrupt service routine but continue from the instruction following the SLEEP command. 9.3 9.3.1 Register Description MCUCR - MCU Control Register The MCU Register contains control bits for interrupt sense control. Bit 7 6 5 4 3 2 1 0 0x35 (0x55) - PUD SE SM1 SM0 - ISC01 ISC00 Read/Write R R/W R/W R/W R/W R R/W R/W Initial Value 0 0 0 0 0 0 0 0 MCUCR * Bits 1, 0 - ISC01, ISC00: Interrupt Sense Control 0 Bit 1 and Bit 0 The External Interrupt 0 is activated by the external pin INT0 or INT1 if the SREG I-flag and the corresponding interrupt mask are set. The level and edges on the external INT0 or INT1 pin that activate the interrupt are defined in Table 9-2. The value on the INT0 or INT1 pin is sampled before detecting edges. If edge or toggle interrupt is selected, pulses that last longer than one clock period will generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If low level interrupt is selected, the low level must be held until the completion of the currently executing instruction to generate an interrupt. Table 9-2. 9.3.2 Interrupt 0 Sense Control ISC01 ISC00 Description 0 0 The low level of INT0 or INT1 generates an interrupt request. 0 1 Any logical change on INT0 or INT1 generates an interrupt request. 1 0 The falling edge of INT0 or INT1 generates an interrupt request. 1 1 The rising edge of INT0 or INT1 generates an interrupt request. GIMSK - General Interrupt Mask Register Bit 7 6 5 4 3 2 1 0x3B (0x5B) INT1 INT0 PCIE1 PCIE0 - - - 0 - Read/Write R/W R/W R/W R/w R R R R Initial Value 0 0 0 0 0 0 0 0 GIMSK * Bit 7 - INT1: External Interrupt Request 1 Enable When the INT1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is enabled. The Interrupt Sense Control0 bits 1/0 (ISC01 and ISC00) in the MCU Control Register (MCUCR) define whether the external interrupt is activated on rising and/or falling edge of the INT1 pin or level sensed. Activity on the pin will cause an interrupt request even if INT1 is configured as an output. The corresponding interrupt of External Interrupt Request 1 is executed from the INT1 Interrupt Vector. * Bit 6 - INT0: External Interrupt Request 0 Enable When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is enabled. The Interrupt Sense Control0 bits 1/0 (ISC01 and ISC00) in the MCU 52 ATtiny261/461/861 2588C-AVR-10/09 ATtiny261/461/861 Control Register (MCUCR) define whether the external interrupt is activated on rising and/or falling edge of the INT0 pin or level sensed. Activity on the pin will cause an interrupt request even if INT0 is configured as an output. The corresponding interrupt of External Interrupt Request 0 is executed from the INT0 Interrupt Vector. * Bit 5 - PCIE1: Pin Change Interrupt Enable When the PCIE1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin change interrupt is enabled. Any change on any enabled PCINT7:0 or PCINT15:12 pin will cause an interrupt. The corresponding interrupt of Pin Change Interrupt Request is executed from the PCI Interrupt Vector. PCINT7:0 and PCINT15:12 pins are enabled individually by the PCMSK0 and PCMSK1 Register. * Bit 4 - PCIE0: Pin Change Interrupt Enable When the PCIE0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin change interrupt is enabled. Any change on any enabled PCINT11:8 pin will cause an interrupt. The corresponding interrupt of Pin Change Interrupt Request is executed from the PCI Interrupt Vector. PCINT11:8 pins are enabled individually by the PCMSK1 Register. * Bits 3:0 - Res: Reserved Bits These bits are reserved and will always read as zero. 9.3.3 GIFR - General Interrupt Flag Register Bit 7 6 5 4 3 2 1 0x3A (0x5A) INT1 INTF0 PCIF - - - - 0 - Read/Write R/W R/W R/W R R R R R Initial Value 0 0 0 0 0 0 0 0 GIFR * Bit 7- INTF1: External Interrupt Flag 1 When an edge or logic change on the INT1 pin triggers an interrupt request, INTF1 becomes set (one). If the I-bit in SREG and the INT1 bit in GIMSK are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it. This flag is always cleared when INT1 is configured as a level interrupt. * Bit 6 - INTF0: External Interrupt Flag 0 When an edge or logic change on the INT0 pin triggers an interrupt request, INTF0 becomes set (one). If the I-bit in SREG and the INT0 bit in GIMSK are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it. This flag is always cleared when INT0 is configured as a level interrupt. * Bit 5 - PCIF: Pin Change Interrupt Flag When a logic change on any PCINT15 pin triggers an interrupt request, PCIF becomes set (one). If the I-bit in SREG and the PCIE bit in GIMSK are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it. * Bits 4:0 - Res: Reserved Bits These bits are reserved and will always read as zero. 53 2588C-AVR-10/09 9.3.4 PCMSK0 - Pin Change Mask Register A Bit 7 6 5 4 3 2 1 0x23 (0x43) PCINT7 PCINT6 PCINT5 PCINT4 PCINT3 PCINT2 PCINT1 0 PCINT0 Read/Write R/W R/W R/W R/w R/W R/W R/W R/W Initial Value 1 1 0 0 1 0 0 0 PCMSK0 * Bits 7:0 - PCINT7:0: Pin Change Enable Mask 7:0 Each PCINT7:0 bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT7:0 is set and the PCIE1 bit in GIMSK is set, pin change interrupt is enabled on the corresponding I/O pin. If PCINT7:0 is cleared, pin change interrupt on the corresponding I/O pin is disabled. 9.3.5 PCMSK1 - Pin Change Mask Register B Bit 7 6 5 4 3 2 1 0x22 (0x42) PCINT15 PCINT14 PCINT13 PCINT12 PCINT11 PCINT10 PCINT9 0 PCINT8 Read/Write R/W R/W R/W R/w R/W R/W R/W R/W Initial Value 1 1 1 1 1 1 1 1 PCMSK1 * Bits 7:0 - PCINT15:8: Pin Change Enable Mask 15:8 Each PCINT15:8 bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT11:8 is set and the PCIE0 bit in GIMSK is set, pin change interrupt is enabled on the corresponding I/O pin, and if PCINT15:12 is set and the PCIE1 bit in GIMSK is set, pin change interrupt is enabled on the corresponding I/O pin. If PCINT15:8 is cleared, pin change interrupt on the corresponding I/O pin is disabled. 54 ATtiny261/461/861 2588C-AVR-10/09 ATtiny261/461/861 10. I/O Ports All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with the SBI and CBI instructions. The same applies when changing drive value (if configured as output) or enabling/disabling of pull-up resistors (if configured as input). Each output buffer has symmetrical drive characteristics with both high sink and source capability. The pin driver is strong enough to drive LED displays directly. All port pins have individually selectable pull-up resistors with a supply-voltage invariant resistance. All I/O pins have protection diodes to both VCC and Ground as indicated in Figure 10-1. See "Electrical Characteristics" on page 187 for a complete list of parameters. Figure 10-1. I/O Pin Equivalent Schematic RPU Logic Pxn CPIN See Figure "General Digital I/O" for Details All registers and bit references in this section are written in general form. A lower case "x" represents the numbering letter for the port, and a lower case "n" represents the bit number. However, when using the register or bit defines in a program, the precise form must be used. For example, PORTB3 for bit no. 3 in Port B, here documented generally as PORTxn. The physical I/O Registers and bit locations are listed in "Register Description" on page 69. Three I/O memory address locations are allocated for each port, one each for the Data Register - PORTx, Data Direction Register - DDRx, and the Port Input Pins - PINx. The Port Input Pins I/O location is read only, while the Data Register and the Data Direction Register are read/write. However, writing a logic one to a bit in the PINx Register, will result in a toggle in the corresponding bit in the Data Register. In addition, the Pull-up Disable - PUD bit in MCUCR disables the pull-up function for all pins in all ports when set. Using the I/O port as General Digital I/O is described in "Ports as General Digital I/O" on page 56. Most port pins are multiplexed with alternate functions for the peripheral features on the device. How each alternate function interferes with the port pin is described in "Alternate Port Functions" on page 60. Refer to the individual module sections for a full description of the alternate functions. Note that enabling the alternate function of some of the port pins does not affect the use of the other pins in the port as general digital I/O. 55 2588C-AVR-10/09 10.1 Ports as General Digital I/O The ports are bi-directional I/O ports with optional internal pull-ups. Figure 10-2 shows a functional description of one I/O-port pin, here generically called Pxn. Figure 10-2. General Digital I/O(1) PUD Q D DDxn Q CLR WDx RESET DATA BUS RDx 1 Q Pxn D 0 PORTxn Q CLR RESET WRx WPx RRx SLEEP SYNCHRONIZER D Q L Q D RPx Q PINxn Q clk I/O PUD: SLEEP: clkI/O: Note: 10.1.1 PULLUP DISABLE SLEEP CONTROL I/O CLOCK WDx: RDx: WRx: RRx: RPx: WPx: WRITE DDRx READ DDRx WRITE PORTx READ PORTx REGISTER READ PORTx PIN WRITE PINx REGISTER 1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clkI/O, SLEEP, and PUD are common to all ports. Configuring the Pin Each port pin consists of three register bits: DDxn, PORTxn, and PINxn. As shown in "Register Description" on page 69, the DDxn bits are accessed at the DDRx I/O address, the PORTxn bits at the PORTx I/O address, and the PINxn bits at the PINx I/O address. The DDxn bit in the DDRx Register selects the direction of this pin. If DDxn is written logic one, Pxn is configured as an output pin. If DDxn is written logic zero, Pxn is configured as an input pin. If PORTxn is written logic one when the pin is configured as an input pin, the pull-up resistor is activated. To switch the pull-up resistor off, PORTxn has to be written logic zero or the pin has to 56 ATtiny261/461/861 2588C-AVR-10/09 ATtiny261/461/861 be configured as an output pin. The port pins are tri-stated when reset condition becomes active, even if no clocks are running. If PORTxn is written logic one when the pin is configured as an output pin, the port pin is driven high (one). If PORTxn is written logic zero when the pin is configured as an output pin, the port pin is driven low (zero). The pull-up resistor is activated, if the PUExn is written logic one. To switch the pull-up resistor off, PUExn has to be written logic zero. 10.1.2 Toggling the Pin Writing a logic one to PINxn toggles the value of PORTxn, independent on the value of DDRxn. Note that the SBI instruction can be used to toggle one single bit in a port. 10.1.3 Switching Between Input and Output When switching between tri-state ({DDxn, PORTxn} = 0b00) and output high ({DDxn, PORTxn} = 0b11), an intermediate state with either pull-up enabled {DDxn, PORTxn} = 0b01) or output low ({DDxn, PORTxn} = 0b10) must occur. Normally, the pull-up enabled state is fully acceptable, as a high-impedant environment will not notice the difference between a strong high driver and a pull-up. If this is not the case, the PUD bit in the MCUCR Register can be set to disable all pull-ups in all ports. Switching between input with pull-up and output low generates the same problem. The user must use either the tri-state ({DDxn, PORTxn} = 0b00) or the output high state ({DDxn, PORTxn} = 0b10) as an intermediate step. Table 10-1 summarizes the control signals for the pin value. Table 10-1. 10.1.4 Port Pin Configurations DDxn PORTxn PUD (in MCUCR) I/O Pull-up 0 0 X Input No Tri-state (Hi-Z) 0 1 0 Input Yes Pxn will source current if ext. pulled low 0 1 1 Input No Tri-state (Hi-Z) 1 0 X Output No Output Low (Sink) 1 1 X Output No Output High (Source) Comment Reading the Pin Value Independent of the setting of Data Direction bit DDxn, the port pin can be read through the PINxn Register bit. As shown in Figure 10-2, the PINxn Register bit and the preceding latch constitute a synchronizer. This is needed to avoid metastability if the physical pin changes value near the edge of the internal clock, but it also introduces a delay. Figure 10-3 shows a timing diagram of the synchronization when reading an externally applied pin value. The maximum and minimum propagation delays are denoted tpd,max and tpd,min respectively. 57 2588C-AVR-10/09 Figure 10-3. Synchronization when Reading an Externally Applied Pin value SYSTEM CLK INSTRUCTIONS XXX XXX in r17, PINx SYNC LATCH PINxn r17 0x00 0xFF t pd, max t pd, min Consider the clock period starting shortly after the first falling edge of the system clock. The latch is closed when the clock is low, and goes transparent when the clock is high, as indicated by the shaded region of the "SYNC LATCH" signal. The signal value is latched when the system clock goes low. It is clocked into the PINxn Register at the succeeding positive clock edge. As indicated by the two arrows tpd,max and tpd,min, a single signal transition on the pin will be delayed between 1/2 and 11/2 system clock period depending upon the time of assertion. When reading back a software assigned pin value, a nop instruction must be inserted as indicated in Figure 10-4. The out instruction sets the "SYNC LATCH" signal at the positive edge of the clock. In this case, the delay tpd through the synchronizer is one system clock period. Figure 10-4. Synchronization when Reading a Software Assigned Pin Value SYSTEM CLK r16 INSTRUCTIONS 0xFF out PORTx, r16 nop in r17, PINx SYNC LATCH PINxn r17 0x00 0xFF t pd 58 ATtiny261/461/861 2588C-AVR-10/09 ATtiny261/461/861 10.1.5 Digital Input Enable and Sleep Modes As shown in Figure 10-2, the digital input signal can be clamped to ground at the input of the schmitt-trigger. The signal denoted SLEEP in the figure, is set by the MCU Sleep Controller in Power-down mode, Power-save mode, and Standby mode to avoid high power consumption if some input signals are left floating, or have an analog signal level close to VCC/2. SLEEP is overridden for port pins enabled as external interrupt pins. If the external interrupt request is not enabled, SLEEP is active also for these pins. SLEEP is also overridden by various other alternate functions as described in "Alternate Port Functions" on page 60. If a logic high level ("one") is present on an asynchronous external interrupt pin configured as "Interrupt on Rising Edge, Falling Edge, or Any Logic Change on Pin" while the external interrupt is not enabled, the corresponding External Interrupt Flag will be set when resuming from the above mentioned Sleep mode, as the clamping in these sleep mode produces the requested logic change. 10.1.6 Unconnected Pins If some pins are unused, it is recommended to ensure that these pins have a defined level. Even though most of the digital inputs are disabled in the deep sleep modes as described above, floating inputs should be avoided to reduce current consumption in all other modes where the digital inputs are enabled (Reset, Active mode and Idle mode). The simplest method to ensure a defined level of an unused pin, is to enable the internal pull-up. In this case, the pull-up will be disabled during reset. If low power consumption during reset is important, it is recommended to use an external pull-up or pulldown. Connecting unused pins directly to VCC or GND is not recommended, since this may cause excessive currents if the pin is accidentally configured as an output. 10.1.7 Program Examples The following code examples show how to set port B pins 0 and 1 high, 2 and 3 low, and define the port pins from 4 to 5 as input with a pull-up assigned to port pin 4. The resulting pin values are read back again, but as previously discussed, a nop instruction is included to be able to read back the value recently assigned to some of the pins. Assembly Code Example ... ; Define pull-ups and set outputs high ; Define directions for port pins ldi r16,(1< CSn2:0 > 1). The number of system clock cycles from when the timer is enabled to the first count occurs can be from 1 to N+1 system clock cycles, where N equals the prescaler divisor (8, 64, 256, or 1024). It is possible to use the Prescaler Reset for synchronizing the Timer/Counter to program execution. External Clock Source An external clock source applied to the T0 pin can be used as Timer/Counter clock (clkT0). The T0 pin is sampled once every system clock cycle by the pin synchronization logic. The synchronized (sampled) signal is then passed through the edge detector. Figure 11-3 shows a functional equivalent block diagram of the T0 synchronization and edge detector logic. The registers are clocked at the positive edge of the internal system clock (clkI/O). The latch is transparent in the high period of the internal system clock. The edge detector generates one clkT0 pulse for each positive (CSn2:0 = 7) or negative (CSn2:0 = 6) edge it detects. See Table 11-4 on page 85 for details. 73 2588C-AVR-10/09 Figure 11-3. T0 Pin Sampling D Tn Q D Q D Tn_sync (To Clock Select Logic) Q LE clk I/O Synchronization Edge Detector The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system clock cycles from an edge has been applied to the T0 pin to the counter is updated. Enabling and disabling of the clock input must be done when T0 has been stable for at least one system clock cycle, otherwise it is a risk that a false Timer/Counter clock pulse is generated. Each half period of the external clock applied must be longer than one system clock cycle to ensure correct sampling. The external clock must be guaranteed to have less than half the system clock frequency (fExtClk < fclk_I/O/2) given a 50/50% duty cycle. Since the edge detector uses sampling, the maximum frequency of an external clock it can detect is half the sampling frequency (Nyquist sampling theorem). However, due to variation of the system clock frequency and duty cycle caused by Oscillator source (crystal, resonator, and capacitors) tolerances, it is recommended that maximum frequency of an external clock source is less than fclk_I/O/2.5. An external clock source can not be prescaled. 11.4 Counter Unit The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. Figure 11-4 shows a block diagram of the counter and its surroundings. Table 11-2. Counter Unit Block Diagram TOVn (Int.Req.) DATA BUS Clock Select count TCNTn Control Logic clkTn Edge Detector Tn ( From Prescaler ) top Signal description (internal signals): count clkTn top Increment or decrement TCNT0 by 1. Timer/Counter clock, referred to as clkT0 in the following. Signalize that TCNT0 has reached maximum value. The counter is incremented at each timer clock (clkT0) until it passes its TOP value and then restarts from BOTTOM. The counting sequence is determined by the setting of the CTC0 bit located in the Timer/Counter Control Register (TCCR0A). For more details about counting sequences, see "Modes of Operation" on page 77. clkT0 can be generated from an external or 74 ATtiny261/461/861 2588C-AVR-10/09 ATtiny261/461/861 internal clock source, selected by the Clock Select bits (CS02:0). When no clock source is selected (CS02:0 = 0) the timer is stopped. However, the TCNT0 value can be accessed by the CPU, regardless of whether clkT0 is present or not. A CPU write overrides (has priority over) all counter clear or count operations. The Timer/Counter Overflow Flag (TOV0) is set when the counter reaches the maximum value and it can be used for generating a CPU interrupt. 11.5 Input Capture Unit The Timer/Counter incorporates an Input Capture unit that can capture external events and give them a time-stamp indicating time of occurrence. The external signal indicating an event, or multiple events, can be applied via the ICP0 pin or alternatively, via the analog-comparator unit. The time-stamps can then be used to calculate frequency, duty-cycle, and other features of the signal applied. Alternatively the time-stamps can be used for creating a log of the events. The Input Capture unit is illustrated by the block diagram shown in Figure 11-4. The elements of the block diagram that are not directly a part of the Input Capture unit are gray shaded. Figure 11-4. Input Capture Unit Block Diagram DATA BUS (8-bit) TEMP (8-bit) OCR0B (8-bit) WRITE TCNT0H (8-bit) ICR0 (16-bit Register) ACO* Analog Comparator ICP0 OCR0A (8-bit) ACIC0* TCNT0L (8-bit) TCNT0 (16-bit Counter) ICNC0 ICES0 Noise Canceler Edge Detector ICF0 (Int.Req.) The Output Compare Register OCR0A is a dual-purpose register that is also used as an 8-bit Input Capture Register ICR0. In 16-bit Input Capture mode the Output Compare Register OCR0B serves as the high byte of the Input Capture Register ICR0. In 8-bit Input Capture mode the Output Compare Register OCR0B is free to be used as a normal Output Compare Register, but in 16-bit Input Capture mode the Output Compare Unit cannot be used as there are no free Output Compare Register(s). Even though the Input Capture register is called ICR0 in this section, it is refering to the Output Compare Register(s). When a change of the logic level (an event) occurs on the Input Capture pin (ICP0), alternatively on the Analog Comparator output (ACO), and this change confirms to the setting of the edge detector, a capture will be triggered. When a capture is triggered, the value of the counter (TCNT0) is written to the Input Capture Register (ICR0). The Input Capture Flag (ICF0) is set at 75 2588C-AVR-10/09 the same system clock as the TCNT0 value is copied into Input Capture Register. If enabled (TICIE0=1), the Input Capture Flag generates an Input Capture interrupt. The ICF0 flag is automatically cleared when the interrupt is executed. Alternatively the ICF0 flag can be cleared by software by writing a logical one to its I/O bit location. 11.5.1 Input Capture Trigger Source The default trigger source for the Input Capture unit is the Input Capture pin (ICP0). Timer/Counter0 can alternatively use the Analog Comparator output as trigger source for the Input Capture unit. The Analog Comparator is selected as trigger source by setting the Analog Comparator Input Capture Enable (ACIC0) bit in the Timer/Counter Control Register A (TCCR0A). Be aware that changing trigger source can trigger a capture. The Input Capture Flag must therefore be cleared after the change. Both the Input Capture pin (ICP0) and the Analog Comparator output (ACO) inputs are sampled using the same technique as for the T0 pin (Figure 11-4 on page 85). The edge detector is also identical. However, when the noise canceler is enabled, additional logic is inserted before the edge detector, which increases the delay by four system clock cycles. An Input Capture can also be triggered by software by controlling the port of the ICP0 pin. 11.5.2 Noise Canceler The noise canceler improves noise immunity by using a simple digital filtering scheme. The noise canceler input is monitored over four samples, and all four must be equal for changing the output that in turn is used by the edge detector. The noise canceler is enabled by setting the Input Capture Noise Canceler (ICNC0) bit in Timer/Counter Control Register B (TCCR0B). When enabled the noise canceler introduces additional four system clock cycles of delay from a change applied to the input, to the update of the ICR0 Register. The noise canceler uses the system clock and is therefore not affected by the prescaler. 11.5.3 Using the Input Capture Unit The main challenge when using the Input Capture unit is to assign enough processor capacity for handling the incoming events. The time between two events is critical. If the processor has not read the captured value in the ICR0 Register before the next event occurs, the ICR0 will be overwritten with a new value. In this case the result of the capture will be incorrect. When using the Input Capture interrupt, the ICR0 Register should be read as early in the interrupt handler routine as possible. The maximum interrupt response time is dependent on the maximum number of clock cycles it takes to handle any of the other interrupt requests. Measurement of an external signal's duty cycle requires that the trigger edge is changed after each capture. Changing the edge sensing must be done as early as possible after the ICR0 Register has been read. After a change of the edge, the Input Capture Flag (ICF0) must be cleared by software (writing a logical one to the I/O bit location). For measuring frequency only, the trigger edge change is not required (if an interrupt handler is used). 11.6 Output Compare Unit The comparator continuously compares Timer/Counter (TCNT0) with the Output Compare Registers (OCR0A and OCR0B), and whenever the Timer/Counter equals to the Output Compare Regisers, the comparator signals a match. A match will set the Output Compare Flag at the next timer clock cycle. In 8-bit mode the match can set either the Output Compare Flag OCF0A or 76 ATtiny261/461/861 2588C-AVR-10/09 ATtiny261/461/861 OCF0B, but in 16-bit mode the match can set only the Output Compare Flag OCF0A as there is only one Output Compare Unit. If the corresponding interrupt is enabled, the Output Compare Flag generates an Output Compare interrupt. The Output Compare Flag is automatically cleared when the interrupt is executed. Alternatively, the flag can be cleared by software by writing a logical one to its I/O bit location. Figure 11-5 shows a block diagram of the Output Compare unit. Figure 11-5. Output Compare Unit, Block Diagram DATA BUS TCNTn OCRnx = (8/16-bit Comparator ) OCFnx (Int.Req.) 11.6.1 Compare Match Blocking by TCNT0 Write All CPU write operations to the TCNT0H/L Register will block any Compare Match that occur in the next timer clock cycle, even when the timer is stopped. This feature allows OCR0A/B to be initialized to the same value as TCNT0 without triggering an interrupt when the Timer/Counter clock is enabled. 11.6.2 Using the Output Compare Unit Since writing TCNT0H/L will block all Compare Matches for one timer clock cycle, there are risks involved when changing TCNT0H/L when using the Output Compare Unit, independently of whether the Timer/Counter is running or not. If the value written to TCNT0H/L equals the OCR0A/B value, the Compare Match will be missed. 11.7 Modes of Operation The mode of operation, i.e., the behavior of the Timer/Counter and the Output Compare pins, is defined by the Timer/Counter Width (TCW0), Input Capture Enable (ICEN0) and Wave Generation Mode (CTC0) bits. See "TCCR0A - Timer/Counter0 Control Register A" on page 84. Table 11-3 summarises the different modes of operation. Table 11-3. Modes of operation Mode ICEN0 TCW0 CTC0 Mode of Operation TOP Update of OCRx at TOV Flag Set on 0 0 0 0 Normal, 8-bit Mode 0xFF Immediate MAX (0xFF) 1 0 0 1 CTC Mode, 8-bit OCR0A Immediate MAX (0xFF) 2 0 1 X Normal, 16-bit Mode 0xFFFF Immediate MAX (0xFFFF) 3 1 0 X Input Capture Mode, 8-bit 0xFF Immediate MAX (0xFF) 4 1 1 X Input Capture Mode, 16-bit 0xFFFF Immediate MAX (0xFFFF) 77 2588C-AVR-10/09 11.7.1 Normal, 8-bit Mode In Normal 8-bit mode (see Table 11-3), the counter (TCNT0L) is incrementing until it overruns when it passes its maximum 8-bit value (MAX = 0xFF) and then restarts from the bottom (0x00). The Overflow Flag (TOV0) is set in the same timer clock cycle as when TCNT0L becomes zero. The TOV0 Flag in this case behaves like a ninth bit, except that it is only set, not cleared. However, combined with the timer overflow interrupt that automatically clears the TOV0 Flag, the timer resolution can be increased by software. There are no special cases to consider in the Normal 8-bit mode, a new counter value can be written anytime. The Output Compare Unit can be used to generate interrupts at some given time. 11.7.2 Clear Timer on Compare Match (CTC) 8-bit Mode In Clear Timer on Compare or CTC mode, see Table 11-3 on page 77, the OCR0A Register is used to manipulate the counter resolution. In CTC mode the counter is cleared to zero when the counter value (TCNT0) matches the OCR0A. The OCR0A defines the top value for the counter, hence also its resolution. This mode allows greater control of the Compare Match output frequency. It also simplifies the operation of counting external events. The timing diagram for the CTC mode is shown in Figure 11-6. The counter value (TCNT0) increases until a Compare Match occurs between TCNT0 and OCR0A, and then counter (TCNT0) is cleared. Figure 11-6. CTC Mode, Timing Diagram OCnx Interrupt Flag Set TCNTn Period 1 2 3 4 An interrupt can be generated each time the counter value reaches the TOP value by using the OCF0A Flag. If the interrupt is enabled, the interrupt handler routine can be used for updating the TOP value. However, changing TOP to a value close to BOTTOM when the counter is running with none or a low prescaler value must be done with care since the CTC mode does not have the double buffering feature. If the new value written to OCR0A is lower than the current value of TCNT0, the counter will miss the Compare Match. The counter will then have to count to its maximum value (0xFF) and wrap around starting at 0x00 before the Compare Match can occur. As for the Normal mode of operation, the TOV0 Flag is set in the same timer clock cycle that the counter counts from MAX to 0x00. 11.7.3 78 Normal, 16-bit Mode In 16-bit mode, see Table 11-3 on page 77, the counter (TCNT0H/L) is a incrementing until it overruns when it passes its maximum 16-bit value (MAX = 0xFFFF) and then restarts from the bottom (0x0000). The Overflow Flag (TOV0) will be set in the same timer clock cycle as the TCNT0H/L becomes zero. The TOV0 Flag in this case behaves like a 17th bit, except that it is only set, not cleared. However, combined with the timer overflow interrupt that automatically clears the TOV0 Flag, the timer resolution can be increased by software. There are no special ATtiny261/461/861 2588C-AVR-10/09 ATtiny261/461/861 cases to consider in the Normal mode, a new counter value can be written anytime. The Output Compare Unit can be used to generate interrupts at some given time. 11.7.4 8-bit Input Capture Mode The Timer/Counter0 can also be used in an 8-bit Input Capture mode, see Table 11-3 on page 77 for bit settings. For full description, see the section "Input Capture Unit" on page 75. 11.7.5 16-bit Input Capture Mode The Timer/Counter0 can also be used in a 16-bit Input Capture mode, see Table 11-3 on page 77 for bit settings. For full description, see the section "Input Capture Unit" on page 75. 11.8 Timer/Counter Timing Diagrams The Timer/Counter is a synchronous design and the timer clock (clkT0) is therefore shown as a clock enable signal in the following figures. The figures include information on when Interrupt Flags are set. Figure 11-7 contains timing data for basic Timer/Counter operation. The figure shows the count sequence close to the MAX value. Figure 11-7. Timer/Counter Timing Diagram, no Prescaling clkI/O clkTn (clkI/O /1) TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1 TOVn Figure 11-8 shows the same timing data, but with the prescaler enabled. Figure 11-8. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O /8) TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1 TOVn Figure 11-9 on page 80 shows the setting of OCF0A and OCF0B in Normal mode. 79 2588C-AVR-10/09 Figure 11-9. Timer/Counter Timing Diagram, Setting of OCF0x, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O /8) TCNTn OCRnx - 1 OCRnx OCRnx OCRnx + 1 OCRnx + 2 OCRnx Value OCFnx Figure 11-10 shows the setting of OCF0A and the clearing of TCNT0 in CTC mode. Figure 11-10. Timer/Counter Timing Diagram, CTC mode, with Prescaler (fclk_I/O/8) clkPCK clkTn (clkPCK /8) TCNTn (CTC) TOP - 1 OCRnx TOP BOTTOM BOTTOM + 1 TOP OCFnx 11.9 Accessing Registers in 16-bit Mode In 16-bit mode (the TCW0 bit is set to one) the TCNT0H/L and OCR0A/B or TCNT0L/H and OCR0B/A are 16-bit registers that can be accessed by the AVR CPU via the 8-bit data bus. The 16-bit register must be byte accessed using two read or write operations. The 16-bit Timer/Counter has a single 8-bit register for temporary storing of the high byte of the 16-bit access. The same temporary register is shared between all 16-bit registers. Accessing the low byte triggers the 16-bit read or write operation. When the low byte of a 16-bit register is written by the CPU, the high byte stored in the temporary register, and the low byte written are both copied into the 16-bit register in the same clock cycle. When the low byte of a 16-bit register is read by the CPU, the high byte of the 16-bit register is copied into the temporary register in the same clock cycle as the low byte is read. There is one exception in the temporary register usage. In the Output Compare mode the 16-bit Output Compare Register OCR0A/B is read without the temporary register, because the Output Compare Register contains a fixed value that is only changed by CPU access. However, in 16bit Input Capture mode the ICR0 register formed by the OCR0A and OCR0B registers must be accessed with the temporary register. To do a 16-bit write, the high byte must be written before the low byte. For a 16-bit read, the low byte must be read before the high byte. 80 ATtiny261/461/861 2588C-AVR-10/09 ATtiny261/461/861 The following code examples show how to access the 16-bit timer registers assuming that no interrupts updates the temporary register. The same principle can be used directly for accessing the OCR0A/B registers. Assembly Code Example ... ; Set TCNT0 to 0x01FF ldi r17,0x01 ldi r16,0xFF out TCNT0H,r17 out TCNT0L,r16 ; Read TCNT0 into r17:r16 in r16,TCNT0L in r17,TCNT0H ... C Code Example unsigned int i; ... /* Set TCNT0 to 0x01FF */ TCNT0H = 0x01; TCNT0L = 0xff; /* Read TCNT0 into i */ i = TCNT0L; i |= ((unsigned int)TCNT0H << 8); ... Note: See "Code Examples" on page 6. The assembly code example returns the TCNT0H/L value in the r17:r16 register pair. It is important to notice that accessing 16-bit registers are atomic operations. If an interrupt occurs between the two instructions accessing the 16-bit register, and the interrupt code updates the temporary register by accessing the same or any other of the 16-bit timer registers, then the result of the access outside the interrupt will be corrupted. Therefore, when both the main code and the interrupt code update the temporary register, the main code must disable the interrupts during the 16-bit access. 81 2588C-AVR-10/09 The following code examples show how to do an atomic read of the TCNT0 register contents. Reading any of the OCR0 register can be done by using the same principle. Assembly Code Example TIM0_ReadTCNT0: ; Save global interrupt flag in r18,SREG ; Disable interrupts cli ; Read TCNT0 into r17:r16 in r16,TCNT0L in r17,TCNT0H ; Restore global interrupt flag out SREG,r18 ret C Code Example unsigned int TIM0_ReadTCNT0( void ) { unsigned char sreg; unsigned int i; /* Save global interrupt flag */ sreg = SREG; /* Disable interrupts */ _CLI(); /* Read TCNT0 into i */ i = TCNT0L; i |= ((unsigned int)TCNT0H << 8); /* Restore global interrupt flag */ SREG = sreg; return i; } Note: See "Code Examples" on page 6. The assembly code example returns the TCNT0H/L value in the r17:r16 register pair. 82 ATtiny261/461/861 2588C-AVR-10/09 ATtiny261/461/861 The following code examples show how to do an atomic write of the TCNT0H/L register contents. Writing any of the OCR0A/B registers can be done by using the same principle. Assembly Code Example TIM0_WriteTCNT0: ; Save global interrupt flag in r18,SREG ; Disable interrupts cli ; Set TCNT0 to r17:r16 out TCNT0H,r17 out TCNT0L,r16 ; Restore global interrupt flag out SREG,r18 ret C Code Example void TIM0_WriteTCNT0( unsigned int i ) { unsigned char sreg; /* Save global interrupt flag */ sreg = SREG; /* Disable interrupts */ _CLI(); /* Set TCNT0 to i */ TCNT0H = (i >> 8); TCNT0L = (unsigned char)i; /* Restore global interrupt flag */ SREG = sreg; } Note: See "Code Examples" on page 6. The assembly code example requires that the r17:r16 register pair contains the value to be written to TCNT0H/L. 11.9.1 Reusing the temporary high byte register If writing to more than one 16-bit register where the high byte is the same for all registers written, then the high byte only needs to be written once. However, note that the same rule of atomic operation described previously also applies in this case. 83 2588C-AVR-10/09 11.10 Register Description 11.10.1 TCCR0A - Timer/Counter0 Control Register A Bit 7 6 5 4 3 2 1 0 0x15 (0x35) TCW0 ICEN0 ICNC0 ICES0 ACIC0 - - CTC0 Read/Write R/W R/W R/W R/W R/W R R R/W Initial Value 0 0 0 0 0 0 0 0 TCCR0A * Bit 7- TCW0: Timer/Counter0 Width When this bit is written to one 16-bit mode is selected as described Figure 11-7 on page 79. Timer/Counter0 width is set to 16-bits and the Output Compare Registers OCR0A and OCR0B are combined to form one 16-bit Output Compare Register. Because the 16-bit registers TCNT0H/L and OCR0B/A are accessed by the AVR CPU via the 8-bit data bus, special procedures must be followed. These procedures are described in section "Accessing Registers in 16bit Mode" on page 80. * Bit 6- ICEN0: Input Capture Mode Enable When this bit is written to onem, the Input Capture Mode is enabled. * Bit 5 - ICNC0: Input Capture Noise Canceler Setting this bit activates the Input Capture Noise Canceler. When the noise canceler is activated, the input from the Input Capture Pin (ICP0) is filtered. The filter function requires four successive equal valued samples of the ICP0 pin for changing its output. The Input Capture is therefore delayed by four System Clock cycles when the noise canceler is enabled. * Bit 4 - ICES0: Input Capture Edge Select This bit selects which edge on the Input Capture Pin (ICP0) that is used to trigger a capture event. When the ICES0 bit is written to zero, a falling (negative) edge is used as trigger, and when the ICES0 bit is written to one, a rising (positive) edge will trigger the capture. When a capture is triggered according to the ICES0 setting, the counter value is copied into the Input Capture Register. The event will also set the Input Capture Flag (ICF0), and this can be used to cause an Input Capture Interrupt, if this interrupt is enabled. * Bit 3 - ACIC0: Analog Comparator Input Capture Enable When written logic one, this bit enables the input capture function in Timer/Counter0 to be triggered by the Analog Comparator. The comparator output is in this case directly connected to the input capture front-end logic, making the comparator utilize the noise canceler and edge select features of the Timer/Counter0 Input Capture interrupt. When written logic zero, no connection between the Analog Comparator and the input capture function exists. To make the comparator trigger the Timer/Counter0 Input Capture interrupt, the TICIE0 bit in the Timer Interrupt Mask Register (TIMSK) must be set. * Bits 2:1 - Res: Reserved Bits These bits are reserved and will always read zero. * Bit 0 - CTC0: Waveform Generation Mode This bit controls the counting sequence of the counter, the source for maximum (TOP) counter value, see Figure 11-7 on page 79. Modes of operation supported by the Timer/Counter unit are: Normal mode (counter) and Clear Timer on Compare Match (CTC) mode (see "Modes of Operation" on page 77). 84 ATtiny261/461/861 2588C-AVR-10/09 ATtiny261/461/861 11.10.2 TCCR0B - Timer/Counter0 Control Register B Bit 7 6 5 4 3 2 1 0 0x33 (0x53) - - - TSM PSR0 CS02 CS01 CS01 Read/Write R R R R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 TCCR0B * Bit 4 - TSM: Timer/Counter Synchronization Mode Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In this mode, the value that is written to the PSR0 bit is kept, hence keeping the Prescaler Reset signal asserted. This ensures that the Timer/Counter is halted and can be configured without the risk of advancing during configuration. When the TSM bit is written to zero, the PSR0 bit is cleared by hardware, and the Timer/Counter start counting. * Bit 3 - PSR0: Prescaler Reset Timer/Counter0 When this bit is one, the Timer/Counter0 prescaler will be Reset. This bit is normally cleared immediately by hardware, except if the TSM bit is set. * Bits 2, 1, 0 - CS02, CS01, CS00: Clock Select0, Bit 2, 1, and 0 The Clock Select0 bits 2, 1, and 0 define the prescaling source of Timer0. Table 11-4. Clock Select Bit Description CS02 CS01 CS00 Description 0 0 0 No clock source (Timer/Counter stopped) 0 0 1 clkI/O/(No prescaling) 0 1 0 clkI/O/8 (From prescaler) 0 1 1 clkI/O/64 (From prescaler) 1 0 0 clkI/O/256 (From prescaler) 1 0 1 clkI/O/1024 (From prescaler) 1 1 0 External clock source on T0 pin. Clock on falling edge. 1 1 1 External clock source on T0 pin. Clock on rising edge. If external pin modes are used for the Timer/Counter0, transitions on the T0 pin will clock the counter even if the pin is configured as an output. This feature allows software control of the counting. 11.10.3 TCNT0L - Timer/Counter0 Register Low Byte Bit 7 6 5 0x32 (0x52) 4 3 2 1 0 TCNT0L[7:0] TCNT0L Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 The Timer/Counter0 Register Low Byte, TCNT0L, gives direct access, both for read and write operations, to the Timer/Counter unit 8-bit counter. Writing to the TCNT0L Register blocks (disables) the Compare Match on the following timer clock. Modifying the counter (TCNT0L) while the counter is running, introduces a risk of missing a Compare Match between TCNT0L and the OCR0x Registers. In 16-bit mode the TCNT0L register contains the lower part of the 16-bit Timer/Counter0 Register. 85 2588C-AVR-10/09 11.10.4 TCNT0H - Timer/Counter0 Register High Byte Bit 7 6 5 0x14 (0x34) 4 3 2 1 0 TCNT0H[7:0] TCNT0H Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 When 16-bit mode is selected (the TCW0 bit is set to one) the Timer/Counter Register TCNT0H combined to the Timer/Counter Register TCNT0L gives direct access, both for read and write operations, to the Timer/Counter unit 16-bit counter. To ensure that both the high and low bytes are read and written simultaneously when the CPU accesses these registers, the access is performed using an 8-bit temporary high byte register (TEMP). This temporary register is shared by all the other 16-bit registers. See "Accessing Registers in 16-bit Mode" on page 80 11.10.5 OCR0A - Timer/Counter0 Output Compare Register A Bit 7 6 5 0x13 (0x33) 4 3 2 1 0 OCR0A[7:0] OCR0A Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 The Output Compare Register A contains an 8-bit value that is continuously compared with the counter value (TCNT0L). A match can be used to generate an Output Compare interrupt. In 16-bit mode the OCR0A register contains the low byte of the 16-bit Output Compare Register. To ensure that both the high and the low bytes are written simultaneously when the CPU writes to these registers, the access is performed using an 8-bit temporary high byte register (TEMP). This temporary register is shared by all the other 16-bit registers. See "Accessing Registers in 16-bit Mode" on page 80. 11.10.6 OCR0B - Timer/Counter0 Output Compare Register B Bit 7 6 5 0x12 (0x32) 4 3 2 1 0 OCR0B[7:0] OCR0B Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 The Output Compare Register B contains an 8-bit value that is continuously compared with the counter value (TCNT0L in 8-bit mode and TCNTH in 16-bit mode). A match can be used to generate an Output Compare interrupt. In 16-bit mode the OCR0B register contains the high byte of the 16-bit Output Compare Register. To ensure that both the high and the low bytes are written simultaneously when the CPU writes to these registers, the access is performed using an 8-bit temporary high byte register (TEMP). This temporary register is shared by all the other 16-bit registers. See "Accessing Registers in 16-bit Mode" on page 80. 11.10.7 TIMSK - Timer/Counter0 Interrupt Mask Register Bit 7 6 5 4 3 2 1 0 0x39 (0x59) OCIE1D OCIE1A OCIE1B OCIE0A OCIE0B TOIE1 TOIE0 TICIE0 Read/Write R/W R/W R/W R/W R/W R/W R/W R Initial Value 0 0 0 0 0 0 0 0 TIMSK * Bit 4 - OCIE0A: Timer/Counter0 Output Compare Match A Interrupt Enable When the OCIE0A bit is written to one, and the I-bit in the Status Register is set, the Timer/Counter0 Compare Match A interrupt is enabled. The corresponding interrupt is executed 86 ATtiny261/461/861 2588C-AVR-10/09 ATtiny261/461/861 if a Compare Match in Timer/Counter0 occurs, i.e., when the OCF0A bit is set in the Timer/Counter 0 Interrupt Flag Register - TIFR0. * Bit 3 - OCIE0B: Timer/Counter Output Compare Match B Interrupt Enable When the OCIE0B bit is written to one, and the I-bit in the Status Register is set, the Timer/Counter Compare Match B interrupt is enabled. The corresponding interrupt is executed if a Compare Match in Timer/Counter occurs, i.e., when the OCF0B bit is set in the Timer/Counter Interrupt Flag Register - TIFR0. * Bit 1 - TOIE0: Timer/Counter0 Overflow Interrupt Enable When the TOIE0 bit is written to one, and the I-bit in the Status Register is set, the Timer/Counter0 Overflow interrupt is enabled. The corresponding interrupt is executed if an overflow in Timer/Counter0 occurs, i.e., when the TOV0 bit is set in the Timer/Counter 0 Interrupt Flag Register - TIFR0. * Bit 0 - TICIE0: Timer/Counter0, Input Capture Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter1 Input Capture interrupt is enabled. The corresponding Interrupt Vector (See "Interrupts" on page 50.) is executed when the ICF0 flag, located in TIFR, is set. 11.10.8 TIFR - Timer/Counter0 Interrupt Flag Register Bit 7 6 5 4 3 2 1 0 0x38 (0x58) OCF1D OCF1A OCF1B OCF0A OCF0B TOV1 TOV0 ICF0 Read/Write R/W R/W R/W R/W R/W R/W R/W R Initial Value 0 0 0 0 0 0 0 0 TIFR * Bit 4- OCF0A: Output Compare Flag 0 A The OCF0A bit is set when a Compare Match occurs between the Timer/Counter0 and the data in OCR0A - Output Compare Register0. OCF0A is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, OCF0A is cleared by writing a logic one to the flag. When the I-bit in SREG, OCIE0A (Timer/Counter0 Compare Match Interrupt Enable), and OCF0A are set, the Timer/Counter0 Compare Match Interrupt is executed. The OCF0A is also set in 16-bit mode when a Compare Match occurs between the Timer/Counter and 16-bit data in OCR0B/A. The OCF0A is not set in Input Capture mode when the Output Compare Register OCR0A is used as an Input Capture Register. * Bit 3 - OCF0B: Output Compare Flag 0 B The OCF0B bit is set when a Compare Match occurs between the Timer/Counter and the data in OCR0B - Output Compare Register0 B. OCF0B is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, OCF0B is cleared by writing a logic one to the flag. When the I-bit in SREG, OCIE0B (Timer/Counter Compare B Match Interrupt Enable), and OCF0B are set, the Timer/Counter Compare Match Interrupt is executed. The OCF0B is not set in 16-bit Output Compare mode when the Output Compare Register OCR0B is used as the high byte of the 16-bit Output Compare Register or in 16-bit Input Capture mode when the Output Compare Register OCR0B is used as the high byte of the Input Capture Register. 87 2588C-AVR-10/09 * Bit 1 - TOV0: Timer/Counter0 Overflow Flag The bit TOV0 is set when an overflow occurs in Timer/Counter0. TOV0 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, TOV0 is cleared by writing a logic one to the flag. When the SREG I-bit, TOIE0 (Timer/Counter0 Overflow Interrupt Enable), and TOV0 are set, the Timer/Counter0 Overflow interrupt is executed. * Bits 0 - ICF0: Timer/Counter0, Input Capture Flag This flag is set when a capture event occurs on the ICP0 pin. When the Input Capture Register (ICR0) is set to be used as the TOP value, the ICF0 flag is set when the counter reaches the TOP value. ICF0 is automatically cleared when the Input Capture Interrupt Vector is executed. Alternatively, ICF0 can be cleared by writing a logic one to its bit location. 88 ATtiny261/461/861 2588C-AVR-10/09 ATtiny261/461/861 12. Timer/Counter1 12.1 Features * * * * * * * * * 12.2 8/10-Bit Accuracy Three Independent Output Compare Units Clear Timer on Compare Match (Auto Reload) Glitch Free, Phase and Frequency Correct Pulse Width Modulator (PWM) Variable PWM Period High Speed Asynchronous and Synchronous Clocking with Dedicated Prescaler Independent Dead Time Generators for Each PWM Channel Fault Protection Unit Can Disable PWM Output Pins Five Independent Interrupt Sources (TOV1, OCF1A, OCD1B, OCF1D, FPF1) Overview Timer/Counter1 is a general purpose high speed Timer/Counter module, with three independent Output Compare Units, and with PWM support. The Timer/Counter1 features a high resolution and a high accuracy usage with the lower prescaling opportunities. It can also support three accurate and high speed Pulse Width Modulators using clock speeds up to 64 MHz. In PWM mode Timer/Counter1 and the output compare registers serve as triple stand-alone PWMs with non-overlapping non-inverted and inverted outputs. Similarly, the high prescaling opportunities make this unit useful for lower speed functions or exact timing functions with infrequent actions. A simplified block diagram of the Timer/Counter1 is shown in Figure 12-1. Figure 12-1. Timer/Counter1 Block Diagram TOV1 OCF1A OCF1B OCF1D OC1A OC1A OC1B OC1B FAULT_PROTECTION DEAD TIME GENERATOR DEAD TIME GENERATOR DEAD TIME GENERATOR OC1D OC1D OCW1A OCW1B FPF1 FPIE1 WGM11 OC1OE0 WGM10 FPAC1 FPF1 OC1OE3 OC1OE1 FPES1 OC1OE4 OC1OE2 FPIE1 FPEN1 FPNC1 T/C CONTROL REGISTER C (TCCR1D) OC1OE5 COM1D0 PWM1D FOC1D COM1D1 COM1B0 COM1B1 COM1A1 T/C CONTROL REGISTER C (TCCR1C) COM1A0 CS10 CS11 CS13 CS12 PSR1 PSR1 T/C CONTROL REGISTER B (TCCR1B) PSR1 PWM1B FOC1B FOC1A PWM1A COM1B1 COM1B0 T/C CONTROL REGISTER A (TCCR1A) COM1A0 OCF1B OCF1D TOV1 T/C INT. FLAG REGISTER (TIFR) COM1A1 T/C INT. MASK REGISTER (TIMSK) OCF1A OCIE1D OCIE1A OCIE1B TOIE1 OCW1D CLK TIMER/COUNTER1 (TCNT1) COUNT TIMER/COUNTER1 CONTROL LOGIC CLEAR DIRECTION 10-BIT COMPARATOR 10-BIT COMPARATOR 10-BIT OUTPUT COMPARE REGISTER A 10-BIT OUTPUT COMPARE REGISTER B 8-BIT OUTPUT COMPARE REGISTER A (OCR1A) 8-BIT OUTPUT COMPARE REGISTER B (OCR1B) 10-BIT COMPARATOR 10-BIT COMPARATOR 10-BIT OUTPUT COMPARE REGISTER C 10-BIT OUTPUT COMPARE REGISTER D 8-BIT OUTPUT COMPARE REGISTER C (OCR1C) 8-BIT OUTPUT COMPARE REGISTER D (OCR1D) T/C CONTROL REGISTER D (TCCR1E) 2-BIT HIGH BYTE REGISTER (TC1H) 8-BIT DATABUS 89 2588C-AVR-10/09 For actual placement of the I/O pins, refer to "Pinout ATtiny261/461/861 and ATtiny261V/461V/861V" on page 2. The device-specific I/O register and bit locations are listed in the "Register Description" on page 112. 12.2.1 Speed The maximum speed of the Timer/Counter1 is 64 MHz. However, if a supply voltage below 2.7 volts is used, it is recommended to use the Low Speed Mode (LSM), because the Timer/Counter1 is not running fast enough on low voltage levels. In the Low Speed Mode the fast peripheral clock is scaled down to 32 MHz. For more details about the Low Speed Mode, see "PLLCSR - PLL Control and Status Register" on page 120. 12.2.2 Accuracy The Timer/Counter1 is a 10-bit Timer/Counter module that can alternatively be used as an 8-bit Timer/Counter. The Timer/Counter1 registers are basically 8-bit registers, but on top of that there is a 2-bit High Byte Register (TC1H) that can be used as a common temporary buffer to access the two MSBs of the 10-bit Timer/Counter1 registers by the AVR CPU via the 8-bit data bus, if the 10-bit accuracy is used. Whereas, if the two MSBs of the 10-bit registers are written to zero the Timer/Counter1 is working as an 8-bit Timer/Counter. When reading the low byte of any 8-bit register the two MSBs are written to the TC1H register, and when writing the low byte of any 8-bit register the two MSBs are written from the TC1H register. Special procedures must be followed when accessing the 10-bit Timer/Counter1 values via the 8-bit data bus. These procedures are described in the section "Accessing 10-Bit Registers" on page 108. 12.2.3 Registers The Timer/Counter (TCNT1) and Output Compare Registers (OCR1A, OCR1B, OCR1C and OCR1D) are 8-bit registers that are used as a data source to be compared with the TCNT1 contents. The OCR1A, OCR1B and OCR1D registers determine the action on the OC1A, OC1B and OC1D pins and they can also generate the compare match interrupts. The OCR1C holds the Timer/Counter TOP value, i.e. the clear on compare match value. The Timer/Counter1 High Byte Register (TC1H) is a 2-bit register that is used as a common temporary buffer to access the MSB bits of the Timer/Counter1 registers, if the 10-bit accuracy is used. Interrupt request (overflow TOV1, and compare matches OCF1A, OCF1B, OCF1D and fault protection FPF1) signals are visible in the Timer Interrupt Flag Register (TIFR) and Timer/Counter1 Control Register D (TCCR1D). The interrupts are individually masked with the Timer Interrupt Mask Register (TIMSK) and the FPIE1 bit in the Timer/Counter1 Control Register D (TCCR1D). Control signals are found in the Timer/Counter Control Registers TCCR1A, TCCR1B, TCCR1C, TCCR1D and TCCR1E. 12.2.4 Synchronization In asynchronous clocking mode the Timer/Counter1 and the prescaler allow running the CPU from any clock source while the prescaler is operating on the fast peripheral clock (PCK) having frequency of 64 MHz (or 32 MHz in Low Speed Mode). This is possible because there is a synchronization boundary between the CPU clock domain and the fast peripheral clock domain. Figure 12-2 shows Timer/Counter 1 synchronization register block diagram and describes synchronization delays in between registers. Note that all clock gating details are not shown in the figure. The Timer/Counter1 register values go through the internal synchronization registers, which cause the input synchronization delay, before affecting the counter operation. The registers 90 ATtiny261/461/861 2588C-AVR-10/09 ATtiny261/461/861 TCCR1A, TCCR1B, TCCR1C, TCCR1D, OCR1A, OCR1B, OCR1C and OCR1D can be read back right after writing the register. The read back values are delayed for the Timer/Counter1 (TCNT1) register, Timer/Counter1 High Byte Register (TC1H) and flags (OCF1A, OCF1B, OCF1D and TOV1), because of the input and output synchronization. The system clock frequency must be lower than half of the PCK frequency, because the synchronization mechanism of the asynchronous Timer/Counter1 needs at least two edges of the PCK when the system clock is high. If the frequency of the system clock is too high, it is a risk that data or control values are lost. Figure 12-2. Timer/Counter1 Synchronization Register Block Diagram. 8-BIT DATABUS IO-registers Input synchronization registers OCR1A OCR1A_SI OCR1B OCR1B_SI OCR1C OCR1C_SI Timer/Counter1 Output synchronization registers TCNT1 TCNT1_SO TC1H TC1H_SO OCR1D OCR1D_SI TCCR1A TCCR1A_SI TCCR1B TCCR1B_SI TCCR1C TCCR1C_SI TCCR1D TCCR1D_SI TCNT1 TCNT1_SI TC1H TC1H_SI OCF1A OCF1A_SI OCF1A OCF1A_SO TCNT1 OCF1B OCF1B_SO OCF1D OCF1D_SO OCF1B OCF1B_SI OCF1D OCF1D_SI TOV1 TOV1_SI TOV1 TOV1_SO PCKE CK S A S PCK SYNC MODE ASYNC MODE 12.2.5 A 1/2 CK Delay ~1/2 CK Delay 1 CK Delay 1 CK Delay 1/2 CK Delay 1 PCK Delay 1 PCK Delay ~1 CK Delay Definitions Many register and bit references in this section are written in general form. A lower case "n" replaces the Timer/Counter number, in this case 0. A lower case "x" replaces the Output Compare Unit, in this case Compare Unit A, B, C or D. However, when using the register or bit defines in a program, the precise form must be used, i.e., TCNT1 for accessing Timer/Counter1 91 2588C-AVR-10/09 counter value and so on. The definitions in Table 12-1 are used extensively throughout the document. Table 12-1. 12.3 Definitions Constant Description BOTTOM The counter reaches BOTTOM when it becomes 0x00 MAX The counter reaches its MAXimum when it becomes 0xFF (decimal 255) TOP The counter reaches the TOP when it becomes equal to the highest value in the count sequence. The TOP value can be assigned to be the fixed value 0xFF (MAX) or the value stored in the OCR0A Register. The assignment depends on the mode of operation Clock Sources The Timer/Counter is clocked internally, either from CK or PCK. See bits CSxx in Table 12-17 on page 116 and bit PCKE in "PLLCSR - PLL Control and Status Register" on page 120. 12.3.1 Prescaler Figure 12-3 shows the Timer/Counter1 prescaler that supports two clocking modes, a synchronous clocking mode and an asynchronous clocking mode. The synchronous clocking mode uses the system clock (CK) as a clock timebase and asynchronous mode uses the fast peripheral clock (PCK) as a clock time base. The PCKE bit from the PLLCSR register enables the asynchronous mode when it is set (`1'). Figure 12-3. Timer/Counter1 Prescaler T1CK/16384 T1CK/8192 T1CK/4096 T1CK/2048 T1CK/1024 T1CK/512 T1CK/256 T1CK/128 T1CK/64 T1CK/32 0 T1CK/16 14-BIT T/C PRESCALER T1CK/8 T1CK T1CK/4 CK S PCK 64/32 MHz A T1CK/2 PSR1 T1CK PCKE CS10 CS11 CS12 CS13 TIMER/COUNTER1 COUNT ENABLE In the asynchronous clocking mode the clock selections are from PCK to PCK/16384 and stop, and in the synchronous clocking mode the clock selections are from CK to CK/16384 and stop. The clock options are illustrated in Figure 12-3 and desribed in "TCCR1B - Timer/Counter1 Control Register B" on page 115. The frequency of the fast peripheral clock is 64 MHz or 32 MHz in Low Speed mode (the LSM bit in PLLCSR register is set to one). The Low Speed Mode is recommended to use when the supply voltage below 2.7 volts are used. 92 ATtiny261/461/861 2588C-AVR-10/09 ATtiny261/461/861 12.3.1.1 Prescaler Reset Setting the PSR1 bit in TCCR1B register resets the prescaler. It is possible to use the Prescaler Reset for synchronizing the Timer/Counter to program execution. 12.3.1.2 Prescaler Initialization for Asynchronous Mode To change Timer/Counter1 to the asynchronous mode follow the procedure below: 1. Enable PLL. 2. Wait 100 s for PLL to stabilize. 3. Poll the PLOCK bit until it is set. 4. Set the PCKE bit in the PLLCSR register which enables the asynchronous mode. 12.4 Counter Unit The main part of the Timer/Counter1 is the programmable bi-directional counter unit. Figure 124 shows a block diagram of the counter and its surroundings. Figure 12-4. Counter Unit Block Diagram DATA BUS TOV1 clkT1 Timer/Counter1 Count Enable ( From Prescaler ) count TCNT1 clear Control Logic direction PCKE PCK CK bottom top Signal description (internal signals): count direction clear clkTn top bottom TCNT1 increment or decrement enable. Select between increment and decrement. Clear TCNT1 (set all bits to zero). Timer/Counter clock, referred to as clkT1 in the following. Signalize that TCNT1 has reached maximum value. Signalize that TCNT1 has reached minimum value (zero). Depending on the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clkT1). The timer clock is generated from an synchronous system clock or an asynchronous PLL clock using the Clock Select bits (CS13:0) and the PCK Enable bit (PCKE). When no clock source is selected (CS13:0 = 0) the timer is stopped. However, the TCNT1 value can be accessed by the CPU, regardless of whether clkT1 is present or not. A CPU write overrides (has priority over) all counter clear or count operations. The counting sequence of the Timer/Counter1 is determined by bits WGM11:10, PWM1A and PWM1B, located in the Timer/Counter1 Control Registers (TCCR1A, TCCR1C and TCCR1D). For more details about advanced counting sequences and waveform generation, see "Modes of Operation" on page 99. The Timer/Counter Overflow Flag (TOV1) is set according to the mode of operation and can be used for generating a CPU interrupt. 93 2588C-AVR-10/09 12.4.1 Counter Initialization for Asynchronous Mode To set Timer/Counter1 to asynchronous mode follow the procedure below: 1. Enable PLL. 2. Wait 100 s for PLL to stabilize. 3. Poll the PLOCK bit until it is set. 4. Set the PCKE bit in the PLLCSR register which enables the asynchronous mode. 12.5 Output Compare Unit The comparator continuously compares TCNT1 with the Output Compare Registers (OCR1A, OCR1B, OCR1C and OCR1D). Whenever TCNT1 equals to the Output Compare Register, the comparator signals a match. A match will set the Output Compare Flag (OCF1A, OCF1B or OCF1D) at the next timer clock cycle. If the corresponding interrupt is enabled, the Output Compare Flag generates an Output Compare interrupt. The Output Compare Flag is automatically cleared when the interrupt is executed. Alternatively, the flag can be cleared by software by writing a logical one to its I/O bit location. The Waveform Generator uses the match signal to generate an output according to operating mode set by bits PWM1A, PWM1B, WGM11:10 and COM1x1:0. The top and bottom signals are used by the Waveform Generator for handling the special cases of the extreme values in some modes of operation (See "Modes of Operation" on page 99.). Figure 12-5 shows a block diagram of the Output Compare unit. Figure 12-5. Output Compare Unit, Block Diagram 8-BIT DATA BUS TCNTn TCnH OCRnx 10-BIT OCRnx 10-BIT TCNTn = (10-bit Comparator ) OCFnx (Int.Req.) TOP BOTTOM PWMnx Waveform Generator FOCn WGM10 COMnX1:0 OCWnx The OCR1x Registers are double buffered when using any of the Pulse Width Modulation (PWM) modes. For the normal mode of operation, the double buffering is disabled. The double buffering synchronizes the update of the OCR1x Compare Registers to either top or bottom of the counting sequence. The synchronization prevents the occurrence of odd-length, non-sym- 94 ATtiny261/461/861 2588C-AVR-10/09 ATtiny261/461/861 metrical PWM pulses, thereby making the output glitch-free. See Figure 12-6 for an example. During the time between the write and the update operation, a read from OCR1A, OCR1B, OCR1C or OCR1D will read the contents of the temporary location. This means that the most recently written value always will read out of OCR1A, OCR1B, OCR1C or OCR1D. Figure 12-6. Effects of Unsynchronized OCR Latching Compare Value changes Counter Value Compare Value Output Compare Waveform OCWnx Synchronized WFnx Latch Compare Value changes Counter Value Compare Value Unsynchronized WFnx Latch Glitch Output Compare Wafeform OCWnx 12.5.1 Force Output Compare In non-PWM waveform generation modes, the match output of the comparator can be forced by writing a one to the Force Output Compare (FOC1x) bit. Forcing Compare Match will not set the OCF1x Flag or reload/clear the timer, but the Waveform Output (OCW1x) will be updated as if a real Compare Match had occurred (the COM1x1:0 bits settings define whether the Waveform Output (OCW1x) is set, cleared or toggled). 12.5.2 Compare Match Blocking by TCNT1 Write All CPU write operations to the TCNT1 Register will block any Compare Match that occur in the next timer clock cycle, even when the timer is stopped. This feature allows OCR1x to be initialized to the same value as TCNT1 without triggering an interrupt when the Timer/Counter clock is enabled. 12.5.3 Using the Output Compare Unit Since writing TCNT1 in any mode of operation will block all Compare Matches for one timer clock cycle, there are risks involved when changing TCNT1 when using the Output Compare Unit, independently of whether the Timer/Counter is running or not. If the value written to TCNT1 equals the OCR1x value, the Compare Match will be missed, resulting in incorrect waveform generation. Similarly, do not write the TCNT1 value equal to BOTTOM when the counter is down-counting. The setup of the Waveform Output (OCW1x) should be performed before setting the Data Direction Register for the port pin to output. The easiest way of setting the OCW1x value is to use the Force Output Compare (FOC1x) strobe bits in Normal mode. The OC1x keeps its value even when changing between Waveform Generation modes. Be aware that the COM1x1:0 bits are not double buffered together with the compare value. Changing the COM1x1:0 bits will take effect immediately. 95 2588C-AVR-10/09 12.6 Dead Time Generator The Dead Time Generator is provided for the Timer/Counter1 PWM output pairs to allow driving external power control switches safely. The Dead Time Generator is a separate block that can be used to insert dead times (non-overlapping times) for the Timer/Counter1 complementary output pairs OC1x and OC1x when the PWM mode is enabled and the COM1x1:0 bits are set to "01". See Figure 12-7 below. Figure 12-7. Block Diagram of Waveform Generator and Dead Time Generator. top bottom Waveform Generator OCWnx OCnx pin OCnx OCnx pin Dead Time Generator FOCn PWMnx WGM10 COMnx OCnx CK OR PCK CLOCK DTPSn DTnH DTnL The tasks are shared as follows: the Waveform Generator generates the output (OCW1x) and the Dead Time Generator generates the non-overlapping PWM output pair from the output. Three Dead Time Generators are provided, one for each PWM output. The non-overlap time is adjustable and the PWM output and it's complementary output are adjusted separately, and independently for both PWM outputs. The Dead Time Generation is based on 4-bit down counters that count the dead time, as shown in Figure 12-8. Figure 12-8. Dead Time Generator PWM1X COMPARATOR OCnx CK OR PCK CLOCK DEAD TIME PRE-SCALER CLOCK CONTROL 4-BIT COUNTER DTnL DTnH DTPSn OCnx PWM1X TCCRnB REGISTER DTn I/O REGISTER OCWnx DATA BUS (8-bit) There is a dedicated prescaler in front of the Dead Time Generator that can divide the Timer/Counter1 clock (PCK or CK) by 1, 2, 4 or 8. This provides for large range of dead times that can be generated. The prescaler is controlled by two control bits DTPS11:10. The block has also a rising and falling edge detector that is used to start the dead time counting period. Depending on the edge, one of the transitions on the rising edges, OC1x or OC1x is delayed until the counter has counted to zero. The comparator is used to compare the counter with zero and stop the dead time insertion when zero has been reached. The counter is loaded with a 4-bit DT1H or DT1L value from DT1 I/O register, depending on the edge of the Waveform Output (OCW1x) when the dead time insertion is started. The Output Compare Output are delayed by one timer clock cycle at minimum from the Waveform Output when the Dead Time is adjusted to 96 ATtiny261/461/861 2588C-AVR-10/09 ATtiny261/461/861 zero. The outputs OC1x and OC1x are inverted, if the PWM Inversion Mode bit PWM1X is set. This will also cause both outputs to be high during the dead time. The length of the counting period is user adjustable by selecting the dead time prescaler setting by using the DTPS11:10 control bits, and selecting then the dead time value in I/O register DT1. The DT1 register consists of two 4-bit fields, DT1H and DT1L that control the dead time periods of the PWM output and its' complementary output separately in terms of the number of prescaled dead time generator clock cycles. Thus the rising edge of OC1x and OC1x can have different dead time periods as the tnon-overlap / rising edge is adjusted by the 4-bit DT1H value and the tnon-overlap / falling edge is adjusted by the 4-bit DT1L value. Figure 12-9. The Complementary Output Pair, COM1x1:0 = 1 OCWnx OCnx OCnx (COMnx = 1) t non-overlap / rising edge 12.7 t non-overlap / falling edge Compare Match Output Unit The Compare Output Mode (COM1x1:0) bits have two functions. The Waveform Generator uses the COM1x1:0 bits for defining the inverted or non-inverted Waveform Output (OCW1x) at the next Compare Match. Also, the COM1x1:0 bits control the OC1x and OC1x pin output source. Figure 12-10 on page 98 shows a simplified schematic of the logic affected by the COM1x1:0 bit setting. The I/O Registers, I/O bits, and I/O pins in the figure are shown in bold. Only the parts of the general I/O Port Control Registers (DDR and PORT) that are affected by the COM1x1:0 bits are shown. In Normal Mode (non-PWM) the Dead Time Generator is disabled and it is working like a synchronizer: the Output Compare (OC1x) is delayed from the Waveform Output (OCW1x) by one timer clock cycle. Whereas in Fast PWM Mode and in Phase and Frequency Correct PWM Mode when the COM1x1:0 bits are set to "01" both the non-inverted and the inverted Output Compare output are generated, and an user programmable Dead Time delay is inserted for these complementary output pairs (OC1x and OC1x). The functionality in PWM modes is similar to Normal mode when any other COM1x1:0 bit setup is used. When referring to the OC1x state, the reference is for the Output Compare output (OC1x) from the Dead Time Generator, not the OC1x pin. If a system reset occur, the OC1x is reset to "0". 97 2588C-AVR-10/09 Figure 12-10. Compare Match Output Unit, Schematic WGM11 clk I/O OC1OE1:0 COM1A1:0 Output Compare Pin Configuration D Q PORTB0 0 D Q PORTB1 1 1 D Q DDRB0 OC1A PIN 0 OCW1A clk Tn Dead Time Q Generator A Q OC1A 1 OC1A 0 D Q DDRB1 WGM11 OC1OE3:2 COM1B1:0 OC1A PIN Output Compare Pin Configuration DATA BUS D Q PORTB2 2 1 0 D Q DDRB2 D Q PORTB3 1 OC1B PIN 0 OCW1B clk Tn Dead Time Q Generator B Q OC1B 1 OC1B 1 0 0 D Q DDRB3 WGM11 OC1OE5:4 COM1D1:0 OC1B PIN Output Compare Pin Configuration D Q PORTB4 2 1 0 D Q DDRB4 D Q PORTB5 1 OC1D PIN 0 OCW1D clk Tn Dead Time Q Generator D Q OC1D OC1D 1 0 1 0 OC1D PIN D Q DDRB5 The general I/O port function is overridden by the Output Compare (OC1x / OC1x) from the Dead Time Generator if either of the COM1x1:0 bits are set. However, the OC1x pin direction (input or output) is still controlled by the Data Direction Register (DDR) for the port pin. The Data Direction Register bit for the OC1x and OC1x pins (DDR_OC1x and DDR_OC1x) must be set as output before the OC1x and OC1x values are visible on the pin. The port override function is independent of the Output Compare mode. 98 ATtiny261/461/861 2588C-AVR-10/09 ATtiny261/461/861 The design of the Output Compare Pin Configuration logic allows initialization of the OC1x state before the output is enabled. Note that some COM1x1:0 bit settings are reserved for certain modes of operation. For Output Compare Pin Configurations refer to Table 12-2 on page 100, Table 12-3 on page 102, Table 12-4 on page 104, Table 12-5 on page 105, Table 12-6 on page 105, and Table 12-7 on page 106. 12.7.1 12.8 Compare Output Mode and Waveform Generation The Waveform Generator uses the COM1x1:0 bits differently in Normal mode and PWM modes. For all modes, setting the COM1x1:0 = 0 tells the Waveform Generator that no action on the OCW1x Output is to be performed on the next Compare Match. For compare output actions in the non-PWM modes refer to Table 12-8 on page 112. For fast PWM mode, refer to Table 12-9 on page 112, and for the Phase and Frequency Correct PWM refer to Table 12-10 on page 113. A change of the COM1x1:0 bits state will have effect at the first Compare Match after the bits are written. For non-PWM modes, the action can be forced to have immediate effect by using the FOC1x strobe bits. Modes of Operation The mode of operation, i.e., the behavior of the Timer/Counter and the Output Compare pins, is defined by the combination of waveform generation mode bits (PWM1A, PWM1B, and WGM11:10) and compare output mode bits (COM1x1:0). The Compare Output mode bits do not affect the counting sequence, while the Waveform Generation mode bits do. The COM1x1:0 bits control whether the PWM output generated should be inverted, non-inverted or complementary. For non-PWM modes the COM1x1:0 bits control whether the output should be set, cleared, or toggled at a Compare Match. 12.8.1 Normal Mode The simplest mode of operation is Normal mode (PWM1A/PWM1B = 0), where the counter counts from BOTTOM to TOP (defined as OCR1C) then restarts from BOTTOM. The OCR1C defines the TOP value for the counter, hence also its resolution, and allows control of the Compare Match output frequency. In toggle Compare Output Mode the Waveform Output (OCW1x) is toggled at Compare Match between TCNT1 and OCR1x. In non-inverting Compare Output Mode the Waveform Output is cleared on the Compare Match. In inverting Compare Output Mode the Waveform Output is set on Compare Match. The timing diagram for Normal mode is shown in Figure 12-11. Figure 12-11. Normal Mode, Timing Diagram TOVn Interrupt Flag Set OCnx Interrupt Flag Set TCNTn OCWnx (COMnx=1) Period 1 2 3 4 99 2588C-AVR-10/09 The counter value (TCNT1) that is shown as a histogram in Figure 12-11 is incremented until the counter value matches the TOP value. The counter is then cleared at the following clock cycle The diagram includes the Waveform Output (OCW1x) in toggle Compare Mode. The small horizontal line marks on the TCNT1 slopes represent Compare Matches between OCR1x and TCNT1. The Timer/Counter Overflow Flag (TOV1) is set in the same clock cycle as the TCNT1 becomes zero. The TOV1 Flag in this case behaves like a 11th bit, except that it is only set, not cleared. However, combined with the timer overflow interrupt, that automatically clears the TOV1 Flag, the timer resolution can be increased by software. There are no special cases to consider in the Normal mode, a new counter value can be written anytime. The Output Compare Unit can be used to generate interrupts at some given time. Using the Output Compare to generate waveforms in Normal mode is not recommended, since this will occupy too much of the CPU time. For generating a waveform, the OCW1x output can be set to toggle its logical level on each Compare Match by setting the Compare Output mode bits to toggle mode (COM1x1:0 = 1). The OC1x value will not be visible on the port pin unless the data direction for the pin is set to output. The waveform generated will have a maximum frequency of fOC1x = fclkT1/4 when OCR1C is set to zero. The waveform frequency is defined by the following equation: f clkT1 f OC1x = -----------------------------------------2 ( 1 + OCR1C ) Resolution, RPWM, shows how many bit is required to express the value in the OCR1C register and it can be calculated using the following equation: R PWM = log 2 ( OCR1C + 1 ) The Output Compare Pin configurations in Normal Mode are described in Table 12-2. Table 12-2. 12.8.2 Output Compare Pin Configurations in Normal Mode COM1x1 COM1x0 OC1x Pin OC1x Pin 0 0 Disconnected Disconnected 0 1 Disconnected OC1x 1 0 Disconnected OC1x 1 1 Disconnected OC1x Fast PWM Mode The fast Pulse Width Modulation or fast PWM mode (PWM1A/PWM1B = 1 and WGM11:10 = 00) provides a high frequency PWM waveform generation option. The fast PWM differs from the other PWM option by its single-slope operation. The counter counts from BOTTOM to TOP (defined as OCR1C) then restarts from BOTTOM. In non-inverting Compare Output mode the Waveform Output (OCW1x) is cleared on the Compare Match between TCNT1 and OCR1x and set at BOTTOM. In inverting Compare Output mode, the Waveform Output is set on Compare Match and cleared at BOTTOM. In complementary Compare Output mode the Waveform Output is cleared on the Compare Match and set at BOTTOM. Due to the single-slope operation, the operating frequency of the fast PWM mode can be twice as high as the Phase and Frequency Correct PWM mode that use dual-slope operation. This high frequency makes the fast PWM mode well suited for power regulation, rectification, and 100 ATtiny261/461/861 2588C-AVR-10/09 ATtiny261/461/861 DAC applications. High frequency allows physically small sized external components (coils, capacitors), and therefore reduces total system cost. The timing diagram for the fast PWM mode is shown in Figure 12-12. The counter is incremented until the counter value matches the TOP value. The counter is then cleared at the following timer clock cycle. The TCNT1 value is in the timing diagram shown as a histogram for illustrating the single-slope operation. The diagram includes the Waveform Output in noninverted and inverted Compare Output modes. The small horizontal line marks on the TCNT1 slopes represent Compare Matches between OCR1x and TCNT1. Figure 12-12. Fast PWM Mode, Timing Diagram OCRnx Interrupt Flag Set OCRnx Update and TOVn Interrupt Flag Set TCNTn OCWnx (COMnx1:0 = 2) OCWnx (COMnx1:0 = 3) Period 1 2 3 4 5 6 7 The Timer/Counter Overflow Flag (TOV1) is set each time the counter reaches TOP. If the interrupt is enabled, the interrupt handler routine can be used for updating the compare value. In fast PWM mode, the compare unit allows generation of PWM waveforms on the OC1x pins. Setting the COM1x1:0 bits to two will produce a non-inverted PWM and setting the COM1x1:0 to three will produce an inverted PWM output. Setting the COM1x1:0 bits to one will enable complementary Compare Output mode and produce both the non-inverted (OC1x) and inverted output (OC1x). The actual value will only be visible on the port pin if the data direction for the port pin is set as output. The PWM waveform is generated by setting (or clearing) the Waveforn Output (OCW1x) at the Compare Match between OCR1x and TCNT1, and clearing (or setting) the Waveform Output at the timer clock cycle the counter is cleared (changes from TOP to BOTTOM). The PWM frequency for the output can be calculated by the following equation: f clkT1 f OCnxPWM = -----------N The N variable represents the number of steps in single-slope operation. The value of N equals either to the TOP value. The extreme values for the OCR1C Register represents special cases when generating a PWM waveform output in the fast PWM mode. If the OCR1C is set equal to BOTTOM, the output will be a narrow spike for each MAX+1 timer clock cycle. Setting the OCR1C equal to MAX will result 101 2588C-AVR-10/09 in a constantly high or low output (depending on the polarity of the output set by the COM1x1:0 bits.) A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by setting the Waveform Output (OCW1x) to toggle its logical level on each Compare Match (COM1x1:0 = 1). The waveform generated will have a maximum frequency of fOC1 = fclkT1/4 when OCR1C is set to three. The general I/O port function is overridden by the Output Compare value (OC1x / OC1x) from the Dead Time Generator, if either of the COM1x1:0 bits are set and the Data Direction Register bits for the OC1X and OC1X pins are set as an output. If the COM1x1:0 bits are cleared, the actual value from the port register will be visible on the port pin. The Output Compare Pin configurations are described in Table 12-3. Table 12-3. 12.8.3 Output Compare Pin Configurations in Fast PWM Mode COM1x1 COM1x0 OC1x Pin OC1x Pin 0 0 Disconnected Disconnected 0 1 OC1x OC1x 1 0 Disconnected OC1x 1 1 Disconnected OC1x Phase and Frequency Correct PWM Mode The Phase and Frequency Correct PWM Mode (PWM1A/PWM1B = 1 and WGM11:10 = 01) provides a high resolution Phase and Frequency Correct PWM waveform generation option. The Phase and Frequency Correct PWM mode is based on a dual-slope operation. The counter counts repeatedly from BOTTOM to TOP (defined as OCR1C) and then from TOP to BOTTOM. In non-inverting Compare Output Mode the Waveform Output (OCW1x) is cleared on the Compare Match between TCNT1 and OCR1x while upcounting, and set on the Compare Match while down-counting. In inverting Output Compare mode, the operation is inverted. In complementary Compare Output Mode, the Waveform Ouput is cleared on the Compare Match and set at BOTTOM. The dual-slope operation has lower maximum operation frequency than single slope operation. However, due to the symmetric feature of the dual-slope PWM modes, these modes are preferred for motor control applications. The timing diagram for the Phase and Frequency Correct PWM mode is shown on Figure 12-13 in which the TCNT1 value is shown as a histogram for illustrating the dual-slope operation. The counter is incremented until the counter value matches TOP. When the counter reaches TOP, it changes the count direction. The TCNT1 value will be equal to TOP for one timer clock cycle. The diagram includes the Waveform Output (OCW1x) in non-inverted and inverted Compare Output Mode. The small horizontal line marks on the TCNT1 slopes represent Compare Matches between OCR1x and TCNT1. 102 ATtiny261/461/861 2588C-AVR-10/09 ATtiny261/461/861 Figure 12-13. Phase and Frequency Correct PWM Mode, Timing Diagram OCnx Interrupt Flag Set OCRnx Update TOVn Interrupt Flag Set TCNTn OCWnx (COMnx = 2) OCWnx (COMnx = 3) Period 1 2 3 The Timer/Counter Overflow Flag (TOV1) is set each time the counter reaches BOTTOM. The Interrupt Flag can be used to generate an interrupt each time the counter reaches the BOTTOM value. In the Phase and Frequency Correct PWM mode, the compare unit allows generation of PWM waveforms on the OC1x pins. Setting the COM1x1:0 bits to two will produce a non-inverted PWM and setting the COM1x1:0 to three will produce an inverted PWM output. Setting the COM1A1:0 bits to one will enable complementary Compare Output mode and produce both the non-inverted (OC1x) and inverted output (OC1x). The actual values will only be visible on the port pin if the data direction for the port pin is set as output. The PWM waveform is generated by clearing (or setting) the Waveform Output (OCW1x) at the Compare Match between OCR1x and TCNT1 when the counter increments, and setting (or clearing) the Waveform Output at Compare Match when the counter decrements. The PWM frequency for the output when using the Phase and Frequency Correct PWM can be calculated by the following equation: f clkT1 f OCnxPCPWM = -----------N The N variable represents the number of steps in dual-slope operation. The value of N equals to the TOP value. The extreme values for the OCR1C Register represent special cases when generating a PWM waveform output in the Phase and Frequency Correct PWM mode. If the OCR1C is set equal to BOTTOM, the output will be continuously low and if set equal to MAX the output will be continuously high for non-inverted PWM mode. For inverted PWM the output will have the opposite logic values. The general I/O port function is overridden by the Output Compare value (OC1x / OC1x) from the Dead Time Generator, if either of the COM1x1:0 bits are set and the Data Direction Register bits for the OC1X and OC1X pins are set as an output. If the COM1x1:0 bits are cleared, the 103 2588C-AVR-10/09 actual value from the port register will be visible on the port pin. The configurations of the Output Compare Pins are described in Table 12-4. Table 12-4. 12.8.4 Output Compare pin configurations in Phase and Frequency Correct PWM Mode COM1x1 COM1x0 OC1x Pin OC1x Pin 0 0 Disconnected Disconnected 0 1 OC1x OC1x 1 0 Disconnected OC1x 1 1 Disconnected OC1x PWM6 Mode The PWM6 Mode (PWM1A = 1, WGM11:10 = 1X) provide PWM waveform generation option e.g. for controlling Brushless DC (BLDC) motors. In the PWM6 Mode the OCR1A Register controls all six Output Compare waveforms as the same Waveform Output (OCW1A) from the Waform Generator is used for generating all waveforms. The PWM6 Mode also provides an Output Compare Override Enable Register (OC1OE) that can be used with an instant response for disabling or enabling the Output Compare pins. If the Output Compare Override Enable bit is cleared, the actual value from the port register will be visible on the port pin. The PWM6 Mode provides two counter operation modes, a single-slope operation and a dualslope operation. If the single-slope operation is selected (the WGM10 bit is set to 0), the counter counts from BOTTOM to TOP (defined as OCR1C) then restart from BOTTOM like in Fast PWM Mode. The PWM waveform is generated by setting (or clearing) the Waveforn Output (OCW1A) at the Compare Match between OCR1A and TCNT1, and clearing (or setting) the Waveform Output at the timer clock cycle the counter is cleared (changes from TOP to BOTTOM). The Timer/Counter Overflow Flag (TOV1) is set each time the counter reaches the TOP and, if the interrupt is enabled, the interrupt handler routine can be used for updating the compare value. Whereas, if the dual-slope operation is selected (the WGM10 bit is set to 1), the counter counts repeatedly from BOTTOM to TOP (defined as OCR1C) and then from TOP to BOTTOM like in Phase and Frequency Correct PWM Mode. The PWM waveform is generated by setting (or clearing) the Waveforn Output (OCW1A) at the Compare Match between OCR1A and TCNT1 when the counter increments, and clearing (or setting) the Waveform Output at the he Compare Match between OCR1A and TCNT1 when the counter decrements. The Timer/Counter Overflow Flag (TOV1) is set each time the counter reaches the BOTTOM and, if the interrupt is enabled, the interrupt handler routine can be used for updating the compare value. The timing diagram for the PWM6 Mode in single-slope operation when the COM1A1:0 bits are set to "10" is shown in Figure 12-14. The counter is incremented until the counter value matches the TOP value. The counter is then cleared at the following timer clock cycle. The TCNT1 value is in the timing diagram shown as a histogram for illustrating the single-slope operation. The timing diagram includes Output Compare pins OC1A and OC1A, and the corresponding Output Compare Override Enable bits (OC1OE1:OC1OE0). 104 ATtiny261/461/861 2588C-AVR-10/09 ATtiny261/461/861 Figure 12-14. PWM6 Mode, Single-slope Operation, Timing Diagram TCNT1 OCW1A OC1OE0 OC1A Pin OC1OE1 OC1A Pin OC1OE2 OC1B Pin OC1OE3 OC1B Pin OC1OE4 OC1D Pin OC1OE5 OC1D Pin The general I/O port function is overridden by the Output Compare value (OC1x / OC1x) from the Dead Time Generator if either of the COM1x1:0 bits are set. The Output Compare pins can also be overriden by the Output Compare Override Enable bits OC1OE5:OC1OE0. If an Override Enable bit is cleared, the actual value from the port register will be visible on the port pin and, if the Override Enable bit is set, the Output Compare pin is allowed to be connected on the port pin. The Output Compare Pin configurations are described in Table 12-5, Table 12-6 and Table 12-7. Table 12-5. Configuration of Output Compare Pins OC1A and OC1A in PWM6 Mode COM1A1 COM1A0 OC1A Pin (PB0) OC1A Pin (PB1) 0 0 Disconnected Disconnected 0 1 OC1A * OC1OE0 OC1A * OC1OE1 1 0 OC1A * OC1OE0 OC1A * OC1OE1 1 1 OC1A * OC1OE0 OC1A * OC1OE1 Table 12-6. Configuration of Output Compare Pins OC1B and OC1B in PWM6 Mode COM1B1 COM1B0 OC1B Pin (PB2) OC1B Pin (PB3) 0 0 Disconnected Disconnected 0 1 OC1A * OC1OE2 OC1A * OC1OE3 1 0 OC1A * OC1OE2 OC1A * OC1OE3 1 1 OC1A * OC1OE2 OC1A * OC1OE3 105 2588C-AVR-10/09 Table 12-7. 12.9 Configuration of Output Compare Pins OC1D and OC1D in PWM6 Mode COM1D1 COM1D0 OC1D Pin (PB4) OC1D Pin (PB5) 0 0 Disconnected Disconnected 0 1 OC1A * OC1OE4 OC1A * OC1OE5 1 0 OC1A * OC1OE4 OC1A * OC1OE5 1 1 OC1A * OC1OE4 OC1A * OC1OE5 Timer/Counter Timing Diagrams The Timer/Counter is a synchronous design and the timer clock (clkT1) is therefore shown as a clock enable signal in the following figures. The figures include information on when Interrupt Flags are set. Figure 12-15 contains timing data for basic Timer/Counter operation. The figure shows the count sequence close to the MAX value in all modes other than Phase and Frequency Correct PWM Mode. Figure 12-15. Timer/Counter Timing Diagram, no Prescaling clkPCK clkTn (clkPCK /1) TCNTn TOP - 1 TOP BOTTOM BOTTOM + 1 TOVn Figure 12-16 shows the same timing data, but with the prescaler enabled, in all modes other than Phase and Frequency Correct PWM Mode. Figure 12-16. Timer/Counter Timing Diagram, with Prescaler (fclkT1/8) clkPCK clkTn (clkPCK /8) TCNTn TOP - 1 TOP BOTTOM BOTTOM + 1 TOVn Figure 12-17 shows the setting of OCF1A, OCF1B and OCF1D in all modes. 106 ATtiny261/461/861 2588C-AVR-10/09 ATtiny261/461/861 Figure 12-17. Timer/Counter Timing Diagram, Setting of OCF1x, with Prescaler (fclkT1/8) clkPCK clkTn (clkPCK /8) TCNTn OCRnx - 1 OCRnx OCRnx OCRnx + 1 OCRnx + 2 OCRnx Value OCFnx Figure 12-18 shows the setting of TOV1 in Phase and Frequency Correct PWM Mode. Figure 12-18. Timer/Counter Timing Diagram, with Prescaler (fclkT1/8) clkPCK clkTn (clkPCK /8) TCNTn BOTTOM + 1 BOTTOM + 1 BOTTOM BOTTOM + 1 TOVn 12.10 Fault Protection Unit The Timer/Counter1 incorporates a Fault Protection unit, which can be set to disable the PWM output pins when an external event is triggered. The external signal indicating an event can be applied via the external interrupt INT0 pin or, alternatively, via the analog-comparator unit. The Fault Protection unit is illustrated in Figure 12-19. The elements of the block diagram that are not directly a part of the Fault Protection unit are gray shaded. Figure 12-19. Fault Protection Unit Block Diagram FAULT_PROTECTION (Int. Req.) ACO* Analog Comparator INT0 FPAC1 FPNC1 Noise Canceler FPES1 FPEN1 Edge Detector Timer/Counter1 Fault Protection mode is enabled by setting the Fault Protection Enable (FPEN1) bit and triggered by a change in logic level at external interrupt pin (INT0). Alternatively, fault protection mode can be triggered by the Analog Comparator Output (ACO). When Fault Protection is triggered, the COM1x bits are cleared, Output Comparators are disconnected from the PWM output pins and PORTB register bits are connected to the PWM output 107 2588C-AVR-10/09 pins. The Fault Protection Enable (FPEN1) is automatically cleared at the same system clock as the COM1nx bits are cleared. If the Fault Protection Interrupt Enable bit (FPIE1) is set, a Fault Protection interrupt is generated and the FPEN1 bit is cleared. Alternatively the FPEN1 bit can be polled by software to figure out when the Timer/Counter has entered to Fault Protection mode. 12.10.1 Fault Protection Trigger Source The main trigger source for the Fault Protection unit is the external interrupt pin (INT0). Alternatively the Analog Comparator output can be used as trigger source for the Fault Protection unit. The Analog Comparator is selected as trigger source by setting the Fault Protection Analog Comparator (FPAC1) bit in the Timer/Counter1 Control Register (TCCR1D). Be aware that changing trigger source can trigger a Fault Protection mode. Therefore it is recommended to clear the FPF1 flag after changing trigger source, setting edge detector or enabling the Fault Protection. Both the external interrupt pin (INT0) and the Analog Comparator output (ACO) inputs are sampled using the same technique as with the T0 pin (see Figure 11-3 on page 74). The edge detectors are also identical but when the noise canceler is enabled additional logic is activated before the edge detector, increasing the propagation delay with four system clock cycles. An Input Capture can also be triggered by software by controlling the port of the INT0 pin. 12.10.2 Noise Canceler The noise canceler uses a simple digital filtering technique to improve noise immunity. Consecutive samples are monitored in a pipeline four units deep. The signal going to the edge detecter is allowed to change only when all four samples are equal. The noise canceler is enabled by setting the Fault Protection Noise Canceler (FPNC1) bit in Timer/Counter1 Control Register D (TCCR1D). When enabled, the noise canceler introduces an additional delay of four system clock cycles to a change applied to the input. The noise canceler uses the system clock directly and is therefore not affected by the prescaler. 12.11 Accessing 10-Bit Registers If 10-bit values are written to the TCNT1 and OCR1A/B/C/D registers, the 10-bit registers can be byte accessed by the AVR CPU via the 8-bit data bus using two read or write operations. The 10-bit registers have a common 2-bit Timer/Counter1 High Byte Register (TC1H) that is used for temporary storing of the two MSBs of the 10-bit access. The same TC1H register is shared between all 10-bit registers. Accessing the low byte triggers the 10-bit read or write operation. When the low byte of a 10-bit register is written by the CPU, the high byte stored in the TC1H register, and the low byte written are both copied into the 10-bit register in the same clock cycle. When the low byte of a 10-bit register is read by the CPU, the high byte of the 10-bit register is copied into the TC1H register in the same clock cycle as the low byte is read. To do a 10-bit write, the high byte must be written to the TC1H register before the low byte is written. For a 10-bit read, the low byte must be read before the high byte. 12.11.1 108 Reusing the temporary high byte register If writing to more than one 10-bit register where the high byte is the same for all registers written, then the high byte only needs to be written once. However, note that the same rule of atomic operation described previously also applies in this case. ATtiny261/461/861 2588C-AVR-10/09 ATtiny261/461/861 12.11.2 Code Examples The following code examples show how to access the 10-bit timer registers assuming that no interrupts updates the TC1H register. The same principle can be used directly for accessing the OCR1A/B/C/D registers. Assembly Code Example ... ; Set TCNT1 to 0x01FF ldi r17,0x01 ldi r16,0xFF out TC1H,r17 out TCNT1,r16 ; Read TCNT1 into r17:r16 in r16,TCNT1 in r17,TC1H ... C Code Example unsigned int i; ... /* Set TCNT1 to 0x01FF */ TC1H = 0x01; TCNT1 = 0xFF; /* Read TCNT1 into i */ i = TCNT1; i |= ((unsigned int)TC1H << 8); ... Note: See "Code Examples" on page 6. The assembly code example returns the TCNT1 value in the r17:r16 register pair. It is important to notice that accessing 10-bit registers are atomic operations. If an interrupt occurs between the two instructions accessing the 10-bit register, and the interrupt code updates the TC1H register by accessing the same or any other of the 10-bit timer registers, then the result of the access outside the interrupt will be corrupted. Therefore, when both the main code and the interrupt code update the TC1H register, the main code must disable the interrupts during the 16-bit access. 109 2588C-AVR-10/09 The following code examples show how to do an atomic read of the TCNT1 register contents. Reading any of the OCR1A/B/C/D registers can be done by using the same principle. Assembly Code Example TIM1_ReadTCNT1: ; Save global interrupt flag in r18,SREG ; Disable interrupts cli ; Read TCNT1 into r17:r16 in r16,TCNT1 in r17,TC1H ; Restore global interrupt flag out SREG,r18 ret C Code Example unsigned int TIM1_ReadTCNT1( void ) { unsigned char sreg; unsigned int i; /* Save global interrupt flag */ sreg = SREG; /* Disable interrupts */ _CLI(); /* Read TCNT1 into i */ i = TCNT1; i |= ((unsigned int)TC1H << 8); /* Restore global interrupt flag SREG = sreg; return i; } Note: See "Code Examples" on page 6. The assembly code example returns the TCNT1 value in the r17:r16 register pair. 110 ATtiny261/461/861 2588C-AVR-10/09 ATtiny261/461/861 The following code examples show how to do an atomic write of the TCNT1 register contents. Writing any of the OCR1A/B/C/D registers can be done by using the same principle. Assembly Code Example TIM1_WriteTCNT1: ; Save global interrupt flag in r18,SREG ; Disable interrupts cli ; Set TCNT1 to r17:r16 out TC1H,r17 out TCNT1,r16 ; Restore global interrupt flag out SREG,r18 ret C Code Example void TIM1_WriteTCNT1( unsigned int i ) { unsigned char sreg; unsigned int i; /* Save global interrupt flag */ sreg = SREG; /* Disable interrupts */ _CLI(); /* Set TCNT1 to i */ TC1H = (i >> 8); TCNT1 = (unsigned char)i; /* Restore global interrupt flag */ SREG = sreg; } Note: See "Code Examples" on page 6. The assembly code example requires that the r17:r16 register pair contains the value to be written to TCNT1. 111 2588C-AVR-10/09 12.12 Register Description 12.12.1 TCCR1A - Timer/Counter1 Control Register A Bit 7 6 5 4 3 2 1 0 0x30 (0x50) COM1A1 COM1A0 COM1B1 COM1B0 FOC1A FOC1B PWM1A PWM1B Read/Write R/W R/W R/W R/W W W R/W R/W Initial value 0 0 0 0 0 0 0 0 TCCR1A * Bits 7,6 - COM1A1, COM1A0: Comparator A Output Mode, Bits 1 and 0 These bits control the behaviour of the Waveform Output (OCW1A) and the connection of the Output Compare pin (OC1A). If one or both of the COM1A1:0 bits are set, the OC1A output overrides the normal port functionality of the I/O pin it is connected to. The complementary OC1B output is connected only in PWM modes when the COM1A1:0 bits are set to "01". Note that the Data Direction Register (DDR) bit corresponding to the OC1A and OC1A pins must be set in order to enable the output driver. The function of the COM1A1:0 bits depends on the PWM1A, WGM10 and WGM11 bit settings. Table 12-8 shows the COM1A1:0 bit functionality when the PWM1A bit is set to Normal Mode (non-PWM). Table 12-8. COM1A1:0 Compare Output Mode, Normal Mode (non-PWM) OCW1A Behaviour OC1A Pin OC1A Pin 00 Normal port operation. Disconnected Disconnected 01 Toggle on Compare Match. Connected Disconnected 10 Clear on Compare Match. Connected Disconnected 11 Set on Compare Match. Connected Disconnected Table 12-9 shows the COM1A1:0 bit functionality when the PWM1A, WGM10 and WGM11 bits are set to fast PWM mode. Table 12-9. COM1A1:0 112 Compare Output Mode, Fast PWM Mode OCW1A Behaviour OC1A OC1A 00 Normal port operation. Disconnected Disconnected 01 Cleared on Compare Match. Set when TCNT1 = 0x000. Connected Connected 10 Cleared on Compare Match. Set when TCNT1 = 0x000. Connected Disconnected 11 Set on Compare Match. Cleared when TCNT1 = 0x000. Connected Disconnected ATtiny261/461/861 2588C-AVR-10/09 ATtiny261/461/861 Table 12-10 shows the COM1A1:0 bit functionality when the PWM1A, WGM10 and WGM11 bits are set to Phase and Frequency Correct PWM Mode. Table 12-10. Compare Output Mode, Phase and Frequency Correct PWM Mode COM1A1:0 OCW1A Behaviour OC1A Pin OC1A Pin 00 Normal port operation. Disconnected Disconnected 01 Cleared on Compare Match when up-counting. Set on Compare Match when down-counting. Connected Connected 10 Cleared on Compare Match when up-counting. Set on Compare Match when down-counting. Connected Disconnected 11 Set on Compare Match when up-counting. Cleared on Compare Match when down-counting. Connected Disconnected Table 12-11 shows the COM1A1:0 bit functionality when the PWM1A, WGM10 and WGM11 bits are set to single-slope PWM6 Mode. In the PWM6 Mode the same Waveform Output (OCW1A) is used for generating all waveforms and the Output Compare values OC1A and OC1A are connected on thw all OC1x and OC1x pins as described below. Table 12-11. Compare Output Mode, Single-Slope PWM6 Mode COM1A1:0 OCW1A Behaviour OC1x Pin OC1x Pin 00 Normal port operation. Disconnected Disconnected 01 Cleared on Compare Match. Set when TCNT1 = 0x000. OC1A OC1A 10 Cleared on Compare Match. Set when TCNT1 = 0x000. OC1A OC1A 11 Set on Compare Match. Cleared when TCNT1 = 0x000. OC1A OC1A Table 12-12 shows the COM1A1:0 bit functionality when the PWM1A, WGM10 and WGM11 bits are set to dual-slope PWM6 Mode.I Table 12-12. Compare Output Mode, Dual-Slope PWM6 Mode COM1A1:0 OCW1A Behaviour OC1x Pin OC1x Pin 00 Normal port operation. Disconnected Disconnected 01 Cleared on Compare Match when up-counting. Set on Compare Match when down-counting. OC1A OC1A 10 Cleared on Compare Match when up-counting. Set on Compare Match when down-counting. OC1A OC1A 11 Set on Compare Match when up-counting. Cleared on Compare Match when down-counting. OC1A OC1A Bits COM1A1 and COM1A0 are shadowed in TCCR1C. Writing to bits COM1A1 and COM1A0 will also change bits COM1A1S and COM1A0S in TCCR1C. Similary, changes written to bits COM1A1S and COM1A0S in TCCR1C will show here. See "TCCR1C - Timer/Counter1 Control Register C" on page 117. 113 2588C-AVR-10/09 * Bits 5,4 - COM1B1, COM1B0: Comparator B Output Mode, Bits 1 and 0 These bits control the behaviour of the Waveform Output (OCW1B) and the connection of the Output Compare pin (OC1B). If one or both of the COM1B1:0 bits are set, the OC1B output overrides the normal port functionality of the I/O pin it is connected to. The complementary OC1B output is connected only in PWM modes when the COM1B1:0 bits are set to "01". Note that the Data Direction Register (DDR) bit corresponding to the OC1B pin must be set in order to enable the output driver. The function of the COM1B1:0 bits depends on the PWM1B and WGM11:10 bit settings. Table 12-13 shows the COM1B1:0 bit functionality when the PWM1B bit is set to Normal Mode (nonPWM). Table 12-13. Compare Output Mode, Normal Mode (non-PWM) COM1B1:0 OCW1B Behaviour OC1B Pin OC1B Pin 00 Normal port operation. Disconnected Disconnected 01 Toggle on Compare Match. Connected Disconnected 10 Clear on Compare Match. Connected Disconnected 11 Set on Compare Match. Connected Disconnected Table 12-14 shows the COM1B1:0 bit functionality when the PWM1B and WGM11:10 bits are set to Fast PWM Mode. Table 12-14. Compare Output Mode, Fast PWM Mode COM1B1:0 OCW1B Behaviour OC1B Pin OC1B Pin 00 Normal port operation. Disconnected Disconnected 01 Cleared on Compare Match. Set when TCNT1 = 0x000. Connected Connected 10 Cleared on Compare Match. Set when TCNT1 = 0x000. Connected Disconnected 11 Set on Compare Match. Cleared when TCNT1 = 0x000. Connected Disconnected Table 12-15 shows the COM1B1:0 bit functionality when the PWM1B and WGM11:10 bits are set to Phase and Frequency Correct PWM Mode. Table 12-15. Compare Output Mode, Phase and Frequency Correct PWM Mode COM1B1:0 OCW1B Behaviour OC1B Pin OC1B Pin 00 Normal port operation. Disconnected Disconnected 01 Cleared on Compare Match when up-counting. Set on Compare Match when down-counting. Connected Connected 10 Cleared on Compare Match when up-counting. Set on Compare Match when down-counting. Connected Disconnected 11 Set on Compare Match when up-counting. Cleared on Compare Match when down-counting. Connected Disconnected Bits COM1B1 and COM1B0 are shadowed in TCCR1C. Writing to bits COM1B1 and COM1B0 will also change bits COM1B1S and COM1B0S in TCCR1C. Similary, changes written to bits 114 ATtiny261/461/861 2588C-AVR-10/09 ATtiny261/461/861 COM1B1S and COM1B0S in TCCR1C will show here. See "TCCR1C - Timer/Counter1 Control Register C" on page 117. * Bit 3 - FOC1A: Force Output Compare Match 1A The FOC1A bit is only active when the PWM1A bit specify a non-PWM mode. Writing a logical one to this bit forces a change in the Waveform Output (OCW1A) and the Output Compare pin (OC1A) according to the values already set in COM1A1 and COM1A0. If COM1A1 and COM1A0 written in the same cycle as FOC1A, the new settings will be used. The Force Output Compare bit can be used to change the output pin value regardless of the timer value. The automatic action programmed in COM1A1 and COM1A0 takes place as if a compare match had occurred, but no interrupt is generated. The FOC1A bit always reads zero. * Bit 2 - FOC1B: Force Output Compare Match 1B The FOC1B bit is only active when the PWM1B bit specify a non-PWM mode. Writing a logical one to this bit forces a change in the Waveform Output (OCW1B) and the Output Compare pin (OC1B) according to the values already set in COM1B1 and COM1B0. If COM1B1 and COM1B0 written in the same cycle as FOC1B, the new settings will be used. The Force Output Compare bit can be used to change the output pin value regardless of the timer value. The automatic action programmed in COM1B1 and COM1B0 takes place as if a compare match had occurred, but no interrupt is generated. The FOC1B bit always reads zero. * Bit 1 - PWM1A: Pulse Width Modulator A Enable When set (one) this bit enables PWM mode based on comparator OCR1A * Bit 0 - PWM1B: Pulse Width Modulator B Enable When set (one) this bit enables PWM mode based on comparator OCR1B. 12.12.2 TCCR1B - Timer/Counter1 Control Register B Bit 7 6 5 4 3 2 1 0 0x2F (0x4F) PWM1X PSR1 DTPS11 DTPS10 CS13 CS12 CS11 CS10 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial value 0 0 0 0 0 0 0 0 TCCR1B * Bit 7 - PWM1X : PWM Inversion Mode When this bit is set (one), the PWM Inversion Mode is selected and the Dead Time Generator outputs, OC1x and OC1x are inverted. * Bit 6 - PSR1 : Prescaler Reset Timer/Counter1 When this bit is set (one), the Timer/Counter1 prescaler (TCNT1 is unaffected) will be reset. The bit will be cleared by hardware after the operation is performed. Writing a zero to this bit will have no effect. This bit will always read as zero. * Bits 5,4 - DTPS11, DTPS10: Dead Time Prescaler Bits The Timer/Counter1 Control Register B is a 8-bit read/write register. 115 2588C-AVR-10/09 The dedicated Dead Time prescaler in front of the Dead Time Generator can divide the Timer/Counter1 clock (PCK or CK) by 1, 2, 4 or 8 providing a large range of dead times that can be generated. The Dead Time prescaler is controlled by two bits DTPS11 and DTPS10 from the Dead Time Prescaler register. These bits define the division factor of the Dead Time prescaler. The division factors are given in Table 12-16. Table 12-16. Division factors of the Dead Time prescaler DTPS11 DTPS10 Prescaler divides the T/C1 clock by 0 0 1x (no division) 0 1 2x 1 0 4x 1 1 8x * Bits 3 : 0 - CS13, CS12, CS11, CS10: Clock Select Bits 3, 2, 1, and 0 The Clock Select bits 3, 2, 1, and 0 define the prescaling source of Timer/Counter1. Table 12-17. Timer/Counter1 Prescaler Select CS13 CS12 CS11 CS10 Asynchronous Clocking Mode Synchronous Clocking Mode 0 0 0 0 T/C1 stopped T/C1 stopped 0 0 0 1 PCK CK 0 0 1 0 PCK/2 CK/2 0 0 1 1 PCK/4 CK/4 0 1 0 0 PCK/8 CK/8 0 1 0 1 PCK/16 CK/16 0 1 1 0 PCK/32 CK/32 0 1 1 1 PCK/64 CK/64 1 0 0 0 PCK/128 CK/128 1 0 0 1 PCK/256 CK/256 1 0 1 0 PCK/512 CK/512 1 0 1 1 PCK/1024 CK/1024 1 1 0 0 PCK/2048 CK/2048 1 1 0 1 PCK/4096 CK/4096 1 1 1 0 PCK/8192 CK/8192 1 1 1 1 PCK/16384 CK/16384 The Stop condition provides a Timer Enable/Disable function. 116 ATtiny261/461/861 2588C-AVR-10/09 ATtiny261/461/861 12.12.3 TCCR1C - Timer/Counter1 Control Register C Bit 7 6 5 4 3 2 1 0 0x27 (0x47) COM1A1 S COM1A0 S COM1B1 S COM1B0 S COM1D1 COM1D0 FOC1D PWM1D Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial value 0 0 0 0 0 0 0 0 TCCR1C * Bits 7,6 - COM1A1S, COM1A0S: Comparator A Output Mode, Shadow Bits 1 and 0 These are shadow bits of COM1A1 and COM1A0 in TCCR1A. Writing to bits COM1A1S and COM1A0S will also change bits COM1A1 and COM1A0 in TCCR1A. Similary, changes written to bits COM1A1 and COM1A0 in TCCR1A will show here. See "TCCR1A - Timer/Counter1 Control Register A" on page 112 for information on bit usage. * Bits 5,4 - COM1B1S, COM1B0S: Comparator B Output Mode, Shadow Bits 1 and 0 These are shadow bits of COM1B1 and COM1B0 in TCCR1A. Writing to bits COM1B1S and COM1B0S will also change bits COM1B1 and COM1B0 in TCCR1A. Similary, changes written to bits COM1B1 and COM1B0 in TCCR1A will show here. See "TCCR1A - Timer/Counter1 Control Register A" on page 112 for information on bit usage. * Bits 3,2 - COM1D1, COM1D0: Comparator D Output Mode, Bits 1 and 0 These bits control the behaviour of the Waveform Output (OCW1D) and the connection of the Output Compare pin (OC1D). If one or both of the COM1D1:0 bits are set, the OC1D output overrides the normal port functionality of the I/O pin it is connected to. The complementary OC1D output is connected only in PWM modes when the COM1D1:0 bits are set to "01". Note that the Data Direction Register (DDR) bit corresponding to the OC1D pin must be set in order to enable the output driver. The function of the COM1D1:0 bits depends on the PWM1D and WGM11:10 bit settings. Table 12-18 shows the COM1D1:0 bit functionality when the PWM1D bit is set to a Normal Mode (nonPWM). Table 12-18. Compare Output Mode, Normal Mode (non-PWM) COM1D1:0 OCW1D Behaviour OC1D Pin OC1D Pin 00 Normal port operation. Disconnected Disconnected 01 Toggle on Compare Match. Connected Disconnected 10 Clear on Compare Match. Connected Disconnected 11 Set on Compare Match. Connected Disconnected Table 12-19 shows the COM1D1:0 bit functionality when the PWM1D and WGM11:10 bits are set to Fast PWM Mode. Table 12-19. Compare Output Mode, Fast PWM Mode COM1D1:0 OCW1D Behaviour OC1D Pin OC1D Pin 00 Normal port operation. Disconnected Disconnected 01 Cleared on Compare Match. Set when TCNT1=0x000. Connected Connected 10 Cleared on Compare Match. Set when TCNT1=0x000. Connected Disconnected 11 Set on Compare Match. Cleared when TCNT1=0x000. Connected Disconnected 117 2588C-AVR-10/09 Table 12-20 shows the COM1D1:0 bit functionality when the PWM1D and WGM11:10 bits are set to Phase and Frequency Correct PWM Mode. Table 12-20. Compare Output Mode, Phase and Frequency Correct PWM Mode COM1D1:0 OCW1D Behaviour OC1D Pin OC1D Pin 00 Normal port operation. Disconnected Disconnected 01 Cleared on Compare Match when up-counting. Set on Compare Match when down-counting. Connected Connected 10 Cleared on Compare Match when up-counting. Set on Compare Match when down-counting. Connected Disconnected 11 Set on Compare Match when up-counting. Cleared on Compare Match when down-counting. Connected Disconnected * Bit 1 - FOC1D: Force Output Compare Match 1D The FOC1D bit is only active when the PWM1D bit specify a non-PWM mode. Writing a logical one to this bit forces a change in the Waveform Output (OCW1D) and the Output Compare pin (OC1D) according to the values already set in COM1D1 and COM1D0. If COM1D1 and COM1D0 written in the same cycle as FOC1D, the new settings will be used. The Force Output Compare bit can be used to change the output pin value regardless of the timer value. The automatic action programmed in COM1D1 and COM1D0 takes place as if a compare match had occurred, but no interrupt is generated. The FOC1D bit is always read as zero. * Bit 0 - PWM1D: Pulse Width Modulator D Enable When set (one) this bit enables PWM mode based on comparator OCR1D. 12.12.4 TCCR1D - Timer/Counter1 Control Register D Bit 7 6 5 4 3 2 1 0 0x26 (0x46) FPIE1 FPEN1 FPNC1 FPES1 FPAC1 FPF1 WGM11 WGM10 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial value 0 0 0 0 0 0 0 0 TCCR1D * Bit 7 - FPIE1: Fault Protection Interrupt Enable Setting this bit (to one) enables the Fault Protection Interrupt. * Bit 6- FPEN1: Fault Protection Mode Enable Setting this bit (to one) activates the Fault Protection Mode. * Bit 5 - FPNC1: Fault Protection Noise Canceler Setting this bit activates the Fault Protection Noise Canceler. When the noise canceler is activated, the input from the Fault Protection Pin (INT0) is filtered. The filter function requires four successive equal valued samples of the INT0 pin for changing its output. The Fault Protection is therefore delayed by four Oscillator cycles when the noise canceler is enabled. * Bit 4 - FPES1: Fault Protection Edge Select This bit selects which edge on the Fault Protection pin (INT0) is used to trigger a fault event. When the FPES1 bit is written to zero, a falling (negative) edge is used as trigger, and when the FPES1 bit is written to one, a rising (positive) edge will trigger the fault. 118 ATtiny261/461/861 2588C-AVR-10/09 ATtiny261/461/861 * Bit 3 - FPAC1: Fault Protection Analog Comparator Enable When written logic one, this bit enables the Fault Protection function in Timer/Counter1 to be triggered by the Analog Comparator. The comparator output is in this case directly connected to the Fault Protection front-end logic, making the comparator utilize the noise canceler and edge select features of the Timer/Counter1 Fault Protection interrupt. When written logic zero, no connection between the Analog Comparator and the Fault Protection function exists. To make the comparator trigger the Timer/Counter1 Fault Protection interrupt, the FPIE1 bit in the Timer/Counter1 Control Register D (TCCR1D) must be set. * Bit 2- FPF1: Fault Protection Interrupt Flag When the FPIE1 bit is set (one), the Fault Protection Interrupt is enabled. Activity on the pin will cause an interrupt request even, if the Fault Protection pin is configured as an output. The corresponding interrupt of Fault Protection Interrupt Request is executed from the Fault Protection Interrupt Vector. The bit FPF1 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, FPF1 is cleared after a synchronization clock cycle by writing a logical one to the flag. When the SREG I-bit, FPIE1 and FPF1 are set, the Fault Interrupt is executed. * Bits 1:0 - WGM11, WGM10: Waveform Generation Mode Bits These bits together with the PWM1A/PWM1B bits control the counting sequence of the counter and the type of waveform generation to be used, as shown in Table 12-21. Modes of operation supported by the Timer/Counter1 are: Normal mode (counter), Fast PWM Mode, Phase and Frequency Correct PWM and PWM6 Modes. Table 12-21. Waveform Generation Mode Bit Description 12.12.5 PWM1A/ PWM1B WGM11:10 Timer/Counter Mode of Operation TOP Update OCR1x at Set TOV1 Flag at 0 XX Normal OCR1C Immediate TOP 1 00 Fast PWM OCR1C TOP TOP 1 01 Phase & Frequency Correct PWM OCR1C BOTTOM BOTTOM 1 10 PWM6 / Single-slope OCR1C TOP TOP 1 11 PWM6 / Dual-slope OCR1C BOTTOM BOTTOM TCCR1E - Timer/Counter1 Control Register E Bit 7 6 5 4 3 2 1 0 0x00 (0x20) - - OC1OE5 OC1OE4 OC1OE3 OC1OE2 OC1OE1 OC1OE0 Read/Write R R R/W R/W R/W R/W R/W R/W Initial value 0 0 0 0 0 0 0 0 TCCR1E * Bits 7:6 - Res: Reserved Bits These bits are reserved and always read zero. * Bits 5:0 - OC1OE5:OC1OE0: Output Compare Override Enable Bits These bits are the Ouput Compare Override Enable bits that are used to connect or disconnect the Output Compare Pins in PWM6 Modes with an instant response on the corresponding Output Compare Pins. The actual value from the port register will be visible on the port pin, when 119 2588C-AVR-10/09 the Output Compare Override Enable Bit is cleared. Table 12-22 shows the Output Compare Override Enable Bits and their corresponding Output Compare pins. Table 12-22. Output Compare Override Enable Bits vs. Output Compare Pins 12.12.6 Output CompareOverride Enable Bit Output Compare Output Output Compare Pin OC1OE0 OC1A PB0 OC1OE1 OC1A PB1 OC1OE2 OC1B PB2 OC1OE3 OC1B PB3 OC1OE4 OC1D PB4 OC1OE5 OC1D PB5 PLLCSR - PLL Control and Status Register Bit 7 6 5 4 3 2 1 0x29 (0x49) LSM - - - - PCKE PLLE 0 PLOCK Read/Write R/W R R R R R/W R/W R Initial value 0 0 0 0 0 0 0/1 0 PLLCSR * Bit 7- LSM: Low Speed Mode The Low Speed mode is set, if the LSM bit is written to one. Then the fast peripheral clock is scaled down to 32 MHz. The Low Speed Mode must be set, if the supply voltage is below 2.7 volts, because the Timer/Counter1 is not running fast enough on low voltage levels. It is recommended that the Timer/Counter1 is stopped whenever the LSM bit is changed. Note, that LSM can not be set if PLLCLK is used as a system clock. * Bit 6:3- Res : Reserved Bits These bits are reserved and always read zero. * Bit 2- PCKE: PCK Enable The PCKE bit change the Timer/Counter1 clock source. When it is set, the asynchronous clock mode is enabled and fast 64 MHz (or 32 MHz in Low Speed Mode) PCK clock is used as a Timer/Counter1 clock source. If this bit is cleared, the synchronous clock mode is enabled, and system clock CK is used as Timer/Counter1 clock source. It is safe to set this bit only when the PLL is locked i.e the PLOCK bit is 1. Note that the PCKE bit can be set only, if the PLL has been enabled earlier. The PLL is enabled when the CKSEL fuse has been programmed to 0x0001 (the PLL clock mode is selected) or the PLLE bit has been set to one. * Bit 1- PLLE: PLL Enable When the PLLE is set, the PLL is started and if needed internal RC-oscillator is started as a PLL reference clock. If PLL is selected as a system clock source the value for this bit is always 1. * Bit 0- PLOCK: PLL Lock Detector When the PLOCK bit is set, the PLL is locked to the reference clock. The PLOCK bit should be ignored during initial PLL lock-in sequence when PLL frequency overshoots and undershoots, before reaching steady state. The steady state is obtained within 100 s. After PLL lock-in it is recommended to check the PLOCK bit before enabling PCK for Timer/Counter1. 120 ATtiny261/461/861 2588C-AVR-10/09 ATtiny261/461/861 12.12.7 TCNT1 - Timer/Counter1 Bit 7 6 5 4 3 2 1 0 0x2E (0x4E) MSB LSB Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial value 0 0 0 0 0 0 0 0 TCNT1 This 8-bit register contains the value of Timer/Counter1. The Timer/Counter1 is realized as a 10-bit up/down counter with read and write access. Due to synchronization of the CPU, Timer/Counter1 data written into Timer/Counter1 is delayed by one and half CPU clock cycles in synchronous mode and at most one CPU clock cycles for asynchronous mode. When a 10-bit accuracy is preferred, special procedures must be followed for accessing the 10-bit TCNT1 register via the 8-bit AVR data bus. These procedures are described in section "Accessing 10-Bit Registers" on page 108. Alternatively the Timer/Counter1 can be used as an 8-bit Timer/Counter. Note that the Timer/Counter1 always starts counting up after writing the TCNT1 register. 12.12.8 TC1H - Timer/Counter1 High Byte Bit 7 6 5 4 3 2 1 0 0x25 (0x45) - - - - - - TC19 TC18 Read/Write R R R R R R R/W R/W Initial value 0 0 0 0 0 0 0 0 TC1H The temporary Timer/Counter1 register is an 2-bit read/write register. * Bits 7:2 - Res: Reserved Bits These bits are reserved and always reads zero. * Bits 1:0 - TC19, TC18: Two MSB bits of the 10-bit accesses If 10-bit accuracy is used, the Timer/Counter1 High Byte Register (TC1H) is used for temporary storing the MSB bits (TC19, TC18) of the 10-bit acceses. The same TC1H register is shared between all 10-bit registers within the Timer/Counter1. Note that special procedures must be followed when accessing the 10-bit TCNT1 register via the 8-bit AVR data bus. These procedures are described in section "Accessing 10-Bit Registers" on page 108. 12.12.9 OCR1A - Timer/Counter1 Output Compare Register A Bit 7 6 5 4 3 2 1 0 0x2D (0x4D) MSB LSB Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial value 0 0 0 0 0 0 0 0 OCR1A The output compare register A is an 8-bit read/write register. The Timer/Counter Output Compare Register A contains data to be continuously compared with Timer/Counter1. Actions on compare matches are specified in TCCR1A. A compare match does only occur if Timer/Counter1 counts to the OCR1A value. A software write that sets TCNT1 and OCR1A to the same value does not generate a compare match. A compare match will set the compare interrupt flag OCF1A after a synchronization delay following the compare event. Note that, if 10-bit accuracy is used special procedures must be followed when accessing the internal 10-bit Ouput Compare Registers via the 8-bit AVR data bus. These procedures are described in section "Accessing 10-Bit Registers" on page 108. 121 2588C-AVR-10/09 12.12.10 OCR1B - Timer/Counter1 Output Compare Register B Bit 7 6 5 4 3 2 1 0 0x2C (0x4C) MSB LSB Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial value 0 0 0 0 0 0 0 0 OCR1B The output compare register B is an 8-bit read/write register. The Timer/Counter Output Compare Register B contains data to be continuously compared with Timer/Counter1. Actions on compare matches are specified in TCCR1. A compare match does only occur if Timer/Counter1 counts to the OCR1B value. A software write that sets TCNT1 and OCR1B to the same value does not generate a compare match. A compare match will set the compare interrupt flag OCF1B after a synchronization delay following the compare event. Note that, if 10-bit accuracy is used special procedures must be followed when accessing the internal 10-bit Output Compare Registers via the 8-bit AVR data bus. These procedures are described in section "Accessing 10-Bit Registers" on page 108. 12.12.11 OCR1C - Timer/Counter1 Output Compare Register C Bit 7 6 5 4 3 2 1 0 0x2B (0x4B) MSB LSB Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial value 1 1 1 1 1 1 1 1 OCR1C The output compare register C is an 8-bit read/write register. The Timer/Counter Output Compare Register C contains data to be continuously compared with Timer/Counter1, and a compare match will clear TCNT1. This register has the same function in Normal mode and PWM modes. Note that, if a smaller value than three is written to the Output Compare Register C, the value is automatically replaced by three as it is a minumum value allowed to be written to this register. Note that, if 10-bit accuracy is used special procedures must be followed when accessing the internal 10-bit Output Compare Registers via the 8-bit AVR data bus. These procedures are described in section "Accessing 10-Bit Registers" on page 108. 12.12.12 OCR1D - Timer/Counter1 Output Compare Register D Bit 7 6 5 4 3 2 1 0 0x2A (0x4A) MSB LSB Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial value 0 0 0 0 0 0 0 0 OCR1D The output compare register D is an 8-bit read/write register. The Timer/Counter Output Compare Register D contains data to be continuously compared with Timer/Counter1. Actions on compare matches are specified in TCCR1A. A compare match does only occur if Timer/Counter1 counts to the OCR1D value. A software write that sets TCNT1 and OCR1D to the same value does not generate a compare match. A compare match will set the compare interrupt flag OCF1D after a synchronization delay following the compare event. 122 ATtiny261/461/861 2588C-AVR-10/09 ATtiny261/461/861 Note that, if 10-bit accuracy is used special procedures must be followed when accessing the internal 10-bit Output Compare Registers via the 8-bit AVR data bus. These procedures are described in section "Accessing 10-Bit Registers" on page 108. 12.12.13 TIMSK - Timer/Counter1 Interrupt Mask Register Bit 7 6 5 4 3 2 1 0 0x39 (0x59) OCIE1D OCIE1A OCIE1B OCIE0A OCIE0B TOIE1 TOIE0 TICIE0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial value 0 0 0 0 0 0 0 0 TIMSK * Bit 7- OCIE1D: Timer/Counter1 Output Compare Interrupt Enable When the OCIE1D bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Compare MatchD, interrupt is enabled. The corresponding interrupt at vector $010 is executed if a compare matchD occurs. The Compare Flag in Timer/Counter1 is set (one) in the Timer/Counter Interrupt Flag Register. * Bit 6 - OCIE1A: Timer/Counter1 Output Compare Interrupt Enable When the OCIE1A bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Compare MatchA, interrupt is enabled. The corresponding interrupt at vector $003 is executed if a compare matchA occurs. The Compare Flag in Timer/Counter1 is set (one) in the Timer/Counter Interrupt Flag Register. * Bit 5 - OCIE1B: Timer/Counter1 Output Compare Interrupt Enable When the OCIE1B bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Compare MatchB, interrupt is enabled. The corresponding interrupt at vector $009 is executed if a compare matchB occurs. The Compare Flag in Timer/Counter1 is set (one) in the Timer/Counter Interrupt Flag Register. * Bit 2 - TOIE1: Timer/Counter1 Overflow Interrupt Enable When the TOIE1 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Overflow interrupt is enabled. The corresponding interrupt (at vector $004) is executed if an overflow in Timer/Counter1 occurs. The Overflow Flag (Timer1) is set (one) in the Timer/Counter Interrupt Flag Register - TIFR. 12.12.14 TIFR - Timer/Counter1 Interrupt Flag Register Bit 7 6 5 4 3 2 1 0 0x38 (0x58) OCF1D OCF1A OCF1B OCF0A OCF0B TOV1 TOV0 ICF0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial value 0 0 0 0 0 0 0 0 TIFR * Bit 7- OCF1D: Output Compare Flag 1D The OCF1D bit is set (one) when compare match occurs between Timer/Counter1 and the data value in OCR1D - Output Compare Register 1D. OCF1D is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, OCF1D is cleared, after synchronization clock cycle, by writing a logic one to the flag. When the I-bit in SREG, OCIE1D, and OCF1D are set (one), the Timer/Counter1 D compare match interrupt is executed. * Bit 6 - OCF1A: Output Compare Flag 1A The OCF1A bit is set (one) when compare match occurs between Timer/Counter1 and the data value in OCR1A - Output Compare Register 1A. OCF1A is cleared by hardware when executing 123 2588C-AVR-10/09 the corresponding interrupt handling vector. Alternatively, OCF1A is cleared, after synchronization clock cycle, by writing a logic one to the flag. When the I-bit in SREG, OCIE1A, and OCF1A are set (one), the Timer/Counter1 A compare match interrupt is executed. * Bit 5 - OCF1B: Output Compare Flag 1B The OCF1B bit is set (one) when compare match occurs between Timer/Counter1 and the data value in OCR1B - Output Compare Register 1A. OCF1B is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, OCF1B is cleared, after synchronization clock cycle, by writing a logic one to the flag. When the I-bit in SREG, OCIE1B, and OCF1B are set (one), the Timer/Counter1 B compare match interrupt is executed. * Bit 2 - TOV1: Timer/Counter1 Overflow Flag In Normal Mode and Fast PWM Mode the TOV1 bit is set (one) each time the counter reaches TOP at the same clock cycle when the counter is reset to BOTTOM. In Phase and Frequency Correct PWM Mode the TOV1 bit is set (one) each time the counter reaches BOTTOM at the same clock cycle when zero is clocked to the counter. The bit TOV1 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, TOV1 is cleared, after synchronization clock cycle, by writing a logical one to the flag. When the SREG I-bit, and TOIE1 (Timer/Counter1 Overflow Interrupt Enable), and TOV1 are set (one), the Timer/Counter1 Overflow interrupt is executed. 12.12.15 DT1 - Timer/Counter1 Dead Time Value Bit 7 6 5 4 3 2 1 0 0x24 (0x44) DT1H3 DT1H2 DT1H1 DT1H0 DT1L3 DT1L2 DT1L1 DT1L0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial value 0 0 0 0 0 0 0 0 DT1 The dead time value register is an 8-bit read/write register. The dead time delay of all Timer/Counter1 channels are adjusted by the dead time value register, DT1. The register consists of two fields, DT1H3:0 and DT1L3:0, one for each complementary output. Therefore a different dead time delay can be adjusted for the rising edge of OC1x and the rising edge of OC1x. * Bits 7:4- DT1H3:DT1H0: Dead Time Value for OC1x Output The dead time value for the OC1x output. The dead time delay is set as a number of the prescaled timer/counter clocks. The minimum dead time is zero and the maximum dead time is the prescaled time/counter clock period multiplied by 15. * Bits 3:0- DT1L3:DT1L0: Dead Time Value for OC1x Output The dead time value for the OC1x output. The dead time delay is set as a number of the prescaled timer/counter clocks. The minimum dead time is zero and the maximum dead time is the prescaled time/counter clock period multiplied by 15. 124 ATtiny261/461/861 2588C-AVR-10/09 ATtiny261/461/861 13. USI - Universal Serial Interface 13.1 Features * * * * * * 13.2 Two-wire Synchronous Data Transfer (Master or Slave) Three-wire Synchronous Data Transfer (Master or Slave) Data Received Interrupt Wakeup from Idle Mode In Two-wire Mode: Wake-up from All Sleep Modes, Including Power-down Mode Two-wire Start Condition Detector with Interrupt Capability Overview The Universal Serial Interface, or USI, provides the basic hardware resources needed for serial communication. Combined with a minimum of control software, the USI allows significantly higher transfer rates and uses less code space than solutions based on software only. Interrupts are included to minimize the processor load. A simplified block diagram of the USI is shown in Figure 13-1 For actual placement of I/O pins refer to "Pinout ATtiny261/461/861 and ATtiny261V/461V/861V" on page 2. Device-specific I/O Register and bit locations are listed in the "Register Descriptions" on page 132. Figure 13-1. Universal Serial Interface, Block Diagram Bit7 Bit0 D Q LE DO (Output only) DI/SDA (Input/Open Drain) USCK/SCL (Input/Open Drain) 3 2 USIDR 1 0 TIM0 COMP USIPF 4-bit Counter USIDC USISIF USIOIF DATA BUS USIDB 3 2 0 1 1 0 CLOCK HOLD [1] Two-wire Clock Control Unit USISR USITC USICLK USICS0 USICS1 USIWM0 USIWM1 USISIE USIOIE 2 USICR The 8-bit USI Data Register (USIDR) is directly accessible via the data bus and contains the incoming and outgoing data. The register has no buffering so the data must be read as quickly as possible to ensure that no data is lost. The data register is a serial shift register where the most significant bit is connected to one of two output pins depending of the wire mode configuration. A transparent latch between the output of the data register and the output pin delays the change of data output to the opposite clock edge of the data input sampling. The serial input is always sampled from the Data Input (DI) pin, regardless of the configuration. 125 2588C-AVR-10/09 The 4-bit counter can be both read and written via the data bus, and it can generate an overflow interrupt. The data register and the counter are clocked simultaneously by the same clock source, allowing the counter to count the number of bits received or transmitted and generate an interrupt when the transfer is complete. Note that when an external clock source is selected the counter counts both clock edges. In this case the counter counts the number of edges, and not the number of bits. The clock can be selected from three different sources: The USCK pin, the Timer/Counter0 Compare Match or from software. The Two-wire clock control unit can generate an interrupt when a start condition is detected on the Two-wire bus. It can also generate wait states by holding the clock pin low after a start condition is detected, or after the counter overflows. 13.3 13.3.1 Functional Descriptions Three-wire Mode The USI Three-wire mode is compliant to the Serial Peripheral Interface (SPI) mode 0 and 1, but does not have the slave select (SS) pin functionality. However, this feature can be implemented in software if necessary. Pin names used by this mode are: DI, DO, and USCK. Figure 13-2. Three-wire Mode Operation, Simplified Diagram DO Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 DI Bit0 USCK SLAVE DO Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 DI Bit0 USCK PORTxn MASTER Figure 13-2 shows two USI units operating in three-wire mode, one as Master and one as Slave. The two USI Data Register are interconnected in such way that after eight USCK clocks, the data in each register are interchanged. The same clock also increments the USI's 4-bit counter. The Counter Overflow (interrupt) Flag, or USIOIF, can therefore be used to determine when a transfer is completed. The clock is generated by the Master device software by toggling the USCK pin via the PORT Register or by writing a one to the USITC bit in USICR. 126 ATtiny261/461/861 2588C-AVR-10/09 ATtiny261/461/861 Figure 13-3. Three-wire Mode, Timing Diagram CYCLE ( Reference ) 1 2 3 4 5 6 7 8 USCK USCK DO MSB DI MSB A B C 6 5 4 3 2 1 LSB 6 5 4 3 2 1 LSB D E The Three-wire mode timing is shown in Figure 13-3. At the top of the figure is a USCK cycle reference. One bit is shifted into the USI Data Register (USIDR) for each of these cycles. The USCK timing is shown for both external clock modes. In External Clock mode 0 (USICS0 = 0), DI is sampled at positive edges, and DO is changed (Data Register is shifted by one) at negative edges. In external clock mode 1 (USICS0 = 1) the opposite edges with respect to mode 0 are used. In other words, data is sampled at negative and output is changed at positive edges. The USI clock modes corresponds to the SPI data mode 0 and 1. Referring to the timing diagram (Figure 13-3), a bus transfer involves the following steps: 1. The slave and master devices set up their data outputs and, depending on the protocol used, enable their output drivers (mark A and B). The output is set up by writing the data to be transmitted to the USI Data Register. The output is enabled by setting the corresponding bit in the Data Direction Register of Port A. Note that there is not a preferred order of points A and B in the figure, but both must be at least one half USCK cycle before point C, where the data is sampled. This is in order to ensure that the data setup requirement is satisfied. The 4-bit counter is reset to zero. 2. The master software generates a clock pulse by toggling the USCK line twice (C and D). The bit values on the data input (DI) pins are sampled by the USI on the first edge (C), and the data output is changed on the opposite edge (D). The 4-bit counter will count both edges. 3. Step 2. is repeated eight times for a complete register (byte) transfer. 4. After eight clock pulses (i.e., 16 clock edges) the counter will overflow and indicate that the transfer has been completed. The data bytes transferred must now be processed before a new transfer can be initiated. The overflow interrupt will wake up the processor if it is set to Idle mode. Depending on the protocol used the slave device can now set its output to high impedance. 13.3.2 SPI Master Operation Example The following code demonstrates how to use the USI module as a SPI Master: SPITransfer: sts USIDR,r16 ldi r16,(1< 2 CPU clock cycles for fck < 12 MHz, 3 CPU clock cycles for fck >= 12 MHz * High:> 2 CPU clock cycles for fck < 12 MHz, 3 CPU clock cycles for fck >= 12 MHz 18.6.1 Serial Programming Algorithm When writing serial data to the ATtiny261/461/861, data is clocked on the rising edge of SCK. When reading, data is clocked on the falling edge of SCK. See Figure 19-4 and Figure 19-5 for timing details. To program and verify the ATtiny261/461/861 in the Serial Programming mode, the following sequence is recommended (see four byte instruction formats in Table 18-11): 1. Power-up sequence: Apply power between VCC and GND while RESET and SCK are set to "0". In some systems, the programmer can not guarantee that SCK is held low during power-up. In this case, RESET must be given a positive pulse after SCK has been set to '0'. The duration of the pulse must be at least tRST (the minimum pulse width on RESET pin, see Table 19-4 on page 190) plus two CPU clock cycles. 2. Wait for at least 20 ms and enable serial programming by sending the Programming Enable serial instruction to pin MOSI. 3. The serial programming instructions will not work if the communication is out of synchronization. When in sync. the second byte (0x53), will echo back when issuing the third byte of the Programming Enable instruction. Whether the echo is correct or not, all four bytes of the instruction must be transmitted. If the 0x53 did not echo back, give RESET a positive pulse and issue a new Programming Enable command. 4. The Flash is programmed one page at a time. The memory page is loaded one byte at a time by supplying the 5 LSB of the address and data together with the Load Program memory Page instruction. To ensure correct loading of the page, the data low byte must be loaded before data high byte is applied for a given address. The Program memory Page is stored by loading the Write Program memory Page instruction with the 6 MSB of the address. If polling (RDY/BSY) is not used, the user must wait at least tWD_FLASH before issuing the next page. (See Table 18-10.) Accessing the serial programming 174 ATtiny261/461/861 2588C-AVR-10/09 ATtiny261/461/861 interface before the Flash write operation completes can result in incorrect programming. 5. A: The EEPROM array is programmed one byte at a time by supplying the address and data together with the appropriate Write instruction. An EEPROM memory location is first automatically erased before new data is written. If polling (RDY/BSY) is not used, the user must wait at least tWD_EEPROM before issuing the next byte. (See Table 18-10.) In a chip erased device, no 0xFFs in the data file(s) need to be programmed. B: The EEPROM array is programmed one page at a time. The Memory page is loaded one byte at a time by supplying the 2 LSB of the address and data together with the Load EEPROM Memory Page instruction. The EEPROM Memory Page is stored by loading the Write EEPROM Memory Page Instruction with the 6 MSB of the address. When using EEPROM page access only byte locations loaded with the Load EEPROM Memory Page instruction is altered. The remaining locations remain unchanged. If polling (RDY/BSY) is not used, the used must wait at least tWD_EEPROM before issuing the next page (See Table 18-8). In a chip erased device, no 0xFF in the data file(s) need to be programmed. 6. Any memory location can be verified by using the Read instruction which returns the content at the selected address at serial output MISO. 7. At the end of the programming session, RESET can be set high to commence normal operation. 8. Power-off sequence (if needed): Set RESET to "1". Turn VCC power off. 18.6.2 Serial Programming Instruction set Table 18-10. Minimum Wait Delay Before Writing the Next Flash or EEPROM Location Symbol Minimum Wait Delay tWD_FLASH 4.5 ms tWD_EEPROM 4.0 ms tWD_ERASE 4.0 ms tWD_FUSE 4.5 ms The instruction set is described in Table 18-11 on page 176 and Figure 18-2 on page 177. 175 2588C-AVR-10/09 Table 18-11. Serial Programming Instruction Set Instruction Format Instruction/Operation Byte 1 Byte 2 Byte 3 Byte4 Programming Enable $AC $53 $00 $00 Chip Erase (Program Memory/EEPROM) $AC $80 $00 $00 Poll RDY/BSY $F0 $00 $00 data byte out Load Extended Address byte(1) $4D $00 Extended adr $00 Load Program Memory Page, High byte $48 adr MSB adr LSB high data byte in Load Program Memory Page, Low byte $40 adr MSB adr LSB low data byte in Load EEPROM Memory Page (page access) $C1 $00 0000 000aa data byte in Read Program Memory, High byte $28 adr MSB adr LSB high data byte out Read Program Memory, Low byte $20 adr MSB adr LSB low data byte out Read EEPROM Memory $A0 $00 00aa aaaa data byte out Read Lock bits $58 $00 $00 data byte out Read Signature Byte $30 $00 0000 000aa data byte out Read Fuse bits $50 $00 $00 data byte out Read Fuse High bits $58 $08 $00 data byte out Read Extended Fuse Bits $50 $08 $00 data byte out Read Calibration Byte $38 $00 $00 data byte out Write Program Memory Page $4C adr MSB adr LSB $00 Write EEPROM Memory $C0 $00 00aa aaaa data byte in Write EEPROM Memory Page (page access) $C2 $00 00aa aa00 $00 Write Lock bits $AC $E0 $00 data byte in Write Fuse bits $AC $A0 $00 data byte in Write Fuse High bits $AC $A8 $00 data byte in Write Extended Fuse Bits $AC $A4 $00 data byte in Load Instructions Read Instructions Write Instructions Notes: (6) 1. Not all instructions are applicable for all parts. 2. a = address 3. Bits are programmed `0', unprogrammed `1'. 4. To ensure future compatibility, unused Fuses and Lock bits should be unprogrammed (`1') . 5. Refer to the correspondig section for Fuse and Lock bits, Calibration and Signature bytes and Page size. 6. Instructions accessing program memory use a word address. This address may be random within the page range. 7. See http://www.atmel.com/avr for Application Notes regarding programming and programmers. 176 ATtiny261/461/861 2588C-AVR-10/09 ATtiny261/461/861 Figure 18-2. Serial Programming Instruction example Serial Programming Instruction Load Program Memory Page (High/Low Byte)/ Load EEPROM Memory Page (page access) Byte 1 Byte 2 Byte 3 Adr MSB A Write Program Memory Page/ Write EEPROM Memory Page Byte 1 Byte 4 Byte 2 Adr LSB Bit 15 B Adr MSB Bit 15 B 0 Byte 3 Byte 4 Adrr LSB B 0 Page Buffer Page Offset Page 0 Page 1 Page 2 Page Number Page N-1 Program Memory/ EEPROM Memory If the LSB in RDY/BSY data byte out is `1', a programming operation is still pending. Wait until this bit returns `0' before the next instruction is carried out. Within the same page, the low data byte must be loaded prior to the high data byte. After data is loaded to the page buffer, program the EEPROM page, see Figure 18-2 on page 177. 18.7 Parallel Programming This section describes how to parallel program and verify Flash Program memory, EEPROM Data memory, Memory Lock bits, and Fuse bits. Pulses are assumed to be at least 250 ns in length, unless otherwise noted. 18.7.1 Signal Names In this section, some pins are referenced by signal names describing their functionality during parallel programming, see Figure 18-3 and Table 18-12. Pins not described in the following table are referenced by pin names. 177 2588C-AVR-10/09 Figure 18-3. Parallel Programming. +5V WR PB0 XA0 PB1 XA1/BS2 PB2 PAGEL/BS1 PB3 VCC +5V AVCC PA7 - PA0 DATA XTAL1/PB4 OE PB5 RDY/BSY PB6 +12 V RESET GND Table 18-12. Pin Name Mapping 178 Signal Name in Programming Mode Pin Name I/O WR PB0 I Write Pulse (Active low). XA0 PB1 I XTAL Action Bit 0 XA1/BS2 PB2 I XTAL Action Bit 1. Byte Select 2 ("0" selects low byte, "1" selects 2'nd high byte). PAGEL/BS1 PB3 I Byte Select 1 ("0" selects low byte, "1" selects high byte). Program Memory and EEPROM Data Page Load. OE PB5 I Output Enable (Active low). RDY/BSY PB6 O 0: Device is busy programming, 1: Device is ready for new command. DATA I/O PA7-PA0 I/O Bi-directional Data bus (Output when OE is low). Function ATtiny261/461/861 2588C-AVR-10/09 ATtiny261/461/861 Table 18-13. Pin Values Used to Enter Programming Mode Pin Symbol Value PAGEL/BS1 Prog_enable[3] 0 XA1/BS2 Prog_enable[2] 0 XA0 Prog_enable[1] 0 WR Prog_enable[0] 0 The XA1/XA0 pins determine the action executed when the XTAL1 pin is given a positive pulse. The bit coding is shown in Table 18-14. Table 18-14. XA1 and XA0 Coding XA1 XA0 Action when XTAL1 is Pulsed 0 0 Load Flash or EEPROM Address (High or low address byte determined by BS1). 0 1 Load Data (High or Low data byte for Flash determined by BS1). 1 0 Load Command 1 1 No Action, Idle When pulsing WR or OE, the command loaded determines the action executed. The different Commands are shown in Table 18-15. Table 18-15. Command Byte Bit Coding Command Byte 18.7.2 Command Executed 1000 0000 Chip Erase 0100 0000 Write Fuse bits 0010 0000 Write Lock bits 0001 0000 Write Flash 0001 0001 Write EEPROM 0000 1000 Read Signature Bytes and Calibration byte 0000 0100 Read Fuse and Lock bits 0000 0010 Read Flash 0000 0011 Read EEPROM Entering Programming Mode The following algorithm puts the device in parallel programming mode: 1. Apply 4.5 - 5.5V between VCC and GND. 2. Set RESET to "0" and toggle XTAL1 at least six times. 3. Set Prog_enable pins listed in Table 18-13 on page 179 to "0000" and wait at least 100 ns. 4. Apply 11.5 - 12.5V to RESET. Any activity on Prog_enable pins within 100 ns after +12V has been applied to RESET, will cause the device to fail entering programming mode. 5. Wait at least 50 s before sending a new command. 179 2588C-AVR-10/09 18.7.3 Considerations for Efficient Programming The loaded command and address are retained in the device during programming. For efficient programming, the following should be considered: * The command needs only be loaded once when writing or reading multiple memory locations. * Skip writing the data value 0xFF, that is the contents of the entire EEPROM (unless the EESAVE Fuse is programmed) and Flash after a Chip Erase. * Address high byte needs only be loaded before programming or reading a new 256 word window in Flash or 256 byte EEPROM. This consideration also applies to Signature bytes reading. 18.7.4 Chip Erase The Chip Erase will erase the Flash and EEPROM memories plus lock bits. The Lock bits are not reset until the program memory has been completely erased. The Fuse bits are not changed. A Chip Erase must be performed before the Flash and/or EEPROM are reprogrammed. 1. Load Command "Chip Erase": a. Set XA1, XA0 to "10". This enables command loading. b. Set BS1 to "0". c. Set DATA to "1000 0000". This is the command for Chip Erase. d. Give XTAL1 a positive pulse. This loads the command. e. Give WR a negative pulse. This starts the Chip Erase. RDY/BSY goes low. f. Note: 18.7.5 Wait until RDY/BSY goes high before loading a new command. The EEPROM memory is preserved during Chip Erase if the EESAVE Fuse is programmed. Programming the Flash The Flash is organized in pages, see Table 18-7 on page 173. When programming the Flash, the program data is latched into a page buffer. This allows one page of program data to be programmed simultaneously. The following procedure describes how to program the entire Flash memory (see Figure 18-5 for signal waveforms): 1. Load Command "Write Flash": a. Set XA1, XA0 to "10". This enables command loading. b. Set BS1 to "0". c. Set DATA to "0001 0000". This is the command for Write Flash. d. Give XTAL1 a positive pulse. This loads the command. 2. Load Address Low byte: a. Set XA1, XA0 to "00". This enables address loading. b. Keep BS1 at "0". This selects low address. c. Set DATA = Address low byte (0x00 - 0xFF). d. Give XTAL1 a positive pulse. This loads the address low byte. 180 ATtiny261/461/861 2588C-AVR-10/09 ATtiny261/461/861 3. Load Data Low Byte: a. Set XA1, XA0 to "01". This enables data loading. b. Set DATA = Data low byte (0x00 - 0xFF). c. Give XTAL1 a positive pulse. This loads the data byte. 4. Load Data High Byte: a. Set BS1 to "1". This selects high data byte. b. Keep XA1, XA0 at "01". This enables data loading. c. Set DATA = Data high byte (0x00 - 0xFF). d. Give XTAL1 a positive pulse. This loads the data byte. 5. Repeat steps 2 to 4 until the entire buffer is filled or until all data within the page is loaded. 6. Load Address High byte: a. Set XA1, XA0 to "00". This enables address loading. b. Set BS1 to "1". This selects high address. c. Set DATA = Address high byte (0x00 - 0xFF). d. Give XTAL1 a positive pulse. This loads the address high byte. 7. Program Page: a. Give WR a negative pulse. This starts programming of the entire page of data. RDY/BSY goes low. b. Wait until RDY/BSY goes high. 8. Repeat steps 2 to 7 until the entire Flash is programmed or until all data has been programmed. 9. End Page Programming: a. Set XA1, XA0 to "10". This enables command loading. b. Set DATA to "0000 0000". This is the command for No Operation. c. Give XTAL1 a positive pulse. This loads the command, and the internal write signals are reset. While the lower bits in the address are mapped to words within the page, the higher bits address the pages within the FLASH. This is illustrated in Figure 18-4. Note that if less than eight bits are required to address words in the page (pagesize < 256), the most significant bit(s) in the address low byte are used to address the page when performing a Page Write. 181 2588C-AVR-10/09 Figure 18-4. Addressing the Flash Which is Organized in Pages PCMSB PROGRAM COUNTER PAGEMSB PCPAGE PCWORD PAGE ADDRESS WITHIN THE FLASH WORD ADDRESS WITHIN A PAGE PROGRAM MEMORY PAGE PAGE PCWORD[PAGEMSB:0]: 00 INSTRUCTION WORD 01 02 PAGEEND Note: PCPAGE and PCWORD are listed in Table 18-7 on page 173. In the figure below, "XX" means don't care. The numbers in the figure refer to the programming description above. WR Figure 18-5. Flash Programming Waveforms 8 5 STEP DATA 1 2 3 4 2 3 4 6 7 9 0x10 ADDR. LOW DATA LOW DATA HIGH ADDR. LOW DATA LOW DATA HIGH ADDR. HIGH XXX 0x00 XA1 / BS2 XA0 PAGEL / BS1 XTAL1 WR RDY / BSY RESET +12V OE 18.7.6 182 Programming the EEPROM The EEPROM is organized in pages, see Table 18-8 on page 173. When programming the EEPROM, the program data is latched into a page buffer. This allows one page of data to be ATtiny261/461/861 2588C-AVR-10/09 ATtiny261/461/861 programmed simultaneously. The programming algorithm for the EEPROM data memory is as follows (refer to "Programming the Flash" on page 180 for details on Command, Address and Data loading): 1. A: Load Command "0001 0001". 2. G: Load Address High Byte (0x00 - 0xFF). 3. B: Load Address Low Byte (0x00 - 0xFF). 4. C: Load Data (0x00 - 0xFF). 5. E: Latch data (give PAGEL a positive pulse). 6. K: Repeat 3 through 5 until the entire buffer is filled. 7. L: Program EEPROM page a. Set BS to "0". b. Give WR a negative pulse. This starts programming of the EEPROM page. RDY/BSY goes low. c. Wait until to RDY/BSY goes high before programming the next page (See Figure 18-6 for signal waveforms). Figure 18-6. Programming the EEPROM Waveforms K DATA A G 0x11 ADDR. HIGH B ADDR. LOW C DATA E XX B ADDR. LOW C DATA E L XX XA1/BS2 XA0 PAGEL/BS1 XTAL1 WR RDY/BSY RESET +12V OE 18.7.7 Reading the Flash The algorithm for reading the Flash memory is as follows (refer to "Programming the Flash" on page 180 for details on Command and Address loading): 1. A: Load Command "0000 0010". 2. G: Load Address High Byte (0x00 - 0xFF). 3. B: Load Address Low Byte (0x00 - 0xFF). 4. Set OE to "0", and BS1 to "0". The Flash word low byte can now be read at DATA. 5. Set BS to "1". The Flash word high byte can now be read at DATA. 6. Set OE to "1". 183 2588C-AVR-10/09 18.7.8 Reading the EEPROM The algorithm for reading the EEPROM memory is as follows (refer to "Programming the Flash" on page 180 for details on Command and Address loading): 1. A: Load Command "0000 0011". 2. G: Load Address High Byte (0x00 - 0xFF). 3. B: Load Address Low Byte (0x00 - 0xFF). 4. Set OE to "0", and BS1 to "0". The EEPROM Data byte can now be read at DATA. 5. Set OE to "1". 18.7.9 Programming the Fuse Low Bits The algorithm for programming the Fuse Low bits is as follows (refer to "Programming the Flash" on page 180 for details on Command and Data loading): 1. A: Load Command "0100 0000". 2. C: Load Data Low Byte. Bit n = "0" programs and bit n = "1" erases the Fuse bit. 3. Give WR a negative pulse and wait for RDY/BSY to go high. 18.7.10 Programming the Fuse High Bits The algorithm for programming the Fuse High bits is as follows (refer to "Programming the Flash" on page 180 for details on Command and Data loading): 1. A: Load Command "0100 0000". 2. C: Load Data Low Byte. Bit n = "0" programs and bit n = "1" erases the Fuse bit. 3. Set BS1 to "1" and BS2 to "0". This selects high data byte. 4. Give WR a negative pulse and wait for RDY/BSY to go high. 5. Set BS1 to "0". This selects low data byte. 18.7.11 Programming the Extended Fuse Bits The algorithm for programming the Extended Fuse bits is as follows (refer to "Programming the Flash" on page 180 for details on Command and Data loading): 1. 1. A: Load Command "0100 0000". 2. 2. C: Load Data Low Byte. Bit n = "0" programs and bit n = "1" erases the Fuse bit. 3. 3. Set BS1 to "0" and BS2 to "1". This selects extended data byte. 4. 4. Give WR a negative pulse and wait for RDY/BSY to go high. 5. 5. Set BS2 to "0". This selects low data byte. 184 ATtiny261/461/861 2588C-AVR-10/09 ATtiny261/461/861 Figure 18-7. Programming the FUSES Waveforms Write Fuse Low byte DATA A C 0x40 DATA XX Write Fuse high byte A C 0x40 DATA XX Write Extended Fuse byte A C 0x40 DATA XX XA1/BS2 XA0 PAGEL/BS1 XTAL1 WR RDY/BSY RESET +12V OE 18.7.12 Programming the Lock Bits The algorithm for programming the Lock bits is as follows (refer to "Programming the Flash" on page 180 for details on Command and Data loading): 1. A: Load Command "0010 0000". 2. C: Load Data Low Byte. Bit n = "0" programs the Lock bit. If LB mode 3 is programmed (LB1 and LB2 is programmed), it is not possible to program the Boot Lock bits by any External Programming mode. 3. Give WR a negative pulse and wait for RDY/BSY to go high. The Lock bits can only be cleared by executing Chip Erase. 18.7.13 Reading the Fuse and Lock Bits The algorithm for reading the Fuse and Lock bits is as follows (refer to "Programming the Flash" on page 180 for details on Command loading): 1. A: Load Command "0000 0100". 2. Set OE to "0", BS2 to "0" and BS1 to "0". The status of the Fuse Low bits can now be read at DATA ("0" means programmed). 3. Set OE to "0", BS2 to "1" and BS1 to "1". The status of the Fuse High bits can now be read at DATA ("0" means programmed). 4. Set OE to "0", BS2 to "1", and BS1 to "0". The status of the Extended Fuse bits can now be read at DATA ("0" means programmed). 5. Set OE to "0", BS2 to "0" and BS1 to "1". The status of the Lock bits can now be read at DATA ("0" means programmed). 6. Set OE to "1". 185 2588C-AVR-10/09 Figure 18-8. Mapping Between BS1, BS2 and the Fuse and Lock Bits During Read 0 Fuse Low Byte 0 Extended Fuse Byte 1 DATA BS2 0 Lock Bits 1 Fuse High Byte 1 BS1 BS2 18.7.14 Reading the Signature Bytes The algorithm for reading the Signature bytes is as follows (refer to "Programming the Flash" on page 180 for details on Command and Address loading): 1. A: Load Command "0000 1000". 2. B: Load Address Low Byte (0x00 - 0x02). 3. Set OE to "0", and BS to "0". The selected Signature byte can now be read at DATA. 4. Set OE to "1". 18.7.15 Reading the Calibration Byte The algorithm for reading the Calibration byte is as follows (refer to "Programming the Flash" on page 180 for details on Command and Address loading): 1. A: Load Command "0000 1000". 2. B: Load Address Low Byte, 0x00. 3. Set OE to "0", and BS1 to "1". The Calibration byte can now be read at DATA. 4. Set OE to "1". 186 ATtiny261/461/861 2588C-AVR-10/09 ATtiny261/461/861 19. Electrical Characteristics 19.1 Absolute Maximum Ratings* Operating Temperature.................................. -55C to +125C *NOTICE: Storage Temperature ..................................... -65C to +150C Voltage on any Pin except RESET with respect to Ground ................................-0.5V to VCC+0.5V Voltage on RESET with respect to Ground......-0.5V to +13.0V Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Maximum Operating Voltage ............................................ 6.0V DC Current per I/O Pin ............................................... 40.0 mA DC Current VCC and GND Pins................................ 200.0 mA 19.2 DC Characteristics Table 19-1. Symbol VIL VIH DC Characteristics. TA = -40C to 85C, VCC = 1.8V to 5.5V (unless otherwise noted). Parameter Condition Input Low-voltage Input High-voltage (4) Min (1)(2) Typ (1) Max (1)(3) Units Except XTAL1 and RESET pins -0.5 0.2VCC V XTAL1 pin, External Clock Selected -0.5 0.1VCC V RESET pin -0.5 0.2VCC V RESET pin as I/O -0.5 0.2VCC V Except XTAL1 and RESET pins 0.7VC VCC +0.5 V XTAL1 pin, External Clock Selected 0.8VCC VCC +0.5 V RESET pin 0.9VCC VCC +0.5 V RESET pin as I/O 0.7VCC VCC +0.5 V 0.6 0.5 V V VOL Output Low Voltage (Except Reset pin) (6) IOL = 10 mA, VCC = 5V IOL = 5 mA, VCC = 3V VOH Output High-voltage (5) (Except Reset pin) (6) IOH = -10 mA, VCC = 5V IOH = -5 mA, VCC = 3V IIL Input Leakage Current I/O Pin Vcc = 5.5V, pin low (absolute value) <0.05 1 A IIH Input Leakage Current I/O Pin Vcc = 5.5V, pin high (absolute value) <0.05 1 A RRST Reset Pull-up Resistor 30 60 k RPU I/O Pin Pull-up Resistor 20 50 k 4.3 2.5 V V 187 2588C-AVR-10/09 Table 19-1. Symbol DC Characteristics. TA = -40C to 85C, VCC = 1.8V to 5.5V (unless otherwise noted). Parameter Min (1)(2) Typ (1) Max (1)(3) Units (7) 0.4 0.6 mA (7) 2 3 mA (7) Active 8MHz, VCC = 5V 6 9 mA Idle 1MHz, VCC = 2V(7) 0.1 0.3 mA Idle 4MHz, VCC = 3V(7) 0.4 1 mA 1.5 3 mA 4 10 A 0.15 2 A Condition Active 1MHz, VCC = 2V Active 4MHz, VCC = 3V Power Supply Current ICC (7) Idle 8MHz, VCC = 5V (8) Power-down mode Notes: WDT enabled, VCC = 3V WDT disabled, VCC = 3V(8) 1. All DC Characteristics contained in this data sheet are based on simulation and characterization of other AVR microcontrollers manufactured in the same process technology. These values are preliminary values representing design targets, and will be updated after characterization of actual silicon. 2. "Min" means the lowest value where the pin is guaranteed to be read as high. 3. "Max" means the highest value where the pin is guaranteed to be read as low. 4. Although each I/O port can sink more than the test conditions (10 mA at VCC = 5V, 5 mA at VCC = 3V) under steady state conditions (non-transient), the sum of all IOL (for all ports) should not exceed 60 mA. If IOL exceeds the test conditions, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test condition. 5. Although each I/O port can source more than the test conditions (10 mA at VCC = 5V, 5 mA at VCC = 3V) under steady state conditions (non-transient), the sum of all IOH (for all ports) should not exceed 60 mA. If IOH exceeds the test condition, VOH may exceed the related specification. Pins are not guaranteed to source current greater than the listed test condition. 6. The RESET pin must tolerate high voltages when entering and operating in programming modes and, as a consequence, has a weak drive strength as compared to regular I/O pins. See Figure 20-23, Figure 20-24, Figure 20-25, and Figure 20-26 (starting on page 209). 7. Values using methods described in "Minimizing Power Consumption" on page 37. Power Reduction is enabled (PRR = 0xFF) and there is no I/O drive. 8. BOD Disabled. 19.3 Speed Grades The maximum operating frequency of the device depends on VCC. As shown in Figure 19-1 and Figure 19-2, the maximum frequency vs. VCC relationship is linear between 1.8V < VCC < 2.7V and between 2.7V < VCC < 4.5V. Figure 19-1. Maximum Frequency vs. VCC (ATtiny261V/461V/861V) 10 MHz Safe Operating Area 4 MHz 1.8V 188 2.7V 5.5V ATtiny261/461/861 2588C-AVR-10/09 ATtiny261/461/861 Figure 19-2. Maximum Frequency vs. VCC (ATtiny261/461/861) 20 MHz 10 MHz Safe Operating Area 2.7V 19.4 4.5V 5.5V Clock Characteristics It is possible to manually calibrate the internal oscillator to be more accurate than default factory calibration. Note that the oscillator frequency depends on temperature and voltage. Voltage and temperature characteristics can be found in Figure 20-38 on page 217 and Figure 20-39 on page 217. Table 19-2. Calibration Accuracy of Internal RC Oscillator Calibration Method Target Frequency VCC Temperature Accuracy at given voltage & temperature (1) 8.0 MHz 3V 25C 10% Fixed frequency within: 7.3 - 8.1 MHz Fixed voltage within: 1.8V - 5.5V(2) 2.7V - 5.5V(3) Fixed temperature within: -40C - 85C 1% Factory Calibration User Calibration Notes: 1. Accuracy of oscillator frequency at calibration point (fixed temperature and fixed voltage). 2. Voltage range for ATtiny261V/461V/861V. 3. Voltage range for ATtiny261/461/861. Figure 19-3. External Clock Drive Waveforms V IH1 V IL1 189 2588C-AVR-10/09 Table 19-3. External Clock Drive Characteristics VCC = 1.8 - 5.5V VCC = 2.7 - 5.5V VCC = 4.5 - 5.5V Symbol Parameter 1/tCLCL Clock Frequency tCLCL Clock Period 250 100 50 ns tCHCX High Time 100 40 20 ns tCLCX Low Time 100 40 20 ns tCLCH Rise Time 2.0 1.6 0.5 s tCHCL Fall Time 2.0 1.6 0.5 s tCLCL Change in period from one clock cycle to the next 2 2 2 % 19.5 Max. Min. Max. Min. Max. Units 0 4 0 10 0 20 MHz System and Reset Characteristics Table 19-4. Symbol Reset, Brown-out, and Internal Voltage Characteristics Parameter VRST RESET Pin Threshold Voltage tRST Minimum pulse width on RESET Pin (1) Condition (1) Min Typ 0.2 VCC VCC = 3V Max Units 0.9 VCC V 2.5 s Brown-out Detector Hysteresis (1) 50 mV tBOD Min Pulse Width on Brown-out Reset (1) 2 s VBG Internal bandgap reference voltage VCC = 2.7V TA = 25C tBG Internal bandgap reference start-up time (1) IBG Internal bandgap reference current consumption (1) VHYST Notes: 19.5.1 Min. 1.0 1.1 1.2 V VCC = 5V TA = 25C 40 70 s VCC = 5V TA = 25C 15 A 1. Not tested. Values are guidelines, only. Power-On Reset Table 19-5. Symbol VPOR Characteristics of Power-On Reset. TA = -40 - 85C Parameter Release threshold of power-on reset (2) VPOA Activation threshold of power-on reset SRON Power-on slope rate Note: (3) Min(1) Typ(1) Max(1) Units 0.7 1.0 1.4 V 0.05 0.9 1.3 V 4.5 V/ms 0.01 1. Not tested. Values are guidelines, only 2. Threshold where device is released from reset when voltage is rising 3. The power-on reset will not work unless the supply voltage has been below VPOA 190 ATtiny261/461/861 2588C-AVR-10/09 ATtiny261/461/861 19.5.2 Brown-Out Detection Table 19-6. BODLEVEL Fuse Coding(1) BODLEVEL [2:0] Fuses Min VBOT 111 Max VBOT Units BOD Disabled 110 1.7 1.8 2.0 101 2.5 2.7 2.9 100 4.1 4.3 4.5 0XX Note: Typ VBOT V Reserved 1. VBOT may be below nominal minimum operating voltage for some devices. For devices where this is the case, the device is tested down to VCC = VBOT during the production test. This guarantees that a Brown-out Reset will occur before VCC drops to a voltage where correct operation of the microcontroller is no longer guaranteed. 191 2588C-AVR-10/09 19.6 ADC Characteristics - Preliminary Data Table 19-7. Symbol ADC Characteristics, Single Ended Channels. T = -40C - 85C Parameter Condition Min(1) Typ(1) Resolution Absolute accuracy (Including INL, DNL, and Quantization, Gain and Offset Errors) Max(1) Units 10 Bits VREF = 4V, VCC = 4V, ADC clock = 200 kHz 2 LSB VREF = 4V, VCC = 4V, ADC clock = 1 MHz 3 LSB VREF = 4V, VCC = 4V, ADC clock = 200 kHz Noise Reduction Mode 1.5 LSB VREF = 4V, VCC = 4V, ADC clock = 1 MHz Noise Reduction Mode 2.5 LSB Integral Non-Linearity (INL) (Accuracy after Offset and Gain Calibration) VREF = 4V, VCC = 4V, ADC clock = 200 kHz 1 LSB Differential Non-linearity (DNL) VREF = 4V, VCC = 4V, ADC clock = 200 kHz 0.5 LSB Gain Error VREF = 4V, VCC = 4V, ADC clock = 200 kHz 2.5 LSB Offset Error VREF = 4V, VCC = 4V, ADC clock = 200 kHz 1.5 LSB Conversion Time Free Running Conversion 13 260 s 50 1000 kHz VCC - 0.3 VCC + 0.3 V Single Ended Conversions 2.0 AVCC V Differential Conversions 2.0 AVCC - 1.0 V GND VREF 0 AVCC (2) Clock Frequency AVCC Analog Supply Voltage AREF External Voltage Reference VIN Input Voltage Single Ended Conversions Differential Conversions Single Ended Conversions 38.5 Input Bandwidth kHz Differential Conversions Internal 1.1V Reference VINT Internal 2.56V Reference V (2) 4 1.0 1.1 1.2 V 2.3 2.56 2.8 V RREF Reference Input Resistance TBD k RAIN Analog Input Resistance 100 M ADC Conversion Output Note: 0 1023 LSB 1. Values are preliminary. 2. VDIFF must be below VREF. 3. Not tested in production. 192 ATtiny261/461/861 2588C-AVR-10/09 ATtiny261/461/861 19.7 Serial Programming Characteristics Figure 19-4. Serial Programming Waveforms SERIAL DATA INPUT (MOSI) MSB LSB SERIAL DATA OUTPUT (MISO) MSB LSB SERIAL CLOCK INPUT (SCK) SAMPLE Figure 19-5. Serial Programming Timing MOSI SCK tSLSH tSHOX tOVSH tSHSL MISO tSLIV Table 19-8. Serial Programming Characteristics, TA = -40C to 85C, VCC = 1.8 - 5.5V (Unless Otherwise Noted) Symbol Parameter 1/tCLCL Oscillator Frequency (ATtiny261V/461V/861V) tCLCL Oscillator Period (ATtiny261V/461V/861V) Min Typ 0 Max Units 4 MHz 250 ns 1/tCLCL Oscillator Frequency (ATtiny261/461/861, VCC = 4.5V - 5.5V) 0 tCLCL Oscillator Period (ATtiny261/461/861, VCC = 4.5V - 5.5V) 50 ns tSHSL SCK Pulse Width High 2 tCLCL(1) ns tSLSH SCK Pulse Width Low 2 tCLCL(1) ns tOVSH MOSI Setup to SCK High tCLCL ns tSHOX MOSI Hold after SCK High 2 tCLCL ns tSLIV SCK Low to MISO Valid Note: TBD 20 TBD TBD MHz ns 1. 2 tCLCL for fck < 12 MHz, 3 tCLCL for fck >= 12 MHz 193 2588C-AVR-10/09 19.8 Parallel Programming Characteristics Figure 19-6. Parallel Programming Timing, Including some General Timing Requirements tXLWL tXHXL XTAL1 tDVXH tXLDX tBVPH tPLBX t BVWL Data & Contol (DATA, XA0, XA1/BS2, PAGEL/BS1) tWLBX tWLWH WR tPLWL WLRL RDY/BSY tWLRH Figure 19-7. Parallel Programming Timing, Loading Sequence with Timing Requirements LOAD ADDRESS (LOW BYTE) LOAD DATA (LOW BYTE) LOAD DATA (HIGH BYTE) LOAD ADDRESS (LOW BYTE) t XLXH XTAL1 PAGEL/BS1 DATA ADDR0 (Low Byte) DATA (Low Byte) DATA (High Byte) ADDR1 (Low Byte) XA0 XA1/BS2 Note: 194 The timing requirements shown in Figure 19-6 (i.e., tDVXH, tXHXL, and tXLDX) also apply to loading operation. ATtiny261/461/861 2588C-AVR-10/09 ATtiny261/461/861 Figure 19-8. Parallel Programming Timing, Reading Sequence (within the Same Page) with Timing Requirements LOAD ADDRESS (LOW BYTE) READ DATA (LOW BYTE) READ DATA (HIGH BYTE) LOAD ADDRESS (LOW BYTE) tXLOL XTAL1 tBVDV PAGEL/BS1 tOLDV OE DATA tOHDZ ADDR0 (Low Byte) ADDR1 (Low Byte) DATA (High Byte) DATA (Low Byte) XA0 XA1/BS2 Note: The timing requirements shown in Figure 19-6 (i.e., tDVXH, tXHXL, and tXLDX) also apply to reading operation. Table 19-9. Parallel Programming Characteristics, VCC = 5V 10% Symbol Parameter Min VPP Programming Enable Voltage 11.5 IPP Programming Enable Current tDVXH Data and Control Valid before XTAL1 High 67 ns tXLXH XTAL1 Low to XTAL1 High 200 ns tXHXL XTAL1 Pulse Width High 150 ns tXLDX Data and Control Hold after XTAL1 Low 67 ns tXLWL XTAL1 Low to WR Low 0 ns tBVPH BS1 Valid before PAGEL High 67 ns tPHPL PAGEL Pulse Width High 150 ns tPLBX BS1 Hold after PAGEL Low 67 ns tWLBX BS2/1 Hold after WR Low 67 ns tPLWL PAGEL Low to WR Low 67 ns tBVWL BS1 Valid to WR Low 67 ns tWLWH WR Pulse Width Low 150 ns tWLRL WR Low to RDY/BSY Low tWLRH WR Low to RDY/BSY High(1) (2) tWLRH_CE WR Low to RDY/BSY High for Chip Erase tXLOL XTAL1 Low to OE Low Typ Max Units 12.5 V 250 A 0 1 s 3.7 4.5 ms 7.5 9 ms 0 ns 195 2588C-AVR-10/09 Table 19-9. Parallel Programming Characteristics, VCC = 5V 10% (Continued) Symbol Parameter tBVDV BS1 Valid to DATA valid tOLDV tOHDZ Notes: 1. Min Max Units 250 ns OE Low to DATA Valid 250 ns OE High to DATA Tri-stated 250 ns 0 Typ tWLRH is valid for the Write Flash, Write EEPROM, Write Fuse bits and Write Lock bits commands. 2. tWLRH_CE is valid for the Chip Erase command. 196 ATtiny261/461/861 2588C-AVR-10/09 ATtiny261/461/861 20. Typical Characteristics The data contained in this section is largely based on simulations and characterization of similar devices in the same process and design methods. Thus, the data should be treated as indications of how the part will behave. The following charts show typical behavior. These figures are not tested during manufacturing. During characterisation devices are operated at frequencies higher than test limits but they are not guaranteed to function properly at frequencies higher than the ordering code indicates. All current consumption measurements are performed with all I/O pins configured as inputs and with internal pull-ups enabled. Current consumption is a function of several factors such as operating voltage, operating frequency, loading of I/O pins, switching rate of I/O pins, code executed and ambient temperature. The dominating factors are operating voltage and frequency. A sine wave generator with rail-to-rail output is used as clock source but current consumption in Power-Down mode is independent of clock selection. The difference between current consumption in Power-Down mode with Watchdog Timer enabled and Power-Down mode with Watchdog Timer disabled represents the differential current drawn by the Watchdog Timer. The current drawn from pins with a capacitive load may be estimated (for one pin) as follows: I CP V CC x C L x f SW where VCC = operating voltage, CL = load capacitance and fSW = average switching frequency of I/O pin. 20.1 Supply Current of I/O modules The tables and formulas below can be used to calculate the additional current consumption for the different I/O modules in Active and Idle mode. The enabling or disabling of the I/O modules are controlled by the Power Reduction Register. See "PRR - Power Reduction Register" on page 39 for details. Table 20-1. Additional Current Consumption for the different I/O modules (absolute values). Typical numbers PRR bit VCC = 2V, f = 1MHz VCC = 3V, f = 4MHz VCC = 5V, f = 8MHz PRTIM1 65 uA 423 uA 1787 uA PRTIM0 7 uA 39 uA 165 uA PRUSI 5 uA 25 uA 457 uA PRADC 18 uA 111 uA 102 uA Table 20-2 below can be used for calculating typical current consumption for other supply voltages and frequencies than those mentioned in the Table 20-1 above. 197 2588C-AVR-10/09 Table 20-2. Additional Current Consumption (percentage) in Active and Idle mode. PRR bit Additional Current consumption compared to Active with external clock (see Figure 20-1 on page 198 and Figure 20-2 on page 199) Additional Current consumption compared to Idle with external clock (see Figure 20-6 on page 201 and Figure 20-7 on page 201) PRTIM1 26.9 % 103.7 % PRTIM0 2.6 % 10.0 % PRUSI 1.7 % 6.5 % PRADC 7.1 % 27.3 % It is possible to calculate the typical current consumption based on the numbers from Table 20-1 for other VCC and frequency settings than listed in Table 20-2. 20.1.0.1 Example Calculate the expected current consumption in idle mode with TIMER0, ADC, and USI enabled at VCC = 2.0V and F = 1MHz. From Table 20-2, third column, we see that we need to add 10% for the TIMER0, 27.3 % for the ADC, and 6.5 % for the USI module. Reading from Figure 20-6 on page 201, we find that the idle current consumption is ~0,085 mA at VCC = 2.0V and F=1MHz. The total current consumption in idle mode with TIMER0, ADC, and USI enabled, gives: I CC total 0.085mA * ( 1 + 0.10 + 0.273 + 0.065 ) 0.122mA 20.2 Active Supply Current Figure 20-1. Active Supply Current vs. Low Frequency (0.1 - 1.0 MHz) ACTIVE SUPPLY CURRENT vs. LOW FREQUENCY 0.1 - 1.0 MHZ 1,2 5.5 V 1 5.0 V 4.5 V ICC (mA) 0,8 4.0 V 0,6 3.3 V 2.7 V 0,4 1.8 V 0,2 0 0 0,1 0,2 0,3 0,4 0,5 0,6 0,7 0,8 0,9 1 Frequency (MHz) 198 ATtiny261/461/861 2588C-AVR-10/09 ATtiny261/461/861 Figure 20-2. Active Supply Current vs. Frequency (1 - 20 MHz) ACTIVE SUPPLY CURRENT vs. FREQUENCY 1 - 20 MHz 16 ICC (mA) 14 5.5 V 12 5.0 V 10 4.5 V 8 4.0 V 6 3.3 V 4 2.7 V 2 1.8 V 0 0 2 4 6 8 10 12 14 16 18 20 Frequency (MHz) Figure 20-3. Active Supply Current vs. VCC (Internal RC Oscillator, 8 MHz) ACTIVE SUPPLY CURRENT vs. VCC INTERNAL RC OSCILLATOR, 8 MHz 7 85 C 25 C 6 -40 C I CC (mA) 5 4 3 2 1 0 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) 199 2588C-AVR-10/09 Figure 20-4. Active Supply Current vs. VCC (Internal RC Oscillator, 1 MHz) ACTIVE SUPPLY CURRENT vs. VCC INTERNAL RC OSCILLATOR, 1 MHz 1,6 85 C 25 C 1,4 I CC (mA) 1,2 -40 C 1 0,8 0,6 0,4 0,2 0 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) Figure 20-5. Active Supply Current vs. VCC (Internal RC Oscillator, 128 kHz) ACTIVE SUPPLY CURRENT vs. VCC INTERNAL RC OSCILLATOR, 128 kHz 0,3 85 C 0,25 -40 C ICC (mA) 0,2 25 C 0,15 0,1 0,05 0 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) 200 ATtiny261/461/861 2588C-AVR-10/09 ATtiny261/461/861 20.3 Idle Supply Current Figure 20-6. Idle Supply Current vs. Low Frequency (0.1 - 1.0 MHz) IDLE SUPPLY CURRENT vs. LOW FREQUENCY 0.1 - 1.0 MHz 0,3 5.5 V 0,25 I CC (mA) 5.0 V 0,2 4.5 V 4.0 V 0,15 3.3 V 2.7 V 0,1 1.8 V 0,05 0 0 0,1 0,2 0,3 0,4 0,5 0,6 0,7 0,8 0,9 1 Frequency (MHz) Figure 20-7. Idle Supply Current vs. Frequency (1 - 20 MHz) IDLE SUPPLY CURRENT vs. FREQUENCY 1 - 20 MHz ICC (mA) 4,5 4 5.5 V 3,5 5.0 V 3 4.5 V 2,5 4.0 V 2 1,5 3.3 V 1 2.7 V 0,5 1.8 V 0 0 2 4 6 8 10 12 14 16 18 20 Frequency (MHz) 201 2588C-AVR-10/09 Figure 20-8. Idle Supply Current vs. VCC (Internal RC Oscillator, 8 MHz) IDLE SUPPLY CURRENT vs. VCC INTERNAL RC OSCILLATOR, 8 MHz 2,5 85 C 25 C -40 C ICC (mA) 2 1,5 1 0,5 0 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) Figure 20-9. Idle Supply Current vs. VCC (Internal RC Oscillator, 1 MHz) IDLE SUPPLY CURRENT vs. VCC INTERNAL RC OSCILLATOR, 1 MHz 0,7 0,6 85 C 25 C -40 C I CC (mA) 0,5 0,4 0,3 0,2 0,1 0 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) 202 ATtiny261/461/861 2588C-AVR-10/09 ATtiny261/461/861 Figure 20-10. Idle Supply Current vs. VCC (Internal RC Oscillator, 128 kHz) IDLE SUPPLY CURRENT vs. VCC INTERNAL RC OSCILLATOR, 128 kHz 0,2 85 C 0,18 0,16 I CC (mA) 0,14 0,12 0,1 25 C 0,08 -40 C 0,06 0,04 0,02 0 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) 20.4 Power-down Supply Current Figure 20-11. Power-down Supply Current vs. VCC (Watchdog Timer Disabled) POWER-DOWN SUPPLY CURRENT vs. VCC WATCHDOG TIMER DISABLED 1,6 1,4 85 C 1,2 ICC (uA) 1 0,8 -40 C 25 C 0,6 0,4 0,2 0 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) 203 2588C-AVR-10/09 Figure 20-12. Power-down Supply Current vs. VCC (Watchdog Timer Enabled) POWER-DOWN SUPPLY CURRENT vs. VCC WATCHDOG TIMER ENABLED 10 9 -40 C 85 C 8 25 C I CC (uA) 7 6 5 4 3 2 1 0 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) 20.5 Pin Pull-up Figure 20-13. I/O Pin pull-up Resistor Current vs. Input Voltage (VCC = 1.8V) I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE VCC = 1.8V 60 50 IOP (uA) 40 30 20 25 C 10 85 C -40 C 0 0 0,2 0,4 0,6 0,8 1 1,2 1,4 1,6 1,8 2 VOP (V) 204 ATtiny261/461/861 2588C-AVR-10/09 ATtiny261/461/861 Figure 20-14. I/O Pin pull-up Resistor Current vs. Input Voltage (VCC = 2.7V) I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE VCC = 2.7V 90 80 70 IOP (uA) 60 50 40 30 25 C 20 85 C 10 -40 C 0 0 0,5 1 1,5 2 2,5 3 VOP (V) Figure 20-15. I/O Pin pull-up Resistor Current vs. Input Voltage (VCC = 5V) I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE VCC = 5V 160 140 120 IOP (uA) 100 80 60 40 25 C 85 C -40 C 20 0 0 1 2 3 4 5 6 VOP (V) 205 2588C-AVR-10/09 Figure 20-16. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 1.8V) RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE VCC = 1.8V 40 35 IRESET(uA) 30 25 20 15 10 25 C 5 -40 C 85 C 0 0 0,2 0,4 0,6 0,8 1 1,2 1,4 1,6 1,8 2 VRESET(V) Figure 20-17. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 2.7V) RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE VCC = 2.7V 70 60 IRESET(uA) 50 40 30 20 25 C 10 -40 C 85 C 0 0 0,5 1 1,5 2 2,5 3 VRESET(V) 206 ATtiny261/461/861 2588C-AVR-10/09 ATtiny261/461/861 Figure 20-18. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 5V) RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE VCC = 5V 120 100 IRESET(uA) 80 60 40 25 C 20 -40 C 85 C 0 0 1 2 3 4 5 6 VRESET(V) 20.6 Pin Driver Strength Figure 20-19. I/O Pin Output Voltage vs. Sink Current (VCC = 3V) I/O PIN OUTPUT VOLTAGE vs. SINK CURRENT VCC = 3V 0,9 85 C 0,8 0,7 25 C VOL (V) 0,6 -40 C 0,5 0,4 0,3 0,2 0,1 0 0 5 10 15 20 25 IOL (mA) 207 2588C-AVR-10/09 Figure 20-20. I/O Pin Output Voltage vs. Sink Current (VCC = 5V) I/O PIN OUTPUT VOLTAGE vs. SINK CURRENT VCC = 5V 0,6 85 C 0,5 25 C VOL (V) 0,4 -40 C 0,3 0,2 0,1 0 0 5 10 15 20 25 IOL (mA) Figure 20-21. I/O Pin Output Voltage vs. Source Current (VCC = 3V) I/O PIN OUTPUT VOLTAGE vs. SOURCE CURRENT VCC = 3V 3,1 2,9 2,7 VOH (V) 2,5 -40 C 2,3 25 C 2,1 85 C 1,9 1,7 1,5 0 5 10 15 20 25 IOH (mA) 208 ATtiny261/461/861 2588C-AVR-10/09 ATtiny261/461/861 Figure 20-22. I/O Pin Output Voltage vs. Source Current (VCC = 5V) I/O PIN OUTPUT VOLTAGE vs. SOURCE CURRENT VCC = 5V 5 VOH (V) 4,8 4,6 -40 C 25 C 4,4 85 C 4,2 4 0 5 10 15 20 25 IOH (mA) Figure 20-23. Reset Pin Output Voltage vs. Sink Current (VCC = 3V) RESET AS I/O PIN OUTPUT VOLTAGE vs. SINK CURRENT VCC = 3V 1.5 85 C VOL (V) 1 0 C -45 C 0.5 0 0 0.5 1 1.5 2 2.5 3 IOL (mA) 209 2588C-AVR-10/09 Figure 20-24. Reset Pin Output Voltage vs. Sink Current (VCC = 5V) RESET AS I/O PIN OUTPUT VOLTAGE vs. SINK CURRENT VCC = 5V 1 0.8 VOL (V) 0.6 85 C 0.4 0 C -45 C 0.2 0 0 0.5 1 1.5 2 2.5 3 IOL (mA) Figure 20-25. Reset Pin Output Voltage vs. Source Current (VCC = 3V) RESET AS I/O PIN OUTPUT VOLTAGE vs. SOURCE CURRENT VCC = 3V 3.5 3 VOH (V) 2.5 2 1.5 -45 C 25 C 85 C 1 0.5 0 0 0.5 1 1.5 2 IOH (mA) 210 ATtiny261/461/861 2588C-AVR-10/09 ATtiny261/461/861 Figure 20-26. Reset Pin Output Voltage vs. Source Current (VCC = 5V) RESET AS I/O PIN OUTPUT VOLTAGE vs. SOURCE CURRENT VCC = 5V 5 4.5 VOH (V) 4 3.5 3 -45 C 25 C 85 C 2.5 0 0.5 1 1.5 2 IOH (mA) 20.7 Pin Threshold and Hysteresis Figure 20-27. I/O Pin Input Threshold Voltage vs. VCC (VIH, I/O Pin Read as `1') I/O PIN INPUT THRESHOLD VOLTAGE vs. VCC VIH, IO PIN READ AS '1' 3,5 -40 C Threshold (V) 3 25 C 85 C 2,5 2 1,5 1 0,5 0 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) 211 2588C-AVR-10/09 Figure 20-28. I/O Pin Input Threshold Voltage vs. VCC (VIL, I/O Pin Read as `0') I/O PIN INPUT THRESHOLD VOLTAGE vs. VCC VIL, IO PIN READ AS '0' 3 85 C 25 C -40 C Threshold (V) 2,5 2 1,5 1 0,5 0 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) Figure 20-29. I/O Pin Input Hysteresis vs. VCC I/O PIN INPUT HYSTERESIS vs. VCC 0,7 Input Hysteresis (mV) 0,6 -40 C 25 C 85 C 0,5 0,4 0,3 0,2 0,1 0 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) 212 ATtiny261/461/861 2588C-AVR-10/09 ATtiny261/461/861 Figure 20-30. Reset Input Threshold Voltage vs. VCC (VIH, Reset Read as `1') RESET INPUT THRESHOLD VOLTAGE vs. VCC VIH, RESET READ AS '1' 3 85 C 25 C -40 C Threshold (V) 2,5 2 1,5 1 0,5 0 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) Figure 20-31. Reset Input Threshold Voltage vs. VCC (VIL, Reset Read as `0') RESET PIN AS I/O THRESHOLD VOLTAGE vs. VCC VIL, RESET READ AS '0' 2,5 85 C 25 C -40 C Threshold (V) 2 1,5 1 0,5 0 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) 213 2588C-AVR-10/09 Figure 20-32. Reset Pin input Hysteresis vs. VCC RESET PIN INPUT HYSTERESIS vs. VCC 1 0,9 Input Hysteresis (mV) 0,8 85 C 25 C -40 C 0,7 0,6 0,5 0,4 0,3 0,2 0,1 0 1,5 2 2,5 3 3,5 4 4,5 5 5,5 80 100 VCC (V) 20.8 BOD and Bandgap Figure 20-33. BOD Threshold vs. Temperature (BOD Level is 4.3V) BOD THRESHOLDS vs. TEMPERATURE BODLEVEL is 4.3V 4,5 4,45 Threshold (V) 4,4 4,35 Rising VCC 4,3 4,25 Falling VCC 4,2 4,15 4,1 -60 -40 -20 0 20 40 60 Temperature (C) 214 ATtiny261/461/861 2588C-AVR-10/09 ATtiny261/461/861 Figure 20-34. BOD Threshold vs. Temperature (BOD Level is 2.7V) BOD THRESHOLDS vs. TEMPERATURE BODLEVEL is 2.7V 2,9 2,85 Threshold (V) 2,8 Rising VCC 2,75 2,7 2,65 Falling VCC 2,6 2,55 2,5 -60 -40 -20 0 20 40 60 80 100 Temperature (C) Figure 20-35. BOD Threshold vs. Temperature (BOD Level is 1.8V) BOD THRESHOLDS vs. TEMPERATURE BODLEVEL is 1.8V 2 1,95 Threshold (V) 1,9 1,85 Rising VCC 1,8 Falling VCC 1,75 1,7 1,65 1,6 -60 -40 -20 0 20 40 60 80 100 Temperature (C) 215 2588C-AVR-10/09 Figure 20-36. Bandgap Voltage vs. Supply Voltage (VCC). BANDGAP VOLTAGE vs. VCC 1.08 85 C Bandgap Voltage ( V ) 1.07 25 C 1.06 -40 C 1.05 1.04 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC ( V ) 20.9 Internal Oscillator Speed Figure 20-37. Watchdog Oscillator Frequency vs. VCC WATCHDOG OSCILLATOR FREQUENCY vs. V CC 0,138 0,136 0,134 -40 C FRC (MHz) 0,132 0,13 25 C 0,128 0,126 0,124 0,122 85 C 0,12 0,118 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) 216 ATtiny261/461/861 2588C-AVR-10/09 ATtiny261/461/861 Figure 20-38. Calibrated 8.0 MHz RC Oscillator Frequency vs. VCC CALIBRATED 8.0 MHz RC OSCILLATOR FREQUENCY vs. VCC 9 8,8 8,6 85 C FRC (MHz) 8,4 8,2 25 C 8 7,8 -40 C 7,6 7,4 7,2 7 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) Figure 20-39. Calibrated 8.0 MHz RC Oscillator Frequency vs. Temperature CALIBRATED 8.0 MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE 9 8,8 8,6 5.0 V FRC (MHz) 8,4 8,2 3.0 V 8 7,8 7,6 7,4 7,2 7 -60 -40 -20 0 20 40 60 80 100 Temperature 217 2588C-AVR-10/09 Figure 20-40. Calibrated 8.0 MHz RC Oscillator Frequency vs. OSCCAL Value CALIBRATED 8.0 MHz RC OSCILLATOR FREQUENCY vs. OSCCAL VALUE 18 85 C 16 25 C 14 -40 C FRC (MHz) 12 10 8 6 4 2 0 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 OSCCAL (X1) 20.10 Current Consumption of Peripheral Units Figure 20-41. ADC Current vs. VCC (AREF = AVCC) ADC CURRENT vs. VCC AREF = AVCC 1000 900 25 C 800 ICC (uA) 700 600 500 400 300 200 100 0 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) 218 ATtiny261/461/861 2588C-AVR-10/09 ATtiny261/461/861 Figure 20-42. AREF External Reference Current vs. VCC AREF EXTERNAL REFERENCE CURRENT vs. VCC 180 25 C 150 ICC (uA) 120 90 60 30 0 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) Figure 20-43. Analog Comparator vs. VCC ANALOG COMPARATOR vs. VCC 160 140 120 ICC (uA) 100 25 C 80 60 40 20 0 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) 219 2588C-AVR-10/09 Figure 20-44. Brownout Detector Current vs. VCC BROWNOUT DETECTOR CURRENT vs. VCC 30 85 C 25 C 25 -40 C I CC (uA) 20 15 10 5 0 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) Figure 20-45. Programming Current vs. VCC PROGRAMMING CURRENT vs. VCC 16000 25 C 14000 12000 I CC (uA) 10000 8000 6000 4000 2000 0 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) 220 ATtiny261/461/861 2588C-AVR-10/09 ATtiny261/461/861 Figure 20-46. Watchdog Timer Current vs. VCC WATCHDOG TIMER CURRENT vs. VCC 10 -40 C 85 C 25 C 9 8 ICC (uA) 7 6 5 4 3 2 1 0 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) 20.11 Current Consumption in Reset and Reset Pulsewidth Figure 20-47. Reset Supply Current vs. Low Frequency (0.1 - 1.0 MHz, Excluding Current Through the Reset Pull-up) RESET SUPPLY CURRENT vs. Low Frequency 0.1 - 1.0 MHz, EXCLUDING CURRENT THROUGH THE RESET PULL-UP 0,14 5.5 V 0,12 5.0 V ICC (mA) 0,1 4.5 V 0,08 4.0 V 0,06 3.3 V 2.7 V 0,04 1.8 V 0,02 0 0 0,1 0,2 0,3 0,4 0,5 0,6 0,7 0,8 0,9 1 Frequency (MHz) 221 2588C-AVR-10/09 Figure 20-48. Reset Supply Current vs. Frequency (1 - 20 MHz, Excluding Current Through the Reset Pull-up) RESET SUPPLY CURRENT vs. VCC 1 - 20 MHz, EXCLUDING CURRENT THROUGH THE RESET PULLUP 2,5 5.5 V 5.0 V 2 ICC (mA) 4.5 V 1,5 4.0 V 1 3.3 V 0,5 2.7 V 1.8 V 0 0 2 4 6 8 10 12 14 16 18 20 Frequency (MHz) Figure 20-49. Minimum Reset Pulse Width vs. VCC MINIMUM RESET PULSE WIDTH vs. VCC 2500 Pulsewidth (ns) 2000 1500 1000 85 C 25 C -40 C 500 0 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) 222 ATtiny261/461/861 2588C-AVR-10/09 ATtiny261/461/861 21. Register Summary Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 0x3F (0x5F) 0x3E (0x5E) Bit 2 Bit 1 Bit 0 Page SREG I T H S V N Z C page 8 SPH - - - - - SP10 SP9 SP8 page 11 0x3D (0x5D) SPL SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 page 11 0x3C (0x5C) Reserved 0x3B (0x5B) GIMSK INT1 INT0 PCIE1 PCIE0 - - - - page 52 0x3A (0x5A) GIFR INTF1 INTF0 PCIF - - - - - page 53 0x39 (0x59) TIMSK OCIE1D OCIE1A OCIE1B OCIE0A OCIE0B TOIE1 TOIE0 TICIE0 page 86, page 123 0x38 (0x58) TIFR OCF1D OCF1A OCF1B OCF0A OCF0B TOV1 TOV0 ICF0 page 87, page 123 0x37 (0x57) SPMCSR - - - CTPB RFLB PGWRT PGERS SPMEN page 169 0x36 (0x56) PRR PRTIM1 PRTIM0 PRUSI PRADC page 37 0x35 (0x55) MCUCR - PUD SE SM1 SM0 - ISC01 ISC00 page 39, page 69, page 52 0x34 (0x54) MCUSR - - - - WDRF BORF EXTRF PORF page 47, 0x33 (0x53) TCCR0B - - - TSM PSR0 CS02 CS01 CS00 page 85 0x32 (0x52) TCNT0L Timer/Counter0 Counter Register Low Byte 0x31 (0x51) OSCCAL Oscillator Calibration Register 0x30 (0x50) TCCR1A COM1A1 COM1A0 COM1B1 PWM1X PSR1 DTPS11 - page 85 page 32 COM1B0 FOC1A FOC1B PWM1A PWM1B page 112 DTPS10 CS13 CS12 CS11 CS10 page 169 0x2F (0x4F) TCCR1B 0x2E (0x4E) TCNT1 Timer/Counter1 Counter Register page 121 0x2D (0x4D) OCR1A Timer/Counter1 Output Compare Register A page 121 0x2C (0x4C) OCR1B Timer/Counter1 Output Compare Register B page 122 0x2B (0x4B) OCR1C Timer/Counter1 Output Compare Register C page 122 0x2A (0x4A) OCR1D Timer/Counter1 Output Compare Register D 0x29 (0x49) PLLCSR LSM 0x28 (0x48) CLKPR CLKPCE 0x27 (0x47) TCCR1C COM1A1S COM1A0S COM1B1S 0x26 (0x46) TCCR1D FPIE1 FPEN1 FPNC1 0x25 (0x45) TC1H 0x24 (0x44) DT1 0x23 (0x43) PCMSK0 PCINT7 PCINT6 PCINT5 PCINT4 PCINT3 PCINT2 0x22 (0x42) PCMSK1 PCINT15 PCINT14 PCINT13 PCINT12 PCINT11 PCINT10 0x21 (0x41) WDTCR WDIF WDIE WDP3 WDCE WDE WDP2 WDP1 0x20 (0x40) DWDR 0x1F (0x3F) EEARH 0x1E (0x3E) EEARL 0x1D (0x3D) EEDR 0x1C (0x3C) EECR - - EEPM1 EEPM0 0x1B (0x3B) PORTA PORTA7 PORTA6 PORTA5 0x1A (0x3A) DDRA DDA7 DDA6 DDA5 0x19 (0x39) PINA PINA7 PINA6 0x18 (0x38) PORTB PORTB7 0x17 (0x37) DDRB 0x16 (0x36) DT1H3 DT1H2 DT1H1 page 122 PCKE PLLE PLOCK CLKPS3 CLKPS2 CLKPS1 CLKPS0 page 32 COM1B0S COM1D1 COM1D0 FOC1D PWM1D page 117 FPES1 FPAC1 FPF1 WGM11 WGM10 page 118 TC19 TC18 page 121 DT1L1 DT1L0 page 124 PCINT1 PCINT0 page 54 PCINT9 PCINT8 page 54 WDP0 page 47 DT1H0 DT1L3 DT1L2 DWDR[7:0] EEAR7 EEAR6 EEAR5 EEAR4 EEAR3 page 120 page 37 EEAR8 page 20 EEAR2 EEAR1 EEAR0 page 21 EERIE EEMPE EEPE EERE page 21 PORTA4 PORTA3 PORTA2 PORTA1 PORTA0 page 69 DDA4 DDA3 DDA2 DDA1 DDA0 page 69 PINA5 PINA4 PINA3 PINA2 PINA1 PINA0 page 70 PORTB6 PORTB5 PORTB4 PORTB3 PORTB2 PORTB1 PORTB0 page 70 DDB7 DDB6 DDB5 DDB4 DDB3 DDB2 DDB1 DDB0 page 70 PINB PINB7 PINB6 PINB5 PINB4 PINB3 PINB2 PINB1 PINB0 page 70 0x15 (0x35) TCCR0A TCW0 ICEN0 ICNC0 ICES0 ACIC0 CTC0 page 84 0x14 (0x34) TCNT0H Timer/Counter0 Counter Register High Byte page 86 0x13 (0x33) OCR0A Timer/Counter0 Output Compare Register A page 86 0x12 (0x32) OCR0B Timer/Counter0 Output Compare Register B 0x11 (0x31) USIPP EEPROM Data Register page 21 page 86 USIPOS page 136 0x10 (0x30) USIBR USI Buffer Register 0x0F (0x2F) USIDR USI Data Register 0x0E (0x2E) USISR USISIF USIOIF USIPF USIDC USICNT3 USICNT2 USICNT1 USICNT0 page 133 0x0D (0x2D) USICR USISIE USIOIE USIWM1 USIWM0 USICS1 USICS0 USICLK USITC page 134 0x0C (0x2C) GPIOR2 General Purpose I/O Register 2 page 22 0x0B (0x2B) GPIOR1 General Purpose I/O Register 1 page 23 0x0A (0x2A) GPIOR0 General Purpose I/O Register 0 0x09 (0x29) ACSRB HSEL HLEV page 133 page 132 page 23 ACM2 ACM1 ACM0 page 140 0x08 (0x28) ACSRA ACD ACBG ACO ACI ACIE ACME ACIS1 ACIS0 page 139 0x07 (0x27) ADMUX REFS1 REFS0 ADLAR MUX4 MUX3 MUX2 MUX1 MUX0 page 155 0x06 (0x26) ADCSRA ADEN ADSC ADATE ADIF ADIE ADPS2 ADPS1 ADPS0 page 159 0x05 (0x25) ADCH ADC Data Register High Byte 0x04 (0x24) ADCL ADC Data Register Low Byte 0x03 (0x23) ADCSRB BIN GSEL 0x02 (0x22) DIDR1 ADC10D ADC9D 0x01 (0x21) DIDR0 ADC6D ADC5D ADC4D ADC3D AREFD ADC2D ADC1D ADC0D page 162 0x00 (0x20) TCCR1E - - OC1OE5 OC1OE4 OC1OE3 OC1OE2 OC1OE1 OC1OE0 page 119 REFS2 ADC8D MUX5 page 160 page 160 ADTS2 ADTS1 ADTS0 ADC7D page 161 page 162 223 2588C-AVR-10/09 Note: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. 2. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. 3. Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI instructions will only operation the specified bit, and can therefore be used on registers containing such Status Flags. The CBI and SBI instructions work with registers 0x00 to 0x1F only. 224 ATtiny261/461/861 2588C-AVR-10/09 ATtiny261/461/861 22. Instruction Set Summary Mnemonics Operands Description Operation Flags #Clocks ARITHMETIC AND LOGIC INSTRUCTIONS ADD Rd, Rr Add two Registers Rd Rd + Rr Z,C,N,V,H ADC Rd, Rr Add with Carry two Registers Rd Rd + Rr + C Z,C,N,V,H 1 ADIW Rdl,K Add Immediate to Word Rdh:Rdl Rdh:Rdl + K Z,C,N,V,S 2 SUB Rd, Rr Subtract two Registers Rd Rd - Rr Z,C,N,V,H 1 SUBI Rd, K Subtract Constant from Register Rd Rd - K Z,C,N,V,H 1 SBC Rd, Rr Subtract with Carry two Registers Rd Rd - Rr - C Z,C,N,V,H 1 SBCI Rd, K Subtract with Carry Constant from Reg. Rd Rd - K - C Z,C,N,V,H 1 SBIW Rdl,K Subtract Immediate from Word Rdh:Rdl Rdh:Rdl - K Z,C,N,V,S 2 AND Rd, Rr Logical AND Registers Rd Rd * Rr Z,N,V 1 ANDI Rd, K Logical AND Register and Constant Rd Rd * K Z,N,V 1 OR Rd, Rr Logical OR Registers Rd Rd v Rr Z,N,V 1 ORI Rd, K Logical OR Register and Constant Rd Rd v K Z,N,V 1 EOR Rd, Rr Exclusive OR Registers Rd Rd Rr Z,N,V 1 1 COM Rd One's Complement Rd 0xFF - Rd Z,C,N,V 1 NEG Rd Two's Complement Rd 0x00 - Rd Z,C,N,V,H 1 SBR Rd,K Set Bit(s) in Register Rd Rd v K Z,N,V 1 CBR Rd,K Clear Bit(s) in Register Rd Rd * (0xFF - K) Z,N,V 1 INC Rd Increment Rd Rd + 1 Z,N,V 1 DEC Rd Decrement Rd Rd - 1 Z,N,V 1 TST Rd Test for Zero or Minus Rd Rd * Rd Z,N,V 1 CLR Rd Clear Register Rd Rd Rd Z,N,V 1 SER Rd Set Register Rd 0xFF None 1 2 BRANCH INSTRUCTIONS RJMP k IJMP RCALL k Relative Jump PC PC + k + 1 None Indirect Jump to (Z) PC Z None 2 Relative Subroutine Call PC PC + k + 1 None 3 3 ICALL Indirect Call to (Z) PC Z None RET Subroutine Return PC STACK None 4 RETI Interrupt Return PC STACK I 4 CPSE Rd,Rr Compare, Skip if Equal if (Rd = Rr) PC PC + 2 or 3 None CP Rd,Rr Compare Rd - Rr Z, N,V,C,H 1 CPC Rd,Rr Compare with Carry Rd - Rr - C Z, N,V,C,H 1 CPI Rd,K Compare Register with Immediate Rd - K Z, N,V,C,H SBRC Rr, b Skip if Bit in Register Cleared if (Rr(b)=0) PC PC + 2 or 3 None 1/2/3 1/2/3 1 SBRS Rr, b Skip if Bit in Register is Set if (Rr(b)=1) PC PC + 2 or 3 None 1/2/3 SBIC P, b Skip if Bit in I/O Register Cleared if (P(b)=0) PC PC + 2 or 3 None 1/2/3 SBIS P, b Skip if Bit in I/O Register is Set if (P(b)=1) PC PC + 2 or 3 None 1/2/3 BRBS s, k Branch if Status Flag Set if (SREG(s) = 1) then PCPC+k + 1 None 1/2 BRBC s, k Branch if Status Flag Cleared if (SREG(s) = 0) then PCPC+k + 1 None 1/2 BREQ k Branch if Equal if (Z = 1) then PC PC + k + 1 None 1/2 BRNE k Branch if Not Equal if (Z = 0) then PC PC + k + 1 None 1/2 BRCS k Branch if Carry Set if (C = 1) then PC PC + k + 1 None 1/2 BRCC k Branch if Carry Cleared if (C = 0) then PC PC + k + 1 None 1/2 BRSH k Branch if Same or Higher if (C = 0) then PC PC + k + 1 None 1/2 BRLO k Branch if Lower if (C = 1) then PC PC + k + 1 None 1/2 BRMI k Branch if Minus if (N = 1) then PC PC + k + 1 None 1/2 BRPL k Branch if Plus if (N = 0) then PC PC + k + 1 None 1/2 BRGE k Branch if Greater or Equal, Signed if (N V= 0) then PC PC + k + 1 None 1/2 BRLT k Branch if Less Than Zero, Signed if (N V= 1) then PC PC + k + 1 None 1/2 BRHS k Branch if Half Carry Flag Set if (H = 1) then PC PC + k + 1 None 1/2 BRHC k Branch if Half Carry Flag Cleared if (H = 0) then PC PC + k + 1 None 1/2 BRTS k Branch if T Flag Set if (T = 1) then PC PC + k + 1 None 1/2 BRTC k Branch if T Flag Cleared if (T = 0) then PC PC + k + 1 None 1/2 BRVS k Branch if Overflow Flag is Set if (V = 1) then PC PC + k + 1 None 1/2 BRVC k Branch if Overflow Flag is Cleared if (V = 0) then PC PC + k + 1 None 1/2 BRIE k Branch if Interrupt Enabled if ( I = 1) then PC PC + k + 1 None 1/2 BRID k Branch if Interrupt Disabled if ( I = 0) then PC PC + k + 1 None 1/2 BIT AND BIT-TEST INSTRUCTIONS SBI P,b Set Bit in I/O Register I/O(P,b) 1 None 2 CBI P,b Clear Bit in I/O Register I/O(P,b) 0 None 2 LSL Rd Logical Shift Left Rd(n+1) Rd(n), Rd(0) 0 Z,C,N,V 1 LSR Rd Logical Shift Right Rd(n) Rd(n+1), Rd(7) 0 Z,C,N,V 1 ROL Rd Rotate Left Through Carry Rd(0)C,Rd(n+1) Rd(n),CRd(7) Z,C,N,V 1 ROR Rd Rotate Right Through Carry Rd(7)C,Rd(n) Rd(n+1),CRd(0) Z,C,N,V 1 225 2588C-AVR-10/09 Mnemonics Operands Description Operation Flags #Clocks ASR Rd Arithmetic Shift Right Rd(n) Rd(n+1), n=0..6 Z,C,N,V 1 SWAP Rd Swap Nibbles Rd(3..0)Rd(7..4),Rd(7..4)Rd(3..0) None 1 BSET s Flag Set SREG(s) 1 SREG(s) 1 BCLR s Flag Clear SREG(s) 0 SREG(s) 1 BST Rr, b Bit Store from Register to T T Rr(b) T 1 BLD Rd, b Bit load from T to Register Rd(b) T None 1 SEC Set Carry C1 C 1 CLC Clear Carry C0 C 1 SEN Set Negative Flag N1 N 1 CLN Clear Negative Flag N0 N 1 SEZ Set Zero Flag Z1 Z 1 CLZ Clear Zero Flag Z0 Z 1 SEI Global Interrupt Enable I1 I 1 CLI Global Interrupt Disable I0 I 1 SES Set Signed Test Flag S1 S 1 CLS Clear Signed Test Flag S0 S 1 SEV Set Twos Complement Overflow. V1 V 1 CLV Clear Twos Complement Overflow V0 V 1 SET Set T in SREG T1 T 1 CLT Clear T in SREG T0 T 1 SEH CLH Set Half Carry Flag in SREG Clear Half Carry Flag in SREG H1 H0 H H 1 Rd Rr Rd+1:Rd Rr+1:Rr None 1 None 1 1 1 DATA TRANSFER INSTRUCTIONS MOV Rd, Rr Move Between Registers MOVW Rd, Rr Copy Register Word LDI Rd, K Load Immediate Rd K None LD Rd, X Load Indirect Rd (X) None 2 LD Rd, X+ Load Indirect and Post-Inc. Rd (X), X X + 1 None 2 LD Rd, - X Load Indirect and Pre-Dec. X X - 1, Rd (X) None 2 LD Rd, Y Load Indirect Rd (Y) None 2 LD Rd, Y+ Load Indirect and Post-Inc. Rd (Y), Y Y + 1 None 2 2 LD Rd, - Y Load Indirect and Pre-Dec. Y Y - 1, Rd (Y) None LDD Rd,Y+q Load Indirect with Displacement Rd (Y + q) None 2 LD Rd, Z Load Indirect Rd (Z) None 2 LD Rd, Z+ Load Indirect and Post-Inc. Rd (Z), Z Z+1 None 2 LD Rd, -Z Load Indirect and Pre-Dec. Z Z - 1, Rd (Z) None 2 LDD Rd, Z+q Load Indirect with Displacement Rd (Z + q) None 2 LDS Rd, k Load Direct from SRAM Rd (k) None 2 ST X, Rr Store Indirect (X) Rr None 2 ST X+, Rr Store Indirect and Post-Inc. (X) Rr, X X + 1 None 2 ST - X, Rr Store Indirect and Pre-Dec. X X - 1, (X) Rr None 2 ST Y, Rr Store Indirect (Y) Rr None 2 ST Y+, Rr Store Indirect and Post-Inc. (Y) Rr, Y Y + 1 None 2 ST - Y, Rr Store Indirect and Pre-Dec. Y Y - 1, (Y) Rr None 2 STD Y+q,Rr Store Indirect with Displacement (Y + q) Rr None 2 ST Z, Rr Store Indirect (Z) Rr None 2 ST Z+, Rr Store Indirect and Post-Inc. (Z) Rr, Z Z + 1 None 2 ST -Z, Rr Store Indirect and Pre-Dec. Z Z - 1, (Z) Rr None 2 STD Z+q,Rr Store Indirect with Displacement (Z + q) Rr None 2 STS k, Rr Store Direct to SRAM (k) Rr None 2 Load Program Memory R0 (Z) None 3 LPM LPM Rd, Z Load Program Memory Rd (Z) None 3 LPM Rd, Z+ Load Program Memory and Post-Inc Rd (Z), Z Z+1 None 3 Store Program Memory (z) R1:R0 None IN Rd, P In Port Rd P None OUT P, Rr Out Port P Rr None 1 PUSH Rr Push Register on Stack STACK Rr None 2 POP Rd Pop Register from Stack Rd STACK None 2 SPM 1 MCU CONTROL INSTRUCTIONS NOP No Operation None 1 SLEEP Sleep (see specific descr. for Sleep function) None 1 WDR BREAK Watchdog Reset Break (see specific descr. for WDR/Timer) For On-chip Debug Only None None 1 N/A 226 ATtiny261/461/861 2588C-AVR-10/09 ATtiny261/461/861 23. Ordering Information 23.1 ATtiny261 Speed (MHz)(3) 10 20 Notes: Power Supply Ordering Code(2) Package(1) 1.8 - 5.5V ATtiny261V-10MU ATtiny261V-10PU ATtiny261V-10SU 32M1-A 20P3 20S2 Industrial (-40C to 85C) 2.7 - 5.5V ATtiny261-20MU ATtiny261-20PU ATtiny261-20SU 32M1-A 20P3 20S2 Industrial (-40C to 85C) Operational Range 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green. 3. For Speed vs. VCC,see Figure 19.3 on page 188 Package Type 32M1-A 32-pad, 5 x 5 x 1.0 mm Body, Lead Pitch 0.50 mm, Micro Lead Frame Package (MLF) 20P3 20-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 20S2 20-lead, 0.300" Wide, Plastic Gull Wing Smal Outline Package (SOIC) 227 2588C-AVR-10/09 23.2 ATtiny461 Speed (MHz)(3) 10 20 Notes: Power Supply Ordering Code(2) Package(1) 1.8 - 5.5V ATtiny461V-10MU ATtiny461V-10PU ATtiny461V-10SU 32M1-A 20P3 20S2 Industrial (-40C to 85C) 2.7 - 5.5V ATtiny461-20MU ATtiny461-20PU ATtiny461-20SU 32M1-A 20P3 20S2 Industrial (-40C to 85C) Operational Range 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green. 3. For Speed vs. VCC,see Figure 19.3 on page 188 Package Type 32M1-A 32-pad, 5 x 5 x 1.0 mm Body, Lead Pitch 0.50 mm, Micro Lead Frame Package (MLF) 20P3 20-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 20S2 20-lead, 0.300" Wide, Plastic Gull Wing Smal Outline Package (SOIC) 228 ATtiny261/461/861 2588C-AVR-10/09 ATtiny261/461/861 23.3 ATtiny861 Speed (MHz)(3) 10 20 Notes: Power Supply Ordering Code(2) Package(1) 1.8 - 5.5V ATtiny861V-10MU ATtiny861V-10PU ATtiny861V-10SU 32M1-A 20P3 20S2 Industrial (-40C to 85C) 2.7 - 5.5V ATtiny861-20MU ATtiny861-20PU ATtiny861-20SU 32M1-A 20P3 20S2 Industrial (-40C to 85C) Operational Range 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green. 3. For Speed vs. VCC,see Figure 19.3 on page 188 Package Type 32M1-A 32-pad, 5 x 5 x 1.0 mm Body, Lead Pitch 0.50 mm, Micro Lead Frame Package (MLF) 20P3 20-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 20S2 20-lead, 0.300" Wide, Plastic Gull Wing Smal Outline Package (SOIC) 229 2588C-AVR-10/09 24. Packaging Information 24.1 32M1-A D D1 1 2 3 0 Pin 1 ID E1 SIDE VIEW E TOP VIEW A3 A2 A1 A K 0.08 C P D2 1 2 3 P Pin #1 Notch (0.20 R) COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX A 0.80 0.90 1.00 A1 - 0.02 0.05 A2 - 0.65 1.00 A3 E2 b K 0.20 REF 0.18 e L BOTTOM VIEW D1 4.75 BSC 2.95 E1 E2 3.10 3.25 5.00 BSC 4.75BSC 2.95 e Note: JEDEC Standard MO-220, Fig. 2 (Anvil Singulation), VHHD-2. 0.30 5.00 BSC E b 0.23 D D2 NOTE 3.10 3.25 0.50 BSC L 0.30 0.40 0.50 P - - 0.60 o 12 0 - K 0.20 - - - 8/19/04 R 230 2325 Orchard Parkway San Jose, CA 95131 TITLE 32M1-A, 32-pad, 5 x 5 x 1.0 mm Body, Lead Pitch 0.50 mm, 3.10 mm Exposed Pad, Micro Lead Frame Package (MLF) DRAWING NO. 32M1-A REV. D ATtiny261/461/861 2588C-AVR-10/09 ATtiny261/461/861 24.2 20P3 D PIN 1 E1 A SEATING PLANE A1 L B B1 e E COMMON DIMENSIONS (Unit of Measure = mm) C eC eB Notes: 1. This package conforms to JEDEC reference MS-001, Variation AD. 2. Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion shall not exceed 0.25 mm (0.010"). SYMBOL MIN NOM MAX A - - 5.334 A1 0.381 - - D 25.493 - 25.984 E 7.620 - 8.255 E1 6.096 - 7.112 B 0.356 - 0.559 B1 1.270 - 1.551 L 2.921 - 3.810 C 0.203 - 0.356 eB - - 10.922 eC 0.000 - 1.524 e NOTE Note 2 Note 2 2.540 TYP 1/12/04 R 2325 Orchard Parkway San Jose, CA 95131 TITLE 20P3, 20-lead (0.300"/7.62 mm Wide) Plastic Dual Inline Package (PDIP) DRAWING NO. 20P3 REV. C 231 2588C-AVR-10/09 24.3 232 20S2 ATtiny261/461/861 2588C-AVR-10/09 ATtiny261/461/861 25. Errata 25.1 Errata ATtiny261 The revision letter in this section refers to the revision of the ATtiny261 device. 25.1.1 Rev A No known errata. 25.2 Errata ATtiny461 The revision letter in this section refers to the revision of the ATtiny461 device. 25.2.1 Rev B Yield improvement. No known errata. 25.2.2 Rev A No known errata. 25.3 Errata ATtiny861 The revision letter in this section refers to the revision of the ATtiny861 device. 25.3.1 Rev B No known errata. 25.3.2 Rev A Not sampled. 233 2588C-AVR-10/09 26. Datasheet Revision History 26.1 Rev. 2588C - 10/09 1. Updated document template. Re-arranged some sections. 2. Changed device status to "Not Recommended for New Designs". 3. Added Sections: - "Data Retention" on page 6 - "Clock Sources" on page 25 - "Low Level Interrupt" on page 51 - "Prescaling and Conversion Timing" on page 145 - "Clock speed considerations" on page 131 4. Updated Sections: - "Code Examples" on page 6 - "High-Frequency PLL Clock" on page 26 - "Normal Mode" on page 99 - "Features" on page 142 - "Temperature Measurement" on page 154 - "Limitations of debugWIRE" on page 164 - Step 1. on page 174 - "Programming the Flash" on page 180 - "System and Reset Characteristics" on page 190 5. Added Figures: - "Flash Programming Waveforms" on page 182 - "Reset Pin Output Voltage vs. Sink Current (VCC = 3V)" on page 209 - "Reset Pin Output Voltage vs. Sink Current (VCC = 3V)" on page 209 - "Reset Pin Output Voltage vs. Sink Current (VCC = 3V)" on page 209 - "Reset Pin Output Voltage vs. Sink Current (VCC = 3V)" on page 209 - "Bandgap Voltage vs. Supply Voltage (VCC)." on page 216 6. Updated Figures: - "Block Diagram" on page 4 - "Clock Distribution" on page 24 7. Added Table: - "Capacitance for Low-Frequency Crystal Oscillator" on page 29 8. Updated Tables: - "Start-up Times for the Internal Calibrated RC Oscillator Clock Selection" on page 28 - "Start-up Times for the 128 kHz Internal Oscillator" on page 29 - "Active Clock Domains and Wake-up Sources in Different Sleep Modes" on page 36 - "Serial Programming Characteristics, TA = -40C to 85C, VCC = 1.8 - 5.5V (Unless Otherwise Noted)" on page 193 9. Updated Register Descriptions: - "TCCR1A - Timer/Counter1 Control Register A" on page 112 234 ATtiny261/461/861 2588C-AVR-10/09 ATtiny261/461/861 - "TCCR1C - Timer/Counter1 Control Register C" on page 117 - "ADMUX - ADC Multiplexer Selection Register" on page 155 10. Updated assembly program example in section "Write" on page 17. 11. Updated "DC Characteristics. TA = -40C to 85C, VCC = 1.8V to 5.5V (unless otherwise noted)." on page 187. 26.2 Rev. 2588B - 11/06 1. Updated "Ordering Information" on page 227. 2. Updated "Packaging Information" on page 230. 26.3 Rev. 2588A - 10/06 1. Initial Revision. 235 2588C-AVR-10/09 236 ATtiny261/461/861 2588C-AVR-10/09 ATtiny261/461/861 Table of Contents Features ..................................................................................................... 1 1 Pin Configurations ................................................................................... 2 1.1 2 Overview ................................................................................................... 4 2.1 3 4 5 6 7 Pin Descriptions .................................................................................................3 Block Diagram ...................................................................................................4 About ......................................................................................................... 6 3.1 Resources .........................................................................................................6 3.2 Code Examples .................................................................................................6 3.3 Data Retention ...................................................................................................6 3.4 Disclaimer ..........................................................................................................6 CPU Core .................................................................................................. 7 4.1 Architectural Overview .......................................................................................7 4.2 ALU - Arithmetic Logic Unit ...............................................................................8 4.3 Status Register ..................................................................................................8 4.4 General Purpose Register File ........................................................................10 4.5 Stack Pointer ...................................................................................................11 4.6 Instruction Execution Timing ...........................................................................11 4.7 Reset and Interrupt Handling ...........................................................................12 Memories ................................................................................................ 15 5.1 In-System Re-programmable Flash Program Memory ....................................15 5.2 SRAM Data Memory ........................................................................................15 5.3 EEPROM Data Memory ..................................................................................16 5.4 I/O Memory ......................................................................................................20 5.5 Register Description ........................................................................................20 Clock System ......................................................................................... 24 6.1 Clock Subsystems ...........................................................................................24 6.2 Clock Sources .................................................................................................25 6.3 System Clock Prescaler ..................................................................................31 6.4 Clock Output Buffer .........................................................................................32 6.5 Register Description ........................................................................................32 Power Management and Sleep Modes ................................................. 36 7.1 Sleep Modes ....................................................................................................36 i 2588C-AVR-10/09 8 9 7.2 Power Reduction Register ...............................................................................37 7.3 Minimizing Power Consumption ......................................................................37 7.4 Register Description ........................................................................................39 System Control and Reset .................................................................... 41 8.1 Reset Sources .................................................................................................42 8.2 Internal Voltage Reference ..............................................................................44 8.3 Watchdog Timer ..............................................................................................44 8.4 Register Description ........................................................................................47 Interrupts ................................................................................................ 50 9.1 Interrupt Vectors ..............................................................................................50 9.2 External Interrupts ...........................................................................................51 9.3 Register Description ........................................................................................52 10 I/O Ports .................................................................................................. 55 10.1 Ports as General Digital I/O .............................................................................56 10.2 Alternate Port Functions ..................................................................................60 10.3 Register Description ........................................................................................69 11 Timer/Counter0 ...................................................................................... 71 11.1 Features ..........................................................................................................71 11.2 Overview ..........................................................................................................71 11.3 Clock Sources .................................................................................................72 11.4 Counter Unit ....................................................................................................74 11.5 Input Capture Unit ...........................................................................................75 11.6 Output Compare Unit .......................................................................................76 11.7 Modes of Operation .........................................................................................77 11.8 Timer/Counter Timing Diagrams .....................................................................79 11.9 Accessing Registers in 16-bit Mode ................................................................80 11.10 Register Description ........................................................................................84 12 Timer/Counter1 ...................................................................................... 89 ii 12.1 Features ..........................................................................................................89 12.2 Overview ..........................................................................................................89 12.3 Clock Sources .................................................................................................92 12.4 Counter Unit ....................................................................................................93 12.5 Output Compare Unit .......................................................................................94 12.6 Dead Time Generator ......................................................................................96 ATtiny261/461/861 2588C-AVR-10/09 ATtiny261/461/861 12.7 Compare Match Output Unit ............................................................................97 12.8 Modes of Operation .........................................................................................99 12.9 Timer/Counter Timing Diagrams ...................................................................106 12.10 Fault Protection Unit ......................................................................................107 12.11 Accessing 10-Bit Registers ............................................................................108 12.12 Register Description ......................................................................................112 13 USI - Universal Serial Interface .......................................................... 125 13.1 Features ........................................................................................................125 13.2 Overview ........................................................................................................125 13.3 Functional Descriptions .................................................................................126 13.4 Alternative USI Usage ...................................................................................132 13.5 Register Descriptions ....................................................................................132 14 AC - Analog Comparator .................................................................... 137 14.1 Analog Comparator Multiplexed Input ...........................................................137 14.2 Register Description ......................................................................................139 15 ADC - Analog to Digital Converter ..................................................... 142 15.1 Features ........................................................................................................142 15.2 Overview ........................................................................................................142 15.3 Operation .......................................................................................................143 15.4 Starting a Conversion ....................................................................................144 15.5 Prescaling and Conversion Timing ................................................................145 15.6 Changing Channel or Reference Selection ...................................................148 15.7 ADC Noise Canceler .....................................................................................149 15.8 Analog Input Circuitry ....................................................................................150 15.9 Noise Canceling Techniques .........................................................................150 15.10 ADC Accuracy Definitions .............................................................................151 15.11 ADC Conversion Result .................................................................................153 15.12 Temperature Measurement ...........................................................................154 15.13 Register Description ......................................................................................155 16 debugWIRE On-chip Debug System .................................................. 163 16.1 Features ........................................................................................................163 16.2 Overview ........................................................................................................163 16.3 Physical Interface ..........................................................................................163 16.4 Software Break Points ...................................................................................164 16.5 Limitations of debugWIRE .............................................................................164 iii 2588C-AVR-10/09 16.6 Register Description ......................................................................................164 17 Self-Programming the Flash ............................................................... 165 17.1 Performing Page Erase by SPM ....................................................................165 17.2 Filling the Temporary Buffer (Page Loading) .................................................165 17.3 Performing a Page Write ...............................................................................166 17.4 Addressing the Flash During Self-Programming ...........................................166 17.5 EEPROM Write Prevents Writing to SPMCSR ..............................................167 17.6 Reading Fuse and Lock Bits from Software ..................................................167 17.7 Preventing Flash Corruption ..........................................................................168 17.8 Programming Time for Flash when Using SPM ............................................168 17.9 Register Description ......................................................................................169 18 Memory Programming ......................................................................... 170 18.1 Program And Data Memory Lock Bits ...........................................................170 18.2 Fuse Bytes .....................................................................................................171 18.3 Signature Bytes .............................................................................................172 18.4 Calibration Byte .............................................................................................173 18.5 Page Size ......................................................................................................173 18.6 Serial Programming .......................................................................................173 18.7 Parallel Programming ....................................................................................177 19 Electrical Characteristics .................................................................... 187 19.1 Absolute Maximum Ratings* .........................................................................187 19.2 DC Characteristics .........................................................................................187 19.3 Speed Grades ...............................................................................................188 19.4 Clock Characteristics .....................................................................................189 19.5 System and Reset Characteristics ................................................................190 19.6 ADC Characteristics - Preliminary Data ........................................................192 19.7 Serial Programming Characteristics ..............................................................193 19.8 Parallel Programming Characteristics ...........................................................194 20 Typical Characteristics ........................................................................ 197 iv 20.1 Supply Current of I/O modules ......................................................................197 20.2 Active Supply Current ....................................................................................198 20.3 Idle Supply Current ........................................................................................201 20.4 Power-down Supply Current ..........................................................................203 20.5 Pin Pull-up .....................................................................................................204 20.6 Pin Driver Strength ........................................................................................207 ATtiny261/461/861 2588C-AVR-10/09 ATtiny261/461/861 20.7 Pin Threshold and Hysteresis ........................................................................211 20.8 BOD and Bandgap ........................................................................................214 20.9 Internal Oscillator Speed ...............................................................................216 20.10 Current Consumption of Peripheral Units ......................................................218 20.11 Current Consumption in Reset and Reset Pulsewidth ..................................221 21 Register Summary ............................................................................... 223 22 Instruction Set Summary .................................................................... 225 23 Ordering Information ........................................................................... 227 23.1 ATtiny261 ......................................................................................................227 23.2 ATtiny461 ......................................................................................................228 23.3 ATtiny861 ......................................................................................................229 24 Packaging Information ........................................................................ 230 24.1 32M1-A ..........................................................................................................230 24.2 20P3 ..............................................................................................................231 24.3 20S2 ..............................................................................................................232 25 Errata ..................................................................................................... 233 25.1 Errata ATtiny261 ............................................................................................233 25.2 Errata ATtiny461 ............................................................................................233 25.3 Errata ATtiny861 ............................................................................................233 26 Datasheet Revision History ................................................................ 234 26.1 Rev. 2588C - 10/09 .......................................................................................234 26.2 Rev. 2588B - 11/06 .......................................................................................235 26.3 Rev. 2588A - 10/06 .......................................................................................235 Table of Contents....................................................................................... i v 2588C-AVR-10/09 Headquarters International Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Atmel Asia Unit 1-5 & 16, 19/F BEA Tower, Millennium City 5 418 Kwun Tong Road Kwun Tong, Kowloon Hong Kong Tel: (852) 2245-6100 Fax: (852) 2722-1369 Atmel Europe Le Krebs 8, Rue Jean-Pierre Timbaud BP 309 78054 Saint-Quentin-enYvelines Cedex France Tel: (33) 1-30-60-70-00 Fax: (33) 1-30-60-71-11 Atmel Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Technical Support avr@atmel.com Sales Contact www.atmel.com/contacts Product Contact Web Site www.atmel.com Literature Requests www.atmel.com/literature Disclaimer: The information in this document is provided in connection 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