ERJU03F3303V - PANASONIC

MCP6546/6R/6U/7/8/9

Features

• Low Quiescent Current: 600 nA/Comparator (typical)

• Rail-to-Rail Input: VSS - 0.3V to VDD + 0.3V

• Open-Drain Output: VOUT ≤10V

•Propagation Delay: 4 µs (typical, 100 mV Overdrive)

• Wide Supply Voltage Range: 1.6V to 5.5V

• Si ngl e Availa ble in SOT-23-5, SC-70 -5* Pac k age s

• Available in Single, Dual and Quad

• Chip Select (CS) with MCP6548

• Low Switching Current

• Inte rnal Hysteresis: 3.3 mV (typic al)

• Temperature Range:

- Industrial: -40°C to +85°C

- Extended: -40°C to +125°C

Typical Applications

• Laptop Computers

• Mobile Phones

• Metering Systems

• Hand -hel d Electronics

• RC Timers

• Alarm and Monitoring Circuits

• Windowed Compar ators

• Multi-vibrators

Related Devices

• CMOS/TTL-Compatible Output: MCP6541/2/3/4

Description

The Microchip Technology Inc. MCP6546/6R/6U/7/8/9

family of comparators, is offered in single (MCP6546,

MCP6546R, MCP6546U), single with chip select (CS)

(MCP6548), dual (MCP6547) and quad (MCP6549)

configurations. The outputs are open-drain and are

capable of driving heavy DC or capacitive lo ads.

These comparators are optimized for low power,

single-supply application with greater than rail-to-rail

input opera tion. The output li mits suppl y current surge s

and dynamic power consumption while switching. The

open-drain output of the MCP6546/6R/6U/7/8/9 family

can be u sed as a lev el-shifte r for up to 10V us ing a pull-

up resistor. It can also be used as a wired-OR logic.

The in tern al Inpu t hyst eresis elim inates outp ut swit ch-

ing due t o internal noise voltage, reducing current draw .

These comparators operate with a single-supply

volt age as low a s 1.6V an d draw a quie scent current of

less than 1 µA/comparator.

The related MCP6541/2/3/4 family of comparators from

Microchip has a push-pull output that supports rail-to-

rail output swing and interfaces with CMOS/TTL logic.

* SC-70-5 E-Temp parts are not available at this

release of the data sheet.

MCP6546U SOT-23-5 is E-Temp only.

Package Types

VIN+

VIN–

MCP6546

VSS

VDD

OUT

PDIP, SOIC, MSOP

SOT-23-5

VDD

OUT

VIN+

VSS

VIN–

MCP6546R MCP6547

VINA+

VINA–

VSS

OUTA

VDD

OUTB

VINB–

VINB+

VIN+

VIN–

MCP6548

VSS

VDD

OUT

PDIP, SOIC, MSOP

MCP6549

VINA+

VINA–

VSS

OUTA +-

VDD

OUTD

VIND–

VIND+

OUTB

VINB–

VINB+VINC+

VINC–

OUTC

PDIP, SOIC, TSSOP

SC-70-5, SOT 23-5

VSS

OUT

VIN+

VDD

VIN–

MCP6546

SC-70-5, SOT-23-5

VSS

VIN+

VIN–

VDD

OUT

MCP6546U

Open-Drain Output Sub-Microamp Comparators

MCP6546/6R/6U/7/8/9

1.0 ELECTRICAL

CHARACTERISTICS

Absolute Maximum Ratings †

VDD - VSS .........................................................................7.0V

Open-Drain Output..............................................VSS + 10.5V

Analog Input (VIN+, VIN-)††.............VSS - 1.0V to VDD + 1.0V

All Other Inputs and Outputs ......... VSS – 0.3V to VDD + 0.3V

Difference Input Voltage ...................................... | VDD – VSS|

Output Sh o rt-Circu it Cu r ren t ............ ...... ....... ...... ..conti n u o us

Current at Input Pins .................. .... .... .. ......... .... .... .... .. .±2 mA

Current at Output and Supply Pins . ...........................±30 mA

Storage Temperature.....................................-65°C to +150°C

Maximum Junction Tem peratur e (TJ)..........................+150°C

ESD Protection on All Pins:

(HBM;MM). ....................................2 kV ;200V (MCP6546U)

(HBM;M M)................................ 4 kV; 200V (all other parts)

† Notice: Stresses above those listed under “Absolute

Maximum Ratings” may cause permanent damage to

the device. This is a stress rating only, and functional

operatio n of the device, at those or any other conditions

above those indicated in the operational listings of this

specif icatio n, is not im plie d. Expos ure to maxim um rat-

ing conditions for extended periods may affect device

reliability.

†† See Section 4.1.2 “Input Voltage and Current

Limits”

DC CHARACTERISTICS

Electrical Specifications: Unless otherwise indicated, VDD = +1.6V to +5.5V, VSS = GND, TA = 25°C, VIN+ = VDD/2,

VIN– = VSS, RPU =2.74kΩ to VPU = VDD (Refer to Figure 1-3).

Parameters Sym Min Typ Max Units Conditions

Power Supply

Supply Voltage VDD 1.6 — 5.5 V VPU ≥ VDD

Quiescent Current

(per comparator) IQ0.3 0.6 1 µA IOUT = 0

Input

Input Voltage Range VCMR VSS −

0.3 —V

DD + 0.3 V

Common Mode Rejection Ratio CMRR 55 70 — dB VDD = 5V, VCM = -0.3V to 5.3V

Common Mode Rejection Ratio CMRR 50 65 — dB VDD = 5V, VCM = 2.5V to 5.3V

Common Mode Rejection Ratio CMRR 55 70 — dB VDD = 5V, VCM = -0.3V to 2.5V

Power Supply Rejection Ratio PSRR 63 80 — dB VCM = VSS

Input Offset Voltage VOS -7.0 ±1.5 +7.0 mV VCM = VSS (Note 1)

Drift with Temperature ΔVOS/ΔTA— ±3—µV/°CT

A = -40°C to +125°C, VCM = VSS

Input Hysteresis Voltage VHYST 1.5 3.3 6.5 mV VCM = VSS (Note 1)

Linear Temp. Co. TC1—6.7—µV/°CT

A = -40°C to +125°C, VCM = VSS

(Note 2)

Quadratic Temp. Co. TC2—-0.035—µV/°C

2TA = -40°C to +125°C, VCM = VSS

(Note 2)

Input Bias Current IB—1—pAV

CM = VSS

At Temperature (I-Temp parts) IB— 25 100 pA TA = +85° C, VCM = VSS (Note 3)

At Temperature (E -Temp parts) IB— 1200 5000 pA TA = +125°C, VCM = VSS (Note 3)

Input Offset Current IOS — ±1 — pAV

CM = VSS

Note 1: The input offset voltage is the center of the input-referred trip points. The input hysteresis is the difference

between the input-referred trip points.

2: VHYST at differential temperatures is estimated using:

VHYST (TA) = VHYST + (TA -25°C) TC1 + (TA - 25°C)2TC2.

3: Input bias current at temperature is not tested for the SC-70-5 package.

4: Do not short the output above VSS + 10V. Limit the output current to Absolute Maximum Rating of 30 mA.

The mi nimum VPU test limit was VDD before Dec. 2004 (week code 52).

MCP6546/6R/6U/7/8/9

Common Mode Input Impedance ZCM —10

13||4 — Ω||pF

Differential Input Impedance ZDIFF —10

13||2 — Ω||pF

Open-Drain Output

Output Pull -Up Voltage VPU 1.6 — 10 V (Note 4)

High-Level Output Current IOH -100 — — nA VDD = 1.6V to 5.5V, VPU = 10V

(Note 4)

Low-Level Output Voltage VOL VSS —V

SS + 0.2 V IOUT = 2 m A, VPU = VDD = 5V

Short-Circuit Current ISC —±1.5— mAV

PU = VDD = 1.6V (Note 4)

ISC –30—mAV

PU = VDD = 5.5V (Note 4)

Output Pin Capacitance COUT —8—pF

AC CHARACTERISTICS

Electrical Specifications: Unless otherwise indicated, VDD = +1.6V to +5.5V, VSS = GND, TA = 25°C, VIN+ = VDD/2,

Step = 200 mV, Overdrive = 100 mV, RPU =2.74kΩ to VPU = VDD, and CL = 36 pF

(Refer to Figure 1-2 and Figure 1-3).

Parameters Sym Min Typ Max Units Conditions

Fall Time tF—0.7—µs(Note 1)

Propagation Delay (High-to-Low) tPHL —4.08.0µs

Propagation Delay (Low-to-High) tPLH —3.08.0µs(Note 1)

Propagation Delay Skew tPDS —-1.0— µs(Notes 1 and 2)

Maximum Toggle Frequency fMAX — 225 — kHz VDD = 1.6V

fMAX — 165 — kHz VDD = 5.5V

Input Noise Voltage Eni — 200 — µVP-P 10 Hz to 100 kHz

Note 1: tR and tPLH depend on the load (RL and CL); these specifications are valid for the indicated load only.

2: Propagation Delay Skew is defined as: tPDS = tPLH - tPHL.

DC CHARACTERISTICS (CONTINUE D)

Electrical Specifications: Unless otherwise indicated, VDD = +1.6V to +5.5V, VSS = GND, TA = 25°C, VIN+ = VDD/2,

VIN– = VSS, RPU =2.74kΩ to VPU = VDD (Refer to Figure 1-3).

Parameters Sym Min Typ Max Units Conditions

Note 1: The input offset voltage is the center of the input-referred trip points. The input hysteresis is the difference

between the input-referred trip points.

2: VHYST at differential temperatures is estimated using:

VHYST (TA) = VHYST + (TA -25°C) TC1 + (TA - 25°C)2TC2.

3: Input bias current at temperature is not tested for the SC-70-5 package.

4: Do not short the output above VSS + 10V. Limit the output current to Absolute Maximum Rati ng of 30 mA.

The mi nimum VPU test limit was VDD before Dec. 2004 (week code 52).

MCP6546/6R/6U/7/8/9

FIGURE 1-1: Timing Diagram for the CS

pin on the MCP6548.

FIGURE 1-2: Propagation Delay Timing

Diagram.

MCP6548 CHIP SELECT (CS) CHARACTERISTICS

Electrical Specifica t ions : U nl es s ot he rwis e in dicated, VDD = +1 .6V to +5 .5V, VSS = GND, TA = 25°C, VIN+ = VDD/2,

VIN– = VSS, RPU =2.74kΩ to VPU = VDD, and CL = 36 pF (Refer to Figures 1-1 and 1-3).

Parameters Sym Min Typ Max Units Conditions

CS Low Specifications

CS Log ic Thresh old, Low VIL VSS —0.2

VDD

CS Input Current, Low ICSL —5—pA

CS = VSS

CS High Specifications

CS Log ic Thresh old, High VIH 0.8 VDD —V

DD V

CS Input Current, High ICSH —1—pA

CS = VDD

CS Input High, VDD Current IDD —18—pA

CS = VDD

CS Input High, GND Current ISS —-20—pA

CS = VDD

Comparator Output Leakage IO(LEAK) —1—pA

VOUT = VSS+10V, CS = VDD

CS Dynamic Specifications

CS Low to Compar ator Output

Low Turn-on Time tON —250ms

CS = 0.2VDD to VOUT = VDD/2,

VIN– = VDD

CS High to Comp a rato r O utp ut

High Z Turn-off Time tOFF —10—µs

CS = 0.8VDD to VOUT = VDD/2,

VIN– = VDD

CS Hysteresis VCS_HYST —0.6—V

VDD = 5V

VIL

High-Z

tON

VIH

tOFF

VOUT

-20 pA (typ.)

High-Z

ISS

ICS

-20 pA (typ.)-0.6 µA (typ.)

1 pA (typ. ) 1 pA (typ.)5 pA (typ.)

VOL

tPLH

VOUT

VIN–100 mV

100 mV tPHL

VOL

VIN+ = VDD/2

VOH

MCP6546/6R/6U/7/8/9

1.1 Test Circuit Configuration

This test circuit configuration is used to determine the

AC and DC speci fic ati on s.

FIGURE 1-3: AC and DC Test Circuit for

the Open-Drain Output Comparators.

TEMPERATURE CHARACTERISTICS

Electrical Specifications: Unless otherwise indicated, VDD = +1.6V to +5.5V and VSS = GND.

Parameters Sym Min Typ Max Units Conditions

Temperature Ranges

Specified Temperat ure Range TA-40 — +85 °C

Operati ng Temperatu re Ra nge TA-40 — +125 °C Note

Storage Temperature Range TA-65 — +150 °C

Thermal Package Resistances

Thermal Resistance, 5L-SC-70 θJA — 331 — °C/W

Thermal Resistance, 5L-SOT-23 θJA — 220.7 — °C/W

Thermal Resistance, 8L-MSOP θJA —211—°C/W

Thermal Resistance, 8L-PDIP θJA —89.3—°C/W

Thermal Resistance, 8L-SOIC θJA — 149.5 — °C/W

Thermal Resistance, 14L-PDIP θJA —70—°C/W

Thermal Resistance, 14L-SOIC θJA —95.3—°C/W

Thermal Resistance, 14L-TSSOP θJA — 100 — °C/W

Note: The MCP6546 /6R/6U/7/8 /9 I-temp family operates over th is extende d tempe rature range, but with redu ced

performance. In any case, the Junction Temperature (TJ) must not exceed the absolute maximum

specification of +150°C.

VDD

VSS = 0V

200 kΩ

100 kΩ

VOUT

VIN = VSS

36 pF

MCP654X RPU =

VPU = VDD

(2 mA)/ VDD

MCP6546/6R/6U/7/8/9

2.0 TYPICAL PERFORMANCE CURVES

Note: Unless otherwise indicated, VDD = +1.6V to +5.5V, VSS = GND, TA = +25°C, VIN+ = VDD/2, VIN– = GND,

RPU = 2.74 kΩ to VPU =V

DD, and CL = 36 pF.

FIGURE 2-1: Input Offset Voltage at

VCM =V

SS.

FIGURE 2-2: Input Offset Voltage Drift at

VCM =V

SS.

FIGURE 2-3: The MCP6546/6R/6U/7/8/9

Comparators Show No Phase Reversal.

FIGURE 2-4: Input Hysteresis Voltage at

VCM =V

SS.

FIGURE 2-5: Input Hysteresis Voltage

Linear Temp. Co. (TC1) at VCM =V

SS.

FIGURE 2-6: Input Hysteresis Voltage

Quadratic Temp. Co. (TC2) at VCM =V

SS.

Note: The gra phs and tab les prov ided fo llow ing this note are a sta tistic al sum mary b ased on a limit ed numb er of

samples and are provided for informational purposes only. The performance characteristics listed herein

are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified

operating range (e.g., outside specified power supply range) and therefore outside the warranted range.

10%

12%

14%

-7-6-5-4-3-2-101234567

Input Offset Voltage (mV)

Percentage of Occurrences

1200 Samples

VCM = VSS

10%

12%

14%

16%

-14

-12

-10

-8

-6

-4

-2

Input Offset Voltage Drift (µV/°C)

Percentage of Occurrences

1200 Samples

VCM = VSS

TA = -40°C to +125°C

-1

012345678910

Time (1 ms/div)

Inverting Input, Output

Voltag e (V)

VOUT

VIN–

VDD = 5.5V

10%

12%

14%

16%

18%

1.62.02.42.83.23.64.04.44.85.25.66.0

Input Hysteresis Voltage (m V)

Percent age of Occu rren ces

1200 Samples

VCM = VSS

10%

15%

20%

25%

4.6

5.0

5.4

5.8

6.2

6.6

7.0

7.4

7.8

8.2

8.6

9.0

9.4

Input Hysteresis Voltage –

Linear Temp. Co.; TC1 (µV/°C)

Percentage of Occurrences

596 Samples

VCM = VSS

TA = -40°C to +125°C

VDD = 1.6VVDD = 5.5V

10%

12%

14%

16%

18%

20%

-0.060

-0.056

-0.052

-0.048

-0.044

-0.040

-0.036

-0.032

-0.028

-0.024

-0.020

-0.016

Input Hysteresis Voltage –

Quadratic Temp. Co.; TC2 (µV/°C2)

Percentage of Occurrences

596 Samples

VCM = VSS

TA = -40°C to +125°C

VDD = 5.5V

VDD = 1.6V

MCP6546/6R/6U/7/8/9

Note: Unless otherwise indicated, VDD = +1.6V to +5.5V, VSS = GND, TA=+25°C, V

IN+=V

DD/2, VIN– = GND,

RPU =2.74kΩ to VPU =V

DD, and CL=36pF.

FIGURE 2-7: Input Offset Voltage vs.

Ambient Temperature at VCM =V

SS.

FIGURE 2-8: Input Offset Voltage vs.

Common Mode Input Voltage at VDD =1.6V.

FIGURE 2-9: Input Offset Voltage vs.

Common Mode Input Voltage at VDD = 5.5V.

FIGURE 2-10: Input Hysteresis Voltage vs.

Ambient Temperature at VCM =V

SS.

FIGURE 2-11: Input Hysteresis Voltage vs.

Common Mode Input Voltage at VDD =1.6V.

FIGURE 2-12: Input Hysteresis Voltage vs.

Common Mode Input Voltage at VDD =5.5V.

-1.0

-0.8

-0.6

-0.4

-0.2

0.0

0.2

0.4

0.6

0.8

1.0

-50 -25 0 25 50 75 100 125

Ambient Temper atu re (°C)

Input Offset Voltage (mV)

VDD = 1.6V

VDD = 5.5V

VCM = VSS

-2.0

-1.5

-1.0

-0.5

0.0

0.5

1.0

1.5

2.0

-0.4

-0.2

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

Common Mode Input Voltage (V)

Input Offset Voltage (mV)

VDD = 1.6V

TA = +125°C

TA = +85°C

TA = +25°C

TA = -40°C

TA = +125°C

-2.0

-1.5

-1.0

-0.5

0.0

0.5

1.0

1.5

2.0

-0.5

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

Common Mode Input Voltage (V)

Input Offset Voltage (mV)

VDD = 5.5V

TA = +85°C

TA = +125°C

TA = -40°C

TA = +25°C

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

6.5

-50 -25 0 25 50 75 100 125

Ambie nt Temper atu re (°C)

Input Hysteresis Voltage (mV)

VDD = 1.6V

VDD = 5.5V

VCM = VSS

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

6.5

-0.4

-0.2

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

Common Mode Input Voltage (V)

Input Hysteresis Voltage (mV)

TA = +25°C

TA = -40°C

TA = +125°C

TA = +85° C

VDD = 1.6V

TA = +125°C

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

6.5

-0.5

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

Common Mode Input Voltage (V)

Input Hysteresis Voltage (mV)

VDD = 5.5V TA = +125°C

TA = +85°C

TA = +25°C

TA = -40°C

MCP6546/6R/6U/7/8/9

Note: Unless otherwise indicated, VDD = +1.6V to +5.5V, VSS = GND, TA=+25°C, V

IN+=V

DD/2, VIN– = GND,

RPU =2.74kΩ to VPU =V

DD, and CL=36pF.

FIGURE 2-13: CMRR,PSRR vs. Ambient

Temperature.

FIGURE 2-14: Input Bias Current, Input

Offset Current vs. Ambient Temperature.

FIGURE 2-15: Quiescent Current vs.

Common Mode Input Voltage at VDD =1.6V.

FIGURE 2-16: Input Bias Current, Input

Offset Current vs. Common Mode Input Vo ltage.

FIGURE 2-17: Quiescent Current vs.

Power Supply Voltage.

FIGURE 2-18: Quiescent Current vs.

Common Mode Input Voltage at VDD =5.5V.

-50 -25 0 25 50 75 100 125

Ambient Tem perat ure (°C)

CMRR, PSRR (dB)

Input Referred

PSRR, VIN+ = VSS, VDD = 1.6V to 5.5V

CMRR, VIN+ = -0.3 to 5.3V, VDD = 5.0V

0.1

100

1000

55 65 75 85 95 105 115 125

Ambient Temperature (°C)

Input Bias, Offset Currents

(pA)

| IOS |

VDD = 5.5V

VCM = VDD

0.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6

Common Mode Input Voltage (V)

Quiescent Curr ent

per Comparator (µA)

VDD = 1.6V

Sweep VIN+, VIN– = VDD/2

Sweep VIN–, VIN+ = VDD/2

IQ does not include pull-up resistor current

0.1

100

1000

10000

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

Common Mode Input V o ltag e (V)

Input Bias, Offset Currents

(A)

VDD = 5.5V

100f

100p

10p

10n IB, TA = +125°C

IB, TA = +85°C

IOS, T A = +125°C

IOS, TA = +85°C

0.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

Power Supply Voltage (V)

Quiescent Current

per Comparato r (µA)

TA= +125°C

TA= +85°C

TA= +25°C

TA = -40°C

0.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

Common Mode Input Voltage (V)

Quiescent Curr ent

per Comparator (µA)

VDD = 5.5V

Sweep VIN+, VIN– = VDD/2

Sweep VIN–, VIN+ = VDD/2

IQ does not include pull-up resistor current

MCP6546/6R/6U/7/8/9

Note: Unless otherwise indicated, VDD = +1.6V to +5.5V, VSS = GND, TA=+25°C, V

IN+=V

DD/2, VIN– = GND,

RPU =2.74kΩ to VPU =V

DD, and CL=36pF.

FIGURE 2-19: Supply Current vs. Pull-Up

Voltage.

FIGURE 2-20: Supply Current vs. Toggle

Frequency.

FIGURE 2-21: Output Voltage Headroom

vs. Output Current at VDD =1.6V.

FIGURE 2-22: Supply Current vs. Pull-Up

to Supply Voltage Difference.

FIGURE 2-23: Output Short Circuit Current

Magnitude vs. Power Supply Voltage.

FIGURE 2-24: Output Voltage Headroom

vs. Output Current at VDD =5.5V.

0.1

01234567891011

Pull-Up Voltage, VPU (V)

Supply Current

per Comparator (µA)

VDD = 2.1V

VDD = 2.6V

VDD = 3.6V

VDD = 4.6V

VDD = 5.6V

IDD spike near VPU = 1.3V

VDD = 1.6V

0.1

0.1 1 10 100

Toggle Frequency (kHz)

Supply Current

per Comparato r (µA)

VDD = 5.5V

VDD = 1.6V

100 mV Ove r dr ive

VCM = VDD/2

IDD does not include

pull-up resistor current

0.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6

Output Current (mA)

Output Voltage Headroom (V)

VDD = 1.6V VOL–VSS:

TA = +125°C

TA = +85°C

TA = +25°C

TA = -40°C

0.1

-4-3-2-10123456789

Pull-up to Supply Voltage Difference,

VPU – VDD (V)

Supply Current

per Comparator (µA)

VDD = 5.6V

VDD = 4.6V

VDD = 3.6V

VDD = 2.6V

VPU = 1.6V to 10.5V

VDD = 1.6V

VDD = 2.1V

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

Power Supply Voltage (V)

Output Short Circuit Current

Magnitude (mA)

TA = -40°C

TA = +25°C

TA = +85°C

TA = +125°C

0.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

0 5 10 15 20 25

Output Current (mA)

Output Voltage Headroom (V)

VDD = 5.5V

TA = +125°C

TA = +85°C

TA = +25°C

TA = -40°C

VOL – VSS:

MCP6546/6R/6U/7/8/9

Note: Unless otherwise indicated, VDD = +1.6V to +5.5V, VSS = GND, TA=+25°C, V

IN+=V

DD/2, VIN– = GND,

RPU =2.74kΩ to VPU =V

DD, and CL=36pF.

FIGURE 2-25: High-to-Low Propagation

Delay.

FIGURE 2-26: Propagation Delay Skew.

FIGURE 2-27: Propagation Delay vs.

Power Supply Voltage.

FIGURE 2-28: Low-to-High Propagation

Delay.

FIGURE 2-29: Propagation Delay vs.

Ambient Temperatu re .

FIGURE 2-30: Propagation Delay vs. Input

Overdrive.

10%

15%

20%

25%

30%

35%

40%

45%

50%

012345678

High-t o- Low Propag ati on Del ay (µs )

Percentage of Occurrences

408 Samples

100 mV Overdrive

VCM = VDD/2

VDD = 5.5VVDD = 1.6V

10%

15%

20%

25%

30%

35%

40%

45%

50%

-2.0

-1.6

-1.2

-0.8

-0.4

0.0

0.4

0.8

1.2

1.6

2.0

Propagation Delay Skew (µs)

Percent age of Occurren ces

408 Samples

100 mV Overdrive

VCM = VDD/2

VDD = 1.6V

VDD = 5.5V

1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

Power Supply Voltage (V)

Propag ati on De lay (µs )

VCM = VDD/2 tPHL

10 mV Overdrive

100 mV Overdrive tPLH

10%

15%

20%

25%

30%

35%

40%

45%

50%

55%

60%

65%

012345678

Low-to-High Propagation Delay (µs)

Percentage of Occurrences

408 Samples

100 mV Overdrive

VCM = VDD/2

VDD = 5.5V

VDD = 1.6V

-50 -25 0 25 50 75 100 125

Ambient Temperature (°C)

Propag ati on De lay (µs )

100 mV Overdrive

VCM = VDD/2

tPHL

tPLH

VDD = 5.5V

VDD = 1.6V

100

1 10 100 1000

Input Overdrive (mV)

Propag ati on Del ay (µs)

VCM = VDD/2

tPLH

VDD = 5.5V tPHL

VDD = 1.6V

MCP6546/6R/6U/7/8/9

Note: Unless otherwise indicated, VDD = +1.6V to +5.5V, VSS = GND, TA=+25°C, V

IN+=V

DD/2, VIN– = GND,

RPU =2.74kΩ to VPU =V

DD, and CL=36pF.

FIGURE 2-31: Propagation Delay vs.

Common Mode Input Voltage at VDD =1.6V.

FIGURE 2-32: Propagation Delay vs.

Pull-up Resistor.

FIGURE 2-33: Propagation Delay vs.

Pull-up Voltage.

FIGURE 2-34: Propagation Delay vs.

Common Mode Input Voltage at VDD =5.5V.

FIGURE 2-35: Propagation Delay vs. Load

Capacitance.

FIGURE 2-36: Output Leakage Current

(CS =V

DD) vs. Output Voltage (MCP6548 only).

0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6

Common Mode Input Voltage (V)

Propag ati on De lay (µs )

VDD = 1.6V

100 mV Overdrive

tPLH

tPHL

0 102030405060708090100

Pull-up Resistor, R

)

Propagation Delay (µs)

= V

+ = V

= 5.5V

– = 100 mV Overdrive

PHL

PLH

= 1.6V

01234567891011

Pull-up Voltage (V)

Propagation Delay (µs)

VCM = VDD/2

VIN+ = VCM tPHL

VIN– = 100 mV Overdrive

VDD = 5.5V

VDD = 1.6V tPLH

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

Common Mode Input Voltage (V)

Propag ati on De lay (µs )

VDD = 5.5V

100 mV Overdrive

tPHL

tPLH

100

120

140

160

180

200

0 102030405060708090

Load Capacitance (nF)

Propag ati on De lay (µs )

100 mV Overdrive

VCM = VDD/2 tPLH

tPHL

VDD = 1.6V

VDD = 5.5V

1.E-01

1.E+00

1.E+01

1.E+02

1.E+03

1.E+04

01234567891011

Output Voltage (V)

Output Leakage Current (A)

TA = +85°C

CS = VDD

VIN+ = VDD/2

VIN– = VSS

TA = +125°C

TA = +25°C

10n

100p

10p

100f

MCP6546/6R/6U/7/8/9

Note: Unless otherwise indicated, VDD = +1.6V to +5.5V, VSS = GND, TA=+25°C, V

IN+=V

DD/2, VIN– = GND,

RPU =2.74kΩ to VPU =V

DD, and CL=36pF.

FIGURE 2-37: Supply Curre nt (Shoo t-

through Current) vs. Chip Select (CS) Voltage at

VDD = 1.6V (MCP6548 only).

FIGURE 2-38: Su pply Current (Charging

Current) vs. Ch ip Select (CS) pulse at

VDD = 1.6V (MCP6548 only).

FIGURE 2-39: Chip Select (CS) Step

Response (MCP6548 only).

FIGURE 2-40: Supply Current (Shoot-

through Current) vs. Chip Select (CS) Voltage at

VDD = 5.5V (MCP6548 only).

FIGURE 2-41: Supply Current (Charging

Current) vs. Chip Select (CS) pulse at

VDD = 5.5V (MCP6548 only).

FIGURE 2-42: Input Bias Current vs. Input

Voltage.

1.E-11

1.E-10

1.E-09

1.E-08

1.E-07

1.E-06

1.E-05

1.E-04

1.E-03

0.00.20.40.60.81.01.21.41.6

Chip Select (CS) Voltage (V)

Supply Current

per Comparator (A)

Comparato

Shuts Of

Comparator

Turns On

VDD = 1.6V

CS Hysteresis

High-to-Low CS

Low-to-High

1µ

10µ

100n

10n

100p

10p

100µ

01234567891011121314

Time (1 ms/div)

Supply Current (µA)

-8.1

-6.5

-4.9

-3.2

-1.6

0.0

1.6

Output Voltag e,

Chip Select Voltage (V),

Start-up

IDD

Charging output

capacitance

VDD = 1.6V

VOUT

-0.5

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

012345678910

Time (ms)

Chip Select, Output Voltage

(V)

VOUT

VDD = 5.5V

1.E-11

1.E-10

1.E-09

1.E-08

1.E-07

1.E-06

1.E-05

1.E-04

1.E-03

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

Chip Select (CS) Voltage (V)

Suppl y Curr ent

per Comparator (A)

Comparato

Shuts Of

Comparator

Turns On

VDD = 5.5V

1µ

10µ

100n

10n

100p

10p

Low-to-High

Hysteresis CS

High-to-Low

100µ

100

120

140

160

180

200

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5

Time (0.5 ms/div)

Supply Current

per Comparator (µA)

-24

-21

-18

-15

-12

-9

-6

-3

Output Voltage,

Chip Select Voltage (V)

Start-up IDD

Charging output

capacitance

VDD = 5.5V

VOUT CS

1.E-12

1.E-11

1.E-10

1.E-09

1.E-08

1.E-07

1.E-06

1.E-05

1.E-04

1.E-03

1.E-02

-1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0

Input Voltage (V)

Input Current Magnitude (A)

+125°C

+85°C

+25°C

-40°C

10m

100µ

10µ

1µ

100n

10n

100p

10p

MCP6546/6R/6U/7/8/9

3.0 PIN DESCRIPTIONS

Descrip tions of the pins are listed in Table 3-1.

3.1 Analog Inputs

The comparator non-inverting and inverting inputs are

high-impedance CMOS inputs with low bias currents.

3.2 CS Digital Input

This i s a CMO S, Schmitt-tri ggered i nput that places the

part into a low power mode of operation.

3.3 Digital Outputs

The co mparator outputs are CM OS, open -drai n digi tal

outputs. They are designed to make level shifting and

wired-OR easy to implement.

3.4 Power Supply (VSS and VDD)

The positive power supply pin (VDD) is 1.6V to 5.5V

higher than the negative power supply pin (VSS). For

normal operation, the other pins are at voltages

between VSS and VDD, except the output pins which

can be as high as 10V above VSS.

Typically, these parts are used in a single (positive)

supply configuration. In this case, VSS is connected to

ground and VDD is connected to the supply. VDD will

need a local bypass capacitor (typically 0.01 µF to

0.1µF) within 2mm of the V

DD pi n. These can s hare a

bulk capacitor with nearby analog parts (within

100 mm), but it is not required.

TABLE 3-1: PIN FUNCTION TABLE

MCP6546

MCP6546R

MCP6546U

MCP6547

MCP6548

MCP6549

Symbol Description

PDIP,

SOIC,

MSOP

SC-70,

SOT-23 SOT-23-5 SC-70,

SOT-23-5

PDIP,

SOIC,

MSOP

PDIP,

SOIC,

MSOP

PDIP,

SOIC,

TSSOP

61 1 4161OUT,

OUTA Digital Output (comparator A)

24 4 3222V

IN–,

VINA–Inverting Input

(comparator A)

33 3 1333V

IN+,

VINA+N on- inv erti ng Inp ut

(comparator A)

75 2 5874V

DD Positive Power Supply

—— — — 5— 5V

INB+ Non-inv erti ng Inp ut

(comparator B)

—— — — 6— 6V

INB– Inverting Input (comparator B)

— — — — 7 — 7 OUTB Digital Output (comparator B)

— — — — — — 8 OUTC Digital Output (comparator C)

—— — ——— 9V

INC– Inverting Input (comparator C)

—— — ———10V

INC+ Non-inverting Inp ut

(comparator C)

42 5 24411V

SS Negative Power Supply

—— — ———12V

IND+ Non-inverting Inp ut

(comparator D)

—— — ———13V

IND– Inverting Input (comparator D)

— — — — — — 14 OUTD Digital Output (comparator D)

—— — ——8 — CSChip Select

1, 5, 8 — — — — 1, 5 — NC No Internal Connection

MCP6546/6R/6U/7/8/9

NOTES:

MCP6546/6R/6U/7/8/9

4.0 APPLICATIONS INFORMATION

The MCP6546/6R/6U/7/8/9 family of push-pull output

comp arator s are fabri cated on Microch ip’s state -of-the-

art CMOS process. They are suitable for a wide range

of applications requiring very low power consumption.

4.1 Comparator Inputs

4.1.1 PHASE REVERSAL

The MCP6546/6R/6U/7/8/9 comparator family uses

CMOS transistors at the input. They are designed to

prevent phase inversion when the input pins exceed

the supp ly v oltag es. Figure 2-3 shows an in pu t vol tage

exceeding both supplies with no resulting phase

inversion.

4.1.2 INPUT VOLTAGE AND CURRENT

LIMITS

The ESD protection on the inputs can be depicted as

shown in Figure 4-1. This struc ture w a s c ho sen to p r o-

tect the input transistors, and to minimize input bias

current (IB). The input ESD diodes clamp the inputs

when they try to go more than one diode drop below

VSS. They also clamp any voltages that go too far

above VDD; their breakdown voltage is high enough to

allow normal operation, and low enough to byp ass ESD

events within the sp eci fied limit s .

FIGURE 4-1: Simplified Analog Input ESD

Structures.

In order to prevent damage and/or improper operation

of these amplifiers, t he circuit s they are in must limit the

currents (and voltages) at the VIN+ and VIN– pins (see

Absolute Maximum Ratings † at the beginning of

Section 1.0 “Electrical Characteristics”). Figure 4-3

shows the reco mm en ded appro ach to protectin g t hes e

inputs. The internal ESD diodes prevent the input pins

(VIN+ and VIN–) from going too far below ground, and

the resistors R1 and R2 limit the possible current dr awn

out of the input pin. Diodes D1 and D2 prevent the inp ut

pin (VIN+ and VIN–) from going too far above VDD.

When imp lemented as sho wn, resistors R1 and R2 als o

limit the current through D1 and D2.

FIGURE 4-2: Protecting the Analog

Inputs.

It is also possible to connect the diodes to the left of

resistors R1 and R2. In this case, the currents through

diodes D1 and D2 need to be limited by some other

mechanism. The resistor the n serves as in-rush current

limiter; the DC current into the input pins (VIN+ and

VIN–) should be very small.

A significant amount of current can flow out of the

inputs when th e c om mo n mo de v ol t ag e (V CM) is bel ow

ground (VSS); see Figure 2-42. Applications that are

high impedance may need to limit the usable voltage

range.

4.1.3 NORMAL OPERATION

The input stage of this family of devices uses two

differential input stages in p arallel, one operates at low

input voltages, and the other at high input voltages.

With this topology , the input volt age is 0.3V above VDD

and 0.3V below VSS. The input offset voltage is

measured at both VSS - 0.3V and VDD + 0.3V to ensure

proper operation.

The MCP6546/6R/6U/7/8/9 family has internally-set

hysteresis that is small enough to maintain input offset

accuracy (<7 mV), and large enough to eliminate

output chattering caused by the comparator’s own

input noise voltage (200 µVP-P). Figure 4-3 illustrates

this capabilit y.

Bond

Pad

Bond

Pad

Bond

Pad

VDD

VIN+

VSS

Input

Stage Bond

Pad VIN–

V1MCP6G0X

VDD

≥

VSS – (minimum exp ec t ed V1)

2mA

VOUT

V2R2R3

–

≥

VSS – (minimum expected V2)

2mA

MCP6546/6R/6U/7/8/9

FIGURE 4-3: The MCP6546/6R/6U/7/8/9

Comparators’ Inte rnal Hys ter esi s E limi nat es

Output Chatter Caused By Input Noise V o ltage.

4.2 Open-Drain Output

The open-drain output is designed to make level-

shifting and wired-OR logic easy to implement. The

output can go as high as 10V for 9V battery-powered

applications. Th e output sta ge minimizes switchin g cur-

rent (shoot-through current from supply-to-supply)

when the output changes stat e. See Figures 2-15,2-18

and 2-37 through 2-41, for more information.

4.3 MCP6548 Chip Select (CS)

The MCP6548 is a single comparator with a Chip

Select (CS) pin. When CS is pulled high, the total

current consumption drops to 20 pA (typical). 1 pA

(typical) flows through the CS pin, 1 pA (typical) flows

through t he output pin and 18 pA (typical) flows through

the VDD pin, as shown in Figure 1-1. When this

happens, the comparator output is put into a high-

impedance state. By pulling CS low, th e co mpar a tor is

enabled . If the CS pin is left floating, the comparator will

not operate properly. Figure 1-1 shows the output

voltage and supply current response to a CS pulse.

The internal CS circuitry is designed to minimize

glitches when cycling the CS pin. This helps conserve

power , which is especially important in battery-powered

applications.

4.4 Externally Set Hysteresis

Greater flexibility in selecting hysteresis, or input trip

poi nts, is achieved by using external resistors.

Input off set vo lta ge (VOS) is the cen ter (average ) of the

(input-referred) low-high and high-low trip points. Input

hysteresis voltage (VHYST) is the difference between

the same trip points. Hysteresis reduces output

chattering when one input is slowly moving past the

other, thus reducing dynamic supply current. It also

helps in systems where it is best not to cycle between

states too frequently (e.g., air conditioner thermostatic

control).

4.4.1 INVERTING CIRCUIT

Figure 4-4 shows an inverting circ uit for a sing le-supply

application using three resistors, besides the pull-up

resistor. The resulting hysteresis diagram is shown in

Figure 4-5.

FIGURE 4-4: Inverting C ircuit with

Hysteresis.

FIGURE 4-5: Hysteresis Diagram for the

Inverting Circuit.

In order to d ete rmi ne th e tri p v oltage s (VTHL and VTLH)

for the circuit shown in Figure 4-4, R2 and R3 can be

simplified to the Thevenin equivalent circuit with

respect to VDD, as shown in Figure 4-6.

FIGURE 4-6: Theven in Equ iv al ent Circuit .

-3

-2

-1

Time (100 ms/div)

Output Voltage (V)

-30

-25

-20

-15

-10

-5

Input Voltage (10 mV/div)

VOUT

VIN–

VDD = 5.0V

Hysteresis

VIN VOUT

MCP654X

VDD

VPU

RPU

VDD IOL

IRF

IPU

VOUT

High-to-LowLow-to-High

VOH

VOL

VSS

VSS VDD

VTLH VTHL

VIN

VPU

VTLH = trip voltage from low to high

VTHL = trip voltage from high to low

V23

VOUT

MCP654X

VPU

R23 RF

-RPU

MCP6546/6R/6U/7/8/9

EQUATION 4-1:

Using this simplified circuit, the trip voltage can be

calculated using the following equation:

EQUATION 4-2:

Figures 2-21 and 2-24 can b e used to det erm ine typi -

cal values for VOL. This voltage is dependent on the

output current IOL as shown in Figure 4-4. This current

can be determined using the equation below:

EQUATION 4-3:

VOH can be calculated using the equation below:

EQUATION 4-4:

As explained in Section 4.1 “Comparator Inputs”, it

is important to keep the non-inverting input below

VDD+0.3V when VPU > VDD.

4.5 Supply Bypass

With this family of comparators, the power supply pin

(VDD for single supply) should have a local bypass

cap aci tor (i .e., 0 .01 µF to 0.1 µF) within 2 mm for good

edge-rate performance.

4.6 Capacitive Loads

Reasonable capacitive loads (e.g., logic gates) have

little impact on propagation delay (see Figure 2-27).

The supply current increases with increasing toggle

frequency (Figure 2-30), especially with higher

capacitive loads.

4.7 Battery Life

In order to maximize battery life in portable

applications, use large resistors and small capacitive

loads. Avoid toggling the output more than necessary.

Do no t us e C hi p S e l ec t (CS ) too frequently, in order to

conserve power. Capacitive loads will draw additional

power at start-up.

4.8 PCB Surface Leakage

In applications where low input bias current is critical,

PCB (Printed Circuit Board) surface leakage effects

need to be considered. Surface leakage is caused by

humidity, dust or other contamination on the board.

Under low-humidity conditions, a typical resistance

between nearby traces is 1012Ω. A 5V difference

would cause 5 pA of current to flow. This is greater

than the MCP6546/6R/6U/7/8/9 family’s bias current at

25°C (1 pA, typical).

The easiest way to reduce surface leakage is to use a

guard ring around se nsi tiv e p ins (or t race s). The guard

ring is biased at the same voltage as the sensitive pin.

An example of this type of layout is shown in

Figure 4-7.

FIGURE 4-7: Example Guard Ring Layout

for Inverting Circuit.

1. For the Inv erti ng Con fig uration (Figures 4-4 and

4-7):

a) Connect the guard ring to the non-inverting

input pin (VIN+). Thi s bi ases the gua rd ri ng

to the same reference voltage as the

compara tor (e.g., VDD/2 or ground).

b) Connec t the inverting pi n (VIN–) to the inp ut

pad, w itho ut touc hi ng the gua rd ring.

R23 R2R3

R2R3

-------------------=

V23 R3

R2R3

------------------- V DD

VTHL VPU R23

R23 RFRPU

----------------------------------------

⎝⎠

⎜⎟

⎛⎞

V23 RFRPU

R23 RFRPU

---------------------------------------

⎝⎠

⎛⎞

VTLH VOL R23

R23 RF

-----------------------

⎝⎠

⎜⎟

⎛⎞

V23 RF

R23 RF

----------------------

⎝⎠

⎛⎞

VTLH = trip voltage from low to high

VTHL = trip voltage from high to low

IOL IPU IRF

IOL VPU VOL

–

RPU

--------------------------

⎝⎠

⎛⎞

V23 VOL

–

R23 RF

------------------------

⎝⎠

⎛⎞

VOH VPU V23

–()

R23 RF

R23 RFRPU

---------------------------------------

⎝⎠

⎛⎞

Guard Ring

VSS

VIN-V

IN+

MCP6546/6R/6U/7/8/9

4.9 Unused Comparators

An unused amplifier in a quad package (MCP6549)

should be configured as shown in Figure 4-8. This

circuit prevents the output from toggling and causing

crosstalk. It uses the minimum number of components

and draws minimal current (see Figure 2-15 and

Figure 2-18).

FIGURE 4-8: Unused Comparators.

4.10 Typical Applications

4.10.1 PRECISE COMPARATOR

Some applications require higher DC precision. An

easy way to solve this problem is to use an amplifier

(such as the MCP6041) to gain-up the input signal

before it reaches the comparator. Figure 4-9 shows an

example of this approach.

FIGURE 4-9: Precise Inverting

Comparator.

4.10.2 WINDOWED COMPARATOR

Figure 4-10 shows one approach to designing a

windowed comparator. The wired-OR connection

produ ces a high o utput ( logic 1) wh en the input v olt age

is between VRB and VRT (where VRT > VRB).

FIGURE 4-10: Windowed Comparator.

¼ MCP6549

VDD

–

VREF

VDD

R1R2VOUT

VIN

VREF

VPU

RPU

MCP6546

MCP6041

VRT

1/2

VRB

VIN

VPU

RPU

VOUT

MCP6547

1/2

MCP6547

MCP6546/6R/6U/7/8/9

5.0 PACKAGING INFORMATION

5.1 Package Marking Information

5-Lead SC-70 (MCP65 46, MCP6 546U) Example: (I-temp)

Device I-Temp

Code E-Temp

Code

MCP6546 ACNN Note 2

MCP6546U BBNN Note 2

Note 1: I-Temp parts prior to March 2005 are

marked “ACN”

2: SC-70-5 E-Temp parts not available at

this release of the data sheet.

Example: (I-temp)

OR AC25

AC25 (Front)

148 (Back)

5-Lead SOT-23 (MCP6546, MCP6546R, MCP6546U) Example: (I-tem p)

Device I-Temp

Code E-Temp

Code

MCP6546 ACNN GWNN

MCP6546R AHNN GXNN

MCP6546U — AWNN

Note: Applies to 5-Lead SOT-23

AC25

8-Lead PDIP (300 mil) (MCP6546, MCP6547, MCP6548, MCP6549) Examples:

MCP6546 I/P^^256

1148

MCP6546

I/P256 1148

8-Lead SOIC (150 mil) (MCP6546, MCP6547, MCP6548, MCP6549)

MCP6547 MCP6547

I/SN1148

256 256

S N^^1148

Legend: XX...X Customer-specific information

Y Year code (last digit of calendar year)

YY Year code (last 2 digits of calendar year)

WW Week code (week of January 1 is week ‘01’)

NNN Alphanumeric traceability code

Pb-free JEDEC designator for Matte Tin (Sn)

*This package is Pb-free. The Pb-free JEDEC designator ( )

Note: In the event the fu ll Mic rochip part nu mber ca nnot be m arked o n one lin e, it will

be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

MCP6546/6R/6U/7/8/9

Package Marking Information (Continued)

8-Lead MSOP (MCP6546, MCP6547, MCP6548)Example:

6546I

148256

14-Lead PDIP (300 mil) (MCP6549) Example:

MCP6549-I/P

1148256

MCP6549-E/P

I/P^^

MCP6549

Legend: XX...X Customer-specific information

Y Year code (last digit of calendar year)

YY Year code (last 2 digits of calendar year)

WW Week code (week of January 1 is week ‘01’)

NNN Alphanumeric traceability code

Pb-free JEDEC designator for Matte Tin (Sn)

*This package is Pb-free. The Pb-free JEDEC designator ( )

Note: In the event the fu ll Mic rochip part nu mber ca nnot be m arked o n one lin e, it will

be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

MCP6546/6R/6U/7/8/9

Package Marking Information (Continued)

XXXXXXXXXX

Example:14-Lead SOIC (150 mil) (MCP6549)

MCP6549ISL

1148256

MCP6549

1148256

E/SL^^

14-Lead TSSOP (MCP6549) Example:

MCP6549I

1148

256

Legend: XX...X Customer-specific information

Y Year code (last digit of calendar year)

YY Year code (last 2 digits of calendar year)

WW Week code (week of January 1 is week ‘01’)

NNN Alphanumeric traceability code

Pb-free JEDEC designator for Matte Tin (Sn)

*This package is Pb-free. The Pb-free JEDEC designator ( )

Note: In the event the fu ll Mic rochip part nu mber ca nnot be m arked o n one lin e, it will

be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

MCP6546/6R/6U/7/8/9





 

 

 

 



 

   

  

  

    

    

    

    

    

    

    

    

    

AA2

   

MCP6546/6R/6U/7/8/9



MCP6546/6R/6U/7/8/9

 !



 



 

   

  

  

  

    

    

    

    

    

    

    

    

   

    

    

123

A2 c

   

MCP6546/6R/6U/7/8/9

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

MCP6546/6R/6U/7/8/9

"#$%!&'#$



 

 

 

 





 

   

  

  

    

    

    

    

    

    

    

    

    

    

    

NOTE 1

123

   

MCP6546/6R/6U/7/8/9

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

MCP6546/6R/6U/7/8/9

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

MCP6546/6R/6U/7/8/9

"%()!*+&'$



MCP6546/6R/6U/7/8/9

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

MCP6546/6R/6U/7/8/9

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

MCP6546/6R/6U/7/8/9

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

MCP6546/6R/6U/7/8/9

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

MCP6546/6R/6U/7/8/9



MCP6546/6R/6U/7/8/9

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

MCP6546/6R/6U/7/8/9

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

MCP6546/6R/6U/7/8/9

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

MCP6546/6R/6U/7/8/9

NOTES:

MCP6546/6R/6U/7/8/9

APPENDIX A: REVISION HISTORY

Revision G (February 2012)

The following is the list of modifications:

1. Updated the Package Types drawing t o correc t

the device repres entation of th e SC-70 package.

2. Updated package temperatures in the

Temperature Characteristics table.

3. Corrected the marking information table for the

5-Lead SC-70 package (MCP6546 and

MCP6546U) in Section 5.1, Package Marking

Information.

4. Updated the package outline drawings in

Section 5.1 “Package Marking Information”,

to show all views for each package.

5. Minor editorial changes.

Revision F (September 2007)

The following is the list of modifications:

1. Corrected polarity of MCP6546U SOT-23-5 pin-

out diagram on the first page.

2. Updated package outline drawings in

Section 5.1 “Package Marking Information”

per Marcom.

Revision E (September 2006)

The following is the list of modifications:

1. Added MCP6546U pinout for the SOT-23-5

package.

2. Clarified Absolute Maximum Analog Input

Voltage and Current Specifications.

3. Added application information on unused

comparators.

4. Added disclaimer to package outline drawings.

Revision D (May 2006)

The following is the list of modifications:

1. Added E-temp parts.

2. Changed minimum pull-up voltage specification

(VPU) to 1.6V for parts starting Dec. 2004 (week

code 52); previous parts are specified at a

minimum of V DD.

3. Changed VHYST temperature specifications to

linear and qua dratic temper atur e coefficients.

4. Changed specifications and plots to include E-

Temp parts.

5. Added Sec tion 3.0 “Pin Descriptions” .

6. Corrected package markings (Section 5.1

“Package Marking Information”).

7. Added Appendix A: “Revision History”.

Revision C (May 2003)

• Undocumented changes.

Revision B (December 2002)

• Undocumented changes.

Revision A (February 2002)

• Original Release of this Document.

MCP6546/6R/6U/7/8/9

NOTES:

MCP6546/6R/6U/7/8/9

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

Device: MCP6546: Single Comparator

MCP6546 T: Single Compara tor (Ta pe and Ree l)

(SC-70, SOT-23, SOIC, MSOP)

MCP 6546RT: Single Comparator (Rotated - Tape and

Reel) (SOT-23 only)

MCP6546 U T: Single Com para tor (Ta pe and Reel )

(SC-70, SO T-23)(SOT-23-5 is E-Temp only)

MCP6547: Dual Comparator

MCP6547T: Dual Comparator

(Tape and Reel for SOIC and MSOP)

MCP6548: Single Com para tor wi th CS

MCP6548T: Single Compara tor wi th CS

(Tape and Reel for SOIC and MSOP)

MCP6549: Quad Comparator

MCP6549T: Quad Comparator

(Tape and Reel for SOIC and TSSOP)

Temperature Range: I = -40°C to +85°C

E * = -40°C to +125°C

* SC-70-5 E-Temp parts not available at this release of the

data sheet.

Package: LT = Plastic Package (SC-70), 5-lead

OT = Plastic Small Outline Transistor (SOT-23), 5-lead

MS = Plastic MSOP, 8-lead

P = Plastic DIP (300 mil Body), 8-lead, 14-lead

SN = Plastic SOIC (150 mil Body), 8-lead

SL = Plastic SOIC (150 mil Body), 14-lead (MCP6549)

ST = Plastic TSSOP (4.4mm Body), 14-lead (MCP6549)

PART NO. –X /XX

PackageTemperature

Range

Device

Examples:

a) MCP6546T-I/LT: Tape and Reel,

Industrial Temperature,

5LD SC-70.

b) MCP6546T-I/OT: Tape and Reel,

Industrial Temperature,

5LD SOT-23.

c) MCP65 46-I/MS: Tape and Reel,

Industrial Temperature,

8LD MSOP.

d) MCP6546-E/P: Extended Temperature,

8LD PDIP.

e) MCP6546-E/SN: Extended Temperature,

8LD SOIC.

a) MCP6546 RT-I/OT: Ta pe and Reel,

Indus trial Tem per atu re ,

5LD SOT23.

a) MCP6546 U T-E/LT: Tape and Reel ,

Indus trial Tem per atu re ,

5LD SC-70

b) MCP6546UT-E/OT: Tape and Reel,

Extended Temper ature,

5LD SOT23.

a) MCP6547-I/MS: Industrial Temperature,

8LD MSOP.

b) MCP6547T-I/MS: Tape and Reel,

Industrial Temperature,

8LD MSOP.

c) MCP6547-I/P: Industrial Temperature,

8LD PDIP.

d) MCP6547-E/SN: Extended Temperature,

8LD SOIC.

a) MCP6548-I/SN: Industrial Temperature,

8LD SOIC.

b) MCP6548T-I/SN: Tape and Reel,

Industrial Temperature,

8LD SOIC.

c) MCP6548-I/P: Industrial Temperature,

8LD PDIP.

d) MCP6548-E/SN: Extended Temperature,

8LD SOIC.

a) MCP6549T-I/SL: Tape and Reel,

Industrial Temperature,

14LD SOIC.

b) MCP6549T-E/SL: Tape and Reel,

Extended Temper ature,

14LD SOIC.

c) MCP6549-I/P: Industrial Temperature,

14LD PDIP.

d) MCP6549-E/ST: Extended Temperature,

14LD TSSOP.

MCP6546/6R/6U/7/8/9

NOTES:

Information contained in this publication regarding device

applications a nd the lik e is provided only f or yo ur convenience

and may be supers ed ed by u pda t es . It is y our responsibil it y to

ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR

WARRANTIES OF ANY KIND WHETHER EXPRESS OR

IMPLIED, WRITTEN OR ORAL, STATUTORY OR

OTHERWISE, RELATED TO THE INFORMATION,

INCLUDING BUT NOT LIMITED TO ITS CONDITION,

QUALITY, PERFORMANCE, MERCHANTABILITY OR

FITNESS FOR PURPOSE. Microchip disclaims all liability

arising from this information and its use. Use of Microchip

devices in life support and/or safety applications is entirely at

the buyer’s risk, and the buyer agrees to defend, indemnify and

hold harmless Microchip from any and all damages, claims,

suits, or expenses resulting from such use. No licenses are

conveyed, implicitly or otherwise, under any Microchip

intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, dsPIC,

KEELOQ, KEELOQ logo, MPL AB, PIC , PI Cmi cro, PI CSTART,

PIC32 logo, rfPIC and UNI/O are registered trademarks of

Microchip Technology Incorporat ed in the U.S.A. and other

countries.

FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,

MXDEV, MXLAB, SEEVAL and The Embedded Contr ol

Solutions Company are registered trademarks of Microchip

Technology Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, chipKIT,

chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net,

dsPICworks, dsSPEAK, ECAN, ECONOMONITOR,

FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP,

Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB,

MPLINK, mTouch, Omniscient Code Generation, PICC,

PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE,

rfLAB, Select Mode, Total Endurance, TSHARC,

UniWinDriver, WiperLock and ZENA are trademarks of

Microchip Technology Incorporat ed in the U.S.A. and other

countries.

SQTP is a service mark of Microchip T echnology Incorporated

in the U.S.A.

All other trademarks mentioned herein are property of their

respective companies.

Printed on recycled paper.

ISBN: 978-1-62076-019-2

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on t he market today, when used in the

intended manner and under normal conditions.

• The re are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is c onstantly evolving. We a t Microc hip are co m mitted to continuously improving the code prot ect ion featur es of our

products. Attempts to break Microchip’ s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Microchip received ISO/TS-16949:2009 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and

Tempe, Arizona; Gresham, Oregon and design centers in California

and India. The Company’s quality system processes and procedures

are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hoppi ng

devices, Serial EEPROMs, microperiph erals, nonvolatile memory and

analog products. In addition, Microchip’s quality system for the design

and manufacture of development systems is ISO 9001:2000 certified.

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11/29/11