General Description
The DS3930 contains six 256-position nonvolatile (NV)
potentiometers, 64 bytes of NV user EEPROM memory,
and four programmable NV I/O pins. The six poten-
tiometers all share a common low side. The potentiome-
ters are separated into two groups of three 50kΩ
potentiometers in parallel. Each group of three poten-
tiometers shares a common high side and forms an
equivalent resistance of 16.6kΩ(three 50kΩpoten-
tiometers in parallel).
Applications
RF Transceivers
Voltage References
Power Supply Calibration
Mobile Phones and PDAs
Fiber Optic Transceiver Modules
Portable Electronics
Radio Tuners
Small, Low-Cost Replacement for Mechanical
Potentiometers
Features
♦Six 256-Position NV Potentiometers
♦Four General-Purpose NV I/O Pins
♦64 Bytes of User EEPROM Memory
♦0 to 5.5V on Any Potentiometer Terminal,
Independent of VCC
♦All Six Potentiometers Share a Common Low Side
♦Potentiometers Separated into Two Groups of
Three Potentiometers, Each Sharing a Common
High Side
♦2-Wire Serial Interface
♦Wide Supply Range (2.7V to 5.5V)
♦Up to Eight DS3930s Can Share the Same
2-Wire Bus
DS3930
Hex Nonvolatile Potentiometer with
I/O and Memory
_____________________________________________ Maxim Integrated Products 1
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
HI0-2
W0
W1
W2
SDA
A2
A1
A0
TOP VIEW
LO0-5
HI3-5
W3
W4
I/O2
I/O1
I/O0
SCL
12
11
9
10
W5
I/O3
GND
VCC
TSSOP
DS3930
Pin Configuration
A2
SDA
GND
SCL
I/O3
I/O2
I/O1
I/O0
LO0-5
A0
A1
HI0-2
HI3-5
W0
W1
W2
W3
W4
W5
VCC
VCC VCC
VCC
DECOUPLING CAP
0.1µF
2-WIRE
INTERFACE
4.7kΩ4.7kΩ
DIGITAL
NONVOLATILE I/O
DIGITAL
NONVOLATILE I/O
WIPER
TERMINALS
WIPER
TERMINALS
DS3930
Typical Operating Circuit
Ordering Information
Rev 0; 4/03
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
PART PIN-PACKAGE
DS3930E20 TSSOP
DS3930
Hex Nonvolatile Potentiometer with
I/O and Memory
2______________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
RECOMMENDED DC OPERATING CONDITIONS
(TA= -40° to +85°C)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Voltage on VCC Relative to Ground...................... -0.5V to +6.0V
Voltage on I/O0, I/O1, I/O2, I/O3, SDA, SCL, A0, A1, and A2
Relative to Ground* .............................. -0.5V to (VCC + 0.5V)
Voltage on LO0-5, W0-5, HI0-2, and HI3-5
Relative to Ground ............................................-0.5V to +6.0V
Current Through W0-5........................................................ ±1mA
Operating Temperature Range .......................... -40°C to +85°C
Programming Temperature Range .........................0°C to +70°C
Storage Temperature Range .............................-55°C to +125°C
Soldering Temperature.................. See IPC/JEDEC J-STD-020A
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX
UNITS
Supply Voltage VCC (Note 1)
+2.7 +5.5
V
Input Logic 1 (SDA, SCL, A0, A1,
A2, I/O0, I/O1, I/O2, I/O3)VIH 0.7 x
VCC
VCC +
0.3 V
Input Logic 0 (SDA, SCL, A0, A1,
A2, I/O0, I/O1, I/O2, I/O3)VIL
-0.3
0.3 x
VCC V
Wiper Current IW-1 +1 mA
Potentiometer Terminals
(LO0-5, W0-5, HI0-2, and HI3-5) VCC = +2.7V to +5.5V
-0.3 +5.5
V
DC ELECTRICAL CHARACTERISTICS
(VCC = +2.7V to +5.5V; TA= -40°C to +85°C, unless otherwise specified.)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX
UNITS
Input Leakage IIL -1 +1 µA
VOL1 3mA sink current 0 0.4 V
Low-Level Output Voltage (SDA,
I/O0, I/O1, I/O2, I/O3)VOL2 6mA sink current 0 0.6 V
I/O Capacitance CI/O 10 pF
I/O Pullup Resistor Value RI/O 3.5 5 7.0 kΩ
3V (Note 2)
160
300
Standby Current ISTBY 5V (Note 2)
195
350 µA
*This voltage must not exceed 6.0V.
DS3930
Hex Nonvolatile Potentiometer with
I/O and Memory
_____________________________________________________________________ 3
AC ELECTRICAL CHARACTERISTICS
(VCC = +2.7V to +5.5V; TA= -40°C to +85°C, unless otherwise specified.)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX
UNITS
Fast mode 0 400
SCL Clock Frequency (Note 3) fSCL Standard mode 0 100 kHz
Fast mode 1.3
Bus Free Time Between STOP
and START Condition (Note 3) tBUF Standard mode 4.7 µs
Fast mode 0.6
Hold Time (Repeated) START
Condition (Notes 3 and 4)
tHD:STA
Standard mode 4.0 µs
Fast mode 1.3
Low Period of SCL Clock (Note 3)
tLOW Standard mode 4.7 µs
Fast mode 0.6
High Period of SCL Clock
(Note 3) tHIGH Standard mode 4.0 µs
ANALOG RESISTOR CHARACTERISTICS
(VCC = +2.7V to +5.5V; TA= -40°C to +85°C, unless otherwise specified.)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX
End-to-End Resistance TA = +25°C (three 50kΩ pots in parallel)
13.2 16.5 19.8
kΩ
Wiper Resistance RW
400 1000
Ω
Factory Default Wiper Setting FF Hex
Factory Default I/O Setting 0F Hex
POT-to-POT Matching -1 +1 LSB
Differential Linearity
-0.5 +0.5
LSB
Integral Linearity -1 +1 LSB
End-to-End Temperature
Coefficient 3 potentiometers in parallel
-250
0
+250
Ratiometric Temperature
Coefficient 2
DS3930
Hex Nonvolatile Potentiometer with
I/O and Memory
4______________________________________________________________________
Note 1: All voltages are referenced to ground.
Note 2: ISTBY specified for VCC equal 3.0V and 5.0V, SDA = SCL = VCC,and I/O0= I/O1 = I/O2 = I/O3 = A0 = A1 = A2 = GND.
Note 3: A fast-mode device can be used in a standard-mode system, but the requirement tSU:DAT > 250ns must then be met.
This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does
stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line tRMAX + tSU:DAT = 1000ns
+250ns = 1250ns before the SCL line is released.
Note 4: After this period, the first clock pulse is generated.
Note 5: The maximum tHD:DAT has only to be met if the device does not stretch the LOW period (tLOW) of the SCL signal.
Note 6: A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the VIH MIN of the SCL sig-
nal) in order to bridge the undefined region of the falling edge of SCL.
Note 7: CB—total capacitance of one bus line in picofarads, timing referenced to 0.9VCC and 0.1VCC.
Note 8: EEPROM write begins after a STOP condition occurs.
AC ELECTRICAL CHARACTERISTICS (continued)
(VCC = +2.7V to +5.5V; TA= -40°C to +85°C, unless otherwise specified.)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
Fast mode 0 0.9
Data Hold Time (Notes 3, 5, 7)
tHD:DAT
Standard mode 0 0.9 µs
Fast mode 100
Data Setup Time (Note 3)
tSU:DAT
Standard mode 250 ns
Fast mode 0.6
Start Setup Time (Note 3) tSU:STA Standard mode 4.7 µs
Fast mode
20 + 0.1CB
300
Rise Time of Both SDA and SCL
Signals (Note 7) tRStandard mode
20 + 0.1CB1000
ns
Fast mode
20 + 0.1CB
300
Fall Time of Both SDA and SCL
Signals (Note 7) tFStandard mode
20 + 0.1CB
300 ns
Fast mode 0.6
Setup Time for STOP Condition
tSU:STO
Standard mode 4.0 µs
Capacitive Load for Each Bus CB(Note 7) 400 pF
EEPROM Write Time tW(Note 8) 5 20 ms
EEPROM CHARACTERISTICS
(VCC = +2.7V to +5.5V; TA= -40°C to +85°C, unless otherwise specified.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Writes +70°C
50,000
DS3930
Hex Nonvolatile Potentiometer with
I/O and Memory
_____________________________________________________________________ 5
VOLTAGE DIVIDER % CHANGE
FROM +25°C vs. TEMPERATURE
DS3930 toc06
TEMPERATURE (°C)
RESISTANCE % CHANGE (FROM +25°C)
8060-20 0 20 40
-0.15
-0.10
-0.05
0
0.05
0.10
0.15
0.20
-0.20
-40 100
HI = VCC
LO0-5 = GND
POSITION 127
END-TO-END RESISTANCE % CHANGE
FROM +25°C vs. TEMPERATURE
DS3930 toc05
TEMPERATURE (°C)
RESISTANCE % CHANGE (FROM +25°C)
806020 400-20
-0.80
-0.60
-0.40
-0.20
0
0.20
0.40
0.60
0.80
1.00
-1.00
-40 100
3 POTS IN PARALLEL
MEASURED FROM HI0-2 TO LO0-5
WIPER VOLTAGE
vs. POWER-UP VOLTAGE
DS3930 toc04
POWER-UP VOLTAGE (V)
WIPER VOLTAGE (V)
4.54.03.53.02.52.01.51.00.5
0.5
1.0
1.5
2.0
2.5
3.0
0
0 5.0
HI = 5V, LO = GND
POSITION 127
EEPROM RECALL
FOLLOWS VCC
CHANGES TO
PROGRAMMED
VALUE ONCE
EEPROM IS
RECALLED
ACTIVE SUPPLY CURRENT
vs. SCL FREQUENCY
DS3930 toc03
SCL FREQUENCY (kHz)
SUPPLY CURRENT (µA)
300200100
260
320
380
440
500
560
620
680
740
200
0 400
VCC = 5V
VCC = 3V
SDA = VCC
WIPER VOLTAGE vs. WIPER SETTING
DS3930 toc02
SETTING (DEC)
VOLTAGE (V)
25020015010050
1
2
3
4
5
6
0
0 300
HI = 5V
LO = GND
SUPPLY CURRENT vs. TEMPERATURE
DS3930 toc01
TEMPERATURE (°C)
SUPPLY CURRENT (µA)
806040200-20
140
160
180
200
220
120
-40 100
VCC = 5V
VCC = 3V
SDA = SCL = 5V
Typical Operating Characteristics
(VCC = 5.0V; TA = +25°C, unless otherwise specified.)
ALL POTS DNL (LSB)
DS3930 toc08
POSITION (DEC)
DNL (LSB)
225200150 17550 75 100 12525
-0.08
-0.06
-0.04
-0.02
0
0.02
0.04
0.06
0.08
0.10
-0.10
0 250
POTS 1, 3, 5 INL (LSB)
DS3930 toc09
POSITION (DEC)
INL (LSB)
225200150 17550 75 100 12525
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
-0.5
0 250
POTS 0, 2, 4, INL (LSB)
DS3930 toc07
POSITION (DEC)
INL (LSB)
225200150 17550 75 100 12525
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
-0.5
0 250
Pin Description
PIN NAME FUNCTION
1A0Address Input. The address input pins determine the 2-wire address of the device.
2A1Address Input
3A2Address Input
4SDA 2-Wire Serial Data I/O. This pin is for serial data transfer to and from the device.
5SCL 2-Wire Serial Clock Input. The serial clock input is used to clock data into and out of the device.
6 I/O0General-Purpose NV I/O Pin
7 I/O1General-Purpose NV I/O Pin
8 I/O2General-Purpose NV I/O Pin
9V
CC Supply Voltage
10 GND Ground
11 I/O3General-Purpose NV I/O Pin
12 W5Wiper Terminal of Potentiometer 5
13 W4Wiper Terminal of Potentiometer 4
14 W3Wiper Terminal of Potentiometer 3
15 HI3-5 High-End Terminal of Potentiometers 3 to 5. This is the common high-side terminal of potentiometers
3, 4, and 5.
16 LO0-5 Low-End Terminal of the Potentiometers. This is the common low-side terminal of all six
potentiometers.
17 W2Wiper Terminal of Potentiometer 2
18 W1Wiper Terminal of Potentiometer 1
19 W0Wiper Terminal of Potentiometer 0
20 HI0-2 High-End Terminal of Potentiometers 0 to 2. This is the common high-side terminal of potentiometers
0, 1, and 2.
DS3930
Hex Nonvolatile Potentiometer with
I/O and Memory
6______________________________________________________________________
Detailed Description
The DS3930 contains six NV potentiometers with 64
bytes of NV user memory (EEPROM), and four pro-
grammable NV I/O pins. Figure 1 is a functional dia-
gram of the DS3930.
Potentiometers
The six potentiometers share a common low side and
are separated into two groups of three potentiometers,
each group sharing a common high side. The six 256-
position potentiometers are controllable using six 8-bit
EEPROM registers through the 2-wire interface.
DS3930
Hex Nonvolatile Potentiometer with
I/O and Memory
_____________________________________________________________________ 7
2-WIRE
INTERFACE
VCC
A0
SDA
SCL
A1
A2
GND
POT0
50kΩ
50kΩ
50kΩ
50kΩ
50kΩ
50kΩ
POT1
POT2
POT3
POT4
POT5
W0
W1
W2
W3
W4
W5
HI0-2
LO0-5
HI3-5
I/O0
I/O1
I/O2
I/O3
I/O CELL X 4
64 BYTES OF
EEPROM
RESERVED
POT0 CONTROL
I/O CONTROL
I/O STATE
RESERVED
FFh
F8h
F7h
F6h
F5h
POT1 CONTROL
POT2 CONTROL
POT3 CONTROL
POT4 CONTROL
POT5 CONTROL
F1h
F2h
F3h
F4h
EFh
F0h
00h
3Fh
40h
8
8
8
8
8
8
8
4
EEPROM
DS3930
Figure 1. DS3930 Functional Diagram
DS3930
Hex Nonvolatile Potentiometer with
I/O and Memory
8______________________________________________________________________
I/O Signals
The I/O pins can be used as general-purpose digital
I/O signals. The I/O pins have CMOS outputs with an
internal pullup resistor (see Figure 2). The I/O pins are
configured with the I/O Control register (F6h) and moni-
tored with the I/O State register (F7h). The I/O Control
register controls the state of the internal pullup resistor
(RI/O) with bits 7 to 4 and the I/O pin setting with bits 3
to 0 (see Table 1). The read-only values of the I/O State
register contains the values of the I/O pin setting bits of
the I/O Control register unless the I/O output is tri-stat-
ed. When the I/O is tri-stated the I/O State register will
read high or low depending on the external source on
the I/O pin. Since the I/O pins are controlled by EEP-
ROM, the number of writes is limited.
Memory
The memory map is shown in Table 2.
Table 2. Memory Map
ADDRESS
BIT DEFAULT (HEX) FUNCTION
00h to 3Fh
FF 64 bytes of general-purpose EEPROM
40h to EFh
FF Reserved
F0h FF Controls potentiometer 0
F1h FF Controls potentiometer 1
F2h FF Controls potentiometer 2
F3h FF Controls potentiometer 3
F4h FF Controls potentiometer 4
F5h FF Controls potentiometer 5
F6h 0F I/O Control
Bit 7 Set to 0 to enable I/O3 pullup, set to 1 to disable pullup
Bit 6 Set to 0 to enable I/O2 pullup, set to 1 to disable pullup
Bit 5 Set to 0 to enable I/O1 pullup, set to 1 to disable pullup
Bit 4 Set to 0 to enable I/O0 pullup, set to 1 to disable pullup
Bit 3 Sets I/O3 to 0 or 1
Bit 2 Sets I/O2 to 0 or 1
Bit 1 Sets I/O1 to 0 or 1
Bit 0 Sets I/O0 to 0 or 1
F7h 0X I/O State
Bit 7 0
Bit 6 0
Bit 5 0
Bit 4 0
Bit 3 Contains state of I/O3 pin (read only)
Bit 2 Contains state of I/O2 pin (read only)
Bit 1 Contains state of I/O1 pin (read only)
Bit 0 Contains state of I/O0 pin (read only)
F8h to FFh
FF Reserved
PULLUP CTRL
(I/O CONTROL
REGISTER)
(BITS 7 TO 4)
I/O PIN SETTING
(I/O CONTROL
REGISTER)
(BITS 3 TO 0)
I/O PIN OUTPUT
00 0
01 1
10 0
11Pullup disabled (HI-Z)
Table 1. I/O Pin Truth Table
DS3930
Hex Nonvolatile Potentiometer with
I/O and Memory
_____________________________________________________________________ 9
2-Wire Serial Port Operation
The 2-wire serial port interface supports a bidirectional
data transmission protocol with device addressing. A
device that sends data on the bus is defined as a trans-
mitter, and a device receiving data as a receiver. The
device that controls the message is called a “master.”
The devices that are controlled by the master are
“slaves.” The bus must be controlled by a master
device that generates the serial clock (SCL), controls
the bus access, and generates the start and stop con-
ditions. The DS3930 operates as a slave on the 2-wire
bus. Connections to the bus are made through the
open-drain I/O lines, SDA and SCL. The following I/O
terminals control the 2-wire serial port: SDA, SCL, and
A0. Timing diagrams for the 2-wire serial port can be
found in Figures 3 and 5. Timing information for the 2-
wire serial port is provided in the AC Electrical
Characteristics table for 2-wire serial communications.
The following bus protocol has been defined:
•Data transfer can be initiated only when the bus is
not busy.
•During data transfer, the data line must remain sta-
ble whenever the clock line is high. Changes in the
data line while the clock line is high are interpreted
as control signals.
Accordingly, the following bus conditions have been
defined:
Bus Not Busy: Both data and clock lines remain high.
Start Data Transfer: A change in the state of the data
line from high to low while the clock is high defines a
start condition.
Stop Data Transfer: A change in the state of the data
line from low to high while the clock line is high defines
the stop condition.
Data Valid: The state of the data line represents valid
data when, after a start condition, the data line is stable
for the duration of the high period of the clock signal. The
data on the line can be changed during the low period of
the clock signal. There is one clock pulse per bit of data.
Figures 3 and 5 detail how data transfer is accomplished
on the 2-wire bus. Depending upon the state of the R/W
bit, two types of data transfer are possible.
Each data transfer is initiated with a start condition and
STOP
CONDITION
OR REPEATED
START
CONDITION
REPEATED IF MORE BYTES
ARE TRANSFERRED
ACK
START
CONDITION
ACK
ACKNOWLEDGEMENT
SIGNAL FROM RECEIVER
ACKNOWLEDGEMENT
SIGNAL FROM RECEIVER
SLAVE ADDRESS
MSB
SCL
SDA
R/W
DIRECTION
BIT
12 678 9 12 893–7
Figure 3. 2-Wire Data Transfer Protocol
PULLUP
CTRL
I/O PIN
SETTING
RI/O
VCC
ESD
I/O
INPUT
Figure 2. I/O Cell
DS3930
Hex Nonvolatile Potentiometer with
I/O and Memory
10 _____________________________________________________________________
terminated with a stop condition. The number of data
bytes transferred between start and stop conditions is
not limited and is determined by the master device. The
information is transferred byte-wise and each receiver
acknowledges with a ninth bit.
Within the bus specifications, a regular mode (100kHz
clock rate) and a fast mode (400kHz clock rate) are
defined. The DS3930 works in both modes.
Acknowledge: Each receiving device, when addressed,
is obliged to generate an acknowledge after the byte has
been received. The master device must generate an
extra clock pulse that is associated with this acknowl-
edge bit.
A device that acknowledges must pull down the SDA
line during the acknowledge clock pulse in such a way
that the SDA line is a stable low during the high period
of the acknowledge-related clock pulse. Of course,
setup and hold times must be taken into account. A
master must signal an end of data to the slave by not
generating an acknowledge bit on the last byte that has
been clocked out of the slave. In this case, the slave
must leave the data line high to enable the master to
generate the stop condition.
Data transfer from a master transmitter to a slave
receiver. The first byte transmitted by the master is the
command/control byte. Next follows a number of data
bytes. The slave returns an acknowledge bit after each
received byte.
Data transfer from a slave transmitter to a master
receiver. The master transmits the first byte (the com-
mand/control byte) to the slave. The slave then returns
an acknowledge bit. Next follows a number of data
bytes transmitted by the slave to the master. The mas-
ter returns an acknowledge bit after all received bytes
other than the last byte. At the end of the last received
byte, a not acknowledge can be returned.
The master device generates all serial clock pulses and
the start and stop conditions. A transfer is ended with a
stop condition or with a repeated start condition. Since
a repeated start condition is also the beginning of the
next serial transfer, the bus is not released.
The DS3930 can operate in the following three modes:
1) Slave Receiver Mode: Serial data and clock are
received through SDA and SCL, respectively. After
each byte is received, an acknowledge bit is trans-
mitted. Start and stop conditions are recognized as
the beginning and end of a serial transfer. Address
recognition is performed by hardware after the
slave (device) address and direction bit have been
received.
2) Slave Transmitter Mode: The first byte is received
and handled as in the slave receiver mode.
However, in this mode the direction bit indicates
that the transfer direction is reversed. Serial data is
transmitted on SDA by the DS3930 while the serial
clock is input on SCL. Start and stop conditions are
recognized as the beginning and end of a serial
transfer.
3) Slave Address: This is the first byte received fol-
lowing the start condition from the master device.
The slave address consists of a 4-bit control code.
For the DS3930, this is set as 1010 binary for
read/write operations. The next bits of the slave
address are the device address (A2–A0). The last
bit of the slave address (R/W) defines the operation
to be performed. When set to a ‘1,’ a read operation
is selected, and when set to a ‘0,’ a write operation
is selected (see Figure 4).
Following the start condition, the DS3930 monitors the
SDA bus checking the device type identifier being
transmitted. Upon receiving the 1010 device identifier,
the appropriate device address bit, and the read/write
bit, the slave device outputs an acknowledge signal on
the SDA line.
MSB
DEVICE
IDENTIFIER
DEVICE
ADDRESS
READ/WRITE BIT
1010A2A1 A0 R/W
LSB
Figure 4. Slave Address
DS3930
Hex Nonvolatile Potentiometer with
I/O and Memory
____________________________________________________________________ 11
Applications Information
Power Supply Decoupling
To achieve the best results when using the DS3930,
decouple the power supply with a 0.1µF high-quality,
ceramic, surface-mount capacitor. Surface-mount com-
ponents minimize lead inductance, which improves
performance, and ceramic capacitors tend to have
adequate high-frequency response for decoupling
applications. The capacitor should be placed as close
as possible to the VCC and GND pins.
SDA
SCL
tHD:STA
tLOW
tHIGH
tRtF
tBUF
tHD:DAT
tSU:DAT REPEATED
START
tSU:STA
tHD:STA
tSU:STO
tSP
STOP START
Figure 5. 2-Wire AC Characteristics
SLAVE
ACK
10 0
1R/WA0*A1* SLAVE
ACK
A2*
MSB LSB
DEVICE IDENTIFIER DEVICE
ADDRESS
READ/
WRITE
MSB LSB
REGISTER ADDRESS
SLAVE
ACK
MSB LSB
b7 b6 b5 b4 b3 b2 b1 b0 SLAVE
ACK STOP
*THE ADDRESS DETERMINED BY A0, A1, AND A2 MUST
MATCH THE ADDRESS SET BY THE ADDRESS PINS.
DATA
TYPICAL 2-WIRE WRITE TRANSACTION
EXAMPLE 2-WIRE TRANSACTIONS (WHEN A0, A1, AND A2 ARE ZERO)
A) SINGLE-BYTE WRITE
-WRITE TO POT 0 REGISTER
B) SINGLE-BYTE READ
-READ FROM POT 0 REGISTER
D) MULTIPLE BYTE WRITE
-2 BYTE WRITE TO EEPROM
E) MULTIPLE BYTE READ
-2 BYTE READ FROM EEPROM
START
START
START
START
START
A0h
A0h
A0h
A0h
SLAVE
ACK
SLAVE
ACK
SLAVE
ACK
SLAVE
ACK
F0h
F0h
00h
00h
SLAVE
ACK
SLAVE
ACK
SLAVE
ACK
SLAVE
ACK
DATA
SLAVE
ACK STOP
POT SETTING10100000
10100000
10100000
10100000 10100001
REPEATED
START
SLAVE
ACK
MASTER
ACK
DATA
MASTER
NACK STOP
DATA
A1h
b7 b6 b5 b4 b3 b2 b1 b0
11110000
C) SINGLE-BYTE WRITE
-SET I/O
0
PIN TO A "1" START
A0h
SLAVE
ACK
F6h
SLAVE
ACK
DATA
SLAVE
ACK STOP
XXX0XXX110100000 11110110
11110000
00000000
00000000
REPEATED
START
DATA
POT SETTING MASTER
NACK STOP
SLAVE
ACK
10100001
A1h
STOP
SLAVE
ACK
DATA
SLAVE
ACK
DATA
Figure 6. Example 2-Wire Transactions
DS3930
Hex Nonvolatile Potentiometer with
I/O and Memory
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implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
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Wiper Resistance
One difference between digital potentiometers and
mechanical potentiometers is the wiper resistance. The
wiper resistance (RW) is a result of the interconnecting
materials on the IC between the internal resistive ele-
ments and the wiper pin. This can be modeled by using
an ideal potentiometer, with a resistance of RWcon-
nected between the ideal wiper and wiper terminal of
the digital potentiometer.
Chip Information
TRANSISTOR COUNT: 27,000
SUBSTRATE CONNECTED TO GROUND.
Package Information
For the latest package outline information, go to
www.maxim-ic.com/DallasPackInfo.
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