L6181ADIP 28 - STMicroelectronics

L6180

L6181

OCTAL LINE RECEIVER

ADVANCE DATA

OCTAL LINE RECEIVERFOR:

- EIA STD RS232D

RS423A

RS422A

- CCIT V.10

V.11

V.28

X.26

NO EXTERNALCOMPONENTS

INPUTFAILSAFINGCAPABILITY

HIGHCROSSTALK REJECTION

L6180 DATA RATE < 100KBIT/S

L6181 DATA RATE < 1MBIT/S

50V EOS OUTPUT PROTECTION

DESCRIPTION

L6180/1 is an octal line receiver in a plastic DIP

or PLCC designed to meet a wide range of digital

communications requirements as outlined in the

EIA standards RS232A without additional compo-

nents, as well as the low speed applications of

RS422A.

The receiver meets the CCIT recommendations

V.10, V.11, X.26 and V.28 low speed applications

(below100KBS).

A low pass filter on the input starts to roll off at a

frequencyof 100KHz.

Thisis advancedinformation on a new productnow in developmentor undergoing evaluation. Detailsare subjectto change without notice.

October 1993

BLOCK DIAGRAM

ORDERING NUMBER: L6180ADIP 28

L6180D PLCC28

L6181A DIP 28

L6181D PLCC28

DIP 28 PLCC 28

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ABSOLUTE MAXIMUMRATINGS

Symbol Parameter Value Unit

VCC SupplyVoltage 7 V

VDD SupplyVoltage 13.5 V

VSS LogicSupply Voltage -13.5 V

CRR Common Mode Range ±15 V

VID DifferentialInput Voltage ±25 V

Ptot Power Dissipation (PLCC 28) 800 mW

Power Dissipation (DIP 28) 1200 mW

IOS Output Sink Current 50 mA

t Output Short Circuit Time 1 sec

Top Operating Free Air Temperature Range 0 to 70 °C

Tstg Storage Temperature Range -65 to 150 °C

ESD 2KV max ESD 50µJ

InputTransient Protection 50V min EOS 100µs

PIN CONNECTIONS (Top views)

DIP28 PLCC28

L6180 - L6181

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ELECTRICAL CHARACTERISTICS (VCC =5V±5%; VCM =-7 to 7V; Tamb = 0 to70°C;

VSS = -9 to 13.5V; VDD = 9 to 13.5V;unless otherwisespecified.)

Symbol Parameter Test Condition Min. Typ. Max. Unit

VIN Input Current (See Fig.1 and note2)

VCC = 0 to 5.25V;

VSS,VDD = 0 to 13.5V

VIN = - 10 to 10V

VIN = - 15 to 15V ±3

±4.25 mA

RIInput Resistance VIA or VIB = 3 to 15V; (see fig.1)

RI=[(VIA or VIN)−V

IOC]

IIN

37KΩ

FS Failsafe Output Voltage IO= -440µA (See Fig.3) 2.7 V

VOH High Level Output Voltage VCC = 4.75V; VID = -1V;

IOH = -440µA2.7 V

VOL Low Level Output Voltage VCC = 5.25V; VID = -1V;

IOL = 2mA 0.4 V

VIT2 VIOH ComparatorThreshold

Voltage (See Fig.4) 1.8 2.2 2.6 V

IIH2 High Operating Threshold

Voltage VOL = 0.4V; IOL =2mA;

(See Fig.4) -25 -75 mV

IIH1 Low OperatingThreshold

Voltage VOH = 2.7V; IO= -440µA

(See Fig.4) -125 -175 mV

VHInput Hysteresis Voltage |VTH2 -VTH1| 50 150 mV

VIOC1 Open Circuit Input Voltage Measured in accordance with

V.28 and RS-232D

(see note 4 and 7)

0.6 2 V

VIOCH Open Circuit Input Voltage Measured in presence of AC

Input Signal (see note 7) 3.5 4 4.5 V

IOS Open Short Circuit Current VCC = 5.25V; VO=0;VID = 1V;

(see note 5) 20 100 mA

VIBV Input for Balance Test (see Figure 7 and note 11) 0.4 V

CIInput Capacitance 100 pF

VCC Supply Current VCC =4.75V to 5.25V;(seenote 6) 100 mA

Vdd Supply Current Vdd = 9 to 3.5V; (see note 6) 30 mA

VSS Supplyt Current VSS = -9 to 13.5V; (see note 6) 30 mA

IOS Open Short Circuit Current VCC = 5.25V; VO=0;VID = 1V;

(see note 5) 20 100 mA

Tplh Propagation Delay Low to High RL= 390Ω;CL= 50pF;

|VIN = 1V|; (see fig 5 test Circuit

Fig. 6)

0 1500 ns

Tphl Propagation Delay Low to High RL= 390Ω;CL= 50pF;

|VIN = 1V|; (see fig 5 test Circuit

Fig. 6)

0 1500 ns

VIOCH Delay VIOCL to VIOCH Switching (see note 7A) 5 ms

VIOCL Delay VIOCH to VIOCL Switching (see note 7B) 200 ms

Vist |Tplh -Tphl|RL= 390Ω;CL= 50pF;

|VIN| = 1V;(see fig. 5; Test

Circuit Fig. 6)

0 500 ns

TSKEW1 Skew between rec’s in PKg Tp

(1) hl/1h - Tp (2) hl/1h RL= 390Ω;CL= 50pF;

|VIN| = 1V;(see fig. 5; Test

Circuit Fig. 6)

0 300 ns

fAFrequency Accepted

(Receiver will Output) VIN = 200mVpp; (see fig. 8 and

note 7; 100 KHz

L6180 - L6181

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ELECTRICAL CHARACTERISTICS (VCC =5V±5%; VCM = -7 to 7V; Tamb = 0 to 70°C;

VSS = -9 to 13.5V; VDD = 9 to 13.5V;unless otherwisespecified.)

Symbol Parameter Test Condition Min. Typ. Max. Unit

fRFrequency Rejected

(No Receiver Output) VIN = 2Vpp;

(see fig. 8 and note 7) 5 MHz

Note:

1) The algebric convention, wherethe less positive (more negative) is designedthe minimum

2) With the voltage VIA or (VIB) ranging between ±15V, while VIB or (VIA) is open or grounded, the resultant input current IIA or (IIB) shallremain

within the shaded region shown in the graph in Fig.1.

3) Either Point B’ or Point A’ is grounded in Figure 1

4) VICC measured from grounded to (+) input with (-) input grounded

VICC measured from grounded to (+) input with (-) input grounded

5) Not more than oneoutput should be shorted at a time and for less than 1 seond

6) The sum of the product of the maximum supply currents and voltages cannot exceed themaximum power dissipation

7) A: The conditions for the inpit switching from VIOCL to VIOCH mode is: Vid in startbit ”spacing condition”for less thanTpVioch (5ms).

B: The conditions for the input switching from VIOCH to VIOCL mode is: Vid> WW2 for greater than TpVIOCL (200ms)

8) An example of a frequencyresponse plot meeting the rejection/acceptance requirements is provided in figure8.

LINE TRANSIENT IMMUNITY (Considering the following cases; powered ON, Powered OFF-LOW im-

pedancepower supplyand poweredOFF-HIGH impedancesupply)

Symbol Parameter Test Condition Min. Typ. Max. Unit

ESD Static tested per MIL-STD-883

(see note 9) 2KV

EOS Stress transient pulse bothpolarities

for 100µs (see note9 and Fig. 2) 50 V

Note:

9) Allpins are required to withstand this parameters.

10) Input pins are required to withstand fig.2 without any degradation tothe circuit.

11) The balance test requirement can be met by use of a currentlimit circuit which reduces the input bias current Iib (see figure7)

for input voltages below a threshold voltage given by (Iib x 1K)- 400mV.

Figure1: Input Current Voltage Mesurements

L6180 - L6181

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Figure3: Output Failsafing

Figure2: EOS Requiremets

The output assumesa logic ”1”under the followingconditions, (see figure 3)

1 Bothinputs open

2 Both inputsshorted

3 SignalOpencircuit

3a Common grounded,signal open circuit

4 Common open, generator powered-on

5 Generatorpowered-down (seenote 7)

6 Common open, generator powered-down

6a Signalgrounded,common open,generator powered-down

7 Lessthan 250mVpp differentialsignal

L6180 - L6181

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Figure4: Thresholdvoltage definition

Figure5: PropagationDelay

Figure6: AC Test Circuit

L6180 - L6181

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INPUT BALANCE MEASUREMENT

The balance of the receiver input voltage-current

characteristics and bias voltages shall be such

that the receiverwill remain in theintended binary

state when a differential voltage Vi of 400mV is

appliedthrough 500Ω ±1% to each input terminal,

as shown above, and Vcm is varied between -7

and +7V.

When the polarity of Vi is reversed, the opposite

binary state shall be maintained under the same

conditions. Maintain input balance with input B

common with another receiver.

The voltage input (VIN) rejection is checked at the

center point between the High Operating Thresh-

old (Vth2) and the Low OperatingThreshold(Vth1)

Figure7: Receiverinput Balance Measurement

Figure 8: High FrequencySignalRejection

L6180 - L6181

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PLCC28 PACKAGE MECHANICAL DATA

DIM. mm inch

MIN. TYP. MAX. MIN. TYP. MAX.

A 12.32 12.57 0.485 0.495

B 11.43 11.58 0.450 0.456

D 4.2 4.57 0.165 0.180

D1 2.29 3.04 0.090 0.120

D2 0.51 0.020

E 9.91 10.92 0.390 0.430

e 1.27 0.050

e3 7.62 0.300

F 0.46 0.018

F1 0.71 0.028

G 0.101 0.004

M 1.24 0.049

M1 1.143 0.045

L6180 - L6181

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DIP28 PACKAGE MECHANICAL DATA

DIM. mm inch

MIN. TYP. MAX. MIN. TYP. MAX.

a1 0.63 0.025

b 0.45 0.018

b1 0.23 0.31 0.009 0.012

b2 1.27 0.050

D 37.34 1.470

E 15.2 16.68 0.598 0.657

e 2.54 0.100

e3 33.02 1.300

F 14.1 0.555

I 4.445 0.175

L 3.3 0.130

L6180 - L6181

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Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the

consequences of use of such informationnor for any infringement ofpatents or other rights of third parties which may result from itsuse. No

license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications men-

tioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied.

SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without ex-

press written approval of SGS-THOMSON Microelectronics.

1995 SGS-THOMSON Microelectronics - All RightsReserved

SGS-THOMSON Microelectronics GROUP OF COMPANIES

Australia - Brazil- France -Germany - Hong Kong - Italy - Japan - Korea -Malaysia - Malta - Morocco - The Netherlands - Singapore -

L6180 - L6181

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