BSP130,115 - NXP Semiconductors / Philips Semiconductors

DATA SH EET

Product speciﬁcation

Supersedes data of 1997 Jun 23 2001 Dec 11

DISCRETE SEMICONDUCTORS

BSP130

N-channel enhancement mode

vertical D-MOS transistor

M3D087

2001 Dec 11 2

Philips Semiconductors Product speciﬁcation

N-channel enhancement mode

vertical D-MOS transistor BSP130

FEATURES

•Direct interface to C-MOS, TTL, etc.

•High-speed switching

•No secondary breakdown.

APPLICATIONS

•Line current interruptor in telephone sets

•Relay, high-speed and line transformer drivers.

DESCRIPTION

N-channel enhancement mode vertical D-MOS transistor

in a SOT223 package.

PINNING - SOT223

PIN DESCRIPTION

1 gate

2 drain

3 source

4 drain

Fig.1 Simplified outline and symbol.

Marking code BSP130.

handbook, halfpage

MAM054

123

Top view

QUICK REFERENCE DATA

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 60134).

Note

1. Device mounted on an epoxy printed-circuit board, 40 x 40 x 1.5 mm, mounting pad for the drain tab minimum 6 cm2.

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

VDS drain-source voltage (DC) −300 V

IDdrain current (DC) −350 mA

Ptot total power dissipation Tamb ≤25 °C−1.5 W

VGSO gate-source voltage open drain −±20 V

RDSon drain-source on-state

resistance ID= 250 mA; VGS =10V −6Ω

GSoff gate-source cut-off voltage ID= 1 mA; VDS =V

GS 0.8 2 V

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

VDS drain-source voltage (DC) −300 V

VGSO gate-source voltage (DC) open drain −±20 V

IDdrain current (DC) −350 mA

IDM peak drain current −1.4 A

Ptot total power dissipation Tamb ≤25 °C; note 1 −1.5 W

Tstg storage temperature −55 +150 °C

Tjjunction temperature −150 °C

2001 Dec 11 3

Philips Semiconductors Product speciﬁcation

N-channel enhancement mode

vertical D-MOS transistor BSP130

THERMAL CHARACTERISTICS

Note

1. Device mounted on an epoxy printed-circuit board, 40 x 40 x 1.5 mm, mounting pad for the drain tab minimum 6 cm2.

STATIC CHARACTERISTICS

Tj = 25 °C unless otherwise speciﬁed.

SYMBOL PARAMETER VALUE UNIT

Rth j-a thermal resistance from junction to ambient; note 1 83.3 K/W

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V(BR)DSS drain-source breakdown voltage ID=10µA; VGS = 0 300 −−V

GSS gate-source leakage current VGS =±20 V; VDS =0 −−±100 nA

VGSth gate-source threshold voltage ID= 1 mA; VDS =V

GS 0.8 −2V

DSon drain-source on-state resistance ID= 20 mA; VGS = 2.4 V −4.8 10 Ω

ID= 250 mA; VGS =10V −3.7 6 Ω

IDSS drain-source leakage current VDS = 240 V; VGS =0 −−100 nA

Yfstransfer admittance ID= 250 mA; VDS = 25 V 200 690 −mS

Ciss input capacitance VDS = 25 V; VGS = 0; f = 1 MHz −100 120 pF

Coss output capacitance VDS = 25 V; VGS = 0; f = 1 MHz −21 30 pF

Crss feedback capacitance VDS = 25 V; VGS = 0; f = 1 MHz −10 15 pF

Switching times (see Figs 2 and 3)

ton turn-on time ID= 250 mA; VDD =50V;

GS =0to10V −610ns

off turn-off time ID = 250 mA; VDD = 50 V;

VGS = 10 to 0 V −46 60 ns

2001 Dec 11 4

Philips Semiconductors Product speciﬁcation

N-channel enhancement mode

vertical D-MOS transistor BSP130

Fig.2 Switching times test circuit.

handbook, halfpage

MBB691

50 Ω

VDD = 50 V

10 V

0 V

Fig.3 Input and output waveforms.

handbook, halfpage

MBB692

10 %

90 %

10 %

ton toff

OUTPUT

INPUT

Fig.4 Power derating curve.

handbook, halfpage

0 50 100 Tj (°C)

Ptot

(W)

200

1.5

0.5

150

MRC218

handbook, halfpage

250

010 30

020

100

150

200

MLD765

VDS (V)

(pF)

Crss

Coss

Ciss

Fig.5 Capacitance as a function of drain-source

voltage; typical values.

VGS = 0; f = 1 MHz; Tj=25°C.

2001 Dec 11 5

Philips Semiconductors Product speciﬁcation

N-channel enhancement mode

vertical D-MOS transistor BSP130

handbook, halfpage

1.2

0.8

VDS (V)

(A)

0.4

04812

MLD766

4 V

3.5 V 3 V

2 V

5 V

2.5 V

VGS = 10 V

Fig.6 Typical output characteristics.

Tj=25°C.

handbook, halfpage

010

1.2

0.4

0.8

(A)

VGS (V)

468

MLD767

Fig.7 Typical transfer characteristics.

VDS = 10 V; Tj=25°C.

handbook, halfpage

MLD768

10−1110

(A)

RDSon

(Ω)

3 V 3.5 V

4 V

10 V

2.5 V

5 V

VGS = 2 V

Fig.8 Drain-source on-state resistance as a

function of drain current; typical values.

Tj=25°C.

handbook, halfpage

02 10

4VGS (V)

RDSon

(Ω)

MLD769

Fig.9 Drain-source on-state resistance as a function

of gate-source voltage; typical values.

VDS = 100 mV; Tj=25°C.

2001 Dec 11 6

Philips Semiconductors Product speciﬁcation

N-channel enhancement mode

vertical D-MOS transistor BSP130

Fig.10 Transient thermal resistance from junction to ambient as a function of pulse time.

handbook, full pagewidth

102

Rth j-a

(K/W)

10−1

MRC221

10−510−410−310−210−11tp (s)

10 102103

δ =

0.5

0.75

0.2

0.1

0.05

0.01

0.02

handbook, halfpage

MLD773

10 102

10−3

10−2

10−1

103

1VDS (V)

(A)

tpT

δ=

(1)

1 ms

10 ms

100 ms

100 µs

tp =

10 µs

Fig.11 SOAR curve.

δ= 0.01; Tamb =25°C.

(1) RDSon limitation.

2001 Dec 11 7

Philips Semiconductors Product speciﬁcation

N-channel enhancement mode

vertical D-MOS transistor BSP130

handbook, halfpage

−50 0

(1)

(2)

Tj (°C)

50 150

1.5

0.5

100

MLD771

Fig.12 Temperature coefficient of drain-source

on-state resistance; typical values.

Typical RDSon;

(1) ID= 250 mA; VGS =10V.

(2) ID= 20 mA; VGS = 2.4 V.

kRDS(on) at Tj

RDS(on)at 25 °C

-----------------------------------------

handbook, halfpage

-50 0 Tj (°C)

50 150

1.25

100

0.75

0.5

0.25

MLD772

Fig.13 Temperature coefficient of gate-source

threshold voltage; typical values.

Typical VGSth at 1 mA.

kVGS th()

at Tj

VGS th()

at 25 °C

------------------------------------------- .=

2001 Dec 11 8

Philips Semiconductors Product speciﬁcation

N-channel enhancement mode

vertical D-MOS transistor BSP130

PACKAGE OUTLINE

UNIT A1bpcDEe

pQywv

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC EIAJ

mm 0.10

0.01

1.8

1.5 0.80

0.60

3.1

2.9 0.32

0.22 6.7

6.3 3.7

3.3 2.3

4.6 7.3

6.7 1.1

0.7 0.95

0.85 0.1 0.10.2

DIMENSIONS (mm are the original dimensions)

SOT223 SC-73 97-02-28

99-09-13

detail X

vMA

0 2 4 mm

scale

132

Plastic surface mounted package; collector pad for good heat transfer; 4 leads SOT223

2001 Dec 11 9

Philips Semiconductors Product speciﬁcation

N-channel enhancement mode

vertical D-MOS transistor BSP130

DATA SHEET STATUS

Notes

1. Please consult the most recently issued data sheet before initiating or completing a design.

2. The product status of the device(s) described in this data sheet may have changed since this data sheet was

published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.

DATA SHEET STATUS(1) PRODUCT

STATUS(2) DEFINITIONS

Objective data Development This data sheet contains data from the objective specification for product

development. Philips Semiconductors reserves the right to change the

speciﬁcation in any manner without notice.

Preliminary data Qualiﬁcation This data sheet contains data from the preliminary specification.

Supplementary data will be published at a later date. Philips

Semiconductors reserves the right to change the speciﬁcation without

notice, in order to improve the design and supply the best possible

product.

Product data Production This data sheet contains data from the product specification. Philips

Semiconductors reserves the right to make changes at any time in order

to improve the design, manufacturing and supply. Changes will be

communicated according to the Customer Product/Process Change

Notiﬁcation (CPCN) procedure SNW-SQ-650A.

DEFINITIONS

Short-form specification  The data in a short-form

specification is extracted from a full data sheet with the

same type number and title. For detailed information see

the relevant data sheet or data handbook.

Limiting values definition Limiting values given are in

accordance with the Absolute Maximum Rating System

(IEC 60134). Stress above one or more of the limiting

values may cause permanent damage to the device.

These are stress ratings only and operation of the device

attheseoratany otherconditionsabove thosegivenin the

Characteristics sections of the specification is not implied.

Exposure to limiting values for extended periods may

affect device reliability.

Application information  Applications that are

described herein for any of these products are for

illustrative purposes only. Philips Semiconductors make

norepresentationor warrantythatsuchapplicationswill be

suitable for the specified use without further testing or

modification.

DISCLAIMERS

Life support applications  These products are not

designed for use in life support appliances, devices, or

systems where malfunction of these products can

reasonably be expected to result in personal injury. Philips

Semiconductorscustomersusing orsellingthese products

for use in such applications do so at their own risk and

agree to fully indemnify Philips Semiconductors for any

damages resulting from such application.

Right to make changes  Philips Semiconductors

reserves the right to make changes, without notice, in the

products, including circuits, standard cells, and/or

software, described or contained herein in order to

improve design and/or performance. Philips

Semiconductors assumes no responsibility or liability for

theuseofanyoftheseproducts,conveys nolicence ortitle

under any patent, copyright, or mask work right to these

products,and makes norepresentationsor warranties that

these products are free from patent, copyright, or mask

work right infringement, unless otherwise specified.

2001 Dec 11 10

Philips Semiconductors Product speciﬁcation

N-channel enhancement mode

vertical D-MOS transistor BSP130

NOTES

2001 Dec 11 11

Philips Semiconductors Product speciﬁcation

N-channel enhancement mode

vertical D-MOS transistor BSP130

NOTES

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Printed in The Netherlands 613510/03/pp12 Date of release: 2001 Dec 11 Document order number: 9397 750 09064