Enpirion® Power Evaluation Board User Guide
EV1320QI PowerSoC
Enpirion EV1320QI 2A Sink/Source
DDR Term ination Converter
E v aluat i on B oar d
Introduction
Thank you for c hoos ing Alter a Enpir ion pow er produc ts !
Along with this doc um ent you will als o need the lates t devic e datas heet.
The EV1320QI operates by charging a pair of capacitors in series and
connecting them in parallel to generate an output voltage which is nearly
one half the input voltage. There is no feedback control, and the output
voltage is not regulated. The output voltage is directly proportional to the
input voltage and is als o affec ted by the load.
The divis ion by tw o proper ty m akes the EV1320 a s uitable par t for VTT
applic ations for up to 2A of load c urrent.
The c apac itor c onfigur ation ar ound the EV1320 pac kage determ ines how
the devic e oper ates . For this evaluation board, the c apac itor s around the
devic e have been c hos en to m inim iz e the output voltage droop as a
function of load current. Please see Figure 1.
V
TT
C1P
22uF +
2 x 10uF
(0603)
22uF +
2 x 10uF
(0603)
VOUT
AVIN
AGND
SS
VDDQ
ENABLE
PGND
PGND
C1N
15nF
22uF +
2 x 10uF
(0603)
VDDQ
3.3V
POK
100k
POK
ENABLE
Figure 1: EV1320 Simplified Application Schematic
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Enpirion® Power Evaluation Board User Guide
EV1320QI PowerSoC
Quick Start Guide
Figure 2: J2 allows control of the Enable pin.
The jum per on Enable pin as s hown in Figure 2 is in disable mode. When jumper
is between the m iddle and right pins the s ignal pin is c onnec ted to ground or logic
low . W hen the jum per is betw een the left and m iddle pins , the s ignal pin is
c onnec ted to AVIN or logic High.
WARNING: complete steps 1 through 4 before applying power to the EV1320QI
evaluation board.
STEP 1: S et the “ENA jum per to the D is able Pos ition. See Figure 2 above.
STEP 2: With the AVIN power s upply off, c onnec t it to the input c onnec tors
AVIN (TP 14) and PGND ( TP16) as indic ated in Figure 3 and s et the
power s upply to the desired voltage (3.3V nominal).
STEP 3: With the VDDQ power supply off, c onnec t it to the input power
connectors VDDQ (TP12) and PGND (TP 17) as indic ated in Figure 3,
and s et the pow er supply to the des ir ed voltage (1.2V1.8V).
CAUTION: Be m indful of the polar ity and m agnitude. This evaluation
board has no reverse polarity or voltage clamping protection on it.
STEP 4: C onnec t the load to the output connectors VOUT (TP13) and PGND
(TP15) , as indicated in Figure 3.
STEP 5: Pow er up the board by turning on the AVIN power s upply fir s t and then
the VD DQ s upply. Next, move the ENA jum per to the enabled position.
The EV1320QI is now powered up and VO UT s hould be half of VD DQ .
You can now m ake Effic ienc y, R ipple, Line/Load R egulation, Load
transient, Power OK, and temperature related measurements.
STEP 6: Power Up/Dow n Behavior R em ove E NA jum per and c onnec t a puls e
generator (output disabled) signal to the middle pin of ENA and
Ground. Set the puls e am plitude to swing fr om 0 to 2.5 volts . Set the
puls e period to 10msec, duty cycle to 50% and fas t tr ans ition (< 1us ec .)
Hook up os c illos c ope pr obes to ENA, POK and VOUT w ith c lean ground
VIN
SIDE
GND
SIDE
Jumper
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Enpirion® Power Evaluation Board User Guide
EV1320QI PowerSoC
returns. Tur n on puls e generator output. O bs erve the VOUT voltage
ram ps as E NA goes high and again as ENA goes low .
STEP 7: You c an als o oper ate the boar d by leaving the E NA jum per in the high
pos ition. Then apply AVIN to the board. Next, turn on the VD DQ
s upply. The output w ill ram p up and down as half of VD DQ all the tim e.
Figure 3: Evaluation Board Top Side
Assembly and Copper Layers
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Enpirion® Power Evaluation Board User Guide
EV1320QI PowerSoC
Figure 4: Evaluat ion Boar d Schemat ic
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Enpirion® Power Evaluation Board User Guide
EV1320QI PowerSoC
Test Recommend atio ns
To guarantee m eas ur em ent ac c urac y, the follow ing prec autions s hould be
observed:
1. Make all input and output voltage m eas ur em ents at the board us ing
the surface mount tes t points provided (TP 1 & TP4 for VD DQ , and
TP9 & TP11 for VO UT). This w ill elim inate voltage dr op ac ros s the
line and load c ables that c an produc e fals e readings .
2. Meas ur e input and output c ur rent w ith calibrated series ammeters or
accurate shunt resistors. This is especially important for measuring
efficiency.
3. Us e a low-loop-inductance pr obe tip s im ilar to the one shown below to
measure VOUT ripple and s w itc hing s ignals to avoid nois e c oupling into
the probe gr ound lead. Output ripple and load transient deviations can
either be m eas ured right after the devic e output c apac itors , or at the
board edge.
Depending on the applic ation, VOUT ripple m ay not m eet the c us tom er
requirement next to the las t output c apac itor C 12. This m ay not m atter
so much because the critical spot to meet ripple requirements is at the
load. This evaluation board comes with c apac itors at the board edge
whic h em ulate bulk load dec oupling. The ripple at the boar d edge is
therefore s ignific antly low er than next to the devic e. For more
ac c urate r ipple m eas urem ent techniques, please refer to Enpirion
O utput R ipple Meas urem ent Methods Application Note
(www.altera.com/enpirion). You c an m odify the boar d edge c apac itor
c onfigur ation as needed to m atc h your s pec ific load dec oupling.
4. The board inc ludes a pull-up for the PO K s ignal and r eady to m onitor
the pow er O K s tatus .
5. A so f t -start c apac itor is populated on the boar d to provide a
reasonable soft-s tart time. It can be changed as needed.
ALW A YS power down device before changing any board level com ponents!
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Enpirion® Power Evaluation Board User Guide
EV1320QI PowerSoC
Bill of Materials
Designator
Qty
Description
C1, C14, C16
3
CAP, 10uF X7R 10V 0805 10%
C2, C5 , C10
3
CAP, 22UF X5R 4V 0603 20%
C3, C4 , C6 ,
C7, C11, C12
6
CAP, 10UF X5R 4V 0603 20%
C9
1
CAP, 15000PF X7R 50V 0805 10%
C15, C17 -C21
6
CAP, 22UF X5R 6.3V 0805 20%
C8, R2 2
NOT US ED
FB1 1
SMT FERRIT E BEAD 4A 0805, WURT H ELECT RONIK
742792012
J1
1
CONN HEADER, VER TIC AL , 3 PO S ITIO N , 0.100”, T I N
R1
1
RES 100K OHM 1/16W 1% 0402 SMD
TP1-TP4, TP7,
TP9, TP11-TP19
15 T EST POINT SURFACE MOUNT , KEY STONE 5016
U1
1
EV1320QI QFN 2A
Contact Information
Altera Corporation
101 I nnovation Drive
San Jose, CA 95134
Phone: 408-544-7000
http://www.altera.com/
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in accor danc e w ith Al ter a' s standar d w ar r anty, but r eser ves t he r ight to make c hanges to any pr oduc ts and ser v ices at an y
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