SY58603UMGTR - Micrel, Inc.

SY58603U

4.25Gbps Prec isi on CML Buffer w i th I nte rnal

Termination and Fail Safe Input

Precision Edge is a registered trademark of Micrel, Inc.

Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com

August 2007

M9999-082707-B

hbwhelp@micrel.com or (408) 955-1690

General Description

The SY58603U is a 2.5/3.3V, high-speed, fully

differential CML buffer optimized to provide less than

10pspp total jitter. The SY58603U can process clock

signals as fast as 2.5GHz or data patterns up to

4.25Gbps.

The differential input includes Micrel’s unique, 3-pin

input termination ar ch itec tu r e that int erfaces to LV PEC L,

LVDS or CML differential signals, (AC-coupled or DC-

coupled) as small as 100mV (200mVpp) without any

level-shifting or termination resistor networks in the

signa l path. For AC-c oupled input interf ace applic ations,

an integrated voltage reference (VREF-AC) is provided to

bias the VT pin. The output is 400mV CML, with

extremely fast rise/fall times guaranteed to be less than

85ps.

The SY58603U operates from a 2.5V ±5% supply or

3.3V ±10% supply and is guaranteed over the full

industrial temperature range (–40°C to +85°C). For

applications that require LVPECL or LVDS outputs,

consider the SY58604U and SY58605U, buffers with

800mV and 325mV output swings respectively. The

SY58603U is part of Micrel’s high-speed, Precision

Edge® product line.

Data sheets and support documentation can be found

on Micrel’s web site at: www.micrel.com.

Functional Block Diagram

Precision Edge®

Features

• Precision 400mV CML buffer

• Guaranteed AC performance over temperature and

voltage:

– DC-to >4.25Gbps throughput

– <300ps propagation delay (IN-to-Q)

– <85ps rise/fall times

• Fail Safe Input

– Prevents output from oscillating when input is

invalid

• Ultra-low jitter design

– <1psRMS cycle-to-cycle jitter

– <10psPP total jitter

– <1psRMS random jitter

– <10psPP deterministic jitter

• High-speed CML output

• 2.5V ±5% or 3.3V ±10% power supply operation

• Industrial temperature range: –40°C to +85 °C

• Available in 8-pin (2mm x 2mm) DFN package

Applications

• Data Distribution: OC-48, OC-48+FEC, XAUI

• Backplane Buf f er ing

• SONET clock or data distribution

• Fibre Channel clock or data distribution

• Gigabit Ethernet clock or data distribution

Markets

• Storage

• ATE

• Test and measurement

• Enterprise networking equipment

• High-end servers

• Access

• Metro area network equipment

Micrel, Inc.

SY58603U

August 2007 2 M9999-082707-

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Ordering Information(1)

Part Number Package

Type Operating

Range Package Marking Lead

Finish

SY58603UMG DFN-8 Industrial 603 with Pb-Free

bar-line indicator NiPdAu

Pb-Free

SY58603UMGTR(2) DFN-8 Industrial 603 with Pb-Free

bar-line indicator NiPdAu

Pb-Free

Notes:

1. Contact f act ory for die availabi lit y. Dice are guaranteed at TA = 25°C, DC Electricals only.

2. Tape and Reel.

Pin Configuration

8-Pin DFN

Pin Description

Pin Number Pin Name Pin Function

1, 4 IN, /IN Differential Input: This input pair is the differential signal input to the device. Input

accepts DC-Coupled differential signals as small as 100mV (200mVpp). Each pin of

this pair internally terminates with 50Ω to the VT pin. If the input swing falls below a

certain threshold (typical 30mV), the Fail Safe Input (FSI) feature will guarantee a

stable output by latching the output to its last valid state. See “Input Interface

Applicat ion s” sect ion for more details.

2 VT Input Termination Center-Tap: Each side of the differential input pair terminates to

VT pin. This pin provides a center-tap to a termination network for maximum

interface flexibility. See “Input Interface Applications” section.

3 VREF-AC Reference Voltage: This output biases to VCC–1.2V. It is used for AC-coupling inp ut

IN and /IN. Connect VREF-AC directly to the corresponding VT pin. Bypass with

0.01µF low ESR capacitor to VCC. Maximum sink/source current is ±1.5mA. Please

refer to the “Input Interface Applications” section for more details.

5 GND

Exposed pad Ground: Exposed pad must be connected to a ground plane that is the same

potential as the ground pin.

6, 7 /Q, Q CML Differential Output Pair: Differential buffered output copy of the input signal.

The output swing is typically 400mV. See “CML Output Termination” section.

8 VCC Positive Power Supply: Bypass with 0.1uF//0.01uF low ESR capacitors as close to

the VCC pin as possible.

Micrel, Inc.

SY58603U

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Absolute Maximum Ratings(1)

Supply Voltage (VCC) ............................... –0.5V to +4.0V

Input Voltage (VIN) ....................................... –0.5V to VCC

CML Output Voltage (VOUT) .......... VCC-1.0V to VCC+0.5V

Current (VT)

Source or sink on VT pin ............................. ±100mA

Input Current

Source or sink Current on (IN, /IN) ................ ±50mA

Current (VREF)

Source or sink current on VREF-AC(4) .............. ±1.5mA

Maximum operating Junction Temperature .......... 125°C

Lead Temperature (soldering, 20sec.) .................. 260°C

Storage Temperature (Ts) .................... –65°C to +150°C

Operating Ratings(2)

Supply Voltage (VIN) ........................ +2.375V to +3.60V

Ambient Temperature (TA) ................... –40°C to +85°C

Package Thermal Resistance(3)

DFN

Still-air (θJA) ............................................ 93°C/W

Junction-to-board (ψJB) .......................... 56°C/W

DC Electrical Characteristics(5)

TA = –40°C to +85°C, unless otherwise stated.

Symbol Parameter Condition Min Typ Max Units

VCC Power Supply Voltage Range 2.375

3.0 2.5

3.3 2.625

3.6 V

ICC Power Supply Current No load, max. VCC 39 50 mA

RDIFF_IN Differential Input Resistance

(IN-to-/IN) 90 100 110 Ω

VIH Input HIGH Voltage

(IN, /IN) IN, /IN, Note 7 VCC–1.6 VCC V

VIL Input LO W Voltage

(IN, /IN) IN, /IN 0 VIH–0.1 V

VIN Input Voltage Swing

(IN, /IN) see Figure 3a, Note 6 0.1 1.7 V

VDIFF_IN Differential Input Voltage Swing

(|IN - /IN|) see Figure 3b 0.2 V

VIN_FSI Input Voltage Threshold that

Triggers FSI 30 100 mV

VREF-AC Output Reference Voltage VCC–1.3 VCC–1.2 VCC–1.1 V

VT_IN Voltage from Input to VT 1.28 V

Notes:

1. Permanent device dam age may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not

implied at conditions other than those detailed i n the operational secti ons of t his data sheet. E xposure to absolute maximum ratings conditions

for extended periods may affect device reliabil ity.

2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings.

3. Package thermal resist ance assumes exposed pad is soldered (or equivalent) to the device's most negative potential on the PCB. ψJB and θJA

values are determined for a 4-layer board in still-air num ber, unless otherwise s tated.

4. Due to the limited drive capabi lit y, use for input of the same package only.

5. The ci rcuit is designed to meet the DC specifications shown in the above table after therm al equilibrium has been est ablis hed.

6. VIN (max) is specified when VT is floating.

7. VIH (min) not lower than 1.2V.

Micrel, Inc.

SY58603U

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CML Output DC Electrical Characteristics(7)

VCC = +2.5V ±5% or +3.3V ±10%, RL = 100Ω across the outputs; TA = –40°C to +85°C, unless otherwise stated.

Symbol Parameter Condition Min Typ Max Units

VOH Output HIGH Voltage RL = 50Ω to VCC VCC-0.020 VCC-0.010 VCC V

VOUT Output Voltage Swing See Figure 3a 325 400 mV

VDIFF_OUT Differ ential Output Voltage Swing See Figure 3b 650 800 mV

ROUT Output Source Impedance 45 50 55 Ω

Note:

7. The ci rcuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been establis hed.

Micrel, Inc.

SY58603U

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AC Electrical Characteristics

VCC = +2.5V ±5% or +3.3V ±10%, RL = 100Ω across the outputs, Input tr/tf: <300ps; TA = –40°C to +85°C, unless

otherwise stated.

Symbol Parameter Condition Min Typ Max Units

fMAX Maximum Frequency NRZ Data 4.25 Gbps

VOUT > 200mV Clock 2.5 3 GHz

tPD Propagation Delay IN-to-Q VIN: 100mV-200mV 150 250 350 ps

VIN: 200mV-800mV 120 190 300 ps

tSkew Part-to-Part Skew Note 8 100 ps

tJitter Data Random Jitter Note 9 1 psRMS

Deterministic Jitter Note 10 10 psPP

Clock Cycle -to-Cycle Jitter Note 11 1 psRMS

Total Jitter Note 12 10 psPP

tr, tf Output Rise/Fall Times

(20% to 80%) At full output swing. 30 50 85 ps

Duty Cycle Differential I/O 47 53 %

Notes:

8. Part-to-part skew is defined for two parts with identical power supply voltages at the same temperature and no skew at the edges at the

respective inputs.

9. Random jitt er is measured with a K28.7 pattern, measured at ≤ f

MAX.

10. Determini st ic jitter is m easured at 2.5Gbps with both K28.5 and 223–1 PRBS pattern.

11. Cycle-to-cycle jitter definition: the variation period bet ween adjacent cycl es over a random sample of adjacent cycle pairs. t JITTER_CC = Tn –Tn+1,

where T is the time between rising edges of the output signal.

12. Total jitter defi niti on: with an ideal clock input frequency of ≤ f

MAX (device), no more than one output edge in 1012 output edges will deviate by

more than the specified peak-to-peak jitter value.

Micrel, Inc.

SY58603U

August 2007 6 M9999-082707-

hbwhelp@micrel.com or (408) 955-1690

Functional Description

Fail-Safe Input (FSI)

The input includes a special failsafe circuit to sense

the amplitude of the input signal and to latch the

output whe n there is no input s ignal present, or when

the amplitude of the input signal drops sufficiently

below 100mVPK (200mVPP), typically 30mVPK.

Maximum frequency of SY58603U is limited by the

FSI function.

Input Clock Failure Case

If the input c lock fails to a float ing, static, or extr emely

low signal swing, the FSI function will eliminate a

metastable condition and guarantee a stable output.

No ringi ng and no undetermined state will oc cur at the

output under these conditions.

Note that the FSI function will not prevent duty cycle

distortion in case of a slowly deteriorating (but still

toggling) input signal. Due to the FSI function, the

propagation delay will depend on rise and fall time of

the input sig nal and on its amplitude . Refer to “T ypical

Characteristics” for detailed information.

Timing Diagrams

Figure 1a. Propagation Delay

Figure 1b. Fail Safe Feature

Micrel, Inc.

SY58603U

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Typical Characteris tics

VCC = 2.5V, GND = 0V, VIN = 100mV, RL = 100Ω across the outputs, TA = 25°C, unless otherwise stated.

Micrel, Inc.

SY58603U

August 2007 8 M9999-082707-

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Functional Characteristics

VCC = 2.5V, GND = 0V, VIN = 325mV, Data Pattern: 223-1, RL = 100Ω across the outputs, TA = 25°C, unless otherwise

stated.

Micrel, Inc.

SY58603U

August 2007 9 M9999-082707-

hbwhelp@micrel.com or (408) 955-1690

Functional Characteristics (continued)

VCC = 2.5V, GND = 0V, VIN = 325mV, RL = 10 0Ω across the outputs, TA = 25°C, unless otherwise stated.

Micrel, Inc.

SY58603U

August 2007 10 M9999-082707-

hbwhelp@micrel.com or (408) 955-1690

Input and Output Stage

Figure 2a. Simplified Differential Input Buffer

Figure 2b. Simplified CML Output Buffer

Single-ended and Differential Swings

Figure 3a. Single-Ended Swing

Figure 3b. Differential Swing

Micrel, Inc.

SY58603U

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Input Interface Applications

Figure 4a. CML Interface

(DC-Coupled)

Option: May connect VT to VCC

Figure 4b. CML Interface

(AC-Coupled)

Figure 4c. LVPECL Interface

(DC-Coupled)

Figure 4d. LVPECL Interface

(AC-Coupled)

Figure 4e. LVDS Interface

Micrel, Inc.

SY58603U

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CML Output Termination

Figure 5a. CML DC-Coupled Termination Figure 5b. CML DC-Coupled Termination

Figure 5c. CML AC-C o u p led Termination