4 Megabit High Speed CMOS SRAM DPS128X32CV3/DPS128X32BV3 DESCRIPTION: The DPS128X32CV3/DPS128X32BV3 `'VERSA-STACK'' module is a revolutionary new high speed memory subsystem using Dense-Pac Microsystems' ceramic Stackable Leadless Chip Carriers (SLCC) mounted on a co-fired ceramic substrate. It offers 4 Megabits of SRAM in a package envelope of 1.090 x 1.090 x 0.252 inches. The DPS128X32CV3/DPS128X32BV3 contains four individual 128K x 8 SRAMs, packaged in their own hermetically sealed SLCCs making the module suitable for commercial, industrial and military applications. By using SLCCs, the `'Versa-Stack'' family of modules offers a higher board density of memory than available with conventional through-hole, surface mount, module, or hybrid techniques. The DPS128X32BV3 has one active low Chip Enable (CE) and while the DPS128X32CV3 an active low Chip Enable (CE) and an active high Select Line (SEL). By using SLCCs, the `'Versa-Stack'' family of modules offer a higher board density of memory than available with conventional through-hole, surface mount or hybrid techniques. FEATURES: * * * * * * * * * Organizations Available: 128K x 32, 256K x 16, or 512K x 8 Access Times: 20*, 25, 30, 35, 45ns Fully Static Operation - No clock or refresh required Low Power Dissipation: 8.0mW (typ.) Full Standby 0.8W (typ.) Operating (x8) Single +5V Power Supply, 10% Tolerance TTL Compatible Common Data Inputs and Outputs Low Data Retention Current: 140A typ. (2.0V) 66-Pin PGA `'VERSA-STACK'' Package FUNCTIONAL BLOCK DIAGRAM PIN-OUT DIAGRAM * Commercial only. PIN NAMES A0 - A16 I/O0 - I/O31 CE0 - CE3 SEL WE0 - WE1 OE VDD VSS N.C. 30A044-24 REV. F Address Inputs Data Input/Output Low Chip Enables High Chip Enable Write Enables Output Enable Power (+5V) Ground No Connect NOTE: SEL applies to the DPS128X32CV3 only, No Connect for the DPS128X32BV3 version. This document contains information on a product that is currently released to production at Dense-Pac Microsystems, Inc. Dense-Pac reserves the right to change products or specifications herein without prior notice. 1 DPS128X32CV3/DPS128X32BV3 RECOMMENDED OPERATING RANGE Dense-Pac Microsystems, Inc. 3 TRUTH TABLE Symbol Characteristic Min. Typ. Max. Unit VDD Supply Voltage 4.5 5.0 5.5 V VIH Input HIGH Voltage 2.2 VDD+0.3 V VIL Input LOW Voltage -0.52 0.8 V M -55 +25 +125 Operating o TA I -40 +25 +85 C Temperature C 0 +25 +70 Mode SEL CE WE Not Selected Not Selected DOUT Disable Read Write L X H H H X H L L L X X H H L H = HIGH Supply OE I/O Pin Current X High-Z Standby X High-Z Standby H High-Z Active L DOUT Active X DIN Active L = LOW X = Don't Care NOTE: SEL applies to DPS128X32CV3 version only. DC OUTPUT CHARACTERISTICS Symbol Parameter VOH HIGH Voltage VOL LOW Voltage Conditions Min. Max. Unit IOH= -4.0mA 2.4 V IOL=8.0mA 0.4 V ABSOLUTE MAXIMUM RATINGS Symbol TSTC TBIAS VDD VI/O CAPACITANCE 4: TA = 25C, F = 1.0MHz Symbol Parameter CADR Address Input CCE Chip Enable Active High CSEL Chip Select CWE Write Enable COE Output Enable CI/O Data Input/Output 3 Parameter Value Storage Temperature -65 to +150 Temperature Under Bias -55 to +125 Supply Voltage 1 -0.5 to +7.0 Input/Output Voltage 1 -0.5 to VDD+0.5 Unit C C C V Max. 50 20 50 25 50 20 Unit Condition pF VIN2 = 0V NOTE: CSEL applies to DPS128X32CV3 version only. DC OPERATING CHARACTERISTICS: Over operating ranges Symbol IIN IOUT ICC ISB1 ISB2 IDR3 IDR2 VOL VOH Characteristics Input Leakage Current Output Leakage Current Test Conditions VIN = 0V to VDD VI/O = 0V to VDD, CE or OE = VIH, or WE = VIL X8 X16 X32 Operating Supply Current Cycle=min., Duty=100% IOUT = 0mA Full Standby Supply Current Standby Current (TTL) Data Retention Supply Current (3V) VIN VDD -0.2V or VIN VSS +0.2V CE = VIH VDR = 3V, CE VDR -0.2V, (or SEL 0.2V, VIN VDD -0.2V or VIN +0.2V) VDR = 2V, CE VDR -0.2V, (or SEL 0.2V, VIN VDD -0.2V or VIN +0.2V) IOUT = 8.0mA IOUT = -4.0mA Data Retention Supply Current (2V) Output Low Voltage Output High Voltage C I M Typ. () Min. Max. Min. Max. Min. Max. - -20 +20 -20 +20 -20 +20 A - -10 +10 -10 +10 -10 Unit +10 A 175 250 400 230 340 560 245 350 560 265 390 640 mA 1.6 20 20 40 mA 100 120 140 140 mA 0.28 1.60 2.40 8.00 mA 0.14 1.00 1.60 7.20 mA 0.4 V V - 0.4 2.4 0.4 2.4 2.4 Typical measurements made at +25oC, Cycle = min., VDD = 5.0V. 2 30A044-24 REV. F DPS128X32CV3/DPS128X32BV3 Dense-Pac Microsystems, Inc. Data Retention AC Characteristics Symbol VDR VCDR tR Parameter VDD for Data Retention Chip Disable to Data Retention Time Operation Recovery Time Test Conditions CE VDR -0.2V, (SEL VDR -0.2V, or VIN VDR -0.2V or VIN 0.2V) 8 Min. Typ. Max. Unit 2.0 - - V See Data Retention Waveform 0 - - ns See Data Retention Waveform 5 - - ms NOTE: Test Conditions in parenthesis apply to DPS128X32CV3 version only. DATA RETENTION WAVEFORM: CE Controlled. VDD 4.5V 2.3V VDR1 CE 0V CE VDD -0.2V DATA RETENTION WAVEFORM: SEL Controlled. (Applies to DPS128X32CV3 only) VDD 4.5V SEL VDR2 0.4V 0V 30A044-24 REV. F SEL -0.2V 3 DPS128X32CV3/DPS128X32BV3 Dense-Pac Microsystems, Inc. OUTPUT LOAD Load CL 1 30pF 2 5pF Parameters Measured except tLZ1, tLZ2, tHZ1, tHZ2, tOHZ, tOLZ, and tWHZ tLZ1, tLZ2, tHZ1, tHZ2, tOHZ, tOLZ, and tWHZ Figure 1. Output Load * Including Probe and Jig Capacitance. +5V NOTE: tLZ2 and tHZ2 apply to DPS128X32CV3 version only. 480 DOUT AC TEST CONDITIONS Input Pulse Levels Input Pulse Rise and Fall Times Input and Output Timing Reference Levels 0V to 3.0V 5ns CL* 255 1.5V AC OPERATING CONDITIONS AND CHARACTERISTICS - READ CYCLE: Over operating ranges No. Symbol 1 2 3 4 5 6 7 8 9 10 11 12 tRC tAA tCO1 tCO2 tOE tLZ1 tLZ2 tOLZ tHZ1 tHZ2 tOHZ tOH Parameter Read Cycle Time Address Access Time CE to Output Valid SEL to Output Valid Output Enable to Output Valid CE to Output in LOW-Z 4, 5 SEL to Output in LOW-Z 4, 5 Output Enable to Output in LOW-Z 4, 5 CE to Output in HIGH-Z 4, 5 SEL to Output in HIGH-Z 4, 5 Output Enable to Output in HIGH-Z 4, 5 Output Hold from Address Change 20ns* Min. Max. 20 25ns Min. Max. 25 20 20 20 8 3 3 0 Max. 30 25 25 25 10 3 3 0 Max. 35 Max. Unit 45 ns ns ns ns ns ns ns ns ns ns ns ns 45 45 45 25 3 3 0 15 15 15 3 45ns Min. 35 35 35 20 3 3 0 12 12 10 3 35ns Min. 30 30 30 15 3 3 0 10 10 8 3 30ns Min. 20 20 20 3 25 25 25 3 * Available in Commercial Only. NOTE: tCO2, tLZ2 and tHZ2 apply to DPS128X32CV3 version only. AC OPERATING CONDITIONS AND CHARACTERISTICS - WRITE CYCLE 6, 7: Over operating ranges No. Symbol 13 14 15 16 17 18 19 20 21 22 tWC tAW tCW tAS tWP tWR tWHZ tDW tDH tOW Parameter Write Cycle Time Address Valid to End of Write Chip Enable to End of Write Address Set-Up Time ** Write Pulse Width Write Recovery Time Write Enable to Output in HIGH-Z 4, 5 Data to Write Time Overlap Data Hold from Write Time Output Active from End of Write 20ns* Min. Max. 20 15 15 0 15 0 25ns Min. 25 20 20 0 20 0 8 12 0 3 Max. 30ns Min. 30 25 25 0 25 0 10 15 0 3 Max. 35ns Min. 35 30 30 0 30 0 12 15 0 3 Max. 45ns Min. 45 40 40 0 35 0 15 20 0 3 Max. 20 25 0 3 Unit ns ns ns ns ns ns ns ns ns ns * Available in Commercial Only. ** Valid for both Read and Write Cycles. 4 30A044-24 REV. F Dense-Pac Microsystems, Inc. DPS128X32CV3/DPS128X32BV3 READ CYCLE ADDRESS CE SEL OE DATA I/O WRITE CYCLE 1: CE Controlled. 8 ADDRESS CE WE DATA IN DATA OUT 30A044-24 REV. F 5 DPS128X32CV3/DPS128X32BV3 Dense-Pac Microsystems, Inc. WRITE CYCLE 2: WE Controlled. OE is HIGH. 8, 9 ADDRESS CE WE DATA IN DATA OUT WRITE CYCLE 3: WE Controlled. OE is LOW. 8, 9 ADDRESS CE WE DATA IN DATA OUT 6 30A044-24 REV. F DPS128X32CV3/DPS128X32BV3 Dense-Pac Microsystems, Inc. ORDERING INFORMATION NOTES: 1. All voltages are with respect to V SS. 2. -2.0V min. for pulse width less than 20ns (VIL min. = -0.5V at DC level). 3. Stresses greater than those under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 4. This parameter is guaranteed and not 100% tested. 5. Transition is measured at the point of 500mV from steady state voltage. 6. When OE and CE are LOW and WE is HIGH, I/O pins are in the output state,and input signals of opposite phase to the outputs must not be applied. 7. The outputs are in a high impedance state when WE is LOW. 8. SEL timing is the same as CE timing (Valid for DPS128X32CV3 only). The Waveform is inverted. 9. CE and WE can initiate and terminate WRITE Cycle. MECHANICAL DRAWING Dense-Pac Microsystems, Inc. 7321 Lincoln Way u Garden Grove, California 92841-1428 (714) 898-0007 u (800) 642-4477 (Outside CA) u FAX: (714) 897-1772 30A044-24 REV. F 7