4 Megabit High Speed CMOS SRAM
DPS128X32CV3/DPS128X32BV3
DESCRIPTION:
The DPS128X32CV3/DPS128X32BV3 ‘’VERSA-STACK’’ module is
a revolutionary new high speed memory subsystem using Dense-Pac
Microsystems’ ceramic Stackable Leadless Chip Carriers (SLCC)
mounted on a co-fired ceramic substrate. It offers 4 Megabits of
SRAM in a package envelope of 1.090 x 1.090 x 0.252 inches.
The DPS128X32CV3/DPS128X32BV3 contains four individual
128K x 8 SRAMs, packaged in their own hermetically sealed SLCCs
making the module suitable for commercial, industrial and military
applications.
By using SLCCs, the ‘’Versa-Stack’’ family of modules offers a higher
board density of memory than available with conventional
through-hole, surface mount, module, or hybrid techniques.
The DPS128X32BV3 has one active low Chip Enable (CE) and while
the DPS128X32CV3 an active low Chip Enable (CE) and an active
high Select Line (SEL).
By using SLCCs, the ‘’Versa-Stack’’ family of modules offer a
higher board density of memory than available with
conventional through-hole, surface mount or hybrid
techniques.
FEATURES:
•Organizations Available:
128K x 32, 256K x 16, or 512K x 8
•Access Times:
20*, 25, 30, 35, 45ns
•Fully Static Operation
- No clock or refresh required
•Low Power Dissipation:
8.0mW (typ.) Full Standby
0.8W (typ.) Operating (x8)
•Single +5V Power Supply,
±10% Tolerance
•TTL Compatible
•Common Data Inputs and Outputs
•Low Data Retention Current:
140µA typ. (2.0V)
•66-Pin PGA ‘’VERSA-STACK’’
Package
*Commercial only.
PIN-OUT DIAGRAM
NOTE: SEL applies to the DPS128X32CV3 only, No Connect for the DPS128X32BV3 version.
PIN NAMES
A0 - A16 Address Inputs
I/O0 - I/O31 Data Input/Output
CE0 - CE3Low Chip Enables
SEL High Chip Enable
WE0 - WE1Write Enables
OE Output Enable
VDD Power (+5V)
VSS Ground
N.C. No Connect
FUNCTIONAL BLOCK DIAGRAM
This document contains information on a product that is currently released
to production at Dense-Pac Microsystems, Inc. Dense-Pac reserves the
right to change products or specifications herein without prior notice.
30A044-24
REV. F 1
DPS128X32CV3/DPS128X32BV3 Dense-Pac Microsystems, Inc.
RECOMMENDED OPERATING RANGE 3
Symbol Characteristic Min. Typ. Max. Unit
VDD Supply Voltage 4.5 5.0 5.5 V
VIH Input HIGH Voltage 2.2 VDD+0.3 V
VIL Input LOW Voltage -0.520.8 V
TAOperating
Temperature
M-55 +25 +125 oCI-40 +25 +85
C0+25 +70
TRUTH TABLE
Mode SEL CE WEOE I/O Pin Supply
Current
Not Selected LXXXHigh-Z Standby
Not Selected XHX X High-Z Standby
DOUT Disable HLH H High-Z Active
Read HLHLDOUT Active
Write HL L XDIN Active
H = HIGH L = LOW X = Don’t Care
NOTE: SEL applies to DPS128X32CV3 version only.
DC OUTPUT CHARACTERISTICS
Symbol Parameter Conditions Min. Max. Unit
VOH HIGH Voltage IOH= -4.0mA 2.4 V
VOL LOW Voltage IOL=8.0mA 0.4 V
ABSOLUTE MAXIMUM RATINGS 3
Symbol Parameter Value Unit
TSTC Storage Temperature -65 to +150 °C
TBIAS Temperature Under Bias -55 to +125 °C
VDD Supply Voltage 1 -0.5 to +7.0 °C
VI/O Input/Output Voltage 1 -0.5 to VDD+0.5 V
DC OPERATING CHARACTERISTICS: Over operating ranges
Symbol Characteristics Test Conditions Typ.
(†)
CIMUnit
Min. Max. Min. Max. Min. Max.
IIN Input
Leakage Current VIN = 0V to VDD --20 +20 -20 +20 -20 +20 µA
IOUT Output
Leakage Current VI/O = 0V to VDD,
CE or OE = VIH, or WE = VIL --10 +10 -10 +10 -10 +10 µA
ICC Operating
Supply Current Cycle=min., Duty=100%
IOUT = 0mA
X8 175 230 245 265
mAX16 250 340 350 390
X32 400 560 560 640
ISB1 Full Standby
Supply Current VIN ≥ VDD -0.2V or
VIN ≤ VSS +0.2V 1.6 20 20 40 mA
ISB2 Standby Current (TTL) CE = VIH 100 120 140 140 mA
IDR3
Data Retention
Supply Current
(3V)
VDR = 3V, CE ≥ VDR -0.2V,
(or SEL ≤ 0.2V, VIN ≥ VDD -0.2V
or VIN ≤ +0.2V)
0.28 1.60 2.40 8.00 mA
IDR2
Data Retention
Supply Current
(2V)
VDR = 2V, CE ≥ VDR -0.2V,
(or SEL ≤ 0.2V, VIN ≥ VDD -0.2V
or VIN ≤ +0.2V)
0.14 1.00 1.60 7.20 mA
VOL Output Low Voltage IOUT = 8.0mA -0.4 0.4 0.4 V
VOH Output High Voltage IOUT = -4.0mA -2.4 2.4 2.4 V
† Typical measurements made at +25oC, Cycle = min., VDD = 5.0V.
CAPACITANCE 4: TA = 25°C, F = 1.0MHz
Symbol Parameter Max. Unit Condition
CADR Address Input 50
pF VIN2 = 0V
CCE Chip Enable 20
CSEL Active High
Chip Select 50
CWE Write Enable 25
COE Output Enable 50
CI/O Data Input/Output 20
NOTE: CSEL applies to DPS128X32CV3 version only.
30A044-24
REV. F
2
Dense-Pac Microsystems, Inc. DPS128X32CV3/DPS128X32BV3
DATA RETENTION WAVEFORM: SEL Controlled. (Applies to DPS128X32CV3 only)
DATA RETENTION WAVEFORM: CE Controlled.
VDD
4.5V
SEL
VDR2
0.4V
0V SEL ≤ -0.2V
VDD
4.5V
2.3V
VDR1
CE
0V
CE ≥ VDD -0.2V
Data Retention AC Characteristics 8
Symbol Parameter Test Conditions Min. Typ. Max. Unit
VDR VDD for Data
Retention CE ≥ VDR -0.2V, (SEL ≥ VDR -0.2V,
or VIN ≤ VDR -0.2V or VIN ≤ 0.2V) 2.0 - - V
VCDR Chip Disable to
Data Retention Time See Data Retention Waveform 0- - ns
tROperation Recovery Time See Data Retention Waveform 5- - ms
NOTE: Test Conditions in parenthesis apply to DPS128X32CV3 version only.
30A044-24
REV. F 3
DPS128X32CV3/DPS128X32BV3 Dense-Pac Microsystems, Inc.
AC OPERATING CONDITIONS AND CHARACTERISTICS - READ CYCLE: Over operating ranges
No. Symbol Parameter 20ns* 25ns 30ns 35ns 45ns Unit
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
1tRC Read Cycle Time 20 25 30 35 45 ns
2tAA Address Access Time 20 25 30 35 45 ns
3tCO1 CE to Output Valid 20 25 30 35 45 ns
4tCO2 SEL to Output Valid 20 25 30 35 45 ns
5tOE Output Enable to Output Valid 810 15 20 25 ns
6tLZ1 CE to Output in LOW-Z 4, 5 33333ns
7tLZ2 SEL to Output in LOW-Z 4, 5 33333ns
8tOLZ Output Enable to Output in LOW-Z 4, 5 00000ns
9tHZ1 CE to Output in HIGH-Z 4, 5 10 12 15 20 25 ns
10 tHZ2 SEL to Output in HIGH-Z 4, 5 10 12 15 20 25 ns
11 tOHZ Output Enable to Output in HIGH-Z 4, 5 810 15 20 25 ns
12 tOH Output Hold from Address Change 33333ns
* Available in Commercial Only.
NOTE: tCO2, tLZ2 and tHZ2 apply to DPS128X32CV3 version only.
AC OPERATING CONDITIONS AND CHARACTERISTICS - WRITE CYCLE 6, 7: Over operating ranges
No. Symbol Parameter 20ns* 25ns 30ns 35ns 45ns Unit
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
13 tWC Write Cycle Time 20 25 30 35 45 ns
14 tAW Address Valid to End of Write 15 20 25 30 40 ns
15 tCW Chip Enable to End of Write 15 20 25 30 40 ns
16 tAS Address Set-Up Time ** 00000ns
17 tWP Write Pulse Width 15 20 25 30 35 ns
18 tWR Write Recovery Time 00000ns
19 tWHZ Write Enable to Output in HIGH-Z 4, 5 810 12 15 20 ns
20 tDW Data to Write Time Overlap 12 15 15 20 25 ns
21 tDH Data Hold from Write Time 00000ns
22 tOW Output Active from End of Write 33333ns
* Available in Commercial Only.
** Valid for both Read and Write Cycles.
+5V
255Ω
480Ω
CL*
DOUT
Figure 1. Output Load
* Including Probe and Jig Capacitance.
OUTPUT LOAD
Load CLParameters Measured
130pF except tLZ1, tLZ2, tHZ1, tHZ2, tOHZ, tOLZ,
and tWHZ
25pF tLZ1, tLZ2, tHZ1, tHZ2, tOHZ, tOLZ, and
tWHZ
NOTE: tLZ2 and tHZ2 apply to DPS128X32CV3 version only.
AC TEST CONDITIONS
Input Pulse Levels 0V to 3.0V
Input Pulse Rise and Fall Times 5ns
Input and Output
Timing Reference Levels 1.5V
30A044-24
REV. F
4
Dense-Pac Microsystems, Inc. DPS128X32CV3/DPS128X32BV3
READ CYCLE
ADDRESS
CE
SEL
OE
DATA I/O
WRITE CYCLE 1: CE Controlled. 8
ADDRESS
CE
WE
DATA IN
DATA OUT
30A044-24
REV. F 5
DPS128X32CV3/DPS128X32BV3 Dense-Pac Microsystems, Inc.
WRITE CYCLE 3: WE Controlled. OE is LOW. 8, 9
ADDRESS
CE
WE
DATA IN
DATA OUT
WRITE CYCLE 2: WE Controlled. OE is HIGH. 8, 9
ADDRESS
CE
WE
DATA IN
DATA OUT
30A044-24
REV. F
6
Dense-Pac Microsystems, Inc. DPS128X32CV3/DPS128X32BV3
ORDERING INFORMATION
MECHANICAL DRAWING
Dense-Pac Microsystems, Inc.
7321 Lincoln Way u Garden Grove, California 92841-1428
(714) 898-0007 u (800) 642-4477 (Outside CA) u FAX: (714) 897-1772
NOTES:
1. All voltages are with respect to VSS.
2. -2.0V min. for pulse width less than 20ns (VIL min. = -0.5V at DC
level).
3. Stresses greater than those under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
4. This parameter is guaranteed and not 100% tested.
5. Transition is measured at the point of ±500mV from steady state
voltage.
6. When OE and CE are LOW and WE is HIGH, I/O pins are in the
output state,and input signals of opposite phase to the outputs must
not be applied.
7. The outputs are in a high impedance state when WE is LOW.
8. SEL timing is the same as CE timing (Valid for DPS128X32CV3 only).
The Waveform is inverted.
9. CE and WE can initiate and terminate WRITE Cycle.
30A044-24
REV. F 7
