a +3 V/+5 V, Rail-to-Rail Quad, 8-Bit DAC AD7304/AD7305* FEATURES Four 8-Bit DACs in One Package +3 V, +5 V and 5 V Operation Rail-to-Rail REF-Input to Voltage Output Swing 2.6 MHz Reference Multiplying Bandwidth Compact 1.1 mm Height TSSOP 16-/20-Lead Package Internal Power ON Reset SPI Serial Interface Compatible--AD7304 Fast Parallel Interface--AD7305 40 A Power Shutdown APPLICATIONS Automotive Output Span Voltage Instrumentation, Digitally Controlled Calibration Pin-Compatible AD7226 Replacement when V DD < 5.5 V FUNCTIONAL BLOCK DIAGRAMS VREFB VREFA VDD PWR ON RESET INPUT 8 REG A DAC A REG INPUT 8 REG B DAC A VOUTA DAC B 8 REG DAC B VOUTB INPUT 8 REG C DAC C 8 REG DAC C VOUTC INPUT 8 REG D DAC D 8 REG DAC D VOUTD 8 CS SDI/SHDN SERIAL REG CLK AD7304 VSS GND CLR LDAC VREFC VREFD VREF VDD GENERAL DESCRIPTION The AD7304/AD7305 are quad, 8-bit DACs that operate from a single +3 V to +5 V supply or 5 V supplies. The AD7304 has a serial interface, while the AD7305 has a parallel interface. Internal precision buffers swing rail-to-rail. The reference input range includes both supply rails allowing for positive or negative fullscale output voltages. Operation is guaranteed over the supply voltage range of +2.7 V to +5.5 V, consuming less than 9 mW from a +3 V supply. The full-scale voltage output is determined by the external reference input voltage applied. The rail-to-rail VREF input to DAC VOUT allows for a full-scale voltage set equal the positive supply VDD, the negative supply VSS or any value in between. The AD7304's doubled-buffered serial-data interface offers high speed, three-wire, SPI and microcontroller compatible inputs using data in (SDI), clock (CLK) and chip select (CS) pins. Additionally, an internal power-on reset sets the output to zero scale. The parallel input AD7305 uses a standard address decode along with the WR control line to load data into the input registers. The double buffered architecture allows all four input registers to be preloaded with new values, followed by a LDAC control strobe which copies all the new data into the DAC registers thereby updating the analog output values. When operating from less than +5.5 V, the AD7305 is pin-compatible with the popular industry standard AD7226. 8 PWR ON RESET DB0 DB1 DB2 DB3 DB4 DB5 DB6 WR A0/SHDN A1 INPUT 8 REG A DAC A 8 REG DAC A VOUTA INPUT 8 REG B DAC B 8 REG DAC B VOUTB INPUT 8 REG C DAC C 8 REG DAC C VOUTC INPUT 8 REG D DAC D 8 REG DAC D VOUTD 8 DECODE AD7305 LDAC VSS GND An internal power ON reset places both parts in the zero-scale state at turn ON. A 40 A power shutdown (SHDN) feature is activated on both parts by tristating the SDI/SHDN pin on the AD7304, and tristating the A0/SHDN address pin on the AD7305. The AD7304/AD7305 are specified over the extended industrial (-40C to +85C), and the automotive (-40C to +125C) temperature ranges. AD7304s are available in 16-lead plastic DIP (N-16), and wide-body SOL-16 (R-16) packages. The parallel input AD7305 is available in the 20-lead plastic DIP (N-20), and the SOL-20 (R-20) surface mount package. For ultracompact applications the thin 1.1 mm TSSOP-16 (RU-16) package will be available for the AD7304, while the TSSOP-20 (RU-20) will house the AD7305. *Protected under Patent Number 5684481. REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 1998 (@ VDD = +3 V or +5 V, VSS = 0 V; or VDD = +5 V and VSS = -5 V, VSS REF VDD, -40C < TA < +85C/+125C, unless otherwise noted.) AD7304/AD7305-SPECIFICATIONS V 3 V 10% 5 V 10% 5 V 10% Units 8 1 1 15 4 5 8 1 1 15 4 5 8 1 1 15 4 5 Bits LSB max LSB max mV max LSB max ppm/C typ4 VSS/VDD 28 7.5 5 VSS/VDD 28 7.5 5 VSS/VDD 28 7.5 5 V min/max k typ k typ pF typ VSS/VDD Code = 80H, VOUT < 1 LSB 3 DAC Outputs Placed in Shutdown State 120 No Oscillation 200 VSS/VDD 3 120 200 VSS/VDD 3 120 200 V min/max mA typ k typ pF typ 0.6 2.1 10 8 0.8 2.4 10 8 0.8 2.4 10 8 V min V max A max pF max 1/2.7 1/3.6 1.1/2 2 15 15 2 1.0/2 2 15 15 2 1/3.6 2.6 0.025 1.0/2 2 15 15 2 -65 V/s min/typ MHz typ % s typ/max s max s typ nVs typ nVs typ dB 6 6 15 40 0.004 30 40 0.004 6 6 60 40 0.004 mA max mA max mW max A typ %/% Parameter Symbol Condition STATIC PERFORMANCE Resolution1 Integral Nonlinearity2 Differential Nonlinearity Zero-Scale Error Full-Scale Voltage Error Full-Scale Tempco3 N INL DNL VZSE VFSE TCVFS REFERENCE INPUT VREFIN Range Input Resistance (AD7304) Input Resistance (AD7305) Input Capacitance3 VREFIN RREFIN RREFIN CREFIN Code = 55H All DACs at Code = 55H ANALOG OUTPUTS Output Voltage Range Output Current Drive Shutdown Resistance Capacitive Load3 VOUT IOUT ROUT CL LOGIC INPUTS Logic Input Low Voltage Logic Input High Voltage Input Leakage Current5 Input Capacitance3 VIL VIH IIL CIL AC CHARACTERISTICS3 Output Slew Rate Reference Multiplying Total Harmonic Distortion Settling Time6 Shutdown Recovery Time Time to Shutdown DAC Glitch Digital Feedthrough Feedthrough SR BW THD tS tSDR tSDN Q Q VOUT/VREF Code = 00H to FFH to 00H Small Signal, VSS = -5 V VREF = 4 V p-p, VSS = -5 V, f = 1 kHz To 0.1% of Full Scale To 0.1% of Full Scale SUPPLY CHARACTERISTICS Positive Supply Current Negative Supply Current Power Dissipation Power Down Power Supply Sensitivity IDD ISS PDISS IDD_SD PSS VLOGIC = 0 V or VDD, No Load VSS = -5 V VLOGIC = 0 V or VDD, No Load SDI/SHDN = Floating VDD = 10% Monotonic, All Codes 0 to FFH Data = 00H Data = FFH Code = 00H, VREF =1 V p-p, f = 100 kHz NOTES 1 One LSB = V REF/256. 2 The first three codes (00 H, 01H, 10H) are excluded from the integral nonlinearity error measurement in single supply operation +3 V or +5 V. 3 These parameters are guaranteed by design and not subject to production testing. 4 Typicals represent average readings measured at +25C. 5 SDI/SHDN and A0/SHDN pins have 30 A maximum IIL input leakage current. 6 The settling time specification does not apply for negative going transitions within the last 3 LSBs of ground in single supply operation. Specifications subject to change without notice. 5V VREF = 10V p-p f = 20kHz 5V 0V 0V -5V VOUT = 10V p-p -5V (OUT) (IN) Figure 1. AD7304/AD7305 Rail-to-Rail Reference Input to Output at 20 kHz -2- REV. A AD7304/AD7305 (@ VDD = +3 V or +5 V, VSS = 0 V; or VDD = +5 V and VSS = -5 V, VSS VREF VDD, -40C < TA < TIMING SPECIFICATIONS +85C/125C, unless otherwise noted.) Parameter Symbol 3 V 10% 5 V 10% 5 V 10% Units 70 70 50 30 70 40 40 60 30 60 55 55 40 20 60 30 30 60 20 40 55 55 40 20 60 30 30 60 20 40 ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min 60 30 60 30 60 60 60 30 40 20 40 20 50 50 40 20 40 20 40 20 50 50 40 20 ns min ns min ns min ns min ns min ns min ns min ns min 1, 2 INTERFACE TIMING SPECIFICATIONS AD7304 Only Clock Width High tCH Clock Width Low tCL Data Setup tDS Data Hold tDH Load Pulsewidth tLDW Load Setup tLD1 Load Hold tLD2 Clear Pulsewidth tCLWR Select tCSS Deselect tCSH AD7305 Only Data Setup tDS Data Hold tDH Address Setup tAS Address Hold tAH Write Width tWR Load Pulsewidth tLDW Load Setup tLS Load Hold tLH NOTES 1 These parameters are guaranteed by design and not subject to production testing. 2 All input control signals are specified with t R = tF = 2 ns (10% to 90% of V DD) and timed from a voltage level of 1.6 V. ABSOLUTE MAXIMUM RATINGS* ORDERING GUIDE VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V, +8 V VSS to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V, -8 V VREFX to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSS, VDD Logic Inputs to GND . . . . . . . . . . . . . . . -0.3 V, VDD + 0.3 V VOUTX to GND . . . . . . . . . . . . . . . . . . . . -0.3 V, VDD + 0.3 V IOUT Short Circuit to GND . . . . . . . . . . . . . . . . . . . . . 50 mA Package Power Dissipation . . . . . . . . . . . . . . (TJ MAX-TA)/JA Thermal Resistance JA 16-Lead Plastic DIP Package (N-16) . . . . . . . . . . 103C/W 16-Lead SOIC Package (R-16) . . . . . . . . . . . . . . . 73C/W TSSOP-16 Package (RU-16) . . . . . . . . . . . . . . . . 180C/W 20-Lead Plastic DIP Package (N-20) . . . . . . . . . . 120C/W 20-Lead SOIC Package (R-20) . . . . . . . . . . . . . . . 74C/W TSSOP-20 Package (RU-20) . . . . . . . . . . . . . . . . 155C/W Maximum Junction Temperature (TJ MAX) . . . . . . . . . +150C Operating Temperature Range . . . . . . . . . . . -40C to +85C Storage Temperature Range . . . . . . . . . . . . -65C to +150C Lead Temperature N-16 and N-20 (Soldering, 10 secs) . . . . . . . . . . . . +300C R-16, R-20, RU-16, RU-20 (Vapor Phase, 60 secs) . . +215C R-16, R-20, RU-16, RU-20 (Infrared, 15 secs) . . . . +220C Model Temperature Range Package Description Package Options AD7304BN AD7304BR AD7304YR AD7304BRU -40C/+85C -40C/+85C -40C/+125C -40C/+85C 16-Lead P-DIP 16-Lead SOIC 16-Lead SOIC TSSOP-16 N-16 R-16 R-16 RU-16 AD7305BN AD7305BR AD7305YR AD7305BRU -40C/+85C -40C/+85C -40C/+125C -40C/+85C 20-Lead P-DIP 20-Lead SOIC 20-Lead SOIC TSSOP-20 N-20 R-20 R-20 RU-20 The AD7304/AD7305 contains 2759 transistors. Die size: 103 mil x 102 mil, 10,506 sq mil. *Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7304/AD7305 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. REV. A -3- WARNING! ESD SENSITIVE DEVICE AD7304/AD7305 SDI SA SI A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 CLK tCSS tCSH CS tLD2 LDAC tLD1 SDI tDS tCL CLK tDH tCH tLDW LDAC CLR tCLRW tS FS 1 LSB ERROR BAND VOUT ZS tS Figure 2. AD7304 Timing Diagram tSDN tSDR SDI/SHDN IDD Figure 3. AD7304 Timing Diagram Table I. AD7304 Control Logic Truth Table CS CLK LDAC CLR Serial Shift Register Function Input REG Function DAC Register Function H L + H H H X + L X X X H H H L H H No Effect Data Advanced 1 Bit No Effect No Effect No Effect No Effect No Effect No Effect Updated with SR Contents2 Latched with SR Contents 2 Loaded with 00H Latched with 00H No Effect No Effect No Effect All Input Register Contents Transferred3 Loaded with 00H Latched with 00H H H H H - + NOTES 1 + positive logic transition; - negative logic transition; X Don't Care. 2 One Input Register receives the data bits D7-D0 decoded from the SR address bits (A1, A0); where REG A = (0, 0); B = (0, 1); C = (1, 0); D = (1, 1). 3 LDAC is a level-sensitive input. Table II. AD7304 Serial Input Register Data Format, Data Is Loaded in the MSB-First Format MSB B11 AD7304 SAC B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 LSB B0 SDC A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 If B11 (SAC), Shutdown All Channels, is set to logic LOW, all DACs are placed in a power shutdown mode, all output voltages become high resistance. If B10 (SDC), Shutdown Decoded Channel, is set to logic LOW, only the DAC decoded by address bits A1 and A0 is placed in the shutdown mode. -4- REV. A AD7304/AD7305 Table III. AD7305 Control Logic Truth Table WR A1 A0 LDAC Input Register Function DAC Register Function L + L + L + L + H L H H L L L L H H H H X X X X L L H H L L H H X X X X H H H H H H H H L L + H Latched with Previous Contents, No Change Latched with Previous Contents, No Change Latched with Previous Contents, No Change Latched with Previous Contents, No Change Latched with Previous Contents, No Change Latched with Previous Contents, No Change Latched with Previous Contents, No Change Latched with Previous Contents, No Change All Input Register Contents Loaded, Register Transparent Register Transparent All Input Register Contents Latched No Effect, Device Not Selected REG A Loaded with DB0-DB7 REG A Latched with DB0-DB7 REG B Loaded with DB0-DB7 REG B Latched with DB0-DB7 REG C Loaded with DB0-DB7 REG C Latched with DB0-DB7 REG D Loaded with DB0-DB7 REG D Latched with DB0-DB7 No Effect Input REG x Transparent to DB0-DB7 No Effect No Effect, Device Not Selected NOTES 1 + positive logic transition; - negative logic transition; X Don't Care. 2 LDAC is a level sensitive input. PIN CONFIGURATIONS WR tAS tAH 20 16 VOUTC VOUTA 2 19 VOUTD VOUTA 2 15 VOUTD VSS 3 18 VDD 17 A0/SHDN 16 A1 tDH D0-D7 tLS tLH tLDW LDAC tS 1 LSB ERROR BAND VOUT Figure 4. AD7305 Timing Diagram tSDN tSDR IDD Figure 5. AD7305 Timing Diagram REV. A VDD VREF 4 13 VREFC GND 5 TOP VIEW VREFB 5 (Not to Scale) 12 VREFD LDAC 6 VREFA 4 tDS A0/SHDN 14 VSS 3 A0, A1 -5- VOUTC VOUTB 1 VOUTB 1 tWR AD7304 AD7305 GND 6 11 SDI/SHDN TOP VIEW 15 WR (Not to Scale) 14 DB0 DB7 7 LDAC 7 10 CLK DB6 8 13 DB1 CLR 8 9 CS DB5 9 12 DB2 DB4 10 11 DB3 AD7304/AD7305 AD7304 PIN FUNCTION DESCRIPTIONS Pin # Name 1 VOUTB 2 VOUTA 3 4 5 6 7 VSS VREFA VREFB GND LDAC 8 9 CLR CS 10 11 CLK SDI/SHDN 12 13 14 15 VREFD VREFC VDD VOUTD 16 VOUTC Function Channel B rail-to-rail buffered DAC voltage output. Full scale set by reference voltage applied to V REFB pin. Output is open circuit when SHDN is enabled. Channel A rail-to-rail buffered DAC voltage output. Full scale set by reference voltage applied to V REFA pin. Output is open circuit when SHDN is enabled. Negative Power Supply Input. Specified range of operation 0 V to -5.5 V. Channel A Reference Input. Establishes VOUTA full-scale voltage. Specified range of operation VSS < VREFA < VDD. Channel B Reference Input. Establishes V OUTB full-scale voltage. Specified range of operation VSS < VREFB < VDD. Common Analog and Digital Ground. Load DAC register strobe, active low. Transfers all four Input Register data into their DAC registers. Asynchronous active low input. DAC Register is transparent when LDAC = 0. See Control Logic Truth Table for operation. Clears all Input and DAC registers to the zero condition. Asynchronous active low input. The serial register is not effected. Chip Select, Active Low Input. Disables shift register loading when high. Transfers Serial Input Register Data to the decoded Input Register when CS returns HIGH. Does not effect LDAC operation. Clock input, positive edge clocks data into shift register. Disabled by chip select CS. Serial Data-Input loads directly into the shift register, MSB first. Hardware shutdown (SHDN) control input, active when pin is left floating by a three-state logic driver. Does not effect DAC register contents as long as power is present on VDD. Channel D Reference Input. Establishes VOUTD full-scale voltage. Specified range of operation VSS < VREFD < VDD. Channel C Reference Input. Establishes VOUTC full-scale voltage. Specified range of operation V SS < VREFC < VDD. Positive power supply input. Specified range of operation +2.7 V to +5.5 V. Channel D rail-to-rail buffered DAC voltage output. Full-scale set by reference voltage applied to V REFD pin. Output is open circuit when SHDN is enabled. Channel C rail-to-rail buffered DAC voltage output. Full-scale set by reference voltage applied to V REFC pin. Output is open circuit when SHDN is enabled. AD7305 PIN FUNCTION DESCRIPTIONS Pin # Name Function 1 VOUTB 2 VOUTA 3 4 5 6 VSS VREF GND LDAC 7 8 9 10 11 12 13 14 15 16 17 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 WR A1 A0/SHDN 18 19 VDD VOUTD 20 VOUTC Channel B rail-to-rail buffered DAC voltage output. Full scale set by reference voltage applied to V REFB pin. Output is open circuit when SHDN is enabled. Channel A rail-to-rail buffered DAC voltage output. Full scale set by reference voltage applied to V REFA pin. Output is open circuit when SHDN is enabled. Negative Power Supply Input. Specified range of operation 0 V to -5.5 V. Channel B Reference Input. Establishes V OUT full-scale voltage. Specified range of operation V SS < VREF < VDD. Common Analog and Digital Ground. Load DAC register strobe, active low. Transfers all four Input Register data into their DAC registers. Asynchronous active low input. DAC Register is transparent when LDAC = 0. See Control Logic Truth Table for operation. MSB Digital Input Data Bit. Data Bit 6. Data Bit 5. Data Bit 4. Data Bit 3. Data Bit 2. Data Bit 1. LSB Digital Input Data Bit. Write data into Input Register control line, active low. See Control Logic Truth Table for operation. Address Bit 1. Address Bit 0/Hardware shutdown (SHDN) control input, active when pin is left floating by a three-state logic driver. Does not effect DAC register contents as long as power is present on V DD. Positive Power Supply Input. Specified range of operation +2.7 V to +5.5 V. Channel D rail-to-rail buffered DAC voltage output. Full scale set by reference voltage applied to V REFD pin. Output is open circuit when SHDN is enabled. Channel C rail-to-rail buffered DAC voltage output. Full scale set by reference voltage applied to V REFC pin. Output is open circuit when SHDN is enabled. -6- REV. A Typical Performance Characteristics-AD7304/AD7305 144 1.0 VDD = +5V VSS = -5V VREF = VDD IOUT SINK CURRENT - mA 120 0.6 DATA = 00H DAC D INL - LSB 96 72 0.2 -0.2 DAC C DAC B 48 -0.6 24 0 VDD = +5V VSS = -5V DATA = 80H TA = +25C 0 3 6 9 -1.0 -5.0 15 12 -3.0 -1.0 1.0 3.0 REFERENCE INPUT VOLTAGE - Volts VOUT - mV Figure 6. IOUTSINK vs. VOUT Rail-to-Rail Performance 5.0 Figure 9. INL vs. Reference Input Voltage 0.500 -35 VDD = +5V VSS = -5V VREF = VDD -28 VDD = +5V VSS = -5V VREF = 2.5V 0.375 0.250 DATA = FFH -21 DNL - LSB IOUT SOURCE CURRENT - mA DAC A -14 0.125 0.000 -0.125 -0.250 -7 -0.375 0 4.0 4.2 -0.500 5.0 4.4 4.6 4.8 VOUT OUTPUT VOLTAGE - Volts 0 32 0 DAC A ZERO SCALE VOLTAGE - mV -1 1 0 INL - LSB 192 224 256 4.0 1 DAC B -1 1 0 VDD = +5V VSS = -5V VREF = +2.5V TA = +25C DAC C -1 1 0 3.6 VDD = +5.5V VSS = 0V VREF = +5.45V 3.2 2.8 2.4 DAC D 0 32 64 96 128 160 CODE - Decimal 192 224 2.0 -55 256 Figure 8. INL vs. Code, All DAC Channels REV. A 96 128 160 CODE - Decimal Figure 10. DNL vs. Code Figure 7. IOUTSOURCE vs. VOUT Rail-to-Rail Performance -1 64 -35 -15 5 25 45 65 TEMPERATURE - C 85 105 125 Figure 11. Zero Scale Voltage vs. Temperature -7- AD7304/AD7305 CS VDD = +5V VREF = +4V VOUT NO LOAD DATA = 00H VDD = +5V CL = 150pF RL = 70k FFH RL = 10k 0V VOUT 5V CS 0V 5s/DIV 2s/DIV Figure 15. Time to Shutdown Figure 12. Large-Signal Settling Time CS 5V DATA = FFH VREFIN (5V @ 50kHz) IDD 1mA/V 0V -5V 5V VDD = +5V 0V VOUT VOUTA -5V 2s/DIV Figure 13. Multiplying Mode Step Response and Output Slew Rate Figure 16. Shutdown Recovery Time (Wakeup) 6 1 0 -4 A VDD = +5V VSS = -5V THD - % GAIN - dB 4 10 VDD = +5V VSS = -5V DATA = FFH VREF = 100mV rms f-3dB = 2.6MHz 0.1 0.010 -6 -8 10k 100k 1M FREQUENCY - Hz 0.001 10m 10M Figure 14. Multiplying Mode Gain vs. Frequency 1 2 3 4 5 6 7 VREF AMPLITUDE - V p-p 8 9 10 Figure 17. THD vs. Reference Input Amplitude -8- REV. A AD7304/AD7305 1 A VDD = +5V VSS = -5V 0.1 VDD = +5V VSS = -5V VREF = 2.5V F = 1MHz DATA = 80H THD - % VOUT 7FH 0.010 CS 0.001 20 100 1k FREQUENCY - Hz 100k 10k Figure 18. THD vs. Frequency Figure 21. Midscale Transition Glitch 3.0 40 VDD = +5V VSS = -5V VREF = 4V DATA = FFH 0 CROSS TALK - dB NOISE DENSITY - V/ Hz 2.4 20 1.8 1.2 0.6 -20 VDD = +5V VSS = -5V VREF = 50mV rms DAC A DATA = FFH DAC B, C, D DATA = 00H -40 -60 -80 -100 V OUTB CT = 20 LOG -120 V REF -140 0 1 10 100 1k FREQUENCY - Hz 10k -160 100 100k 1k 10k 100k FREQUENCY - Hz 1M 10M Figure 22. Crosstalk vs. Frequency Figure 19. Output Noise Voltage Density vs. Frequency 60 -PSRR, VSS = -5V 10% +PSRR, VDD = +5V 10% 50 PSRR - dB 40 VOUTB VDD = +5V VSS = -5V VREF = 2.5V DAC A = FFH DAC B = OOH F = 2MHz -PSRR, VSS = -3V 10% 30 20 10 CLK 0 10 50ns/DIV DATA = 80H TA = +25C 100 1k FREQUENCY - Hz 10k 100k Figure 23. Power Supply Rejection vs. Frequency Figure 20. Digital Feedthrough REV. A +PSRR, VDD = +3V 10% -9- AD7304/AD7305 80 12 VDD = +5V VSS = -5V VREF = 2.5V A0 = 5V ALL OTHER DIGITAL PINS VARYING 8 6 IDD 4 60 50 40 ISS 2 0 30 0 1 2 3 DIGITAL INPUT VOLTAGE - Volts 20 -55 5 4 Figure 24. Supply Current vs. Digital Input Voltage -15 -35 5 25 45 65 TEMPERATURE - C 85 105 125 Figure 27. Shutdown Supply Current vs. Temperature 10.0000 NORMALIZED TOTAL UNADJUSTED ERROR DRIFT - LSB 0.08 1.0000 SUPPLY CURRENT - mA VDD = +5.5V VSS = -5.5V VREF = 2.5V PIN A0 FLOATING 70 SHUTDOWN SUPPLY - A SUPPLY CURRENT - mA 10 VDD = +5V VSS = -5V VREF = 2.5V ALL DIGITAL PINS VARY, EXCEPT A0 = 5V 0.1000 IDD 0.0100 0.0001 0 1 0.04 VDD = 2.7V 0 VDD = 5.5V -0.04 ISS 0.0010 READING MADE AT TA = +25C SAMPLE SIZE = 924 UNITS -0.08 5 2 3 4 DIGITAL INPUT VOLTAGE - Volts Figure 25. Shutdown Supply Current vs. Digital Input Voltage (A0 Only) 0 84 168 252 336 DEGREES CELCIUS 420 504 Figure 28. Normalized TUE Drift Accelerated by Burn-In Hours of Operation @ 150 C 5.0 VDD = +5V VSS = -5V VREF = 2.5V SUPPLY CURRENT - mA 4.4 IDD AND ISS 3.8 3.2 2.6 2.0 -55 -35 -15 5 25 45 65 TEMPERATURE - C 85 105 125 Figure 26. Supply Current vs. Temperature -10- REV. A AD7304/AD7305 CIRCUIT OPERATION directly to the same supply as the VDD or VSS pin (Figure 30). Under these conditions clean power supply voltages (low ripple, avoid switching supplies) appropriate for the application should be used. The AD7304/AD7305 are a set of four-channel, 8-bit, voltageoutput, digital-to-analog converters differing primarily in digital logic interface and number of reference inputs. Both parts share the same internal DAC design and true rail-to-rail output buffers. The AD7304 contains four independent multiplying reference inputs, while the AD7305 has one common reference input. The AD7304 uses a 3-wire SPI compatible serial data interface, while the AD7305 offers a 8-bit parallel data interface. VDD Q1 VOUTX Q2 D/A Converter Section Each part contains four voltage-switched R-2R ladder DACs. Figure A shows a typical equivalent DAC. These DACs are designed to operate both single-supply or dual supply, depending on whether the user supplies a negative voltage on the VSS pin. In a single-supply application the VSS is tied to ground. In either mode the DAC output voltage is determined by the VREF input voltage and the digital data (D) loaded into the corresponding DAC register according to Equation 1. VOUT = VREF x D/256 VSS Figure 30. Equivalent DAC Amplifier Output Circuit AD7304 SERIAL DATA INTERFACE (1) Note that the output full-scale polarity is the same as the VREF polarity for dc reference voltages. VDD VREF DB7 DB6 DB0 VOUT 2R R 2R VSS 2R 2R Figure 29. Typical Equivalent DAC Channel These DACs are also designed to accommodate ac reference input signals. As long as the ac signals are maintained between VSS < VREF <VDD, the user can expect 50 kHz of full-power multiplying bandwidth performance. In order to use negative input reference voltages, the VSS pin must be biased with a negative voltage of equal or greater magnitude than the reference voltage. The reference inputs are code-dependent, exhibiting worst case minimum resistance values specified in the parametric specification table. The DAC outputs VOUTA, B, C, D are each capable of driving 2 k loads in parallel with up to 500 pF loads. Output source and sink current is shown in Figures 6 and 7. The output slew rate is nominally 3.6 V/s while operating from 5 V supplies. The low output impedance of the buffers minimizes crosstalk between analog input channels. At 100 kHz, 65 dB of channel-to-channel isolation exists (Figure 22). Output voltage noise is plotted in Figure 19. In order to maintain good analog performance, power supply bypassing of 0.01 F in parallel with 1 F is recommended. The true rail-to-rail capability of the AD7304/AD7305 allows the user to connect the reference inputs REV. A 120k The AD7304 uses a 3-wire (CS, SDI, CLK) SPI compatible serial data interface. New serial data is clocked into the serial input register in a 12-bit data-word format. MSB bits are loaded first. Table II defines the 12 data-word bits. Data is placed on the SDI/SHDN pin and clocked into the register on the positive clock edge of CLK subject to the data setup and data hold time requirements specified in the TIMING SPECIFICATIONS. Data can only be clocked in while the CS chip select pin is active low. Only the last 12-bits clocked into the serial register will be interrogated when the CS pin returns to the logic high state, extra data bits are ignored. Since most microcontrollers output serial data in 8-bit bytes, two right justified data bytes can be written to the AD7304. Keeping the CS line low between the first and second byte transfer will result in a successful serial register update. Once the data is properly aligned in the shift register the positive edge of the CS initiates either the transfer of new data to the target DAC register, determined by the decoding of address bits A1 and A0, or the shutdown features will be activated based on the SAC or SDC bits. When either SAC or SDC pins are set (Logic = 0) the loading of new data determined by Bits B9 to B0 are still loaded, but the results do not appear on the buffer outputs until the device is brought out of the shutdown state. The selected DAC output voltages become high impedance with a nominal resistance of 120 k to ground, Figure 30. If both SAC and SDC pins are set, all channels are still placed in the shutdown mode. When the AD7304 has been programmed into the power shutdown state, the present DAC register data is maintained as long as VDD remains greater than 2.7 volts. The remaining characteristics of the software serial interface are defined by Tables I, II and Figure 3 timing diagram. Two additional pins CLR and LDAC on the AD7304 provide hardware control over the clear function and the DAC Register loading. If these functions are not needed the CLR pin can be tied to logic high, and the LDAC pin can be tied to logic low. The asynchronous input CLR pin forces all input and DAC registers to the zero-code state. The asynchronous LDAC pin can be strobed to active low when all DAC Registers need to be updated simultaneously from their respective Input Registers. The LDAC pin places the DAC Register in a transparent mode while in the logic low state. -11- AD7304/AD7305 VREFA CS CLK SDI VREFB VREFC VREFD VDD VREF AD7304 EN D0 D1 D2 D3 D4 D5 D6 D7 A0 A1 INPUT REGISTER R DAC A REGISTER R DAC A DAC B REGISTER R DAC B OE VOUTA WR VOUTB A1 AD7305 8 DATA DB0-DB7 VDD INPUT REGISTER R DAC A REGISTER R DAC A INPUT REGISTER R DAC B REGISTER R DAC B INPUT REGISTER DAC C REGISTER DAC C VOUTA OE g 8 D Q DACA B 2:4 C DECODE D INPUT REGISTER R OE g DAC A B 2:4 C DECODE D A0/SHDN D Q VOUTB OE SDC SAC VDD 640k 680k INPUT REGISTER DAC C REGISTER R DAC C OE R VOUTC g DAC D REGISTER R DAC D OE DAC D REGISTER R DAC D VOUTC INPUT REGISTER R VOUTD OE 80k D Q POWERON RESET GND 680k VOUTD g 320k OE VDD 640k 280k R D Q INPUT REGISTER R 80k R 280k LDAC CLR VSS 320k GND Figure 31. AD7304 Equivalent Logic Interface POWERON RESET LDAC VSS Figure 32. AD7305 Equivalent Logic Interface AD7304 Hardware Shutdown SHDN the same time. This will result in the analog outputs all changing to their new values at the same time. The LDAC pin is a level-sensitive input. If the simultaneous update feature is not required the LDAC pin can be tied to logic low. When the LDAC is tied to logic low, the DAC Registers become transparent and the Input Register data determines the DAC output voltage. See Figure 32 for an equivalent interface logic diagram. If a three-state driver is used on the SDI/SHDN pin, the AD7304 can be placed into a power shutdown mode when the SDI/ SHDN pin is placed in a high impedance state. For proper operation no other termination voltages should be present on this pin. An internal window comparator will detect when the logic voltage on the SHDN pin is between 28% and 36% of VDD. A high impedance internal bias generator provides this voltage on the SHDN pin. The four DAC output voltages become high impedance with a nominal resistance of 120 k to ground. See Figure 30 for an equivalent circuit. AD7226 Pin Compatibility By tying the LDAC pin to ground, the AD7305 has the same pin out and functionality as the AD7226, with the exception of a lower power supply operating voltage. AD7304/AD7305 POWER ON RESET AD7305 Hardware Shutdown SHDN When the VDD power supply is turned on, an internal reset strobe forces all the Input and DAC registers to the zero-code state. The VDD power supply should have a monotonically increasing ramp in order to have consistent results, especially in the region of VDD = 1.5 V to 2.3 V. The VSS supply has no effect on the power ON reset performance. The DAC register data will stay at zero until a valid serial register software load takes place. In the case of the double buffered AD7305 the output DAC register can only be changed once the LDAC strobe is initiated. If a three state driver is used on the A0/SHDN pin, the AD7305 can be placed into a power shutdown mode when the A0/SHDN pin is placed in a high impedance state. For proper operation no other termination voltages should be present on this pin. An internal window comparator will detect when the logic voltage on the SHDN pin is between 28% and 36% of VDD. A high impedance internal bias generator provides this voltage on the SHDN pin. The four DAC output voltages become high impedance with a nominal resistance of 120 k to ground. AD7305 PARALLEL DATA INTERFACE The AD7305 has an 8-bit parallel interface DB7 = MSB, DB0 = LSB. Two address Bits A1 and A0 are decoded when an active low write strobe is placed on the WR pin, see Table III. The WR is a level-sensitive input pin, therefore the data setup and data hold times defined in the TIMING SPECIFICATIONS need to be adhered to. ESD Protection Circuits All logic input pins contain back-biased ESD protection Zeners connected to ground (GND). The VREF pins also contain a back-biased ESD protection Zener connected to VDD (see Figure 33). The LDAC pin provides the capability of simultaneously updating all DAC registers with new data from the Input Registers at DIGITAL INPUTS VDD VREFX GND Figure 33. Equivalent ESD Protection Circuits -12- REV. A AD7304/AD7305 APPLICATIONS +5V 10k The AD7304/AD7305 is inherently a 2-quadrant multiplying D/A converter. That is, it can easily be set up for unipolar output operation. The full-scale output polarity is the same as the reference input voltage polarity. -5V < VOUT < +5V REF In some applications it may be necessary to generate the full 4-quadrant multiplying capability or a bipolar output swing. This is easily accomplished using an external true rail-to-rail op amp, such as the OP295. Connecting the external amplifier with two equal value resistors as shown in Figure 34 results in a full 4-quadrant multiplying circuit. In this circuit the amplifier provides a gain of two, which increases the output span magnitude to 10 volts. The transfer equation of this circuit shows that both negative and positive output voltages are created as the input data (D) is incremented from code zero (VOUT = -5 V) to midscale (VOUT = 0 V) to full scale (VOUT = +5 V). VOUT = (D/128 -1) x VREF REV. A 10k (2) -13- AD7304 Figure 34. Four-Quadrant Multiplying Application Circuit AD7304/AD7305 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 20-Lead SOIC (R-20) 16-Lead Wide SOIC (R-16) 0.1043 (2.65) 0.0926 (2.35) 0.0500 (1.27) BSC 0.0192 (0.49) SEATING 0.0138 (0.35) PLANE 1 10 PIN 1 0.0291 (0.74) x 45 0.0098 (0.25) 8 0.0500 (1.27) 0.0125 (0.32) 0 0.0157 (0.40) 0.0091 (0.23) 0.1043 (2.65) 0.0926 (2.35) 8 0.0500 (1.27) 0.0500 0.0192 (0.49) 0 0.0157 (0.40) (1.27) 0.0138 (0.35) SEATING 0.0125 (0.32) PLANE 0.0091 (0.23) BSC 0.0118 (0.30) 0.0040 (0.10) 16-Lead Plastic DIP (N-16) 20-Lead Plastic DIP (N-20) 1.060 (26.90) 0.925 (23.50) 0.840 (21.33) 0.745 (18.93) 16 9 1 8 PIN 1 0.280 (7.11) 0.240 (6.10) 11 1 10 PIN 1 0.022 (0.558) 0.014 (0.356) 16-Lead TSSOP (RU-16) 20 0.015 (0.381) 0.008 (0.204) 0.256 (6.50) 0.246 (6.25) 1 0.006 (0.15) 0.002 (0.05) PIN 1 0.0433 (1.10) MAX 0.0118 (0.30) 0.0075 (0.19) 11 0.177 (4.50) 0.169 (4.30) 9 8 0.0256 SEATING (0.65) PLANE BSC 0.070 (1.77) SEATING 0.045 (1.15) PLANE 0.260 (6.60) 0.252 (6.40) 0.256 (6.50) 0.246 (6.25) 0.177 (4.50) 0.169 (4.30) 0.006 (0.15) 0.002 (0.05) 1 0.100 (2.54) BSC 20-Lead Thin Surface Mount (TSSOP) (RU-20) 0.201 (5.10) 0.193 (4.90) 16 0.325 (8.25) 0.300 (7.62) 0.195 (4.95) 0.115 (2.93) 0.130 (3.30) MIN 0.160 (4.06) 0.115 (2.93) 0.015 (0.381) 0.008 (0.204) 0.070 (1.77) SEATING 0.045 (1.15) PLANE 0.280 (7.11) 0.240 (6.10) 0.060 (1.52) 0.015 (0.38) 0.210 (5.33) MAX 0.130 (3.30) MIN 0.100 (2.54) BSC 20 0.325 (8.25) 0.300 (7.62) 0.195 (4.95) 0.115 (2.93) 0.060 (1.52) 0.015 (0.38) 0.210 (5.33) MAX 0.160 (4.06) 0.115 (2.93) 0.022 (0.558) 0.014 (0.356) 0.0291 (0.74) x 45 0.0098 (0.25) 8 0 0.0079 (0.20) 0.0035 (0.090) 0.028 (0.70) 0.020 (0.50) SEATING PLANE -14- 10 PIN 1 0.0433 (1.10) MAX 0.0256 (0.65) 0.0118 (0.30) BSC 0.0075 (0.19) 8 0 0.0079 (0.20) 0.0035 (0.090) 0.028 (0.70) 0.020 (0.50) REV. A PRINTED IN U.S.A. PIN 1 0.0118 (0.30) 0.0040 (0.10) 11 C3252a-2-2/98 8 20 0.2992 (7.60) 0.2914 (7.40) 1 0.4193 (10.65) 0.3937 (10.00) 9 0.2992 (7.60) 0.2914 (7.40) 16 0.4193 (10.65) 0.3937 (10.00) 0.5118 (13.00) 0.4961 (12.60) 0.4133 (10.50) 0.3977 (10.00)