1
®
FN7385.6
EL5152, EL5153, EL5252, EL5455
270MHz Ultra-Accurate Amplifiers
The EL5152, EL5153, EL5252, and EL5455 are 270MHz,
-3dB bandwidth, voltage mode feedback amplifiers with DC
accuracy of <0.01%, 1mV offsets and 50kV/V open loop
gains. These amplifiers are i deally suited for applications
ranging from precision measurement instrumentation to
high-speed video and monitor app lications demanding
higher linearity at higher frequency. Capable of operating
with as little as 3.0mA of current from a single supply ranging
from 5V to 12V dual supplies ranging from ±2.5V to ±5.0V
these amplifiers are also well suite d for handheld, portable
and battery-powered equipment.
Single amplifiers are of fered in SOT -23 p ackages and duals in
a 10 Ld MSOP package for applications where board sp ace is
critical. Quad amplifiers are available in a 14 Ld SOIC
package. Addi ti onally, singles and duals are available i n th e
industry-standard 8 Ld SOIC. All part s operate over the
industrial temperature ran ge of -40°C to +85°C.
Features
• 270MHz -3dB bandwidth
• 180V/µs slew rate
• ±1mV maximum VOS
• Very high open loop gains 50kV/V
• Low supply current = 3mA
• 105mA output current
• Single supplies from 5V to 12V
• Dual supplies from ±2.5V to ±5V
• Fast disable on the EL5152 and EL5252
• Pb-free available (RoHS co mpliant)
Applications
•Imaging
• Instrumentation
•Video
• Communications devices
Pinouts EL5152
(8 LD SOIC)
TOP VIEW
EL5153
(5 LD SOT-23)
TOP VIEW
EL5252
(10 LD MSOP)
TOP VIEW
EL5455
(14 LD SOIC)
TOP VIEW
1
2
3
4
8
7
6
5
-
+
NC
IN-
IN+
VS-
CE
VS+
OUT
NC
1
2
3
5
4
-+
OUT
VS-
IN+
VS+
IN-
1
2
3
4
10
9
8
7
5 6
-
+
-
+
INA+
CEA
VS-
CEB
INA-
OUTA
VS+
OUTB
INB+ INB-
OUTA
INA-
INA+
VS+
OUTD
IND-
IND+
VS-
INB+ INC+
1
2
3
4
14
13
12
11
5
6
7
10
9
8
INC-
OUTC
INB-
OUTB
-+ -+
-+ -+
Data Sheet March 2, 2009
CAUTION: These devices are sensitive to electrosta tic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2004, 2005, 2007, 2009. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
2FN7385.6
March 2, 2009
Ordering Information
PART NUMBER PART MARKING TEMP. RANGE
(°C) PACKAGE PKG.
DWG. #
EL5152IS 5152IS -40 to +85 8 Ld SOIC MDP0027
EL5152IS-T7* 5152IS -40 to +85 8 Ld SOIC MDP0027
EL5152IS-T13* 5152IS -40 to +85 8 Ld SOIC MDP0027
EL5152ISZ (Note) 5152ISZ -40 to +85 8 Ld SOIC (Pb-free) MDP0027
EL5152ISZ-T7* (Note) 5152ISZ -40 to +85 8 Ld SOIC Tape and Reel (Pb-free) MDP0027
EL5152ISZ-T13* (Note) 5152ISZ -40 to +85 8 Ld SOIC Tape and Reel (Pb-free) MDP0027
EL5153IW-T7* BGAA -40 to +85 5 Ld SOT-23 MDP0038
EL5153IW-T7A* BGAA -40 to +85 5 Ld SOT-23 Tape and Reel MDP0038
EL5153IWZ-T7* (Note) BAAL -40 to +85 5 Ld SOT-23 Tape and Reel (Pb-free) MDP0038
EL5153IWZ-T7A* (Note) BAAL -40 to +85 5 Ld SOT-23 Tape and Reel (Pb-free) MDP0038
EL5252IY BAGAA -40 to +85 10 Ld MSOP MDP0043
EL5252IY-T7* BAGAA -40 to +85 10 Ld MSOP Tape and Reel MDP0043
EL5252IY-T13* BAGAA -40 to +85 10 Ld MSOP Tape and Reel MDP0043
EL5455IS 5455IS -40 to +85 14 Ld SOIC MDP0027
EL5455IS-T7* 5455IS -40 to +85 14 Ld SOIC Tape and Reel MDP0027
EL5455IS-T13* 5455IS -40 to +85 14 Ld SOIC Tape and Reel MDP0027
EL5455ISZ (Note) 5455ISZ -40 to +85 14 Ld SOIC (Pb-free) MDP0027
EL5455ISZ-T7* (Note) 5455ISZ -40 to +85 14 Ld SOIC Tape and Reel (Pb-free) MDP0027
EL5455ISZ-T13* (Note) 5455ISZ -40 to +85 14 Ld SOIC Tape and Reel (Pb-free) MDP0027
*Please refer to TB347 for details on reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100%
matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
EL5152, EL5153, EL5252, EL5455
3FN7385.6
March 2, 2009
Absolute Maximum Ratings (TA = +25°C) Thermal Information
Supply Voltage between VS and GND. . . . . . . . . . . . . . . . . . . 13.2V
Maximum Continuous Output Current . . . . . . . . . . . . . . . . . . . 50mA
Current into IN+, IN-, CE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA
Pin Voltages. . . . . . . . . . . . . . . . . . . . . . . . . GND -0.5V to VS +0.5V
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+125°C
Storage Temperature. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Ambient Operating Temperature . . . . . . . . . . . . . . . .-40°C to +85°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests
are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications VS+ = +5V, VS- = ±5V, RF = RG = 750Ω, RL = 150Ω, TA = +25°C, Unless Otherwise Specified.
PARAMETER DESCRIPTION CONDITIONS MIN TYP MAX UNIT
AC PERFORMANCE
BW -3dB Bandwidth AV = +1, RL = 500Ω, CL = 5.0pF 270 MHz
AV = +2, RL = 150Ω85 MHz
GBWP Gain Bandwidth Product RL = 150Ω165 MHz
BW1 0.1dB Bandwidth AV = +1, RL = 500Ω50 MHz
SR Slew Rate VO = -3V to +3V, AV = +2 120 155 V/µs
VO = -3V to +3V, AV = 1, RL = 500Ω180 V/µs
tS0.1% Settling Time VOUT = -1V to +1V, AV = +2 30 ns
dG Differential Gain Error AV = +2, RL = 150Ω0.06 %
dP Differential Phase Error AV = +2, RL = 150Ω0.045 °
VNInput Referred Voltage Noise 12 nV/√Hz
INInput Referred Current Noise 1.8 pA/√Hz
DC PERFORMANCE
VOS Offset Voltage -1 0.5 1 mV
TCVOS Input Offset Voltage Temperature
Coefficient Measured from TMIN to TMAX -2 µV/°C
AVOL Open Loop Gain VO is from -2.5V to 2.5V (EL5152 & EL5153) 10 20 kV/V
VO is from -2.5V to 2.5V (EL5252 & EL5455) 15 50 kV/V
INPUT CHARACTERISTICS
CMIR Common Mode Input Range Guaranteed by CMRR test -2.5 2.5 V
CMRR Common Mode Rejection Ratio VCM = 2.5 to -2.5 85 110 dB
IBBias Current -0.4 0.12 +0.6 µA
IOS Input Offset Current -80 12 80 nA
RIN Input Resistance 25 60 MΩ
CIN Input Capacitance 1pF
OUTPUT CHARACTERISTICS
VOUT Output Voltage Swing RL = 150Ω to GND ±3.0 ±3.3 V
RL = 500Ω to GND ±3.4 ±3.7 V
IOUT Output Current RL = 10Ω to GND 60 105 mA
EL5152, EL5153, EL5252, EL5455
4FN7385.6
March 2, 2009
ENABLE (SELECTED PACKAGES ONLY)
tEN Enable Time 200 ns
tDIS Disable Time 300 ns
IIHCE CE Pin Input High Current CE = VS+0-1µA
IILCE CE Pin Input Low Current CE = VS- 5 13 25 µA
VIHCE CE Input High Voltage for Power-d own VS+ -1 V
VILCE CE Input Low Voltage for Power-up VS+ -3 V
SUPPLY
ISON Supply Current - Enabled (per amplifier) No load, VIN = 0V, CE = +5V 2.46 3.0 3.43 mA
ISOFF Supply Current - Disabled (per amplifier) No load, VIN = 0V, CE = 5V 5 13 25 µA
PSRR Power Supply Rejection Ratio DC, VS = ±3.0V to ±6.0V (EL5152 & EL5153) 85 1 16 dB
DC, VS = ±3.0V to ±6.0V (EL5252 & EL5455) 80 95 dB
Electrical Specifications VS+ = +5V, VS- = ±5V, RF = RG = 750Ω, RL = 150Ω, TA = +25°C, Unless Otherwise Specified. (Continued)
PARAMETER DESCRIPTION CONDITIONS MIN TYP MAX UNIT
Typical Performance Curves
FIGURE 1. EL5152 SMALL SIGNAL FREQUENCY FOR
VARIOUS GAINS FIGURE 2. EL5152 SMALL SIGNAL FREQUENCY PHASE
FOR VARIOUS GAINS
FIGURE 3. FREQUENCY RESPONSE FOR VARIOUS RLFIGURE 4. FREQUENCY RESPONSE FOR VARIOUS CL
NORMALIZED GAIN (dB)
100k 1M 10M 500M
FREQUENCY (Hz)
100M
SUPPLY = ±5.0V
INPUT = -30dBm = 20mV
RL = 500Ω
CL = 5pF
AV = +1
AV = +5
AV = +2
3
1
-1
-3
-5
4
2
0
-2
-4
-6
PHASE (°)
60
0
-60
-120
-180
90
30
-30
-90
-150
100k 1M 10M 500M
FREQUENCY (Hz)
100M
SUPPLY = ±5.0V
INPUT = -30dBm = 20mV
RL = 500Ω
CL = 5pF
-210
AV = +5
AV = +2
AV = +1
NORMALIZED GAIN (dB)
4
2
0
-2
-4
5
3
1
-1
-3
100k 1M 10M 500M
FREQUENCY (Hz)
100M
CL = 5pF
AV = +1
10Ω
50Ω
150Ω
500Ω
-5
NORMALIZED GAIN (dB)
4
2
0
-2
-4
5
3
1
-1
-3
100k 1M 10M 500M
FREQUENCY (Hz)
100M
AV = +1
RL = 500Ω10pF
12pF
4.7pF
3.3pF
2.2pF
1pF
-5
NO CL
EL5152, EL5153, EL5252, EL5455
5FN7385.6
March 2, 2009
FIGURE 5. FREQUENCY RESPONSE FOR VARIOUS RLFIGURE 6. FREQUENCY RESPONSE FOR VARIOUS CL
FIGURE 7. FREQUENCY RESPONSE FOR VARIOUS RLFIGURE 8. FREQUENCY RESPONSE FOR VARIOUS CL
FIGURE 9. FREQUENCY RESPONSE FOR
VARIOUS CIN
FIGURE 10. FREQUENCY RESPONSE vs RF/RG
Typical Performance Curves (Continued)
NORMALIZED GAIN (dB)
3
1
-1
-3
-5
4
2
0
-2
-4
100k 1M 10M 800M
FREQUENCY (Hz)
100M
AV = +2
CL = 5pF
RF = 500Ω
50Ω
100Ω
200Ω
250Ω
500Ω
-6
NORMALIZED GAIN (dB)
4
2
0
-2
-4
5
3
1
-1
-3
100k 1M 10M 500M
FREQUENCY (Hz)
100M
AV = +2
RL = 500Ω
RF = 500Ω
22pF
18pF
12pF
4.7pF
2.7pF
-5
NORMALIZED GAIN (dB)
3
1
-1
-3
-5
4
2
0
-2
-4
100k 1M 10M
FREQUENCY (Hz)
100M
50Ω
200Ω
500Ω
250Ω
-6
AV = +5
CL = 5pF
RF = 102Ω
NORMALIZED GAIN (dB)
3
1
-1
-3
-5
4
2
0
-2
-4
100k 1M 10M 500M
FREQUENCY (Hz)
100M
RL = 500Ω
AV = +5
RF = 102Ω
87pF
68pF
50pF
39pF
27pF
18pF
-6
NORMALIZED GAIN (dB)
4
2
0
-2
-4
5
3
1
-1
-3
100k 1M 10M 500M
FREQUENCY (Hz)
100M
RL = 150Ω
AV = +2
RF = 500Ω
4.7pF
3.3pF
3.2pF
1pF
-5
NORMALIZED GAIN (dB)
4
2
0
-2
-4
5
3
1
-1
-3
100k 1M 10M 500M
FREQUENCY (Hz)
100M
RL = 500Ω
CL = 5pF
AV = +2
RF = RG =
1000Ω
1500Ω
750Ω
500Ω
-5
EL5152, EL5153, EL5252, EL5455
6FN7385.6
March 2, 2009
FIGURE 11. FREQUENCY RESPONSE FOR VARIOUS CIN FIGURE 12. FREQUENCY RESPONSE FOR V ARIOUS POWER
SUPPLY
FIGURE 13. PSRR FIGURE 14. CMRR FOR VARIOUS POWER SUPPLY VALUES
FIGURE 15. OUTPUT IMPEDANCE FIGURE 16. ENABLE/DISABLE RESPONSE
Typical Performance Curves (Continued)
NORMALIZED GAIN (dB)
-4
-2
0
-2
-4
-5
-3
-1
-1
-3
100k 1M 10M 300M
FREQUENCY (Hz)
100M
RL = 500Ω
AV = +5
RF = 102Ω
-5
0pF
22pF
34pF
NORMALIZED GAIN (dB)
4
2
0
-2
-4
5
3
1
-1
-3
100k 1M 10M 500M
FREQUENCY (Hz)
100M
SUPPLY = ±5.0V
RL = 500Ω
AV = +2
RF = 500Ω
±2.0V
±3.0V
±4.0V
±5.0V
-5
10k 100k 100M
FREQUENCY (Hz)
1k 10M
1M
-70
-60
-50
-40
-30
-20
-10
0
PSRR (dB)
-80
-90
-100
AV = +1
CMRR (dB)
-40
-60
-80
-100
-120
-30
-50
-70
-90
-110
100 1k 100k 100M
FREQUENCY (Hz)
10k 10M1M
-130
±2.5
±3.0
±5.0
10k100k100M
FREQUENCY (Hz)
1k10M
1M
1
10
100
1000
OUTPUT IMPEDANCE (
Ω
)
0.01
0.001
A
V
= +1
TIME (400ns/DIV)
CH 2
CH 1
216ns
ENABLE
328ns
DISABLE
AV = +1
RL = 500Ω
CL = 0
EL5152, EL5153, EL5252, EL5455
7FN7385.6
March 2, 2009
FIGURE 17. RISE TIME - LARGE SIGNAL RESPONSE FIGURE 18. FALL TIME - LARGE SIGNAL RESPONSE
FIGURE 19. RISE TIME - SMALL SIGNAL RESPONSE FIGURE 20. FALL TIME - SMALL SIGNAL RESPONSE
FIGURE 21. EL5152 SMALL SIGNAL OPEN LOOP GAIN vs
FREQUENCY INVERTING FIGURE 22. EL5252 SMALL SIGNAL FREQUENCY vs
CROSSTALK
Typical Performance Curves (Continued)
VOLTAGE (500mV/DIV)
TIME (4ns/DIV)
AV = +1
RL = 500Ω
CL = 5pF
0V
VOLTAGE (500mV/DIV)
TIME (4ns/DIV)
AV = +1
RL = 500Ω
CL = 5pF
0V
TIME (2ns/DIV)
VOLTAGE (100mV/DIV)
AV = +1
RL = 500Ω
CL = 5pF
0V
TIME (2ns/DIV)
VOLTAGE (100mV/DIV)
AV = +1
RL = 500Ω
CL = 5pF
0V
10k100k100M
FREQUENCY (Hz)
1k10M
1M
GAIN (dB)
PHASE (°)
500M
80
60
40
20
0
90
70
50
30
10
-10
-45
0
45
90
135
180
GAIN
PHASE
CROSSTALK (dB)
-20
-40
-60
-80
-10
-30
-50
-70
-90
100k 1M 10M 1G
FREQUENCY (Hz)
100M
AV = +1
RL = 500Ω
CL = 0pF
-100
IN #2
OUT #1
IN #1
OUT #2
EL5152, EL5153, EL5252, EL5455
8FN7385.6
March 2, 2009
FIGURE 23. SUPPLY CURRENT vs SUPPLY VOLTAGE FIGURE 24. FREQUENCY RESPONSE FOR VARIOUS
VOLTAGE SUPPLY LEVELS
FIGURE 25. EL5252 SMALL SIGNAL FREQUENCY - CHANNEL TO CHANNEL
FIGURE 26. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
FIGURE 27. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
Typical Performance Curves (Continued)
0
2
3
4
5
6
7
±1 ±1.5 ±2.5 ±3 ±3.5 ±4 ±4.5 ±5
VOLTAGE (V)
SUPPLY CURRENT (mA)
±2
1
AV = +2
RL = 500Ω
CL = 5pF
NORMALIZED GAIN (dB)
3
1
-1
-3
-5
4
2
0
-2
-4
100k 1M 10M 800M
FREQUENCY (Hz)
100M
RL = 500Ω
CL = 0pF
-6
±2.0V
±3.0V
±4.0V
±5.0V
NORMALIZED GAIN (dB)
4
2
0
-2
-4
5
3
1
-1
-3
100K 1M 10M 1G
FREQUENCY (Hz)
100M
AV = +1
RL = 500Ω
CL = 0pF
-5
CHANNEL #1
CHANNEL #2
1.136W
909mW
SO14
θJA = 88°C/W
1.4
1.2
1
0.8
0.6
0.2
00 255075100 150
AMBIENT TEMPERATURE (°C)
POWER DISSIPATION (W)
12585
JEDEC JESD51-7 HIGH EFFECTIVE
THERMAL CONDUCTIVITY TEST BOARD
0.4 435mW
870mW
0.9 SO8
θJA = 110°C/W
MSOP8/10
θJA = 115°C/W
SOT23-5/6
θJA = 230°C/W
833mW
625mW θJA = 160°C/W
SO8
θJA = 120°C/W
SO14
1
0.9
0.8
0.6
0.4
0.1
00 255075100 150
AMBIENT TEMPERATURE (°C)
POWER DISSIPATION (W)
12585
JEDEC JESD51-3 LOW EFFECTIVE
THERMAL CONDUCTIVITY TEST BOARD
0.2
0.7
0.3
0.5
391mW
θ
JA
= 256°C/W
SOT23-5/6
486mW
θJA = 206°C/W
MSOP8/10
EL5152, EL5153, EL5252, EL5455
9FN7385.6
March 2, 2009
EL5152 Product Description
The EL5152, EL5153, EL5252, and EL5455 are wide
bandwidth, low power, low offset voltage feedback
operational amplifiers capable of operating from a single or
dual power supplies. This family of operational amplifiers are
internally compensated for closed loop gain of +1 or greater .
Connected in voltage follower mode, driving a 500Ω load
members of this amplifier family demonstrate a -3dB
bandwidth of about 270MHz. With the loading set to
accommodate typical video application, 150Ω load and gain
set to +2, bandwidth reduces to about 180MHz with a
600V/µs slew rate. Power down pins on the EL5152 and
EL5252 reduce the already low power demands of this
amplifier family to 17µA typical while the amplifier is
disabled.
Input, Output and Supply Voltage Range
The EL5152 and EL5153 families have been designed to
operate with supply voltage ranging from 5V to 12V. Supply
voltages range from ±2.5V to ±5V for split supply operati on.
Of course split supply operation can easily be achieved
using single supplies by splitting off half of the single supply
with a simple voltage divider as illustrated in the application
circuit section.
Input Common Mode Range
These amplifiers have an input common mode voltage
ranging from 1.5V above the negative supply (VS- pin) to
1.5V below the positive supply (VS+ pin). If the input signal is
driven beyond this range the output signal will exhibit
distortion.
Maximum Output Swing & Load Resistance
The outputs of the EL5152 and EL5153 families maximum
output swing ranges from -4V to 4V for VS = ±5V with a load
resistance of 500Ω. Naturally, as the load resistance
becomes lower, the output swin g lowers accordingly; for
instance, if the load resistor is 150Ω, the output swing
ranges from -3.5V to 3.5V. This response is a simple
application of Ohms law indicating a lower value resistance
results in greater current demands of the amplifier.
Additionally, the load resistance affects the frequency
response of this family as well as all operational amplifiers,
as clearly indicated by the Gain vs Frequency for V arious RL
curves clearly indicate. In the case of the frequency
response reduced bandwidth with decreasing load
resistance is a function of load resistance in conjunction with
the output zero response of the amplifier.
Choosing a Feedback Resistor
A feedback resistor is required to achieve unity gain; simply
short the output pin to the inverting input pin. Gains greater
than +1 require a feedback and gain resistor to set the
desired gain. This gets interesting because the feedback
resistor forms a pole with the parasitic capacitance at the
inverting input. As the feedback resistance increases the
position of the pole shifts in the frequency domain, the
amplifier's phase margin is reduced and the amplifier
becomes less stable. Peaking in the frequency domain and
ringing in the time domain are symptomatic of this shift in
pole location. So we want to keep the feedback resistor as
small as possible. You may want to use a large feedback
resistor for some reason; in this case to compensate the shift
of the pole and maintain stability a small capacitor in the few
Pico farad range in parallel with the feedback resistor is
recommended.
For the gains greater than unity, it has been determined a
feedback resistance ranging from 500Ω to 750Ω provides
optimal response.
Gain Bandwidth Product
The EL5156 and EL5157 families have a gain bandwidth
product of 210MHz for a gain of +5. Bandwidth can be
predicted by the following Equatio n 1:
Video Performance
For good video performance, an amplifier is required to
maintain the same output impedance and same frequency
response as DC levels are changed at the output; this
characteristic is widely referred to as “diffgain-diffphase”.
Many amplifiers have a difficult time with this especially while
driving standard video loads of 150Ω, as the output current
has a natural tendency to change with DC level. The EL5152
dG and dP for these families is a respectable 0.006% and
0.04%, while driving 150Ω at a gain of 2. Driving high
impedance loads would give a similar or better dG and dP
performance as the current output demands placed on the
amplifier lessen with incre ased load.
Driving Capacitive Loads
The EL5152 and EL5153 families can easily drive capacitive
loads as demanding as 27pF in parallel with 500Ω while
holding peaking to within 5dB of peaking at unity gain. Of
course if less peaking is desired, a small series resistor
(usually between 5Ω to 50Ω) can be placed in series with the
output to eliminate most peaking. However, there will be a
small sacrifice of gain which can be recovered by simply
adjusting the value of the gain resistor.
Driving Cables
Both ends of all cables must always be properly terminated;
double termination is absolutely necessary for reflection-free
performance. Additionally, a back-termination series resistor
at the amplifier's output will isolate the amplifier from the
cable and allow extensive capacitive drive. However, other
applications may have high capacitive loads without a back-
termination resistor. Again, a small series resistor at the
output can help to reduce peaking.
Gain BW GainBandwidthProduct=×(EQ. 1
)
EL5152, EL5153, EL5252, EL5455
10 FN7385.6
March 2, 2009
Disable/Power-Down
The EL5152 and EL5253 can be disabled with their output
placed in a high impedance state. The turn off time is about
330ns and the turn on time is about 130ns. When disabled,
the amplifier's supply current is reduced to 17µA typically;
essentially eliminating power consumption. The amplifier's
power down is controlled by standard TTL or CMOS signal
levels at the ENABLE pin. The applied logic signal is relative
to VS- pin. Letting the ENABLE pin float or the application of
a signal that is less than 0.8V above VS- enables the
amplifier. The amplifie r is disabled when the signal at
ENABLE pin is above VS+ - 1.5V.
Output Drive Capability
The EL5152 and EL5153 familie s do not have internal short
circuit protection circuitry. Typically, short circuit currents as
high as 95mA and 70mA can be expected and naturally, if
the output is shorted indefini tely the part can easily be
damaged from overheating, or excessive current density
may eventually compromise metal integrity. Maximum
reliability is maintained if the output current is always held
below ±40mA. This limit is set and limited by the design of
the internal metal interconnect. Note that in transient
applications, the part is extremely robust.
Power Dissipation
With the high output drive capability of the EL5152 and
EL5153 families, it is possible to exceed the +125°C
absolute maximum junction temperature under certain load
current conditions. Therefore, it is important to calculate the
maximum junction temperature for an application to
determine if load conditions or package types need to be
modified to assure operation of the amplifier in a safe
operating area.
The maximum power dissipation allowed in a package is
determined according to Equation 2:
Where:
TJMAX = Maximum junction temperature
TAMAX = Maximum ambient temperature
θJA = Thermal resistance of the p ackage
The maximum power dissipation actually produced by an IC
is the total quiescent supply current times the total power
supply voltage, plus the power in the IC due to the load, or:
For sourcing:
For sinking:
Where:
VS = Supply voltage
ISMAX = Maximum quiescent supply current
VOUT = Maximum output voltage of the application
RLOAD = Load resistance tied to ground
ILOAD = Load current
N = number of amplifiers (Max = 2)
By setting the two PDMAX equations equal to each other , we
can solve the output current and RLOAD to avoid the device
overheat.
Power Supply Bypassing Printed Circuit Board
Layout
As with any high frequency device, a good printed circuit
board layout is necessary for optimum performance. Lead
lengths should be as short as possi ble. The power supply
pin must be well bypassed to reduce the risk of oscillation.
For normal single supply operation, where the VS- pin is
connected to the ground plane, a sing le 4.7µF tantalum
capacitor in parallel with a 0.1µF ceramic capacitor from VS+
to GND will suffice. This same capacitor combination should
be placed at each supply pin to ground if split supplies are to
be used. In this case, the VS- pin becomes the negative
supply rail. See Figure 1 for a complete tuned power supply
bypass methodology.
Printed Circuit Board Layout
For good AC performance, parasitic capacitance should be
kept to minimum. Use of wire wound resistors should be
avoided because of their additi onal series inductance. Use
of sockets should also be avoided if possible. Sockets add
parasitic inductance and capacitance that can result in
compromised performance. Minimizing parasitic capacitance
at the amplifier's inverting input pin is very im portant. The
feedback resistor should be placed very close to the
inverting input pin. S trip line design techniques are
recommended for the signal traces.
PDMAX TJMAX TAMAX
–
ΘJA
---------------------------------------------
=(EQ. 2)
PDMAX VSISMAX VSVOUTi
–()
i1=
n
∑VOUTi
RLi
-----------------
×+×=(EQ. 3)
PDMAX VSISMAX VOUTi VS
–()
i1=
n
∑ILOADi
×+×=(EQ. 4)
EL5152, EL5153, EL5252, EL5455
11 FN7385.6
March 2, 2009
Application Circuits
Sullen Key Low Pass Filter
A common and easy to implement filter taking advantage of
the wide bandwidth, low offset and low power demands of
the EL5152. A derivation of the transfer function is provid ed
for convenience . (See Fi gu re 28.)
Sullen Key High Pass Filter
Again this useful filter benefits from the characteristics of the
EL5152. The transfer function is very similar to the low pass
so only the results are presented. (See Figure 29.)
FIGURE 28. SULLEN KEY LOW PASS FILTER
K3 1
Q
RC
1
wo
KHolp
CR CR
CR CR
CR CR
)K1(
1
Q
CRCR 1
wo
KHolp )CRCRCR)K1((jwCRCRw1 1
)jw(H
1s)CRCRCR)K1((sCRCR K
)s(H
0
sC1ViVo
RVKVo
1
RViV
V
1sCR 1
KVo
R
R
1K
11 22
12 21
22 11
2211
2221112211
2
2212111
2
2211
1
21
1
1
1
22
A
B
−
=
=
=
++−
=
=
=
++−+−
=
+++−+
=
=
−
+
−
+
−
+
=
+=
Equations simplify if we let all
components be equal R = C
+
-
1n
5V
V2
C1
R1 R2
V1
1k
C2
RA 1k
1k
RB
5V
V3
R7 1k
VOUT
1
3
2V+
V-
4
U1A
1n
1n
1k
11
L1
10µH
C6
1n
C3
R5
1k
1n
C5
L3
10µH
1n
C4
R6
1k
EL5152, EL5153, EL5252, EL5455
12 FN7385.6
March 2, 2009
Differe ntial Output Instrumentation Amplifier
The addition of a third amplifier to the conventional three
amplifier Instrumentation Amplifier introduces the benefits of
differential signal realization, specifically the advantage of
using common mode rejection to remove coupled noise and
ground-potential errors inherent in remote transmission. This
configuration also provide s en hanced bandwidth, wider
output swing and faster slew rate than conventional three
amplifier solutions with only the cost of an additional
amplifier and few resistors.
FIGURE 29. SULLEN KEY HIGH PASS FILTER
K4 2
Q
RC
2
wo
K4K
Holp
CR CR
CR CR
CR CR
)K1(
1
Q
CRCR 1
wo
KHolp
11 22
12 21
22 11
2211
−
=
=
−
=
++−
=
=
=
Equations simplify if we let
all components be equal R = C
+
-
1n
5V
V2
C9
R8
V1
1k
C2
RA 1k
1k
RB
5V
V3
R7 1k
VOUT
1
3
2V+
V-
4
U1A
1n
1n 11
L1
10µH
C6
1n
C3
R5
1k
1n
C5
L3
10µH
1n
C4
R6
1k
C7
1n
+
-
-
+
-
+
+
-
eo
eo4
eo3
REF
R3
R3
R3
R3
R3
R3
R2
R2
RG
A2
e2
A4
A3
R3
R3
A1
e1
+
-
eo3 12R
2RG
⁄+()e1e2
–()–= eo4 12R
2RG
⁄+()e1e2
–()=
eo21 2R
2RG
⁄+()e1e2
–()–=
BW 2fC1 2,
ADi
------------------
=ADi 21 2R
2RG
⁄+()–=
EL5152, EL5153, EL5252, EL5455
13 FN7385.6
March 2, 2009
Strain Gauge
The strain gauge is an ideal application to take advantage of
the moderate bandwi dth and hi gh accuracy of the EL5152.
The operation of the circuit is very straight forward. As the
strain variable component resistor in the balanced bridge is
subjected to increasing strain its resistance changes
resulting in an imbalance in the bridge. A voltage variation
from the referenced high accuracy source is generated and
translated to the difference amplifier through the buffer
stage. This voltage difference as a function of the strain is
converted into an output voltage.
+
-
5V
V2
22 R17
1k
1k
RF
5V
V4
RL 1k
VOUT (V1+V2+V3+V4)
1
3
2V+
V-
4
U1A
22
11
R18
1k
1k
R15
V5 1k
0V
VARIABLE SUBJECT TO STRAIN
R16 1k
R14
4
4
1n
L4
10µH
C6
1n
C3
R5
1k
1k
1n
C12
1n
C11
R11
1k
L1
10µH
EL5152, EL5153, EL5252, EL5455
14 FN7385.6
March 2, 2009
EL5152, EL5153, EL5252, EL5455
Small Outline Package Family (SO)
GAUGE
PLANE
A2
A1 L
L1
DETAIL X 4° ±4°
SEATING
PLANE
eH
b
C
0.010 BMCA
0.004 C
0.010 BMCA
B
D
(N/2)
1
E1
E
NN (N/2)+1
A
PIN #1
I.D. MARK
h X 45°
A
SEE DETAIL “X”
c
0.010
MDP0027
SMALL OUTLINE PACKAGE FAMILY (SO)
SYMBOL
INCHES
TOLERANCE NOTESSO-8 SO-14
SO16
(0.150”)
SO16 (0.300”)
(SOL-16)
SO20
(SOL-20)
SO24
(SOL-24)
SO28
(SOL-28)
A 0.068 0.068 0.068 0.104 0.104 0.104 0.104 MAX -
A1 0.006 0.006 0.006 0.007 0.007 0.007 0.007 ±0.003 -
A2 0.057 0.057 0.057 0.092 0.092 0.092 0.092 ±0.002 -
b 0.017 0.017 0.017 0.017 0.017 0.017 0.017 ±0.003 -
c 0.009 0.009 0.009 0.011 0.011 0.011 0.011 ±0.001 -
D 0.193 0.341 0.390 0.406 0.504 0.606 0.704 ±0.004 1, 3
E 0.236 0.236 0.236 0.406 0.406 0.406 0.406 ±0.008 -
E1 0.154 0.154 0.154 0.295 0.295 0.295 0.295 ±0.004 2, 3
e 0.050 0.050 0.050 0.050 0.050 0.050 0.050 Basic -
L 0.025 0.025 0.025 0.030 0.030 0.030 0.030 ±0.009 -
L1 0.041 0.041 0.041 0.056 0.056 0.056 0.056 Basic -
h 0.013 0.013 0.013 0.020 0.020 0.020 0.020 Reference -
N 8 14 16 16 20 24 28 Reference -
Rev. M 2/07
NOTES:
1. Plastic or metal protrusions of 0.006” maximum per side are not included.
2. Plastic interlead protrusions of 0.010” maximum per side are not included.
3. Dimensions “D” and “E1” are measured at Datum Plane “H”.
4. Dimensioning and tolerancing per ASME Y14.5M-1994
15 FN7385.6
March 2, 2009
EL5152, EL5153, EL5252, EL5455
SOT-23 Package Family
e1
N
A
D
E
4
321
E1
0.15 DC
2X 0.20 C
2X
e
B0.20 MDC A-B
b
NX
6
2 3
5
SEATING
PLANE
0.10 C
NX
1 3
C
D
0.15 A-BC
2X
A2
A1
H
c
(L1)
L
0.25
0° +3°
-0°
GAUGE
PLANE
A
MDP0038
SOT-23 PACKAGE FAMILY
SYMBOL
MILLIMETERS
TOLERANCESOT23-5 SOT23-6
A 1.45 1.45 MAX
A1 0.10 0.10 ±0.05
A2 1.14 1.14 ±0.15
b 0.40 0.40 ±0.05
c 0.14 0.14 ±0.06
D 2.90 2.90 Basic
E 2.80 2.80 Basic
E1 1.60 1.60 Basic
e 0.95 0.95 Basic
e1 1.90 1.90 Basic
L 0.45 0.45 ±0.10
L1 0.60 0.60 Reference
N 5 6 Reference
Rev. F 2/07
NOTES:
1. Plastic or metal protrusions of 0.25mm maximum per side are not
included.
2. Plastic interlead protrusions of 0.25mm maximum per side are not
included.
3. This dimension is measured at Datum Plane “H”.
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
5. Index area - Pin #1 I.D. will be located within the indicated zone
(SOT23-6 only).
6. SOT23-5 version has no center lead (shown as a dashed line).
16
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No lice nse is gran t ed by i mpli catio n or other wise u nder an y p a tent or patent rights of Intersi l or i t s sub sidi ari es.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN7385.6
March 2, 2009
EL5152, EL5153, EL5252, EL5455
Mini SO Package Family (MSOP)
1(N/2)
(N/2)+1
N
PLANE
SEATING
N LEADS
0.10 C
PIN #1
I.D.
E1E
b
DETAIL X
3° ±3°
GAUGE
PLANE
SEE DETAIL "X"
c
A
0.25
A2
A1 L
0.25 C A B
D
A
M
B
e
C
0.08 C A B
M
H
L1
MDP0043
MINI SO PACKAGE FAMILY
SYMBOL
MILLIMETERS
TOLERANCE NOTESMSOP8 MSOP10
A1.101.10 Max. -
A1 0.10 0.10 ±0.05 -
A2 0.86 0.86 ±0.09 -
b 0.33 0.23 +0.07/-0.08 -
c0.180.18 ±0.05 -
D 3.00 3.00 ±0.10 1, 3
E4.904.90 ±0.15 -
E1 3.00 3.00 ±0.10 2, 3
e0.650.50 Basic -
L0.550.55 ±0.15 -
L1 0.95 0.95 Basic -
N 8 10 Reference -
Rev. D 2/07
NOTES:
1. Plastic or metal protrusions of 0.15mm maximum per side are not
included.
2. Plastic interlead protrusions of 0.25mm maximum per side are
not included.
3. Dimensions “D” and “E1” are measured at Datum Plane “H”.
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
