VDD
CSS
CIN
COUT
VIN
FB
SW
SS
AGND
POS
NEG
SHDN FREQ
LM3310
VC
D3
D2
D1VOUT
L
RFB1
RFB2
VIN
RC
PGND
OUT
VDPM
VGHM
VFLK
CERE
VGH
RECE
AVIN
C1 C2
R1
R2
CC
VOUT
= 2 X
VOH
LM3310
www.ti.com
SNVS341E –AUGUST 2005–REVISED MAY 2013
LM3310 Step-Up PWM DC/DC Converter with Integrated Op-Amp and Gate Pulse
Modulation Switch
Check for Samples: LM3310
1FEATURES DESCRIPTION
The LM3310 is a step-up DC/DC converter integrated
2• Boost Converter with a 2A, 0.18ΩSwitch with an Operational Amplifier and a gate pulse
• Boost Output Voltage Adjustable up to 20V modulation switch. The boost (step-up) converter is
• Operating Voltage Range of 2.5V to 7V used to generate an adjustable output voltage and
features a low RDSON internal switch for maximum
• 660kHz/1.28MHz Pin Selectable Switching efficiency. The operating frequency is selectable
Frequency between 660kHz and 1.28MHz allowing for the use of
• Adjustable Soft-Start Function small external components. An external soft-start pin
• Input Undervoltage Protection enables the user to tailor the soft-start time to a
specific application and limit the inrush current. The
• Over Temperature Protection Op-Amp is capable of sourcing/sinking 135mA of
• Integrated Op-Amp current (typical). The gate pulse modulation switch
• Integrated Gate Pulse Modulation (GPM) can operate with a VGH voltage of 5V to 30V. The
Switch LM3310 is available in a low profile 24-lead WQFN
package.
• 24-Lead WQFN Package
APPLICATIONS
• TFT Bias Supplies
• Portable Applications
Typical Application Circuit
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2005–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
NC
VGHM
VFLK
NEG
VDPM
POS
AGND
VDD
NC
AVIN
OUT
SW
VIN
VC
12
11
10
9
8
7
13
14
18
17
16
15
1
2
3
4
5
6
21
22
23
24
NC
SS
NC
FREQ
LM3310
19
20
PGND
RE
CE
VGH
SHDN
FB
LM3310
SNVS341E –AUGUST 2005–REVISED MAY 2013
www.ti.com
Connection Diagram
Top View
Figure 1. WQFN-24 Package
See Package Number RTW0024A
θJA=37°C/W
Pin Descriptions
Pin Name Function
1 NC Not internally connected. Leave pin open.
2 VGHM Output of GPM circuit. This output directly drives the supply for the gate driver circuits.
3 VFLK Determines when the TFT LCD is on or off. This is controlled by the timing controller in the LCD
module.
4 VDPM VDPM pin is the enable signal for the GPM block. Pulling this pin high enables the GPM while
pulling this pin low disables it. VDPM is used for timing sequence control.
5 VDD Reference input for gate pulse modulation (GPM) circuit. The voltage at VDD is used to set the lower
VGHM voltage. If the GPM function is not used connect VDD to VIN.
6 AVIN Op-Amp analog power input.
7 OUT Output of the Op-Amp.
8 NEG Negative input terminal of the Op-Amp.
9 POS Positive input terminal of the Op-Amp.
10 AGND Analog ground for the step-up regulator, LDO, and Op-Amp. Connect directly to DAP and PGND
beneath the device.
11 NC Not internally connected. Leave pin open.
12 NC Not internally connected. Leave pin open.
13 NC Not internally connected. Leave pin open.
14 SS Boost converter soft start pin.
15 VCBoost compensation network connection. Connected to the output of the voltage error amplifier.
16 FREQ Switching frequency select input. Connect this pin to VIN for 1.28MHz operation and AGND for
660kHz operation.
17 VIN Boost converter and GPM power input.
18 SW Boost power switch input. Switch connected between SW pin and PGND pin.
19 SHDN Shutdown pin. Active low, pulling this pin low disable the LM3310.
20 FB Boost output voltage feedback input.
21 PGND Power Ground. Source connection of the step-up regulator NMOS switch and ground for the GPM
circuit. Connect AGND and PGND directly to the DAP beneath the device.
2Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated
Product Folder Links: LM3310
Boost Converter
+
-
+
-
+
-
+
-R
S
Q
Current
Sense
osc
+
-
Softstart
Bandgap
+
-
BG
REF
DREF
VIN
BG
TREF
BG
PWM
Comp
EAMP
LLcomp
Dcomp
Driver
N1
UVP
Comp
TSD
Comp
Reset
UVP REF
20
15
21
18
19
350 k:
17
VIN
16
14
PGND
10
AGND
AGND PGND
SHDN
FB
VC
VIN FREQ
SW
SS
ISS
VIN
LM3310
www.ti.com
SNVS341E –AUGUST 2005–REVISED MAY 2013
Pin Descriptions (continued)
Pin Name Function
22 CE Connect capacitor from this pin to AGND.
23 RE Connect a resistor between RE and PGND.
24 VGH GPM power supply input. VGH range is 5V to 30V.
DAP Die Attach Pad. Internally connected to GND. Connect AGND and PGND pins directly to this pad
beneath the device.
Block Diagrams
Figure 2.
Copyright © 2005–2013, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Links: LM3310
+
-
10
AGND
7
6
9
8
OUT
POS
NEG
AV IN
Reset
Op-Amp
+
-
x
BG
+
-
Reset
BG
AGND
AGND
PGND
10
AGND
AGND 21
PGND
PGND
24
2
23
4
22
3
5
VDD
VGH
VGHM
RE
VDPM
CE
VFLK
PGND
PGND
350 k:
350 k:
1 k:
9R
R
AGND
CE
P2
P3
N2
N3
AGND
2x or 3x Charge
Pump
PGND
R1
R2
RE
VIN
ICE
GPM Block
LM3310
SNVS341E –AUGUST 2005–REVISED MAY 2013
www.ti.com
Figure 3.
Figure 4.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
4Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated
Product Folder Links: LM3310
LM3310
www.ti.com
SNVS341E –AUGUST 2005–REVISED MAY 2013
Absolute Maximum Ratings (1)(2)
VIN 7.5V
SW Voltage 21V
FB Voltage VIN
VCVoltage (3) 1.265V ± 0.3V
SHDN Voltage 7.5V
FREQ VIN
AVIN 14.5V
Amplifier Inputs/Output Rail-to-Rail
VGH Voltage 31V
VGHM Voltage VGH
VFLK, VDPM, VDD Voltage 7.5V
CE Voltage (3) 1.265 + 0.3V
RE Voltage VGH
Maximum Junction Temperature 150°C
Power Dissipation(4) Internally Limited
Lead Temperature 300°C
Vapor Phase (60 sec.) 215°C
Infrared (15 sec.) 220°C
ESD Susceptibility (5)
Human Body Model 2kV
(1) Absolute maximum ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions for which the
device is intended to be functional, but device parameter specifications may not be ensured. For specifications and test conditions, see
the Electrical Characteristics.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
(3) Under normal operation the VCand CE pins may go to voltages above this value. The maximum rating is for the possibility of a voltage
being applied to the pin, however the VCand CE pins should never have a voltage directly applied to them.
(4) The maximum allowable power dissipation is a function of the maximum junction temperature, TJ(MAX), the junction-to-ambient thermal
resistance, θJA, and the ambient temperature, TA. See the Electrical Characteristics table for the thermal resistance of various layouts.
The maximum allowable power dissipation at any ambient temperature is calculated using: PD(MAX) = (TJ(MAX) −TA)/θJA. Exceeding
the maximum allowable power dissipation will cause excessive die temperature, and the regulator will go into thermal shutdown.
(5) The human body model is a 100pF capacitor discharged through a 1.5kΩresistor into each pin per JEDEC standard JESD22-A114.
Operating Conditions
Operating Junction Temperature Range (1) −40°C to +125°C
Storage Temperature −65°C to +150°C
Supply Voltage 2.5V to 7V
Maximum SW Voltage 20V
VGH Voltage Range 5V to 30V
Op-Amp Supply, AVIN 4V to 14V
(1) All limits specified at room temperature (standard typeface) and at temperature extremes (bold typeface). All room temperature limits are
100% production tested. All limits at temperature extremes are specified via correlation using standard Statistical Quality Control (SQC)
methods. All limits are used to calculate Average Outgoing Quality Level (AOQL).
Copyright © 2005–2013, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Links: LM3310
LM3310
SNVS341E –AUGUST 2005–REVISED MAY 2013
www.ti.com
Electrical Characteristics
Specifications in standard type face are for TJ= 25°C and those with boldface type apply over the full Operating
Temperature Range ( TJ=−40°C to +125°C). Unless otherwise specified, VIN =2.5V and IL= 0A.
Parameter Test Conditions Min(1) Typ(2) Max(1) Units
IQQuiescent Current FB = 2V (Not Switching) 690 1100 µA
VSHDN = 0V 0.5
0.04 8.5
660kHz Switching 2.1 2.8 mA
1.28MHz Switching 3.1 4.0
VFB Feedback Voltage 1.231 1.263 1.287 V
%VFB/ΔVIN Feedback Voltage Line 2.5V ≤VIN ≤7V -0.26 0.089 0.42 %/V
Regulation
ICL Switch Current Limit (3) (4) 2.0 2.6 A
IBFB Pin Bias Current (5) 27 160 nA
ISS SS Pin Current 8.5 11 13.5 µA
VSS SS Pin Voltage 1.20 1.24 1.28 V
VIN Input Voltage Range 2.5 7 V
gmError Amp Transconductance ΔI = 5µA 26 74 133 µmho
AVError Amp Voltage Gain 69 V/V
DMAX Maximum Duty Cycle fS= 660kHz 80 91 %
fS= 1.28MHz 80 89
fSSwitching Frequency FREQ = Ground 440 660 760 kHz
FREQ = VIN 1.0 1.28 1.5 MHz
ISHDN Shutdown Pin Current VSHDN = 2.5V 8 13.5 µA
VSHDN = 0.3V 1 2
ILSwitch Leakage Current VSW = 20V 0.03 5µA
RDSON Switch RDSON ISW = 500mA 0.18 0.35 Ω
ThSHDN SHDN Threshold Output High, VIN = 2.5V to 7V 1.4 V
Output Low, VIN = 2.5V to 7V 0.4
UVP Undervoltage Protection On Threshold (Switch On) 2.5 2.4 V
Threshold Off Threshold (Switch Off) 2.3 2.1
IFREQ FREQ Pin Current FREQ = VIN = 2.5V 2.7 13.5 µA
Operational Amplifier
VOS Input Offset Voltage Buffer configuration, VO=5.7 15 mV
AVIN/2, no load
IBInput Bias Current (POS Pin) Buffer configuration, VO=200 550 nA
AVIN/2, no load (5)
VOUT Swing Buffer, RL=2kΩ, VOmin. 0.001 0.03 V
Buffer, RL=2kΩ, VOmax. 7.9 7.97
AVIN Supply Voltage 4 14 V
Is+ Supply Current Buffer, VO= AVIN/2, No Load 1.5 7.8 mA
IOUT Output Current Source 90 138 195 mA
Sink 105 135 175
Gate Pulse Modulation
VFLK VFLK Voltage Levels Rising edge threshold 1.4 V
Falling edge threshold 0.4
(1) All limits specified at room temperature (standard typeface) and at temperature extremes (bold typeface). All room temperature limits are
100% production tested. All limits at temperature extremes are specified via correlation using standard Statistical Quality Control (SQC)
methods. All limits are used to calculate Average Outgoing Quality Level (AOQL).
(2) Typical numbers are at 25°C and represent the most likely norm.
(3) Duty cycle affects current limit due to ramp generator.
(4) Current limit at 0% duty cycle. See Typical Performance Characteristics section for Switch Current Limit vs. VIN
(5) Bias current flows into pin.
6Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated
Product Folder Links: LM3310
LM3310
www.ti.com
SNVS341E –AUGUST 2005–REVISED MAY 2013
Electrical Characteristics (continued)
Specifications in standard type face are for TJ= 25°C and those with boldface type apply over the full Operating
Temperature Range ( TJ=−40°C to +125°C). Unless otherwise specified, VIN =2.5V and IL= 0A.
Parameter Test Conditions Min(1) Typ(2) Max(1) Units
VDPM VDPM Voltage Levels Rising edge threshold 1.4 V
Falling edge threshold 0.4
VDD(TH) VDD Threshold VGHM = 30V 2.8 33.3 V
VGHM = 5V 0.4 0.5 0.7
IVFLK VFLK Current VFLK = 1.5V 4.8 11 µA
VFLK = 0.3V 1.1 2.5
IVDPM VDPM Current VDPM = 1.5V 4.8 11 µA
VDPM = 0.3V 1.1 2.5
IVGH VGH Bias Current VGH = 30V, VFLK High 59 300 µA
VGH = 30V, VFLK Low 11 35.5
RVGH-VGHM VGH to VGHM Resistance 20mA Current, VGH = 30V 14 28.5
Ω
RVGHM-RE VGHM to RE Resistance 20mA Current, VGH = VGHM 27 55
= 30V
RVGHM(OFF) VGH Resistance VDPM is Low, VGHM = 2V 1.2 1.7 kΩ
ICE CE Current CE = 0V 711 16 µA
VCE(TH) CE Voltage Threshold 1.16 1.22 1.34 V
Copyright © 2005–2013, Texas Instruments Incorporated Submit Documentation Feedback 7
Product Folder Links: LM3310
VDPM PIN VOLTAGE (V)
0
5
10
15
20
25
VDPM PIN CURRENT (PA)
0.5 1.5 2.5 3.5 4.5 5.5 6.5
0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0
TJ= 25°C
J
T= -40°C
J
T= 125°C
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0
INPUT VOLTAGE (V)
CE PIN CURRENT (PA)
TJ= 25°C
10.4
10.9
11.4
11.9
12.4
12.9
13.4
TJ= -40°C
TJ= 125°C
FB = 1.265V
0
10
20
30
40
50
60
-40 -25 -10 5 20 35 50 65 80 95 110125
JUNCTION TEMPERATURE (°C)
V = 7.0V
IN
V = 2.5V
IN
FB PIN CURRENT (nA)
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0
INPUT VOLTAGE (V)
FREQ PIN CURRENT (PA)
TJ= 25°C
1.5
2.0
2.5
3.0
3.5
4.0
4.5
6.5
7.0
TJ= 125°C
TJ= -40°C
5.0
5.5
6.0
SHDN PIN VOLTAGE (V)
0
5
10
15
20
30
SHDN PIN CURRENT (PA)
0.5 1.5 2.5 3.5 4.5 5.5 6.5
0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0
TJ= 25°C
J
T= -40°C
T = 125°C
J
25
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0
INPUT VOLTAGE (V)
TJ= 25°C
TJ= -40°C
TJ= 125°C
SS PIN CURRENT (PA)
10.4
10.6
10.8
11.0
11.2
11.4
11.6
11.8
12.0
LM3310
SNVS341E –AUGUST 2005–REVISED MAY 2013
www.ti.com
Typical Performance Characteristics
SHDN Pin Current SS Pin Current
vs. vs.
SHDN Pin Voltage Input Voltage
Figure 5. Figure 6.
FREQ Pin Current FB Pin Current
vs. vs.
Input Voltage Temperature
Figure 7. Figure 8.
CE Pin Current VDPM Pin Current
vs. vs.
Input Voltage VDPM Pin Voltage
Figure 9. Figure 10.
8Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated
Product Folder Links: LM3310
-25 -10 5 20 35 50 65 80 95 110125
JUNCTION TEMPERATURE (oC)
550
560
570
580
590
600
610
SWITCHING FREQUENCY (kHz)
-40
VIN = 2.5V
VIN = 7.0V
2.8
3.2
3.6
4.0
4.4
4.8
5.2
5.6
6.0
6.4
6.8
-40 -25 -10 5 20 35 50 65 80 95 110125
JUNCTION TEMPERATURE (°C)
SWITCHING IQ (mA)
V = 2.5V
IN
V = 7.0V
IN
-25 -10 5 20 35 50 65 80 95 110125
JUNCTION TEMPERATURE (oC)
1.8
2.2
2.6
3.0
3.4
3.8
4.2
SWITCHING IQ (mA)
-40
VIN = 2.5V
2.0
2.4
2.8
3.2
3.6
4.0 VIN = 7.0V
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0
INPUT VOLTAGE (V)
SWITCHING IQ (mA)
TJ= 25°C
2.75
3.25
3.75
4.25
4.75
5.25
5.75
6.25
6.75
TJ= -40°C
TJ= 125°C
2.5 7.0
1.8
2.0
2.4
2.8
3.0
3.2
3.6
3.8
4.0
SWITCHING IQ (mA)
INPUT VOLTAGE (V)
2.2
3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5
3.4
2.6 TJ = 125oC
TJ = -40oC
TJ = 25oC
VFLK PIN VOLTAGE (V)
0
5
10
15
20
25
VFLK PIN CURRENT (PA)
0.5 1.5 2.5 3.5 4.5 5.5 6.5
0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0
TJ= 25°C
J
T= -40°C
J
T= 125°C
LM3310
www.ti.com
SNVS341E –AUGUST 2005–REVISED MAY 2013
Typical Performance Characteristics (continued)
VFLK Pin Current 660kHz Switching Quiescent Current
vs. vs.
VFLK Pin Voltage Input Voltage
Figure 11. Figure 12.
1.28MHz Switching Quiescent Current 660kHz Switching Quiescent Current
vs. vs.
Input Voltage Temperature
Figure 13. Figure 14.
1.28MHz Switching Quiescent Current 660kHz Switching Frequency
vs. vs.
Temperature Temperature
Figure 15. Figure 16.
Copyright © 2005–2013, Texas Instruments Incorporated Submit Documentation Feedback 9
Product Folder Links: LM3310
JUNCTION TEMPERATURE (°C)
NON-SWITCHING IQ (mA)
0.66
0.69
0.72
0.75
0.78
0.81
0.84
-40 -25 -10 5 20 35 50 65 80 95 110125
VIN = 7.0V
VIN = 2.5V
GPM Disabled
JUNCTION TEMPERATURE (°C)
NON-SWITCHING IQ (mA)
0.93
0.99
1.02
1.08
1.14
1.23
-40 -25 -10 5 20 35 50 65 80 95 110125
GPM Enabled
VIN = 7.0V
VIN = 2.5V
0.96
1.05
1.11
1.17
1.20
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0
INPUT VOLTAGE (V)
NON-SWITCHING IQ (mA)
0.66
0.69
0.72
0.75
0.78
0.81
0.84
J= -40°CT
J= 25°CT
J= 125°CT
GPM Disabled
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0
INPUT VOLTAGE (V)
NON-SWITCHING IQ (mA)
0.93
0.96
1.02
1.05
1.11
1.14
1.20
J= 125°CT
J= 25°CT
J= -40°CT
0.99
1.08
1.17 GPM Enabled
3.3 3.9 4.5 5.1 5.7 6.3 6.9
INPUT VOLTAGE (V)
2.12
2.14
2.16
2.18
2.2
2.22
2.24
2.26
2.28
2.3
2.32
SWITCH CURRENT LIMIT (A)
2.7
VOUT = 8V
VOUT = 10V
1.16
1.18
1.20
1.22
1.24
1.26
1.28
1.30
1.32
1.34
1.36
1.38
-40 -25 -10 5 20 35 50 65 80 95 110 125
JUNCTION TEMPERATURE (°C)
SWITCHING FREQUENCY (MHz)
V = 2.5V
IN
V = 7.0V
IN
LM3310
SNVS341E –AUGUST 2005–REVISED MAY 2013
www.ti.com
Typical Performance Characteristics (continued)
1.28MHz Switching Frequency Switch Current Limit
vs. vs.
Temperature Input Voltage
Figure 17. Figure 18.
Non-Switching Quiescent Current Non-Switching Quiescent Current
vs. vs.
Input Voltage Input Voltage
GPM Disabled GPM Enabled
Figure 19. Figure 20.
Non-Switching Quiescent Current Non-Switching Quiescent Current
vs. vs.
Temperature Temperature
GPM Disabled GPM Enabled
Figure 21. Figure 22.
10 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated
Product Folder Links: LM3310
65
70
75
80
85
90
95
0.01 0.10 1.00
LOAD CURRENT (A)
EFFICIENCY (%)
VOUT = 8.5V VIN = 5.5V
VIN = 3.3V
VIN = 2.5V
VIN = 4.2V
JUNCTION TEMPERATURE (°C)
MAXIMUM DUTY CYCLE (%)
89.0-40 -25 -10 5 20 35 50 65 80 95 110125
VIN = 7.0V
VIN = 2.5V
89.5
90.0
91.0
92.0
93.5
90.5
91.5
92.5
93.0
-25 -10 5 20 35 50 65 80 95 110 125
JUNCTION TEMPERATURE (oC)
90.5
93.0
MAXIMUM DUTY CYCLE (%)
-40
92.5
92.0
91.5
91.0
VIN = 7.0V
VIN = 2.5V
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0
INPUT VOLTAGE (V)
MAXIMUM DUTY CYCLE (%)
J= -40°CT
89.0
90.0
90.5
91.5
92.5
94.0
89.5
91.0
92.0
93.0
93.5
J= 25°CT
J= 125°CT
90.5
91.0
91.5
92.0
92.5
93.0
INPUT VOLTAGE (V)
MAXIMUM DUTY CYCLE (%)
2.5 3 3.5 4 4.5 5 5.5 6 6.5 7
TJ = 25oC
TJ = 125oC
TJ = -40oC
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0
INPUT VOLTAGE (V)
POWER NMOS RDSON (:)
0.09
0.11
0.13
0.15
0.17
0.19
0.21
0.23
0.25
TA = 100°C
TA = 25°C
TA = -40°C
ISW = 1A
LM3310
www.ti.com
SNVS341E –AUGUST 2005–REVISED MAY 2013
Typical Performance Characteristics (continued)
Power NMOS RDSON 660kHz Max. Duty Cycle
vs. vs.
Input Voltage Input Voltage
Figure 23. Figure 24.
1.28MHz Max. Duty Cycle 660kHz Max. Duty Cycle
vs. vs.
Input Voltage Temperature
Figure 25. Figure 26.
1.28MHz Max. Duty Cycle
vs.
Temperature 1.28MHz Application Efficiency
Figure 27. Figure 28.
Copyright © 2005–2013, Texas Instruments Incorporated Submit Documentation Feedback 11
Product Folder Links: LM3310
-40 -25 -10 5 20 35 50 65 80 95 110 125
JUNCTION TEMPERATURE (°C)
1150
1200
1250
1300
1350
1400
1450 VIN =2.5V
VGHM OFF RESISTANCE (:)
5 8 10 13 15 18 20 23 25 28 30
VGHM PIN VOLTAGE (V)
18
23
28
33
38
43
48
GPM PMOS 3 RDSON (:)
J= 125°CT
J= 25°CT
J= -40°CT
VGH=VGHM
IRE = 20 mA
0 4 8 12 16 20 24 28 32
VGH PIN VOLTAGE (V)
0
10
20
30
40
50
60
70
80
VGH PIN CURRENT (PA)
VFLK = high
TJ = 125°C
TJ = -40°C
TJ = 25°C
4 8 12 16 20 24 28 32
VGH PIN VOLTAGE (V)
10
12
14
16
18
20
22
24
26
28
GPM PMOS 2 RDSON (:)
IVGHM = 20 mA
TJ = 125°C
TJ = 25°C
TJ = -40°C
0 4 8 12 16 20 24 28 32
VGH PIN VOLTAGE (V)
0
2
4
6
8
10
12
14
16
VGH PIN CURRENT (PA)
VFLK = low
TJ = 125°C
TJ = -40°C
TJ = 25°C
65
70
75
80
85
90
95
0.01 0.10 1.00
LOAD CURRENT (A)
EFFICIENCY (%)
VOUT = 10.5V
VIN = 4.2V
VIN = 3.0V
VIN = 5.0V
LM3310
SNVS341E –AUGUST 2005–REVISED MAY 2013
www.ti.com
Typical Performance Characteristics (continued)
VGH Pin Bias Current
vs.
1.28MHz Application Efficiency VGH Pin Voltage
Figure 29. Figure 30.
VGH Pin Bias Current VGH-VGHM PMOS RDSON
vs. vs.
VGH Pin Voltage VGH Pin Voltage
Figure 31. Figure 32.
VGHM-RE PMOS RDSON VGHM OFF Resistance
vs. vs.
VGHM Pin Voltage Temperature
Figure 33. Figure 34.
12 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated
Product Folder Links: LM3310
0 20 40 60 80 100 120
-10
10
70
90
110
170
190
210
OUT - POS (mV)
OP-AMP LOAD CURRENT (mA)
140
150
130
30
50
AVIN = 12V
Unity Gain, POS = AVIN/2
AVIN = 8V
AVIN = 4V
0.50
0.75
1.00
1.25
1.50
1.75
2.00
2.25
2.50
2.75
OP-AMP IQ (mA)
4 5 6 7 8 9 10 11 12
OP-AMP INPUT VOLTAGE (V)
TJ = 125oC
Unity Gain, POS = AVIN/2
TJ = 25oC
TJ = -40oC
-5.7
-5.6
-5.5
-5.4
-5.3
-5.2
-5.1
-5.0
-4.9
-4.8
OUT - POS (mV)
4 5 6 7 8 9 10 11 12
OP-AMP INPUT VOLTAGE (V)
TJ = 125oC
Unity Gain, POS = AVIN/2
TJ = 25oC
TJ = -40oC
45 6 7 8 9 10 11 12
OP-AMP INPUT VOLTAGE (V)
100
110
120
130
140
150
160
170
OP-AMP SOURCE CURRENT (mA)
POS-NEG = 0.2V
TA = 125oC
TA = 25oC
TA = -40oC
4 5 6 7 8 9 10 11 12
OP-AMP INPUT VOLTAGE (V)
100
110
120
130
140
150
160
OP-AMP SINK CURRENT (mA)
NEG-POS = 0.2V
TA = 125oC
TA = -40oC
TA = 25oC
LM3310
www.ti.com
SNVS341E –AUGUST 2005–REVISED MAY 2013
Typical Performance Characteristics (continued)
Op-Amp Source Current Op-Amp Sink Current
vs. vs.
AVIN AVIN
Figure 35. Figure 36.
Op-Amp Quiescent Current Op-Amp Offset Voltage
vs. vs.
AVIN AVIN (No Load)
Figure 37. Figure 38.
Op-Amp Offset Voltage
vs.
Load Current 1.28MHz, 8.5V Application Boost Load Step
VOUT = 8.5V, VIN = 3.3V, COUT = 20µF
1) VOUT, 200mV/div, AC
3) ILOAD, 200mA/div, DC
T = 200µs/div
Figure 39. Figure 40.
Copyright © 2005–2013, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Links: LM3310
LM3310
SNVS341E –AUGUST 2005–REVISED MAY 2013
www.ti.com
Typical Performance Characteristics (continued)
1.28MHz, 8.5V Application Boost Startup Waveform 1.28MHz, 8.5V Application Boost Startup Waveform
VOUT = 8.5V, VIN = 3.3V, COUT = 20µF, RLOAD = 20Ω, CSS = 100nF
VOUT = 8.5V, VIN = 3.3V, COUT = 20µF, RLOAD = 20Ω, CSS = 10nF 1) VSHDN, 2V/div, DC
1) VSHDN, 2V/div, DC 2) VOUT, 5V/div, DC
2) VOUT, 5V/div, DC 3) IIN, 500mA/div, DC
3) IIN, 500mA/div, DC T = 1ms/div
T = 200µs/div Figure 41. Figure 42.
1.28MHz, 8.5V Application Boost Startup Waveform
VOUT = 8.5V, VIN = 3.3V, COUT = 20µF, RLOAD = 20Ω, CSS = open
1) VSHDN, 2V/div, DC
2) VOUT, 5V/div, DC
3) IIN, 1A/div, DC
T = 40µs/div Figure 43.
14 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated
Product Folder Links: LM3310
:
RFB1 = RFB2 xVOUT - 1.263
1.263
VOUT = VIN
1-D , D' = (1-D) = VIN
VOUT
VIN COUT
PWM
L
RLOAD
VIN
L
COUT RLOAD
X
VIN
L
COUT RLOAD
Cycle 1 Cycle 2
(a) (b)
+
VOUT
-
+
VOUT
-
D
LM3310
www.ti.com
SNVS341E –AUGUST 2005–REVISED MAY 2013
Operation
(a) First Cycle of Operation
(b) Second Cycle Of Operation
Figure 44. Simplified Boost Converter Diagram
CONTINUOUS CONDUCTION MODE
The LM3310 contains a current-mode, PWM boost regulator. A boost regulator steps the input voltage up to a
higher output voltage. In continuous conduction mode (when the inductor current never reaches zero at steady
state), the boost regulator operates in two cycles.
In the first cycle of operation, shown in Figure 44 (a), the transistor is closed and the diode is reverse biased.
Energy is collected in the inductor and the load current is supplied by COUT.
The second cycle is shown in Figure 44 (b). During this cycle, the transistor is open and the diode is forward
biased. The energy stored in the inductor is transferred to the load and output capacitor.
The ratio of these two cycles determines the output voltage. The output voltage is defined approximately as:
where
• D is the duty cycle of the switch
• D and D′will be required for design calculations (1)
SETTING THE OUTPUT VOLTAGE (BOOST CONVERTER)
The output voltage is set using the feedback pin and a resistor divider connected to the output as shown in the
Typical Application Circuit. The feedback pin voltage is 1.263V, so the ratio of the feedback resistors sets the
output voltage according to the following equation:
(2)
Copyright © 2005–2013, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Links: LM3310
LM3310
SNVS341E –AUGUST 2005–REVISED MAY 2013
www.ti.com
SOFT-START CAPACITOR
The LM3310 has a soft-start pin that can be used to limit the inductor inrush current on start-up. The external SS
pin is used to tailor the soft-start for a specific application but is not required for all applications and can be left
open when not needed. When used a current source charges the external soft-start capacitor CSS until it reaches
its typical clamp voltage, VSS. The soft-start time can be estimated as:
TSS = CSS*VSS/ISS (3)
THERMAL SHUTDOWN
The LM3310 includes thermal shutdown. If the die temperature reaches 145°C the device will shut down until it
cools to a safe temperature at which point the device will resume operation. If the adverse condition that is
heating the device is not removed (ambient temperature too high, short circuit conditions, etc...) the device will
continue to cycle on and off to keep the die temperature below 145°C. The thermal shutdown has approximately
20°C of hysteresis. When in thermal shutdown the boost regulator, Op-Amp, and GPM blocks will all be disabled.
INPUT UNDER-VOLTAGE PROTECTION
The LM3310 includes input under-voltage protection (UVP). The purpose of the UVP is to protect the device both
during start-up and during normal operation from trying to operate with insufficient input voltage. During start-up
using a ramping input voltage the UVP circuitry ensures that the device does not begin switching until the input
voltage reaches the UVP On threshold. If the input voltage is present and the shutdown pin is pulled high the
UVP circuitry will prevent the device from switching if the input voltage present is lower than the UVP On
threshold. During normal operation the UVP circuitry will disable the device if the input voltage falls below the
UVP Off threshold for any reason. In this case the device will not turn back on until the UVP On threshold voltage
is exceeded.
OPERATIONAL AMPLIFIER
Compensation:
The architecture used for the amplifier in the LM3310 requires external compensation on the output. Depending
on the equivalent resistive and capacitive distributed load of the TFT-LCD panel, external components at the
amplifier outputs may or may not be necessary. If the capacitance presented by the load is equal to or greater
than an equivalent distibutive load of 50Ωin series with 4.7nF no external components are needed as the TFT-
LCD panel will act as compensation itself. Distributed resistive and capacitive loads enhance stability and
increase performance of the amplifiers. If the capacitance and resistance presented by the load is less than 50Ω
in series with 4.7nF, external components will be required as the load itself will not ensure stability. No external
compensation in this case will lead to oscillation of the amplifier and an increase in power consumption. A good
choice for compensation in this case is to add a 50Ωin series with a 4.7nF capacitor from the output of the
amplifier to ground. This allows for driving zero to infinite capacitance loads with no oscillations, minimal
overshoot, and a higher slew rate than using a single large capacitor. The high phase margin created by the
external compensation will ensure stability and good performance for all conditions.
Layout and Filtering considerations:
When the power supply for the amplifiers (AVIN) is connected to the output of the switching regulator, the output
ripple of the regulator will produce ripple at the output of the amplifiers. This can be minimized by directly
bypassing the AVIN pin to ground with a low ESR ceramic capacitor. For best noise reduction a resistor on the
order of 5Ωto 20Ωfrom the supply being used to the AVIN pin will create and RC filter and give you a cleaner
supply to the amplifier. The bypass capacitor should be placed as close to the AVIN pin as possible and
connected directly to the AGND plane.
For best noise immunity all bias and feedback resistors should be in the low kΩrange due to the high input
impedance of the amplifier. It is good practice to use a small capacitance at the high impedance input terminals
as well to reduce noise susceptibility. All resistors and capacitors should be placed as close to the input pins as
possible.
Special care should also be taken in routing of the PCB traces. All traces should be as short and direct as
possible. The output pin trace must never be routed near any trace going to the positive input. If this happens
cross talk from the output trace to the positive input trace will cause the circuit to oscillate.
16 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated
Product Folder Links: LM3310
VGHMMAX
VGHMMIN
MR
~1.94V
0
0
0
t
t
t
VGHM
VFLK
CE
~1.265V
tDELAY
LM3310
www.ti.com
SNVS341E –AUGUST 2005–REVISED MAY 2013
The op-amp is not a three terminal device it has 5 terminals: positive voltage power pin, AGND, positive input,
negative input, and the output. The op-amp "routes" current from the power input pin and AGND to the output
pin. So in effect an opamp has not two inputs but four, all of which must be kept noise free relative to the
external circuits which are being driven by the op-amp. The current from the power pins goes through the output
pin and into the load and feedback loop. The current exiting the load and feedback loops then must have a return
path back to the op-amp power supply pins. Ideally this return path must follow the same path as the output pin
trace to the load. Any deviation that makes the loop area larger between the output current path and the return
current path adds to the probability of noise pick up.
GATE PULSE MODULATION
The Gate Pulse Modulation (GPM) block is designed to provide a modulated voltage to the gate driver circuitry of
a TFT LCD display. Operation is best understood by referring to the GPM block diagram in the Block Diagrams
section, the drawing in Figure 45 and the transient waveforms in Figure 46 and Figure 47.
There are two control signals in the GPM block, VDPM and VFLK. VDPM is the enable pin for the GPM block. If
VDPM is high, the GPM block is active and will respond to the VFLK drive signal from the timing controller.
However, if VDPM is low, the GPM block will be disabled and both PMOS switches P2 and P3 will be turned off.
The VGHM node will be discharged through a 1kΩresistor and the NMOS switch N2.
When VDPM is high, typical waveforms for the GPM block can be seen in Figure 45. The pin VGH is typically
driven by a 2x or 3x charge pump. In most cases, the 2x or 3x charge pump is a discrete solution driven from the
SW pin and the output of the boost switching regulator. When VFLK is high, the PMOS switch P2 is turned on
and the PMOS switch P3 is turned off. With P2 on, the VGHM pin is pulled to the same voltage applied to the
VGH pin. This provides a high gate drive voltage, VGHMMAX, and can source current to the gate drive circuitry.
When VFLK is high, NMOS switch N3 is on which discharges the capacitor CE.
Figure 45.
When VFLK is low, the NMOS switch N3 is turned off which allows current to charge the CEcapacitor. This
creates a delay, tDELAY, given by the following equations:
tDELAY ≊1.265V(CE+ 7pF)/ICE (4)
When the voltage on CE reaches about 1.265V and the VFLK signal is low, the PMOS switch P2 will turn off and
the PMOS switch P3 will turn on connecting resistor R3 to the VGHM pin through P3. This will discharge the
voltage at VGHM at some rate determined by R3 creating a slope, MR, as shown in Figure 45. The VGHM pin is
no longer a current source, it is now sinking current from the gate drive circuitry.
Copyright © 2005–2013, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Links: LM3310
LM3310
SNVS341E –AUGUST 2005–REVISED MAY 2013
www.ti.com
As VGHM is discharged through R3, the comparator connected to the pin VDD monitors the VGHM voltage.
PMOS switch P3 will turn off when the following is true:
VGHMMIN ≊10VXR2/(R1 + R2)
where
• VXis some voltage connected to the resistor divider on pin VDD (5)
VXis typically connected to the output of the boost switching regulator. When PMOS switch P3 turns off, VGHM
will be high impedance until the VFLK pin is high again.
Figure 46 and Figure 47 give typical transient waveforms for the GPM block. Waveform (1) is the VGHM pin, (2)
is the VFLK and (3) is the VDPM. The output of the boost switching regulator is operating at 8.5V and there is a
3x discrete charge pump (~23.5V) supplying the VGH pin. In Figure 46 and Figure 47, the VGHM pin is driving a
purely capacitive load, 4.7nF. The value of resistor R1 is 15kohm, R2 is 1.1kΩand R3 is 750Ω. In both transient
plots, there is no CEdelay capacitor.
Figure 46. Waveform
Figure 47. Waveform
In the GPM block diagram, a signal called “Reset” is shown. This signal is generated from the VIN under-voltage
lockout, thermal shutdown, or the SHDN pin. If the VIN supply voltage drops below 2.3V, typically, then the GPM
block will be disabled and the VGHM pin will discharge through NMOS switch N2 and the 1kΩresistor. This
applies also if the junction temperature of the device exceeds 145°C or if the SHDN signal is low. As shown in
the Block Diagrams, both VDPM and VFLK have internal 350kΩpull down resistors. This puts both VDPM and
VFLK in normally “off” states. Typical VDPM and VFLK pin currents can be found in the Typical Performance
Characteristics section.
18 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated
Product Folder Links: LM3310
Hz
1
2S(RC + RO)CC
fPC =
Hz
1
fZC =2SRCCC
t (s)
t (s)
L
i'
IL_AVG
ID_AVG
=IOUT_AVG
D*Ts Ts
D*Ts Ts
IL (A)
ID (A)
L
VIN
LVV OUTIN
LVV OUTIN
(a)
(b)
LM3310
www.ti.com
SNVS341E –AUGUST 2005–REVISED MAY 2013
INTRODUCTION TO COMPENSATION (BOOST CONVERTER)
(a) Inductor current
(b) Diode current
Figure 48.
The LM3310 is a current mode PWM boost converter. The signal flow of this control scheme has two feedback
loops, one that senses switch current and one that senses output voltage.
To keep a current programmed control converter stable above duty cycles of 50%, the inductor must meet
certain criteria. The inductor, along with input and output voltage, will determine the slope of the current through
the inductor (see Figure 48 (a)). If the slope of the inductor current is too great, the circuit will be unstable above
duty cycles of 50%. A 10µH inductor is recommended for most 660 kHz applications, while a 4.7µH inductor may
be used for most 1.28 MHz applications. If the duty cycle is approaching the maximum of 85%, it may be
necessary to increase the inductance by as much as 2X. See INDUCTOR AND DIODE SELECTION for more
detailed inductor sizing.
The LM3310 provides a compensation pin (VC) to customize the voltage loop feedback. It is recommended that a
series combination of RCand CCbe used for the compensation network, as shown in the Typical Application
Circuit. For any given application, there exists a unique combination of RCand CCthat will optimize the
performance of the LM3310 circuit in terms of its transient response. The series combination of RCand CC
introduces a pole-zero pair according to the following equations:
(6)
Copyright © 2005–2013, Texas Instruments Incorporated Submit Documentation Feedback 19
Product Folder Links: LM3310
iL(AVE) + 'iL
iL(PEAK)
|
IOUT
KD'
iL(AVE)
|
'iL = (in Amps)
VIND
2Lfs
VINRDSON
0.144 fs
L > D
D' - 1 (in H)
LM3310
SNVS341E –AUGUST 2005–REVISED MAY 2013
www.ti.com
where
• ROis the output impedance of the error amplifier, approximately 900kΩ(7)
For most applications, performance can be optimized by choosing values within the range 5kΩ≤RC≤100kΩ(RC
can be up to 200kΩif CC2 is used, see HIGH OUTPUT CAPACITOR ESR COMPENSATION) and 68pF ≤CC≤
4.7nF. Refer to the Application Information section for recommended values for specific circuits and conditions.
Refer to the COMPENSATION section for other design requirement.
COMPENSATION
This section will present a general design procedure to help insure a stable and operational circuit. The designs
in this datasheet are optimized for particular requirements. If different conversions are required, some of the
components may need to be changed to ensure stability. Below is a set of general guidelines in designing a
stable circuit for continuous conduction operation, in most all cases this will provide for stability during
discontinuous operation as well. The power components and their effects will be determined first, then the
compensation components will be chosen to produce stability.
INDUCTOR AND DIODE SELECTION
Although the inductor sizes mentioned earlier are fine for most applications, a more exact value can be
calculated. To ensure stability at duty cycles above 50%, the inductor must have some minimum value
determined by the minimum input voltage and the maximum output voltage. This equation is:
where
• fs is the switching frequency
• D is the duty cycle
• RDSON is the ON resistance of the internal switch taken from the graph "RDSON vs. VIN" in the Typical
Performance Characteristics section (8)
This equation is only good for duty cycles greater than 50% (D>0.5), for duty cycles less than 50% the
recommended values may be used. The value given by this equation is the inductance necessary to supress
sub-harmonic oscillations. In some cases the value given by this equation may be too small for a given
application. In this case the average inductor current and the inductor current ripple must be considered.
The corresponding inductor current ripple, average inductor current, and peak inductor current as shown in
Figure 48 (a) is given by:
(9)
(10)
(11)
Continuous conduction mode occurs when ΔiLis less than the average inductor current and discontinuous
conduction mode occurs when ΔiLis greater than the average inductor current. Care must be taken to make sure
that the switch will not reach its current limit during normal operation. The inductor must also be sized
accordingly. It should have a saturation current rating higher than the peak inductor current expected. The output
voltage ripple is also affected by the total ripple current.
The output diode for a boost regulator must be chosen correctly depending on the output voltage and the output
current. The typical current waveform for the diode in continuous conduction mode is shown in Figure 48 (b). The
diode must be rated for a reverse voltage equal to or greater than the output voltage used. The average current
rating must be greater than the maximum load current expected, and the peak current rating must be greater
than the peak inductor current. During short circuit testing, or if short circuit conditions are possible in the
application, the diode current rating must exceed the switch current limit. Using Schottky diodes with lower
forward voltage drop will decrease power dissipation and increase efficiency.
20 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated
Product Folder Links: LM3310
fP1 = 1
2S(RESR + RL)COUT (in Hz)
m1
#
VINRDSON
L(in V/s)
n = 1+ 2mc
m1 (no unit)
Leff = L
(D')2
Zc(in rad/s)
2fs
nD'
#
ADC(DB) = 20log10 {[(ZcLeff)// RL]//RL}(in dB)
RFB1 + RFB2
RFB2
()gmROD'
RDSON
LM3310
www.ti.com
SNVS341E –AUGUST 2005–REVISED MAY 2013
DC GAIN AND OPEN-LOOP GAIN
Since the control stage of the converter forms a complete feedback loop with the power components, it forms a
closed-loop system that must be stabilized to avoid positive feedback and instability. A value for open-loop DC
gain will be required, from which you can calculate, or place, poles and zeros to determine the crossover
frequency and the phase margin. A high phase margin (greater than 45°) is desired for the best stability and
transient response. For the purpose of stabilizing the LM3310, choosing a crossover point well below where the
right half plane zero is located will ensure sufficient phase margin.
To ensure a bandwidth of ½ or less of the frequency of the RHP zero, calculate the open-loop DC gain, ADC.
After this value is known, you can calculate the crossover visually by placing a −20dB/decade slope at each pole,
and a +20dB/decade slope for each zero. The point at which the gain plot crosses unity gain, or 0dB, is the
crossover frequency. If the crossover frequency is less than ½ the RHP zero, the phase margin should be high
enough for stability. The phase margin can also be improved by adding CC2 as discussed later in this section.
The equation for ADC is given below with additional equations required for the calculation:
where
• RLis the minimum load resistance
• gmis the error amplifier transconductance found in the Electrical Characteristics table (12)
(13)
(14)
(15)
mc ≊0.072fs (in V/s) (16)
where
• VIN is the minimum input voltage
• RDSON is the value chosen from the graph "NMOS RDSON vs. Input Voltage" in the Typical Performance
Characteristics section (17)
INPUT AND OUTPUT CAPACITOR SELECTION
The switching action of a boost regulator causes a triangular voltage waveform at the input. A capacitor is
required to reduce the input ripple and noise for proper operation of the regulator. The size used is dependant on
the application and board layout. If the regulator will be loaded uniformly, with very little load changes, and at
lower current outputs, the input capacitor size can often be reduced. The size can also be reduced if the input of
the regulator is very close to the source output. The size will generally need to be larger for applications where
the regulator is supplying nearly the maximum rated output or if large load steps are expected. A minimum value
of 10µF should be used for the less stressful condtions while a 22µF to 47µF capacitor may be required for
higher power and dynamic loads. Larger values and/or lower ESR may be needed if the application requires very
low ripple on the input source voltage.
The choice of output capacitors is also somewhat arbitrary and depends on the design requirements for output
voltage ripple. It is recommended that low ESR (Equivalent Series Resistance, denoted RESR) capacitors be used
such as ceramic, polymer electrolytic, or low ESR tantalum. Higher ESR capacitors may be used but will require
more compensation which will be explained later on in the section. The ESR is also important because it
determines the peak to peak output voltage ripple according to the approximate equation:
ΔVOUT ≊2ΔiLRESR (in Volts) (18)
A minimum value of 10µF is recommended and may be increased to a larger value. After choosing the output
capacitor you can determine a pole-zero pair introduced into the control loop by the following equations:
Copyright © 2005–2013, Texas Instruments Incorporated Submit Documentation Feedback 21
Product Folder Links: LM3310
fPC2 = 1
2SCC2(RC //RO)(in Hz)
fZC = 1
2SCCRC(in Hz)
fPC = 1
2S(RC + RO)CC(in Hz)
(in Hz)
RHPzero = VOUT(D')2
2S,LOADL
fZ1 = 1
2SRESRCOUT (in Hz)
LM3310
SNVS341E –AUGUST 2005–REVISED MAY 2013
www.ti.com
where
• RLis the minimum load resistance corresponding to the maximum load current (19)
(20)
The zero created by the ESR of the output capacitor is generally very high frequency if the ESR is small. If low
ESR capacitors are used it can be neglected. If higher ESR capacitors are used see the HIGH OUTPUT
CAPACITOR ESR COMPENSATION section. Some suitable capacitor vendors include Vishay, Taiyo-Yuden,
and TDK.
RIGHT HALF PLANE ZERO
A current mode control boost regulator has an inherent right half plane zero (RHP zero). This zero has the effect
of a zero in the gain plot, causing an imposed +20dB/decade on the rolloff, but has the effect of a pole in the
phase, subtracting another 90° in the phase plot. This can cause undesirable effects if the control loop is
influenced by this zero. To ensure the RHP zero does not cause instability issues, the control loop should be
designed to have a bandwidth of less than ½ the frequency of the RHP zero. This zero occurs at a frequency of:
where
• ILOAD is the maximum load current (21)
SELECTING THE COMPENSATION COMPONENTS
The first step in selecting the compensation components RCand CCis to set a dominant low frequency pole in
the control loop. Simply choose values for RCand CCwithin the ranges given in the Introduction to
Compensation section to set this pole in the area of 10Hz to 500Hz. The frequency of the pole created is
determined by the equation:
where
• ROis the output impedance of the error amplifier, approximately 900kΩ(22)
Since RCis generally much less than RO, it does not have much effect on the above equation and can be
neglected until a value is chosen to set the zero fZC. fZC is created to cancel out the pole created by the output
capacitor, fP1. The output capacitor pole will shift with different load currents as shown by the equation, so setting
the zero is not exact. Determine the range of fP1 over the expected loads and then set the zero fZC to a point
approximately in the middle. The frequency of this zero is determined by:
(23)
Now RCcan be chosen with the selected value for CC. Check to make sure that the pole fPC is still in the 10Hz to
500Hz range, change each value slightly if needed to ensure both component values are in the recommended
range.
HIGH OUTPUT CAPACITOR ESR COMPENSATION
When using an output capacitor with a high ESR value, or just to improve the overall phase margin of the control
loop, another pole may be introduced to cancel the zero created by the ESR. This is accomplished by adding
another capacitor, CC2, directly from the compensation pin VCto ground, in parallel with the series combination of
RCand CC. The pole should be placed at the same frequency as fZ1, the ESR zero. The equation for this pole
follows:
(24)
To ensure this equation is valid, and that CC2 can be used without negatively impacting the effects of RCand CC,
fPC2 must be greater than 10fZC.
22 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated
Product Folder Links: LM3310
LM3310
www.ti.com
SNVS341E –AUGUST 2005–REVISED MAY 2013
CHECKING THE DESIGN
With all the poles and zeros calculated the crossover frequency can be checked as described in the section DC
GAIN AND OPEN-LOOP GAIN. The compensation values can be changed a little more to optimize performance
if desired. This is best done in the lab on a bench, checking the load step response with different values until the
ringing and overshoot on the output voltage at the edge of the load steps is minimal. This should produce a
stable, high performance circuit. For improved transient response, higher values of RCshould be chosen. This
will improve the overall bandwidth which makes the regulator respond more quickly to transients. If more detail is
required, or the most optimum performance is desired, refer to a more in depth discussion of compensating
current mode DC/DC switching regulators.
POWER DISSIPATION
The output power of the LM3310 is limited by its maximum power dissipation. The maximum power dissipation is
determined by the formula
PD= (Tjmax - TA)/θJA
where
• Tjmax is the maximum specified junction temperature (125°C)
• TAis the ambient temperature
•θJA is the thermal resistance of the package (25)
LAYOUT CONSIDERATIONS
The input bypass capacitor CIN, as shown in the Typical Application Circuit, must be placed close to the IC. This
will reduce copper trace resistance which effects input voltage ripple of the IC. For additional input voltage
filtering, a 100nF bypass capacitor can be placed in parallel with CIN, close to the VIN pin, to shunt any high
frequency noise to ground. The output capacitor, COUT, should also be placed close to the IC. Any copper trace
connections for the COUT capacitor can increase the series resistance, which directly effects output voltage ripple.
The feedback network, resistors RFB1 and RFB2, should be kept close to the FB pin, and away from the inductor,
to minimize copper trace connections that can inject noise into the system. REand CEshould also be close to the
RE and CE pins to minimize noise in the GPM circuitry. Trace connections made to the inductor and schottky
diode should be minimized to reduce power dissipation and increase overall efficiency. For more detail on
switching power supply layout considerations see Application Note AN-1149:Layout Guidelines for Switching
Power Supplies.
For Op-Amp layout please refer to the OPERATIONAL AMPLIFIER section.
Figure 49,Figure 50, and Figure 51 in the Application Information section following show the schematic and an
example of a good layout as used in the LM3310/11 evaluation board.
Copyright © 2005–2013, Texas Instruments Incorporated Submit Documentation Feedback 23
Product Folder Links: LM3310
VDD
CIN
CIN1
COUT
COUT1
COUT2
VIN
FB
SW
SS
AGND
POS
NEG
SHDN FREQ
LM3310
VC
DCP1
D1
L1
RFB1
VIN
PGND
OUT
VDPM
VGHM
VFLK
CE
RE
VGH
RE CE
AVIN
CCP1
RVDD1
RVDD2
VOUTX2
RFB2
CSS
CC1
RC1
CC2
VOUT
CCP2
DCP2
CCP3
VOUTX3
CCP4
CCP5
DCP3
-VOUT
CG1
CG2
POS
RC6
RC7 CO2
NEG
RAC2
CAC2
CAC1
RAC1
OUT
VFLK
VDPM
VGHM
VGH CO1
LM3310
SNVS341E –AUGUST 2005–REVISED MAY 2013
www.ti.com
APPLICATION INFORMATION
Figure 49. Evaluation Board Schematic
Figure 50. Evaluation Board Layout (top layer)
24 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated
Product Folder Links: LM3310
VDD
CSS
CIN
COUT
VIN
FB
SW
SS
AGND
POS
NEG
SHDN FREQ
LM3310
VC
D3
D2
D1
L
RFB1
160k
VIN
CC
RC
PGND
OUT
VDPM
VGHM
VFLK
CERE
VGH
RECE
= 15V
AVIN
C3 C4
R1
R2
VOUT
VOH
22 PF
2 X 10 PF
ceramic
RFB2
30k
10 PH
2.4k 33 pF
13k
1.2k
10 nF
1 nF
30k
1 PF 1 PF
= 8V
= 2.9V - 4.2V
Connect to
VGH
68 pF
CC2
LM3310
www.ti.com
SNVS341E –AUGUST 2005–REVISED MAY 2013
Figure 51. Evaluation Board Layout (bottom layer)
Figure 52. Li-Ion to 8V, 1.28MHz Application
Copyright © 2005–2013, Texas Instruments Incorporated Submit Documentation Feedback 25
Product Folder Links: LM3310
VDD
CSS
CIN
COUT
VIN
FB
SW
SS
AGND
POS
NEG
SHDN FREQ
LM3310
VC
D3
D2
D1
L
RFB1
16k
VIN
CC
RC
PGND
OUT
VDPM
VGHM
VFLK
CERE
VGH
RECE
= 20V
AVIN
C3 C4
R1
R2
VOUT
VOH
22 PF
4 X 10 PF
ceramic
RFB2
2.2k
10 PH
2.4k 33 pF
13k
1.2k
10 nF
100 pF
33k
CFF
33 pF
1 PF 1 PF
= 10.5V
= 5V
Connect to
VGH
LM3310
SNVS341E –AUGUST 2005–REVISED MAY 2013
www.ti.com
Figure 53. 5V to 10.5V, 1.28MHz Application
Table 1. Some Recommended Inductors (Others May Be Used)
Manufacturer Inductor Contact Information
Coilcraft DO3316 and DT3316 series www.coilcraft.com
800-3222645
TDK SLF10145 series www.component.tdk.com
847-803-6100
Pulse P0751 and P0762 series www.pulseeng.com
Sumida CDRH8D28 and CDRH8D43 series www.sumida.com
Table 2. Some Recommended Input And Output Capacitors (Others May Be Used)
Manufacturer Capacitor Contact Information
Vishay Sprague 293D, 592D, and 595D series tantalum www.vishay.com
407-324-4140
Taiyo Yuden High capacitance MLCC ceramic www.t-yuden.com
408-573-4150
ESRD seriec Polymer Aluminum Electrolytic
Cornell Dubilier www.cde.com
SPV and AFK series V-chip series
High capacitance MLCC ceramic
Panasonic www.panasonic.com
EEJ-L series tantalum
26 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated
Product Folder Links: LM3310
LM3310
www.ti.com
SNVS341E –AUGUST 2005–REVISED MAY 2013
REVISION HISTORY
Changes from Revision D (May 2013) to Revision E Page
• Changed layout of National Data Sheet to TI format .......................................................................................................... 26
Copyright © 2005–2013, Texas Instruments Incorporated Submit Documentation Feedback 27
Product Folder Links: LM3310
PACKAGE OPTION ADDENDUM
www.ti.com 8-Oct-2015
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
LM3310SQ/NOPB ACTIVE WQFN RTW 24 1000 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 L3310SQ
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 8-Oct-2015
Addendum-Page 2
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
LM3310SQ/NOPB WQFN RTW 24 1000 178.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 2-Sep-2015
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LM3310SQ/NOPB WQFN RTW 24 1000 210.0 185.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 2-Sep-2015
Pack Materials-Page 2
www.ti.com
PACKAGE OUTLINE
C
24X 0.3
0.2
24X 0.5
0.3
0.8 MAX
(0.1) TYP
0.05
0.00
20X 0.5
2X
2.5
2X 2.5
2.6 0.1
A4.1
3.9 B
4.1
3.9
WQFN - 0.8 mm max heightRTW0024A
PLASTIC QUAD FLATPACK - NO LEAD
4222815/A 03/2016
PIN 1 INDEX AREA
0.08 C
SEATING PLANE
1
613
18
7 12
24 19
(OPTIONAL)
PIN 1 ID 0.1 C A B
0.05 C
EXPOSED
THERMAL PAD
25
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
SCALE 3.000
www.ti.com
EXAMPLE BOARD LAYOUT
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
24X (0.25)
24X (0.6)
( ) TYP
VIA
0.2
20X (0.5)
(3.8)
(3.8)
(1.05)
( 2.6)
(R )
TYP
0.05
(1.05)
WQFN - 0.8 mm max heightRTW0024A
PLASTIC QUAD FLATPACK - NO LEAD
4222815/A 03/2016
SYMM
1
6
712
13
18
19
24
SYMM
LAND PATTERN EXAMPLE
SCALE:15X
25
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
METAL
SOLDER MASK
OPENING
SOLDER MASK DETAILS
NON SOLDER MASK
DEFINED
(PREFERRED)
www.ti.com
EXAMPLE STENCIL DESIGN
24X (0.6)
24X (0.25)
20X (0.5)
(3.8)
(3.8)
4X ( 1.15)
(0.675)
TYP
(0.675) TYP
(R ) TYP0.05
WQFN - 0.8 mm max heightRTW0024A
PLASTIC QUAD FLATPACK - NO LEAD
4222815/A 03/2016
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
SYMM
METAL
TYP
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 25:
78% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:20X
SYMM
1
6
712
13
18
19
24
25
IMPORTANT NOTICE
Texas Instruments Incorporated (TI) reserves the right to make corrections, enhancements, improvements and other changes to its
semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers
should obtain the latest relevant information before placing orders and should verify that such information is current and complete.
TI’s published terms of sale for semiconductor products (http://www.ti.com/sc/docs/stdterms.htm) apply to the sale of packaged integrated
circuit products that TI has qualified and released to market. Additional terms may apply to the use or sale of other types of TI products and
services.
Reproduction of significant portions of TI information in TI data sheets is permissible only if reproduction is without alteration and is
accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such reproduced
documentation. Information of third parties may be subject to additional restrictions. Resale of TI products or services with statements
different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the
associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.
Buyers and others who are developing systems that incorporate TI products (collectively, “Designers”) understand and agree that Designers
remain responsible for using their independent analysis, evaluation and judgment in designing their applications and that Designers have
full and exclusive responsibility to assure the safety of Designers' applications and compliance of their applications (and of all TI products
used in or for Designers’ applications) with all applicable regulations, laws and other applicable requirements. Designer represents that, with
respect to their applications, Designer has all the necessary expertise to create and implement safeguards that (1) anticipate dangerous
consequences of failures, (2) monitor failures and their consequences, and (3) lessen the likelihood of failures that might cause harm and
take appropriate actions. Designer agrees that prior to using or distributing any applications that include TI products, Designer will
thoroughly test such applications and the functionality of such TI products as used in such applications.
TI’s provision of technical, application or other design advice, quality characterization, reliability data or other services or information,
including, but not limited to, reference designs and materials relating to evaluation modules, (collectively, “TI Resources”) are intended to
assist designers who are developing applications that incorporate TI products; by downloading, accessing or using TI Resources in any
way, Designer (individually or, if Designer is acting on behalf of a company, Designer’s company) agrees to use any particular TI Resource
solely for this purpose and subject to the terms of this Notice.
TI’s provision of TI Resources does not expand or otherwise alter TI’s applicable published warranties or warranty disclaimers for TI
products, and no additional obligations or liabilities arise from TI providing such TI Resources. TI reserves the right to make corrections,
enhancements, improvements and other changes to its TI Resources. TI has not conducted any testing other than that specifically
described in the published documentation for a particular TI Resource.
Designer is authorized to use, copy and modify any individual TI Resource only in connection with the development of applications that
include the TI product(s) identified in such TI Resource. NO OTHER LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE
TO ANY OTHER TI INTELLECTUAL PROPERTY RIGHT, AND NO LICENSE TO ANY TECHNOLOGY OR INTELLECTUAL PROPERTY
RIGHT OF TI OR ANY THIRD PARTY IS GRANTED HEREIN, including but not limited to any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information
regarding or referencing third-party products or services does not constitute a license to use such products or services, or a warranty or
endorsement thereof. Use of TI Resources may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
TI RESOURCES ARE PROVIDED “AS IS” AND WITH ALL FAULTS. TI DISCLAIMS ALL OTHER WARRANTIES OR
REPRESENTATIONS, EXPRESS OR IMPLIED, REGARDING RESOURCES OR USE THEREOF, INCLUDING BUT NOT LIMITED TO
ACCURACY OR COMPLETENESS, TITLE, ANY EPIDEMIC FAILURE WARRANTY AND ANY IMPLIED WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL
PROPERTY RIGHTS. TI SHALL NOT BE LIABLE FOR AND SHALL NOT DEFEND OR INDEMNIFY DESIGNER AGAINST ANY CLAIM,
INCLUDING BUT NOT LIMITED TO ANY INFRINGEMENT CLAIM THAT RELATES TO OR IS BASED ON ANY COMBINATION OF
PRODUCTS EVEN IF DESCRIBED IN TI RESOURCES OR OTHERWISE. IN NO EVENT SHALL TI BE LIABLE FOR ANY ACTUAL,
DIRECT, SPECIAL, COLLATERAL, INDIRECT, PUNITIVE, INCIDENTAL, CONSEQUENTIAL OR EXEMPLARY DAMAGES IN
CONNECTION WITH OR ARISING OUT OF TI RESOURCES OR USE THEREOF, AND REGARDLESS OF WHETHER TI HAS BEEN
ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
Unless TI has explicitly designated an individual product as meeting the requirements of a particular industry standard (e.g., ISO/TS 16949
and ISO 26262), TI is not responsible for any failure to meet such industry standard requirements.
Where TI specifically promotes products as facilitating functional safety or as compliant with industry functional safety standards, such
products are intended to help enable customers to design and create their own applications that meet applicable functional safety standards
and requirements. Using products in an application does not by itself establish any safety features in the application. Designers must
ensure compliance with safety-related requirements and standards applicable to their applications. Designer may not use any TI products in
life-critical medical equipment unless authorized officers of the parties have executed a special contract specifically governing such use.
Life-critical medical equipment is medical equipment where failure of such equipment would cause serious bodily injury or death (e.g., life
support, pacemakers, defibrillators, heart pumps, neurostimulators, and implantables). Such equipment includes, without limitation, all
medical devices identified by the U.S. Food and Drug Administration as Class III devices and equivalent classifications outside the U.S.
TI may expressly designate certain products as completing a particular qualification (e.g., Q100, Military Grade, or Enhanced Product).
Designers agree that it has the necessary expertise to select the product with the appropriate qualification designation for their applications
and that proper product selection is at Designers’ own risk. Designers are solely responsible for compliance with all legal and regulatory
requirements in connection with such selection.
Designer will fully indemnify TI and its representatives against any damages, costs, losses, and/or liabilities arising out of Designer’s non-
compliance with the terms and provisions of this Notice.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2018, Texas Instruments Incorporated
