Am29LV320MT110REI - Advanced Micro Devices

July 2003

The following document specifies Spansion memory products that are now offered by both Advanced

Micro Devices and Fujitsu. Although the document is marked with the name of the company that orig-

inally developed the specification, these products will be offered to customers of both AMD and

Fujitsu.

Continuity of Specifications

There is no change to this datasheet as a result of offering the device as a Spansion product. Any

changes that have been made are the result of normal datasheet improvement and are noted in the

document revision summary, where supported. Future routine revisions will occur when appropriate,

and changes will be noted in a revision summary.

Continuity of Ordering Part Numbers

AMD and Fujitsu continue to support existing part numbers beginning with “Am” and “MBM”. To order

these products, please use only the Ordering Part Numbers listed in this document.

For More Information

Please contact your local AMD or Fujitsu sales office for additional information about Spansion

memory solutions.

Am29LV320MT/B

Data Sheet

Publication Number 26518 Revision CAmendment 1Issue Date May 4, 2004

For new designs, S29GL032M supercedes Am29LV320MT/B and is the factory-recommended migra-

tion path for this device. Please refer to the S29GLxxxM Family Datasheet for specifications and

ordering information.

THIS PAGE LEFT INTENTIONALLY BLANK.

Publication# 26518 Rev: CAmendment/1

Issue Date: May 4, 2004

Refer to AMD’s Website (www.amd.com) for the latest information.

This Data Sheet states AMD’s current technical specifications regarding the Products described herein. This Data

Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.

For new designs, S29GL032M supercedes Am29LV320MT/B and is the factory-recommended migration path

for this device. Please refer to the S29GLxxxM Family Datasheet for specifications and ordering information.

Am29LV320MT/B

32 Megabit (2 M x 16-Bit/4 M x 8-Bit) MirrorBit™

3.0 Volt-only Boot Sector Flash Memory

DISTINCTIVE CHARACTERISTICS

ARCHITECTURAL ADVANTAGES

■Single power supply operation

— 3 V for read, erase, and program operations

■Manufactured on 0.23 µm MirrorBit process

technology

■SecSi™ (Secured Silicon) Sector region

— 128-word/256-byte sector for permanent, secure

identification through an 8-word/16-byte random

Electronic Serial Number, accessible through a

command sequence

— May be programmed and locked at the factory or by

the customer

■Flexible sector architecture

— Sixty-three 32 Kword/64-Kbyte sectors

— Eight 4 Kword/8 Kbyte boot sectors

■Compatibility with JEDEC standards

— Provides pinout and software compatibility for

single-power supply flash, and superior inadvertent

write protection

■Minimum 100,000 erase cycle guarantee per sector

■20-year data retention at 125°C

PERFORMANCE CHARACTERISTICS

■High performance

— 90 ns access time

— 25 ns page read times

— 0.5 s typical sector erase time

— 15 µs typical effective write buffer word programming

time: 16-word/32-byte write buffer reduces overall

programming time for multiple-word/byte updates

— 4-word/8-byte page read buffer

— 16-word/32-byte write buffer

■Low power consumption (typical values at 3.0 V, 5

MHz)

— 13 mA typical active read current

— 50 mA typical erase/program current

— 1 µA typical standby mode current

■Package options

— 48-pin TSOP

— 48-ball Fine-pitch BGA

— 64-ball Fortified BGA

SOFTWARE & HARDWARE FEATURES

■Software features

— Program Suspend & Resume: read other sectors

before programming operation is completed

— Erase Suspend & Resume: read/program other

sectors before an erase operation is completed

— Data# polling & toggle bits provide status

— Unlock Bypass Program command reduces overall

multiple-word programming time

— CFI (Common Flash Interface) compliant: allows host

system to identify and accommodate multiple flash

devices

■Hardware features

— Sector Group Protection: hardware-level method of

preventing write operations within a sector group

— Temporary Sector Unprotect: VID-level method of

changing code in locked sectors

— WP#/ACC input:

Write Protect input (WP#) protects top or bottom two

sectors regardless of sector protection settings

ACC (high voltage) accelerates programming time for

higher throughput during system production

— Hardware reset input (RESET#) resets device

— Ready/Busy# output (RY/BY#) indicates program or

erase cycle completion

2 Am29LV320MT/B

26518C1 / May 4, 2004

DATASHEET

GENERAL DESCRIPTION

The Am29LV320M/TB is a 32 Mbit, 3.0 volt single

power supply flash memory device organized as

2,097,152 words or 4,194,304 bytes. The device has

an 8-bit/16-bit bus and can be programmed either in

the host system or in standard EPROM programmers.

An access time of 90, 100, 110, or 120 ns is available.

Note that each access time has a specific operating

voltage range (VCC) and an I/O voltage range (VIO), as

specified in the Product Selector Guide and the Order-

ing Information sections. The device is offered in a

48-pin TSOP, 48-ball Fine-pitch BGA or 64-ball Forti-

fied BGA package. Each device has separate chip en-

able (CE#), write enable (WE#) and output enable

(OE#) controls.

Each device requires only a single 3.0 volt power

supply for both read and write functions. In addition to

a VCC input, a high-voltage accelerated program

(ACC) function provides shorter programming times

through increased current on the WP#/ACC input. This

feature is intended to facilitate factory throughput dur-

ing system production, but may also be used in the

field if desired.

The device is entirely command set compatible with

the JEDEC single-power-supply Flash standard.

Commands are written to the device using standard

microprocessor write timing. Write cycles also inter-

nally latch addresses and data needed for the pro-

gramming and erase operations.

The sector erase architecture allows memory sec-

tors to be erased and reprogrammed without affecting

the data contents of other sectors. The device is fully

erased when shipped from the factory.

Device programming and erasure are initiated through

command sequences. Once a program or erase oper-

ation has begun, the host system need only poll the

DQ7 (Data# Polling) or DQ6 (toggle) status bits or

monitor the Ready/Busy# (RY/BY#) output to deter-

mine whether the operation is complete. To facilitate

programming, an Unlock Bypass mode reduces com-

mand sequence overhead by requiring only two write

cycles to program data instead of four.

Hardware data protection measures include a low

VCC detector that automatically inhibits write opera-

tions during power transitions. The hardware sector

protection feature disables both program and erase

operations in any combination of sectors of memory.

This can be achieved in-system or via programming

equipment.

The Erase Suspend/Erase Resume feature allows

the host system to pause an erase operation in a given

sector to read or program any other sector and then

complete the erase operation. The Program Sus-

pend/Program Resume feature enables the host sys-

tem to pause a program operation in a given sector to

read any other sector and then complete the program

operation.

The hardware RESET# pin terminates any operation

in progress and resets the device, after which it is then

ready for a new operation. The RESET# pin may be

tied to the system reset circuitry. A system reset would

thus also reset the device, enabling the host system to

read boot-up firmware from the Flash memory device.

The device reduces power consumption in the

standby mode when it detects specific voltage levels

on CE# and RESET#, or when addresses have been

stable for a specified period of time.

The Write Protect (WP#) feature protects the top or

bottom two sectors by asserting a logic low on the

WP#/ACC pin. The protected sector will still be pro-

tected even during accelerated programming.

The SecSi™ (Secured Silicon) Sector provides a

128-word/256-byte area for code or data that can be

permanently protected. Once this sector is protected,

no further changes within the sector can occur.

AMD MirrorBit flash technology combines years of

Flash memory manufacturing experience to produce

the highest levels of quality, reliability and cost effec-

tiveness. The device electrically erases all bits within a

sector simultaneously via hot-hole assisted erase. The

data is programmed using hot electron injection.

26518C1 / May 4, 2004

Am29LV320MT/B 3

DATASHEET

MIRRORBIT 32 MBIT DEVICE FAMILY

RELATED DOCUMENTS

More information on MirrorBit technology and prod-

ucts, and other documents relating to this device such

as white papers, application notes, simulation models,

and FAQs are available via the internet at

www.amd.com. Type or paste in the following URL in a

web browser:

http://www.amd.com/us-en/FlashMemory/ProductIn-

formation/0,37_1447_2248,00.html.

Device Bus Sector Architecture Packages VIO RY/BY# WP#, ACC WP# Protection

LV033MU x8 Uniform (64 Kbyte) 40-pin TSOP (std. & rev. pinout),

48-ball FBGA Yes Yes ACC only No WP#

LV320MT/B x8/x16 Boot (8 x 8 Kbyte

at top & bottom)

48-pin TSOP, 48-ball Fine-pitch BGA,

64-ball Fortified BGA No Yes WP#/ACC pin 2 x 8 Kbyte

top or bottom

LV320MH/L x8/x16 Uniform (64 Kbyte) 56-pin TSOP (std. & rev. pinout),

64-ball Fortified BGA Yes Yes WP#/ACC pin 1 x 64 Kbyte

high or low

4 Am29LV320MT/B
26518C1 / May 4, 2004
DATASHEET
TABLE OF CONTENTS
Continuity of Specifications  ...................................................... 1
Continuity of Ordering Part Numbers  ....................................... 1
For More Information  ................................................................ 1
Product Selector Guide . . . . . . . . . . . . . . . . . . . . .  5
Block Diagram  . . . . . . . . . . . . . . . . . . . . . . . . . . . .   5
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . .   6
Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . .  8
Ordering Information . . . . . . . . . . . . . . . . . . . . . . .   9
Device Bus Operations . . . . . . . . . . . . . . . . . . . .   11
Table 1. Device Bus Operations  .....................................................11
Requirements for Reading Array Data  ................................... 11
Writing Commands/Command Sequences  ............................ 12
Automatic Sleep Mode  ........................................................... 13
RESET#: Hardware Reset Pin  ............................................... 13
Output Disable Mode .............................................................. 13
Table 2. Am29LV320MT Top Boot Sector Architecture  ..................13
Table 3. Am29LV320MB Bottom Boot Sector Architecture .............15
Table 4. Autoselect Codes, (High Voltage Method)   .......................17
Sector Group Protection and Unprotection ............................. 18
Table 5. Am29LV320MT Top Boot Sector Protection  .....................18
Table 6. Am29LV320MB Bottom Boot Sector Protection ................18
Write Protect (WP#) ................................................................ 18
Temporary Sector Group Unprotect  ....................................... 19
Figure 1. Temporary Sector Group Unprotect Operation................ 19
Figure 2. In-System Sector Group Protect/Unprotect Algorithms ... 20
SecSi (Secured Silicon) Sector Flash Memory Region  .......... 21
Table 7. SecSi Sector Contents ......................................................21
Figure 3. SecSi Sector Protect Verify.............................................. 22
Hardware Data Protection  ...................................................... 22
Common Flash Memory Interface (CFI) . . . . . . .   22
Command Definitions . . . . . . . . . . . . . . . . . . . . .  25
Reading Array Data  ................................................................ 25
Reset Command ..................................................................... 26
Autoselect Command Sequence  ............................................ 26
Enter SecSi Sector/Exit SecSi Sector Command Sequence .. 26
Word/Byte Program Command Sequence  ............................. 26
Figure 4. Write Buffer Programming Operation............................... 29
Figure 5. Program Operation .......................................................... 30
Program Suspend/Program Resume Command Sequence ... 30
Figure 6. Program Suspend/Program Resume............................... 31
Chip Erase Command Sequence ........................................... 31
Sector Erase Command Sequence  ........................................ 31
Figure 7. Erase Operation............................................................... 32
Erase Suspend/Erase Resume Commands ........................... 32
Write Operation Status  . . . . . . . . . . . . . . . . . . . .   35
DQ7: Data# Polling ................................................................. 35
Figure 8. Data# Polling Algorithm ................................................... 35
DQ6: Toggle Bit I  .................................................................... 36
Figure 9. Toggle Bit Algorithm......................................................... 37
DQ2: Toggle Bit II  ................................................................... 37
Reading Toggle Bits DQ6/DQ2 ............................................... 37
DQ5: Exceeded Timing Limits  ................................................ 38
DQ3: Sector Erase Timer  ....................................................... 38
DQ1: Write-to-Buffer Abort  ..................................................... 38
Table 14. Write Operation Status ................................................... 38
Absolute Maximum Ratings. . . . . . . . . . . . . . . . .  39
Figure 10.  Maximum Negative Overshoot Waveform ...................  39
Figure 11.  Maximum Positive Overshoot Waveform.....................  39
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . .  40
Test Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . .  41
Figure 12.  Test Setup....................................................................  41
Table 15. Test Specifications  ......................................................... 41
Key to Switching Waveforms. . . . . . . . . . . . . . . .  41
Figure 13. Input Waveforms and
Measurement Levels......................................................................  41
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . .  42
Read-Only Operations  ........................................................... 42
Figure 14. Read Operation Timings ...............................................  42
Figure 15. Page Read Timings ......................................................  43
Hardware Reset (RESET#)  .................................................... 44
Figure 16. Reset Timings ...............................................................  44
Erase and Program Operations .............................................. 45
Figure 17. Program Operation Timings..........................................  46
Figure 18. Accelerated Program Timing Diagram..........................  46
Figure 19. Chip/Sector Erase Operation Timings ..........................  47
Figure 20. Data# Polling Timings (During Embedded Algorithms).  48
Figure 21. Toggle Bit Timings (During Embedded Algorithms)......  49
Figure 22. DQ2 vs. DQ6.................................................................  49
Temporary Sector Unprotect  .................................................. 50
Figure 23. Temporary Sector Group Unprotect Timing Diagram ...  50
Figure 24. Sector Group Protect and Unprotect Timing Diagram ..  51
Alternate CE# Controlled Erase and Program Operations  ..... 52
Figure 25. Alternate CE# Controlled Write (Erase/Program)
Operation Timings..........................................................................  53
Erase And Programming Performance. . . . . . . .  54
Latchup Characteristics . . . . . . . . . . . . . . . . . . . .  54
TSOP Pin and BGA Package Capacitance . . . . .  55
Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . .  55
Physical Dimensions  . . . . . . . . . . . . . . . . . . . . . .  56
TS 048—48-Pin Standard Pinout Thin Small Outline Package 
(TSOP) ................................................................................... 56
FBC048—48-Ball Fine-pitch Ball Grid Array (BGA) 
9 x 8 mm Package .................................................................. 57
LAA064—64-Ball Fortified Ball Grid Array (BGA) 
13 x 11 mm Package .............................................................. 58
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . .  59

26518C1 / May 4, 2004

Am29LV320MT/B 5

DATASHEET

PRODUCT SELECTOR GUIDE

Note: See “AC Characteristics” for full specifications.

BLOCK DIAGRAM

Part Number Am29LV320MT/B

Speed Option

VCC = 3.0–3.6 V 90R 95R 100R 110R 120R

VCC = 2.7–3.6 V 100 110 120

Max. Access Time (ns) 90 95 100 110 120

Max. CE# Access Time (ns) 90 95 100 110 120

Max. Page access time (tPAC C ) 25303030403040

Max. OE# Access Time (ns) 25 30 30 30 40 30 40

Input/Output

Buffers

X-Decoder

Y-Decoder

Chip Enable

Output Enable

Logic

Erase Voltage

Generator

PGM Voltage

Generator

Timer

VCC Detector

State

Control

Command

VCC

VSS

WE#

WP#/ACC

BYTE#

CE#

OE#

STB

DQ0

–

DQ15 (A-1)

Sector Switches

RY/BY#

RESET#

Data

Latch

Y-Gating

Cell Matrix

Address Latch

A20–A0

6 Am29LV320MT/B

26518C1 / May 4, 2004

DATASHEET

CONNECTION DIAGRAMS

A15

A18

A14

A13

A12

A11

A10

A19

A20

WE#

RESET#

WP#/ACC

RY/BY#

A17

A16

DQ2

BYTE#

VSS

DQ15/A-1

DQ7

DQ14

DQ6

DQ13

DQ9

DQ1

DQ8

DQ0

OE#

VSS

CE#

DQ5

DQ12

DQ4

VCC

DQ11

DQ3

DQ10

A1 B1 C1 D1 E1 F1 G1 H1

A2 B2 C2 D2 E2 F2 G2 H2

A3 B3 C3 D3 E3 F3 G3 H3

A4 B4 C4 D4 E4 F4 G4 H4

A5 B5 C5 D5 E5 F5 G5 H5

A6 B6 C6 D6 E6 F6 G6 H6

DQ15/A-1 VSSBYTE#A16A15A14A12A13

DQ13 DQ6DQ14DQ7A11A10A8A9

VCC DQ4DQ12DQ5A19NCRESET#WE#

DQ11 DQ3DQ10DQ2A20A18WP#/ACCRY/BY#

DQ9 DQ1DQ8DQ0A5A6A17A7

OE# VSSCE#A0A1A2A4A3

48-Pin Standard TSOP

48-ball Fine-pitch BGA

Top View, Balls Facing Down

26518C1 / May 4, 2004

Am29LV320MT/B 7

DATASHEET

CONNECTION DIAGRAMS

Special Package Handling Instructions

Special handling is required for Flash Memory products

in molded packages (TSOP and BGA). The package

and/or data integrity may be compromised if the

package body is exposed to temperatures above 150°C

for prolonged periods of time.

B3 C3 D3 E3 F3 G3 H3

B4 C4 D4 E4 F4 G4 H4

B5 C5 D5 E5 F5 G5 H5

B6 C6 D6 E6 F6 G6 H6

B7 C7 D7 E7 F7 G7 H7

B8 C8 D8 E8 F8 G8 H8

NCNCNCVSS

NCNCNC

VSS

DQ15/A-1BYTE#A16A15A14A12

DQ6

DQ13DQ14DQ7A11A10A8

DQ4VCC

DQ12DQ5A19NCRESET#

DQ3DQ11DQ10DQ2A20A18WP#/ACC

DQ1DQ9DQ8DQ0A5A6A17

A13

WE#

RY/BY#

B2 C2 D2 E2 F2 G2 H2

VSS

OE#CE#A0A1A2A4

B1 C1 D1 E1 F1 G1 H1

NCNCNCNCNCNCNC

64-Ball Fortified BGA

Top View, Balls Facing Down

8 Am29LV320MT/B

26518C1 / May 4, 2004

DATASHEET

PIN DESCRIPTION

A20–A0 = 21 Address inputs

DQ14–DQ0 = 15 Data inputs/outputs

DQ15/A-1 = DQ15 (Data input/output, word mode),

A-1 (LSB Address input, byte mode)

CE# = Chip Enable input

OE# = Output Enable input

WE# = Write Enable input

WP#/ACC = Hardware Write Protect input/Pro-

gramming Acceleration input

RESET# = Hardware Reset Pin input

RY/BY# = Ready/Busy output

BYTE# = Selects 8-bit or 16-bit mode

VCC = 3.0 volt-only single power supply

(see Product Selector Guide for

speed options and voltage

supply tolerances)

VSS = Device Ground

NC = Pin Not Connected Internally

LOGIC SYMBOL

16 or 8

DQ15–DQ0

(A-1)

A20–A0

CE#

OE#

WE#

RESET#

RY/BY#

WP#/ACC

BYTE#

26518C1 / May 4, 2004

Am29LV320MT/B 9

DATASHEET

ORDERING INFORMATION

Standard Products in TSOP Packages

The order number (Valid Combination) for products in TSOP packages is formed by the following designators:

Valid Combinations

Valid Combinations list configurations planned to be supported in vol-

ume for this device. Consult the local AMD sales office to confirm

availability of specific valid combinations and to check on newly re-

leased combinations.

Am29LV320M T 120R E I

TEMPERATURE RANGE

C = Commercial (0°C to +70°C)

I = Industrial (–40°C to +85°C)

PACKAGE TYPE

E = 48-Pin Thin Small Outline Package (TSOP) Standard Pinout (TS 048)

SPEED OPTION

See Product Selector Guide and Valid Combinations

SECTOR ARCHITECTURE AND WP# PROTECTION (WP# = VIL)

T = Top boot sector device, top two address sectors protected

B = Bottom boot sector device, bottom two address sectors protected

DEVICE NUMBER/DESCRIPTION

Am29LV320MT/B

32 Megabit (2 M x 16-Bit/4 M x 8-Bit) MirrorBit™ Boot Sector Flash Memory

3.0 Volt-only Read, Program, and Erase

Valid Combinations for

TSOP Package

Speed

(ns)

VCC

Range

Am29LV320MT90R,

Am29LV320MB90R EC,

3.0–3.6 V

Am29LV320MT95R,

Am29LV320MB95R 95

Am29LV320MT100R,

Am29LV320MB100R

100

Am29LV320MT110R,

Am29LV320MB110R 110

Am29LV320MT120R,

Am29LV320MB120R 120

Am29LV320MT100,

Am29LV320MB100 100

2.7–3.6 V

Am29LV320MT110,

Am29LV320MB110 110

Am29LV320MT120,

Am29LV320MB120 120

10 Am29LV320MT/B

26518C1 / May 4, 2004

DATASHEET

ORDERING INFORMATION

Standard Products in BGA Packages

The order number (Valid Combination) for products in BGA packages is formed by the following designators:

Valid Combinations

Valid Combinations list configurations planned to be supported in vol-

ume for this device. Consult the local AMD sales office to confirm

availability of specific valid combinations and to check on newly re-

leased combinations.

Am29LV320M T 120R PC I

TEMPERATURE RANGE

C = Commercial (0°C to +70°C)

I = Industrial (–40°C to +85°C)

PACKAGE TYPE

PC = 64-Ball Fortified Ball Grid Array (FBGA),

1.0 mm pitch, 13 x 11 mm package (LAA064)

WC = 48-Ball Fine Pitch Ball Grid Array (FBGA),

0.80 mm pitch, 9 x 8 mm package (FBC048)

SPEED OPTION

See Product Selector Guide and Valid Combinations

SECTOR ARCHITECTURE AND WP# PROTECTION (WP# = VIL)

T = Top boot sector device, top two address sectors protected

B = Bottom boot sector device, bottom two address sectors protected

DEVICE NUMBER/DESCRIPTION

Am29LV320MT/B

32 Megabit (2 M x 16-Bit/4 M x 8-Bit) MirrorBit™ Boot Sector Flash Memory

3.0 Volt-only Read, Program, and Erase

Valid Combinations for

BGA Packages Speed

(ns)

VCC

Range

Order Number Package

Marking

Am29LV320MT95R WCC,

WCI

L320MT95QC,

L320MT95QI 95 3.0–

3.6 V

Am29LV320MB95R L320MB95QC,

L320MB95QI

Am29LV320MT90R

WCC,

WCI

L320MT90QC,

L320MT90QI

90 3.0–

3.6 V

PCI L320MT90NI

Am29LV320MB90R

WCC,

WCI

L320MB90QC,

L320MB90QI

PCI L320MB10NI

Am29LV320MT100R WCI L320MT10QI

100 3.0–

3.6 V

PCI L320MT10NI

Am29LV320MB100R WCI L320MB10QI

PCI L320MB10NI

Am29LV320MT110R WCI L320MT11QI

110 3.0–

3.6 V

PCI L320MT11NI

Am29LV320MB110R WCI L320MB11QI

PCI L320MB11NI

Am29LV320MT120R WCI L320MT12QI

120 3.0–

3.6 V

PCI L320MT12NI

Am29LV320MB120R WCI L320MB12QI

PCI L320MB12NI

Valid Combinations for

BGA Packages Speed

(ns)

VCC

Range

Order Number Package Marking

Am29LV320MT100 WCI L320MT10UI

100

2.7–

3.6 V

PCI L320MT10PI

Am29LV320MB100 WCI L320MB10UI

PCI L320MB10PI

Am29LV320MT110 WCI L320MT11UI

110

PCI L320MT11PI

Am29LV320MB110 WCI L320MB11UI

PCI L320MB11PI

Am29LV320MT120 WCI L320MT12UI

120

PCI L320MT12PI

Am29LV320MB120 WCI L320MB12UI

PCI L320MB12PI

26518C1 / May 4, 2004
Am29LV320MT/B 11
DATASHEET
DEVICE BUS OPERATIONS
This section describes the requirements and use of
the device bus operations, which are initiated through
the internal command register. The command register
itself does not occupy any addressable memory loca-
tion. The register is a latch used to store the com-
mands, along with the address and data information
needed to execute the command. The contents of the
register serve as inputs to the internal state machine.
The state machine outputs dictate the function of the
device. Ta ble 1  lists the device bus operations, the in-
puts and control levels they require, and the resulting
output. The following subsections describe each of
these operations in further detail.
Table 1. Device Bus Operations
Legend: L = Logic Low = V
IL
, H = Logic High = V
IH
, V
ID
 = 11.5–12.5
 
V,  V
HH
 = 11.5–12.5
 
V, X = Don’t Care, SA = Sector Address, 
A
IN
 = Address In, D
IN
 = Data In, D
OUT
 = Data Out
Notes:
1. Addresses are A20:A0 in word mode; A20:A-1 in byte mode. Sector addresses are A20:A12 in both modes.
2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector Group 
Protection and Unprotection” section.
3. If WP# = V
IL
, the first or last sector remains protected. If WP# = V
IH
, the top two or bottom two sectors will be protected or 
unprotected as determined by the method described in “Sector Group Protection and Unprotection”. All sectors are unprotected 
when shipped from the factory (The SecSi Sector may be factory protected depending on version ordered.)
4. D
IN
 or D
OUT
 as required by command sequence, data polling, or sector protect algorithm (see Figure 2).
Word/Byte Configuration
The BYTE# pin controls whether the device data I/O
pins operate in the byte or word configuration. If the
BYTE# pin is set at logic ‘1’, the device is in word con-
figuration, DQ0–DQ15 are active and controlled by
CE# and OE#.
If the BYTE# pin is set at logic ‘0’, the device is in byte
configuration, and only data I/O pins DQ0–DQ7 are
active and controlled by CE# and OE#. The data I/O
pins DQ8–DQ14 are tri-stated, and the DQ15 pin is
used as an input for the LSB (A-1) address function.
Requirements for Reading Array Data
To read array data from the outputs, the system must
drive the CE# and OE# pins to VIL. CE# is the power
control and selects the device. OE# is the output con-
trol and gates array data to the output pins. WE#
should remain at VIH.
Operation CE# OE# WE# RESET# WP# ACC
Addresses
(Note 2)
DQ0–
DQ7
DQ8–DQ15
BYTE#
= VIH
BYTE# 
= VIL
Read L L H H XL/H AIN DOUT DOUT DQ8–DQ14
= High-Z, 
DQ15 = A-1
Write (Program/Erase) L H L H (Note 3) L/H AIN (Note 4) (Note 4)
Accelerated Program L H L H (Note 3) VHH AIN (Note 4) (Note 4)
Standby VCC ± 
0.3 V XX
VCC ± 
0.3 V XH XHigh-Z High-Z High-Z
Output Disable L H H H XL/H XHigh-Z High-Z High-Z
Reset X X X L XL/H XHigh-Z High-Z High-Z
Sector Group Protect 
(Note 2) LHL V
ID HL/H
SA, A6 =L, 
A3=L, A2=L, 
A1=H, A0=L
(Note 4) X X
Sector Group Unprotect 
(Note 2) LHL V
ID HL/H
SA, A6=H, 
A3=L, A2=L, 
A1=H, A0=L
(Note 4) X X
Temporary Sector Group 
Unprotect XXX V
ID HL/H AIN (Note 4) (Note 4) High-Z

12 Am29LV320MT/B
26518C1 / May 4, 2004
DATASHEET
The internal state machine is set for reading array data
upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory
content occurs during the power transition. No com-
mand is necessary in this mode to obtain array data.
Standard microprocessor read cycles that assert valid
addresses on the device address inputs produce valid
data on the device data outputs. The device remains
enabled for read access until the command register
contents are altered.
See “Reading Array Data” for more information. Refer
to the AC Read-Only Operations table for timing speci-
fications and to Figure 14 for the timing diagram. Refer
to the DC Characteristics table for the active current
specification on reading array data.
Page Mode Read
The device is capable of fast page mode read and is
compatible with the page mode Mask ROM read oper-
ation. This mode provides faster read access speed
for random locations within a page. The page size of
the device is 4 words/8 bytes. The appropriate page is
selected by the higher address bits A(max)–A2. Ad-
dress bits A1–A0 in word mode (A1–A-1 in byte mode)
determine the specific word within a page. This is an
asynchronous operation; the microprocessor supplies
the specific word location.
The random or initial page access is equal to tACC or
tCE and subsequent page read accesses (as long as
the locations specified by the microprocessor falls
within that page) is equivalent to tPA C C. When CE# is
deasserted and reasserted for a subsequent access,
the access time is tACC or tCE. Fast page mode ac-
cesses are obtained by keeping the “read-page ad-
dresses” constant and changing the “intra-read page”
addresses.
Writing Commands/Command Sequences
To write a command or command sequence (which in-
cludes programming data to the device and erasing
sectors of memory), the system must drive WE# and
CE# to VIL, and OE# to VIH.
The device features an Unlock Bypass mode to facili-
tate faster programming. Once the device enters the
Unlock Bypass mode, only two write cycles are re-
quired to program a word or byte, instead of four. The
“Word/Byte Program Command Sequence” section
has details on programming data to the device using
both standard and Unlock Bypass command se-
quences.
An erase operation can erase one sector, multiple sec-
tors, or the entire device. Tables 3 and 2 indicates the
address space that each sector occupies.
Refer to the DC Characteristics table for the active
current specification for the write mode. The AC Char-
acteristics section contains timing specification tables
and timing diagrams for write operations.
Write Buffer
Write Buffer Programming allows the system to write a
maximum of 16 words/32 bytes in one programming
operation. This results in faster effective programming
time than the standard programming algorithms. See
“Write Buffer” for more information.
Accelerated Program Operation
The device offers accelerated program operations
through the ACC function. This is one of two functions
provided by the WP#/ACC pin. This function is prima-
rily intended to allow faster manufacturing throughput
at the factory. 
If the system asserts VHH on this pin, the device auto-
matically enters the aforementioned Unlock Bypass
mode, temporarily unprotects any protected sectors,
and uses the higher voltage on the pin to reduce the
time required for program operations. The system
would use a two-cycle program command sequence
as required by the Unlock Bypass mode. Removing
VHH from the WP#/ACC pin returns the device to nor-
mal operation. 
Note that the WP#/ACC pin must not be
at V
HH
 for operations other than accelerated program-
ming, or device damage may result.
 
In addition, no ex-
ternal pullup is necessary since the WP#/ACC pin has
internal pullup to V
CC
.
Autoselect Functions
If the system writes the autoselect command se-
quence, the device enters the autoselect mode. The
system can then read autoselect codes from the inter-
nal register (which is separate from the memory array)
on DQ7–DQ0. Standard read cycle timings apply in
this mode. Refer to the Autoselect Mode and Autose-
lect Command Sequence sections for more informa-
tion.
Standby Mode
When the system is not reading or writing to the de-
vice, it can place the device in the standby mode. In
this mode, current consumption is greatly reduced,
and the outputs are placed in the high impedance
state, independent of the OE# input. 
The device enters the CMOS standby mode when the
CE# and RESET# pins are both held at VCC ± 0.3 V.
(Note that this is a more restricted voltage range than
VIH.) If CE# and RESET# are held at VIH, but not within
VCC ± 0.3 V, the device will be in the standby mode,
but the standby current will be greater. The device re-
quires standard access time (tCE) for read access
when the device is in either of these standby modes,
before it is ready to read data.

26518C1 / May 4, 2004

Am29LV320MT/B 13

DATASHEET

If the device is deselected during erasure or program-

ming, the device draws active current until the

operation is completed.

Refer to the DC Characteristics table for the standby

current specification.

Automatic Sleep Mode

The automatic sleep mode minimizes Flash device en-

ergy consumption. The device automatically enables

this mode when addresses remain stable for tACC +

30 ns. The automatic sleep mode is independent of

the CE#, WE#, and OE# control signals. Standard ad-

dress access timings provide new data when ad-

dresses are changed. While in sleep mode, output

data is latched and always available to the system.

Refer to the DC Characteristics table for the automatic

sleep mode current specification.

RESET#: Hardware Reset Pin

The RESET# pin provides a hardware method of re-

setting the device to reading array data. When the RE-

SET# pin is driven low for at least a period of tRP

, the

device immediately terminates any operation in

progress, tristates all output pins, and ignores all

read/write commands for the duration of the RESET#

pulse. The device also resets the internal state ma-

chine to reading array data. The operation that was in-

terrupted should be reinitiated once the device is

ready to accept another command sequence, to en-

sure data integrity.

Current is reduced for the duration of the RESET#

pulse. When RESET# is held at VSS±0.3 V, the device

draws CMOS standby current (ICC4). If RESET# is held

at VIL but not within VSS±0.3 V, the standby current will

be greater.

The RESET# pin may be tied to the system reset cir-

cuitry. A system reset would thus also reset the Flash

memory, enabling the system to read the boot-up firm-

ware from the Flash memory.

Refer to the AC Characteristics tables for RESET# pa-

rameters and to Figure 16 for the timing diagram.

Output Disable Mode

When the OE# input is at VIH, output from the device is

disabled. The output pins are placed in the high

impedance state.

Table 2. Am29LV320MT Top Boot Sector Architecture

Sector Sector Address

A20–A12

Sector Size

(Kbytes/Kwords)

(x8)

Address Range

(x16)

Address Range

SA0 000000xxx 64/32 000000h–00FFFFh 00000h–07FFFh

SA1 000001xxx 64/32 010000h–01FFFFh 08000h–0FFFFh

SA2 000010xxx 64/32 020000h–02FFFFh 10000h–17FFFh

SA3 000011xxx 64/32 030000h–03FFFFh 18000h–1FFFFh

SA4 000100xxx 64/32 040000h–04FFFFh 20000h–27FFFh

SA5 000101xxx 64/32 050000h–05FFFFh 28000h–2FFFFh

SA6 000110xxx 64/32 060000h–06FFFFh 30000h–37FFFh

SA7 000111xxx 64/32 070000h–07FFFFh 38000h–3FFFFh

SA8 001000xxx 64/32 080000h–08FFFFh 40000h–47FFFh

SA9 001001xxx 64/32 090000h–09FFFFh 48000h–4FFFFh

SA10 001010xxx 64/32 0A0000h–0AFFFFh 50000h–57FFFh

SA11 001011xxx 64/32 0B0000h–0BFFFFh 58000h–5FFFFh

SA12 001100xxx 64/32 0C0000h–0CFFFFh 60000h–67FFFh

SA13 001101xxx 64/32 0D0000h–0DFFFFh 68000h–6FFFFh

SA14 001101xxx 64/32 0E0000h–0EFFFFh 70000h–77FFFh

SA15 001111xxx 64/32 0F0000h–0FFFFFh 78000h–7FFFFh

SA16 010000xxx 64/32 100000h–00FFFFh 80000h–87FFFh

SA17 010001xxx 64/32 110000h–11FFFFh 88000h–8FFFFh

SA18 010010xxx 64/32 120000h–12FFFFh 90000h–97FFFh

SA19 010011xxx 64/32 130000h–13FFFFh 98000h–9FFFFh

SA20 010100xxx 64/32 140000h–14FFFFh A0000h–A7FFFh

SA21 010101xxx 64/32 150000h–15FFFFh A8000h–AFFFFh

SA22 010110xxx 64/32 160000h–16FFFFh B0000h–B7FFFh

SA23 010111xxx 64/32 170000h–17FFFFh B8000h–BFFFFh

SA24 011000xxx 64/32 180000h–18FFFFh C0000h–C7FFFh

SA25 011001xxx 64/32 190000h–19FFFFh C8000h–CFFFFh

SA26 011010xxx 64/32 1A0000h–1AFFFFh D0000h–D7FFFh

SA27 011011xxx 64/32 1B0000h–1BFFFFh D8000h–DFFFFh

14 Am29LV320MT/B

26518C1 / May 4, 2004

DATASHEET

SA28 011000xxx 64/32 1C0000h–1CFFFFh E0000h–E7FFFh

SA29 011101xxx 64/32 1D0000h–1DFFFFh E8000h–EFFFFh

SA30 011110xxx 64/32 1E0000h–1EFFFFh F0000h–F7FFFh

SA31 011111xxx 64/32 1F0000h–1FFFFFh F8000h–FFFFFh

SA32 100000xxx 64/32 200000h–20FFFFh F9000h–107FFFh

SA33 100001xxx 64/32 210000h–21FFFFh 108000h–10FFFFh

SA34 100010xxx 64/32 220000h–22FFFFh 110000h–117FFFh

SA35 101011xxx 64/32 230000h–23FFFFh 118000h–11FFFFh

SA36 100100xxx 64/32 240000h–24FFFFh 120000h–127FFFh

SA37 100101xxx 64/32 250000h–25FFFFh 128000h–12FFFFh

SA38 100110xxx 64/32 260000h–26FFFFh 130000h–137FFFh

SA39 100111xxx 64/32 270000h–27FFFFh 138000h–13FFFFh

SA40 101000xxx 64/32 280000h–28FFFFh 140000h–147FFFh

SA41 101001xxx 64/32 290000h–29FFFFh 148000h–14FFFFh

SA42 101010xxx 64/32 2A0000h–2AFFFFh 150000h–157FFFh

SA43 101011xxx 64/32 2B0000h–2BFFFFh 158000h–15FFFFh

SA44 101100xxx 64/32 2C0000h–2CFFFFh 160000h–167FFFh

SA45 101101xxx 64/32 2D0000h–2DFFFFh 168000h–16FFFFh

SA46 101110xxx 64/32 2E0000h–2EFFFFh 170000h–177FFFh

SA47 101111xxx 64/32 2F0000h–2FFFFFh 178000h–17FFFFh

SA48 110000xxx 64/32 300000h–30FFFFh 180000h–187FFFh

SA49 110001xxx 64/32 310000h–31FFFFh 188000h–18FFFFh

SA50 110010xxx 64/32 320000h–32FFFFh 190000h–197FFFh

SA51 110011xxx 64/32 330000h–33FFFFh 198000h–19FFFFh

SA52 100100xxx 64/32 340000h–34FFFFh 1A0000h–1A7FFFh

SA53 110101xxx 64/32 350000h–35FFFFh 1A8000h–1AFFFFh

SA54 110110xxx 64/32 360000h–36FFFFh 1B0000h–1B7FFFh

SA55 110111xxx 64/32 370000h–37FFFFh 1B8000h–1BFFFFh

SA56 111000xxx 64/32 380000h–38FFFFh 1C0000h–1C7FFFh

SA57 111001xxx 64/32 390000h–39FFFFh 1C8000h–1CFFFFh

SA58 111010xxx 64/32 3A0000h–3AFFFFh 1D0000h–1D7FFFh

SA59 111011xxx 64/32 3B0000h–3BFFFFh 1D8000h–1DFFFFh

SA60 111100xxx 64/32 3C0000h–3CFFFFh 1E0000h–1E7FFFh

SA61 111101xxx 64/32 3D0000h–3DFFFFh 1E8000h–1EFFFFh

SA62 111110xxx 64/32 3E0000h–3EFFFFh 1F0000h–1F7FFFh

SA63 111111000 8/4 3F0000h–3F1FFFh 1F8000h–1F8FFFh

SA64 111111001 8/4 3F2000h–3F3FFFh 1F9000h–1F9FFFh

SA65 111111010 8/4 3F4000h–3F5FFFh 1FA000h–1FAFFFh

SA66 111111011 8/4 3F6000h–3F7FFFh 1FB000h–1FBFFFh

SA67 111111100 8/4 3F8000h–3F9FFFh 1FC000h–1FCFFFh

SA68 111111101 8/4 3FA000h–3FBFFFh 1FD000h–1FDFFFh

SA69 111111110 8/4 3FC000h–3FDFFFh 1FE000h–1FEFFFh

SA70 111111111 8/4 3FE000h–3FFFFFh 1FF000h–1FFFFFh

Table 2. Am29LV320MT Top Boot Sector Architecture (Continued)

Sector Sector Address

A20–A12

Sector Size

(Kbytes/Kwords)

(x8)

Address Range

(x16)

Address Range

26518C1 / May 4, 2004

Am29LV320MT/B 15

DATASHEET

Table 3. Am29LV320MB Bottom Boot Sector Architecture

Sector Sector Address

A20–A12

Sector Size

(Kbytes/Kwords)

(x8)

Address Range

(x16)

Address Range

SA0 000000000 8/4 000000h–001FFFh 00000h–00FFFh

SA1 000000001 8/4 002000h–003FFFh 01000h–01FFFh

SA2 000000010 8/4 004000h–005FFFh 02000h–02FFFh

SA3 000000011 8/4 006000h–007FFFh 03000h–03FFFh

SA4 000000100 8/4 008000h–009FFFh 04000h–04FFFh

SA5 000000101 8/4 00A000h–00BFFFh 05000h–05FFFh

SA6 000000110 8/4 00C000h–00DFFFh 06000h–06FFFh

SA7 000000111 8/4 00E000h–00FFFFFh 07000h–07FFFh

SA8 000001xxx 64/32 010000h–01FFFFh 08000h–0FFFFh

SA9 000010xxx 64/32 020000h–02FFFFh 10000h–17FFFh

SA10 000011xxx 64/32 030000h–03FFFFh 18000h–1FFFFh

SA11 000100xxx 64/32 040000h–04FFFFh 20000h–27FFFh

SA12 000101xxx 64/32 050000h–05FFFFh 28000h–2FFFFh

SA13 000110xxx 64/32 060000h–06FFFFh 30000h–37FFFh

SA14 000111xxx 64/32 070000h–07FFFFh 38000h–3FFFFh

SA15 001000xxx 64/32 080000h–08FFFFh 40000h–47FFFh

SA16 001001xxx 64/32 090000h–09FFFFh 48000h–4FFFFh

SA17 001010xxx 64/32 0A0000h–0AFFFFh 50000h–57FFFh

SA18 001011xxx 64/32 0B0000h–0BFFFFh 58000h–5FFFFh

SA19 001100xxx 64/32 0C0000h–0CFFFFh 60000h–67FFFh

SA20 001101xxx 64/32 0D0000h–0DFFFFh 68000h–6FFFFh

SA21 001101xxx 64/32 0E0000h–0EFFFFh 70000h–77FFFh

SA22 001111xxx 64/32 0F0000h–0FFFFFh 78000h–7FFFFh

SA23 010000xxx 64/32 100000h–00FFFFh 80000h–87FFFh

SA24 010001xxx 64/32 110000h–11FFFFh 88000h–8FFFFh

SA25 010010xxx 64/32 120000h–12FFFFh 90000h–97FFFh

SA26 010011xxx 64/32 130000h–13FFFFh 98000h–9FFFFh

SA27 010100xxx 64/32 140000h–14FFFFh A0000h–A7FFFh

SA28 010101xxx 64/32 150000h–15FFFFh A8000h–AFFFFh

SA29 010110xxx 64/32 160000h–16FFFFh B0000h–B7FFFh

SA30 010111xxx 64/32 170000h–17FFFFh B8000h–BFFFFh

SA31 011000xxx 64/32 180000h–18FFFFh C0000h–C7FFFh

SA32 011001xxx 64/32 190000h–19FFFFh C8000h–CFFFFh

SA33 011010xxx 64/32 1A0000h–1AFFFFh D0000h–D7FFFh

SA34 011011xxx 64/32 1B0000h–1BFFFFh D8000h–DFFFFh

SA35 011000xxx 64/32 1C0000h–1CFFFFh E0000h–E7FFFh

SA36 011101xxx 64/32 1D0000h–1DFFFFh E8000h–EFFFFh

SA37 011110xxx 64/32 1E0000h–1EFFFFh F0000h–F7FFFh

SA38 011111xxx 64/32 1F0000h–1FFFFFh F8000h–FFFFFh

SA39 100000xxx 64/32 200000h–20FFFFh F9000h–107FFFh

SA40 100001xxx 64/32 210000h–21FFFFh 108000h–10FFFFh

SA41 100010xxx 64/32 220000h–22FFFFh 110000h–117FFFh

SA42 101011xxx 64/32 230000h–23FFFFh 118000h–11FFFFh

SA43 100100xxx 64/32 240000h–24FFFFh 120000h–127FFFh

SA44 100101xxx 64/32 250000h–25FFFFh 128000h–12FFFFh

SA45 100110xxx 64/32 260000h–26FFFFh 130000h–137FFFh

SA46 100111xxx 64/32 270000h–27FFFFh 138000h–13FFFFh

SA47 101000xxx 64/32 280000h–28FFFFh 140000h–147FFFh

SA48 101001xxx 64/32 290000h–29FFFFh 148000h–14FFFFh

SA49 101010xxx 64/32 2A0000h–2AFFFFh 150000h–157FFFh

SA50 101011xxx 64/32 2B0000h–2BFFFFh 158000h–15FFFFh

SA51 101100xxx 64/32 2C0000h–2CFFFFh 160000h–167FFFh

SA52 101101xxx 64/32 2D0000h–2DFFFFh 168000h–16FFFFh

SA53 101110xxx 64/32 2E0000h–2EFFFFh 170000h–177FFFh

16 Am29LV320MT/B

26518C1 / May 4, 2004

DATASHEET

Note: The address range is A20:A-1 in byte mode (BYTE# = V

) or A20:A0 in word mode (BYTE# = V

)

SA54 101111xxx 64/32 2F0000h–2FFFFFh 178000h–17FFFFh

SA55 110000xxx 64/32 300000h–30FFFFh 180000h–187FFFh

SA56 110001xxx 64/32 310000h–31FFFFh 188000h–18FFFFh

SA57 110010xxx 64/32 320000h–32FFFFh 190000h–197FFFh

SA58 110011xxx 64/32 330000h–33FFFFh 198000h–19FFFFh

SA59 100100xxx 64/32 340000h–34FFFFh 1A0000h–1A7FFFh

SA60 110101xxx 64/32 350000h–35FFFFh 1A8000h–1AFFFFh

SA61 110110xxx 64/32 360000h–36FFFFh 1B0000h–1B7FFFh

SA62 110111xxx 64/32 370000h–37FFFFh 1B8000h–1BFFFFh

SA63 111000xxx 64/32 380000h–38FFFFh 1C0000h–1C7FFFh

SA64 111001xxx 64/32 390000h–39FFFFh 1C8000h–1CFFFFh

SA65 111010xxx 64/32 3A0000h–3AFFFFh 1D0000h–1D7FFFh

SA66 111011xxx 64/32 3B0000h–3BFFFFh 1D8000h–1DFFFFh

SA67 111100xxx 64/32 3C0000h–3CFFFFh 1E0000h–1E7FFFh

SA68 111101xxx 64/32 3D0000h–3DFFFFh 1E8000h–1EFFFFh

SA69 111110xxx 64/32 3E0000h–3EFFFFh 1F0000h–1F7FFFh

SA70 111111xxx 64/32 3F0000h–3FFFFFh 1F8000h–1FFFFFh

Table 3. Am29LV320MB Bottom Boot Sector Architecture (Continued)

Sector Sector Address

A20–A12

Sector Size

(Kbytes/Kwords)

(x8)

Address Range

(x16)

Address Range

26518C1 / May 4, 2004
Am29LV320MT/B 17
DATASHEET
Autoselect Mode
The autoselect mode provides manufacturer and de-
vice identification, and sector protection verification,
through identifier codes output on DQ7–DQ0. This
mode is primarily intended for programming equip-
ment to automatically match a device to be pro-
grammed with its corresponding programming
algorithm. However, the autoselect codes can also be
accessed in-system through the command register.
When using programming equipment, the autoselect
mode requires VID on address pin A9. Address pins
A6, A3, A2, A1, and A0 must be as shown in Ta b l e  4 .
In addition, when verifying sector protection, the sector
address must appear on the appropriate highest order
address bits (see Tables 2 and 3). Tabl e  4  shows the
remaining address bits that are don’t care. When all
necessary bits have been set as required, the pro-
gramming equipment may then read the correspond-
ing identifier code on DQ7–DQ0.
To access the autoselect codes in-system, the host
system can issue the autoselect command via the
command register, as shown in Tables 12 and 13. This
method does not require VID. Refer to the Autoselect
Command Sequence section for more information.
Table 4. Autoselect Codes, (High Voltage Method)  
Legend: L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care.
Description CE# OE# WE#
A21
to 
A15
A14
to
A10
A9
A8
to
A7
A6
A5
to
A4
A3
to
A2
A1 A0
DQ8 to DQ15
DQ7 to DQ0
BYTE#
= VIH
BYTE# 
= VIL
Manufacturer ID: AMD L L H X X VID X L X L L L 00 X 01h
Device ID
Cycle 1
LLHXX
VID XL X
LLH 22 X 7Eh
Cycle 2 H H L 22 X 1Ah
Cycle 3 H H H 22 X 00 (bottom boot)
01h (top boot)
Sector Protection 
Verification LLHSAX
VID XL X L H L X X 01h (protected),
00h (unprotected)
SecSi Sector Indicator 
Bit (DQ7), WP# 
protects top two 
address sector
LLHXX
VID XL X L H H X X 98h (factory locked),
18h (not factory locked)
SecSi Sector Indicator 
Bit (DQ7), WP# 
protects bottom two 
address sector
LLHXX
VID XL X L H H X X 88h (factory locked),
08h (not factory locked)

18 Am29LV320MT/B

26518C1 / May 4, 2004

DATASHEET

Sector Group Protection and

Unprotection

The hardware sector group protection feature disables

both program and erase operations in any sector

group. In this device, a sector group consists of four

adjacent sectors that are protected or unprotected at

the same time (see Tables 5 and 6). The hardware

sector group unprotection feature re-enables both pro-

gram and erase operations in previously protected

sector groups. Sector group protection/unprotection

can be implemented via two methods.

Sector protection/unprotection requires VID on the RE-

SET# pin only, and can be implemented either in-sys-

tem or via programming equipment. Figure 2 shows

the algorithms and Figure 24 shows the timing dia-

gram. This method uses standard microprocessor bus

cycle timing. For sector group unprotect, all unpro-

tected sector groups must first be protected prior to

the first sector group unprotect write cycle.

The device is shipped with all sector groups unpro-

tected. AMD offers the option of programming and pro-

tecting sector groups at its factory prior to shipping the

device through AMD’s ExpressFlash™ Service. Con-

tact an AMD representative for details.

It is possible to determine whether a sector group is

protected or unprotected. See the Autoselect Mode

section for details.

Table 5. Am29LV320MT Top Boot

Sector Protection

Write Protect (WP#)

The Write Protect function provides a hardware

method of protecting the top two or bottom two sectors

without using VID. WP# is one of two functions pro-

vided by the WP#/ACC input.

If the system asserts VIL on the WP#/ACC pin, the de-

vice disables program and erase functions in the first

or last sector independently of whether those sectors

were protected or unprotected using the method de-

scribed in “Sector Group Protection and Unprotection”.

Note that if WP#/ACC is at VIL when the device is in

the standby mode, the maximum input load current is

increased. See the table in “DC Characteristics”.

Sector A20–A12

Sector/

Sector Block Size

SA0-SA3 0000XXXXXh 256 (4x64) Kbytes

SA4-SA7 0001XXXXXh 256 (4x64) Kbytes

SA8-SA11 0010XXXXXh 256 (4x64) Kbytes

SA12-SA15 0011XXXXXh 256 (4x64) Kbytes

SA16-SA19 0100XXXXXh 256 (4x64) Kbytes

SA20-SA23 0101XXXXXh 256 (4x64) Kbytes

SA24-SA27 0110XXXXXh 256 (4x64) Kbytes

SA28-SA31 0111XXXXXh 256 (4x64) Kbytes

SA32–SA35 1000XXXXXh, 256 (4x64) Kbytes

SA36–SA39 1001XXXXXh 256 (4x64) Kbytes

SA40–SA43 1010XXXXXh 256 (4x64) Kbytes

SA44–SA47 1011XXXXXh 256 (4x64) Kbytes

SA48–SA51 1100XXXXXh 256 (4x64) Kbytes

SA52-SA55 1101XXXXXh 256 (4x64) Kbytes

SA56-SA59 1110XXXXXh 256 (4x64) Kbytes

SA60-SA62

111100XXXh

111101XXXh

111110XXXh

192 (3x64) Kbytes

SA63 111111000h 8 Kbytes

SA64 111111001h 8 Kbytes

SA65 111111010h 8 Kbytes

SA66 111111011h 8 Kbytes

SA67 111111100h 8 Kbytes

SA68 111111101h 8 Kbytes

SA69 111111110h 8 Kbytes

SA70 111111111h 8 Kbytes

Table 6. Am29LV320MB Bottom Boot

Sector Protection

Sector A20–A12

Sector/

Sector Block Size

SA0 000000000h 8 Kbytes

SA1 000000001h 8 Kbytes

SA2 000000010h 8 Kbytes

SA3 000000011h 8 Kbytes

SA4 000000100h 8 Kbytes

SA5 000000101h 8 Kbytes

SA6 000000110h 8 Kbytes

SA7 000000111h 8 Kbytes

SA8–SA10

000001XXXh,

000010XXXh,

000011XXXh,

192 (3x64) Kbytes

SA11–SA14 0001XXXXXh 256 (4x64) Kbytes

SA15–SA18 0010XXXXXh 256 (4x64) Kbytes

SA19–SA22 0011XXXXXh 256 (4x64) Kbytes

SA23–SA26 0100XXXXXh 256 (4x64) Kbytes

SA27-SA30 0101XXXXXh 256 (4x64) Kbytes

SA31-SA34 0110XXXXXh 256 (4x64) Kbytes

SA35-SA38 0111XXXXXh 256 (4x64) Kbytes

SA39-SA42 1000XXXXXh 256 (4x64) Kbytes

SA43-SA46 1001XXXXXh 256 (4x64) Kbytes

SA47-SA50 1010XXXXXh 256 (4x64) Kbytes

SA51-SA54 1011XXXXXh 256 (4x64) Kbytes

SA55–SA58 1100XXXXXh 256 (4x64) Kbytes

SA59–SA62 1101XXXXXh 256 (4x64) Kbytes

SA63–SA66 1110XXXXXh 256 (4x64) Kbytes

SA67–SA70 1111XXXXXh 256 (4x64) Kbytes

Sector A20–A12

Sector/

Sector Block Size

26518C1 / May 4, 2004

Am29LV320MT/B 19

DATASHEET

If the system asserts VIH on the WP#/ACC pin, the de-

vice reverts to whether the top or bottom two sectors

were previously set to be protected or unprotected

using the method described in “Sector Group Protec-

tion and Unprotection”.

Note: No external pullup is

necessary since the WP#/ACC pin has internal pullup

to V

Temporary Sector Group Unprotect

(Note: In this device, a sector group consists of four adjacent

sectors that are protected or unprotected at the same time

(see Ta b l e 6 ).

This feature allows temporary unprotection of previ-

ously protected sector groups to change data in-sys-

tem. The Sector Group Unprotect mode is activated by

setting the RESET# pin to VID. During this mode, for-

merly protected sector groups can be programmed or

erased by selecting the sector group addresses. Once

VID is removed from the RESET# pin, all the previously

protected sector groups are protected again. Figure 1

shows the algorithm, and Figure 23 shows the timing

diagrams, for this feature.

Figure 1. Temporary Sector Group

Unprotect Operation

START

Perform Erase or

Program Operations

RESET# = VIH

Temporary Sector

Group Unprotect

Completed (Note 2)

RESET# = VID

(Note 1)

Notes:

1. All protected sector groups unprotected (If WP# = V

the first or last sector will remain protected).

2. All previously protected sector groups are protected

once again.

20 Am29LV320MT/B

26518C1 / May 4, 2004

DATASHEET

Figure 2. In-System Sector Group Protect/Unprotect Algorithms

Sector Group Protect:

Write 60h to sector

group address with

A6–A0 = 0xx0010

Set up sector

group address

Wait 150 µs

Verify Sector Group

Protect: Write 40h

to sector group

address with

A6–A0 = 0xx0010

Read from

sector group address

with A6–A0

= 0xx0010

START

PLSCNT = 1

RESET# = VID

Wait 1 µs

First Write

Cycle = 60h?

Data = 01h?

Remove VID

from RESET#

Write reset

command

Sector Group

Protect complete

Yes

PLSCNT

= 25?

Yes

Device failed

Increment

PLSCNT

Temporary Sector

Group Unprotect

Mode

Sector Group

Unprotect:

Write 60h to sector

group address with

A6–A0 = 1xx0010

Set up first sector

group address

Wait 15 ms

Verify Sector Group

Unprotect: Write

40h to sector group

address with

A6–A0 = 1xx0010

Read from

sector group

address with

A6–A0 = 1xx0010

START

PLSCNT = 1

RESET# = VID

Wait 1 µs

Data = 00h?

Last sector

group

verified?

Remove VID

from RESET#

Write reset

command

Sector Group

Unprotect complete

Yes

PLSCNT

= 1000?

Yes

Device failed

Increment

PLSCNT

Temporary Sector

Group Unprotect

Mode

No All sector

groups

protected?

Yes

Protect all sector

groups: The indicated

portion of the sector

group protect algorithm

must be performed for all

unprotected sector

groups prior to issuing

the first sector group

unprotect address

Set up

next sector group

address

Yes

Sector Group

Protect

Algorithm

Sector Group

Unprotect

Algorithm

First Write

Cycle = 60h?

Protect

another

sector group?

Reset

PLSCNT = 1

26518C1 / May 4, 2004

Am29LV320MT/B 21

DATASHEET

SecSi (Secured Silicon) Sector Flash

Memory Region

The SecSi (Secured Silicon) Sector feature provides a

Flash memory region that enables permanent part

identification through an Electronic Serial Number

(ESN). The SecSi Sector is 256 bytes in length, and

uses a SecSi Sector Indicator Bit (DQ7) to indicate

whether or not the SecSi Sector is locked when

shipped from the factory. This bit is permanently set at

the factory and cannot be changed, which prevents

cloning of a factory locked part. This ensures the secu-

rity of the ESN once the product is shipped to the field.

AMD offers the device with the SecSi Sector either

customer lockable (standard shipping option) or fac-

tory locked (contact an AMD sales representative for

ordering information). The customer-lockable version

is shipped with the SecSi Sector unprotected, allowing

customers to program the sector after receiving the

device. The customer-lockable version also has the

SecSi Sector Indicator Bit permanently set to a “0.”

The factory-locked version is always protected when

shipped from the factory, and has the SecSi (Secured

Silicon) Sector Indicator Bit permanently set to a “1.”

Thus, the SecSi Sector Indicator Bit prevents cus-

tomer-lockable devices from being used to replace de-

vices that are factory locked.

Note that the ACC

function and unlock bypass modes are not available

when the SecSi Sector is enabled.

The SecSi sector address space in this device is allo-

cated as follows:

The system accesses the SecSi Sector through a

command sequence (see “Enter SecSi Sector/Exit

SecSi Sector Command Sequence”). After the system

has written the Enter SecSi Sector command se-

quence, it may read the SecSi Sector by using the ad-

dresses normally occupied by the first sector (SA0).

This mode of operation continues until the system is-

sues the Exit SecSi Sector command sequence, or

until power is removed from the device. On power-up,

or following a hardware reset, the device reverts to

sending commands to sector SA0.

Customer Lockable: SecSi Sector NOT

Programmed or Protected At the Factory

Unless otherwise specified, the device is shipped such

that the customer may program and protect the

256-byte SecSi sector.

The system may program the SecSi Sector using the

write-buffer, accelerated and/or unlock bypass meth-

ods, in addition to the standard programming com-

mand sequence. See Command Definitions.

Programming and protecting the SecSi Sector must be

used with caution since, once protected, there is no

procedure available for unprotecting the SecSi Sector

area and none of the bits in the SecSi Sector memory

space can be modified in any way.

The SecSi Sector area can be protected using one of

the following procedures:

■Write the three-cycle Enter SecSi Sector Region

command sequence, and then follow the in-system

sector protect algorithm as shown in Figure 2, ex-

cept that

RESET# may be at either V

or V

. This

allows in-system protection of the SecSi Sector

without raising any device pin to a high voltage.

Note that this method is only applicable to the SecSi

Sector.

■To verify the protect/unprotect status of the SecSi

Sector, follow the algorithm shown in Figure 3.

Once the SecSi Sector is programmed, locked and

verified, the system must write the Exit SecSi Sector

Region command sequence to return to reading and

writing within the remainder of the array.

Factory Locked: SecSi Sector Programmed and

Protected At the Factory

In devices with an ESN, the SecSi Sector is protected

when the device is shipped from the factory. The SecSi

Sector cannot be modified in any way. An ESN Factory

Locked device has an 16-byte random ESN at ad-

dresses 000000h–000007h. Please contact your local

AMD sales representative for details on ordering ESN

Factory Locked devices.

Customers may opt to have their code programmed by

AMD through the AMD ExpressFlash service (Express

Flash Factory Locked). The devices are then shipped

from AMD’s factory with the SecSi Sector permanently

locked. Contact an AMD representative for details on

using AMD’s ExpressFlash service.

Table 7. SecSi Sector Contents

SecSi Sector

Address Range

Customer

Lockable

ESN Factory

Locked

ExpressFlash

Factory Locked

000000h–000007h Determined by

customer

ESN

ESN or

determined by

customer

000008h–00007Fh Unavailable Determined by

customer

22 Am29LV320MT/B

26518C1 / May 4, 2004

DATASHEET

Figure 3. SecSi Sector Protect Verify

Hardware Data Protection

The command sequence requirement of unlock cycles

for programming or erasing provides data protection

against inadvertent writes (refer to Tables 12 and 13

for command definitions). In addition, the following

hardware data protection measures prevent accidental

erasure or programming, which might otherwise be

caused by spurious system level signals during VCC

power-up and power-down transitions, or from system

noise.

Low VCC Write Inhibit

When VCC is less than VLKO, the device does not ac-

cept any write cycles. This protects data during VCC

power-up and power-down. The command register

and all internal program/erase circuits are disabled,

and the device resets to the read mode. Subsequent

writes are ignored until VCC is greater than VLKO. The

system must provide the proper signals to the control

pins to prevent unintentional writes when VCC is

greater than VLKO.

Write Pulse “Glitch” Protection

Noise pulses of less than 5 ns (typical) on OE#, CE#

or WE# do not initiate a write cycle.

Logical Inhibit

Write cycles are inhibited by holding any one of OE# =

VIL, CE# = VIH or WE# = VIH. To initiate a write cycle,

CE# and WE# must be a logical zero while OE# is a

logical one.

Power-Up Write Inhibit

If WE# = CE# = VIL and OE# = VIH during power up,

the device does not accept commands on the rising

edge of WE#. The internal state machine is automati-

cally reset to the read mode on power-up.

COMMON FLASH MEMORY INTERFACE (CFI)

The Common Flash Interface (CFI) specification out-

lines device and host system software interrogation

handshake, which allows specific vendor-specified

software algorithms to be used for entire families of

devices. Software support can then be device-inde-

pendent, JEDEC ID-independent, and forward- and

backward-compatible for the specified flash device

families. Flash vendors can standardize their existing

interfaces for long-term compatibility.

This device enters the CFI Query mode when the sys-

tem writes the CFI Query command, 98h, to address

55h, any time the device is ready to read array data.

The system can read CFI information at the addresses

given in Tables 8–11. To terminate reading CFI data,

the system must write the reset command.

The system can also write the CFI query command

when the device is in the autoselect mode. The device

enters the CFI query mode, and the system can read

CFI data at the addresses given in Tables 8–11. The

system must write the reset command to return the

device to reading array data.

For further information, please refer to the CFI Specifi-

cation and CFI Publication 100, available via the World

Wide Web at http://www.amd.com/flash/cfi. Alterna-

tively, contact an AMD representative for copies of

these documents.

Write 60h to

any address

Write 40h to SecSi

Sector address

with A6 = 0,

A1 = 1, A0 = 0

START

RESET# =

or V

Wait 1 ms

Read from SecSi

Sector address

with A6 = 0,

A1 = 1, A0 = 0

If data = 00h,

SecSi Sector is

unprotected.

If data = 01h,

SecSi Sector is

protected.

Remove V

or V

from RESET#

Write reset

command

SecSi Sector

Protect Verify

complete

26518C1 / May 4, 2004

Am29LV320MT/B 23

DATASHEET

Table 8. CFI Query Identification String

Table 9. System Interface String

Addresses

(x16)

Addresses

(x8) Data Description

10h

11h

12h

20h

22h

24h

0051h

0052h

0059h

Query Unique ASCII string “QRY”

13h

14h

26h

28h

0002h

0000h Primary OEM Command Set

15h

16h

2Ah

2Ch

0040h

0000h Address for Primary Extended Table

17h

18h

2Eh

30h

0000h

0000h Alternate OEM Command Set (00h = none exists)

19h

1Ah

32h

34h

0000h

0000h Address for Alternate OEM Extended Table (00h = none exists)

Addresses

(x16)

Addresses

(x8) Data Description

1Bh 36h 0027h VCC Min. (write/erase)

D7–D4: volt, D3–D0: 100 millivolt

1Ch 38h 0036h VCC Max. (write/erase)

D7–D4: volt, D3–D0: 100 millivolt

1Dh 3Ah 0000h VPP Min. voltage (00h = no VPP pin present)

1Eh 3Ch 0000h VPP Max. voltage (00h = no VPP pin present)

1Fh 3Eh 0007h Typical timeout per single byte/word write 2N µs

20h 40h 0007h Typical timeout for Min. size buffer write 2N µs (00h = not supported)

21h 42h 000Ah Typical timeout per individual block erase 2N ms

22h 44h 0000h Typical timeout for full chip erase 2N ms (00h = not supported)

23h 46h 0001h Max. timeout for byte/word write 2N times typical

24h 48h 0005h Max. timeout for buffer write 2N times typical

25h 4Ah 0004h Max. timeout per individual block erase 2N times typical

26h 4Ch 0000h Max. timeout for full chip erase 2N times typical (00h = not supported)

24 Am29LV320MT/B

26518C1 / May 4, 2004

DATASHEET

Table 10. Device Geometry Definition

Addresses

(x16)

Addresses

(x8) Data Description

27h 4Eh 0016h Device Size = 2N byte

28h

29h

50h

52h

0002h

0000h Flash Device Interface description (refer to CFI publication 100)

2Ah

2Bh

54h

56h

0005h

0000h

Max. number of byte in multi-byte write = 2N

(00h = not supported)

2Ch 58h 0002h Number of Erase Block Regions within device (01h = uniform device, 02h = boot

device)

2Dh

2Eh

2Fh

30h

5Ah

5Ch

5Eh

60h

007Fh

0000h

0020h

0000h

Erase Block Region 1 Information

(refer to the CFI specification or CFI publication 100)

31h

32h

33h

34h

62h

64h

66h

68h

003Eh

0000h

0001h

Erase Block Region 2 Information (refer to CFI publication 100)

35h

36h

37h

38h

6Ah

6Ch

6Eh

70h

0000h

Erase Block Region 3 Information (refer to CFI publication 100)

39h

3Ah

3Bh

3Ch

72h

74h

76h

78h

0000h

Erase Block Region 4 Information (refer to CFI publication 100)

26518C1 / May 4, 2004

Am29LV320MT/B 25

DATASHEET

Table 11. Primary Vendor-Specific Extended Query

COMMAND DEFINITIONS

Writing specific address and data commands or se-

quences into the command register initiates device op-

erations. Tables 12 and 13 define the valid register

command sequences. Writing incorrect address and

data values or writing them in the improper se-

quence may place the device in an unknown state. A

reset command is then required to return the device to

reading array data.

All addresses are latched on the falling edge of WE#

or CE#, whichever happens later. All data is latched on

the rising edge of WE# or CE#, whichever happens

first. Refer to the AC Characteristics section for timing

diagrams.

Reading Array Data

The device is automatically set to reading array data

after device power-up. No commands are required to

retrieve data. The device is ready to read array data

after completing an Embedded Program or Embedded

Erase algorithm.

After the device accepts an Erase Suspend command,

the device enters the erase-suspend-read mode, after

Addresses

(x16)

Addresses

(x8) Data Description

40h

41h

42h

80h

82h

84h

0050h

0052h

0049h

Query-unique ASCII string “PRI”

43h 86h 0031h Major version number, ASCII

44h 88h 0033h Minor version number, ASCII

45h 8Ah 0008h

Address Sensitive Unlock (Bits 1-0)

0 = Required, 1 = Not Required

Process Technology (Bits 7-2) 0010b = 0.23 µm MirrorBit

46h 8Ch 0002h Erase Suspend

0 = Not Supported, 1 = To Read Only, 2 = To Read & Write

47h 8Eh 0001h Sector Protect

0 = Not Supported, X = Number of sectors in per group

48h 90h 0001h Sector Temporary Unprotect

00 = Not Supported, 01 = Supported

49h 92h 0004h Sector Protect/Unprotect scheme

04 = 29LV800 mode

4Ah 94h 0000h Simultaneous Operation

00 = Not Supported, X = Number of Sectors in Bank

4Bh 96h 0000h Burst Mode Type

00 = Not Supported, 01 = Supported

4Ch 98h 0001h Page Mode Type

00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page

4Dh 9Ah 00B5h ACC (Acceleration) Supply Minimum

00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV

4Eh 9Ch 00C5h ACC (Acceleration) Supply Maximum

00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV

4Fh 9Eh 0002h/

0003h

Top/Bottom Boot Sector Flag

00h = Uniform Device without WP# protect, 02h = Bottom Boot Device, 03h = Top

Boot Device, 04h = Uniform sectors bottom WP# protect, 05h = Uniform sectors top

WP# protect

50h A0h 0001h Program Suspend

00h = Not Supported, 01h = Supported

26 Am29LV320MT/B
26518C1 / May 4, 2004
DATASHEET
which the system can read data from any
non-erase-suspended sector. After completing a pro-
gramming operation in the Erase Suspend mode, the
system may once again read array data with the same
exception. See the Erase Suspend/Erase Resume
Commands section for more information.
The system 
must
 issue the reset command to return
the device to the read (or erase-suspend-read) mode if
DQ5 goes high during an active program or erase op-
eration, or if the device is in the autoselect mode. See
the next section, Reset Command, for more informa-
tion.
See also Requirements for Reading Array Data in the
Device Bus Operations section for more information.
The Read-Only Operations table provides the read pa-
rameters, and Figure 14 shows the timing diagram.
Reset Command
Writing the reset command resets the device to the
read or erase-suspend-read mode. Address bits are
don’t cares for this command.
The reset command may be written between the se-
quence cycles in an erase command sequence before
erasing begins. This resets the device to the read
mode. Once erasure begins, however, the device ig-
nores reset commands until the operation is complete.
The reset command may be written between the
sequence cycles in a program command sequence
before programming begins. This resets the device to
the read mode. If the program command sequence is
written while the device is in the Erase Suspend mode,
writing the reset command returns the device to the
erase-suspend-read mode. Once programming be-
gins, however, the device ignores reset commands
until the operation is complete.
The reset command may be written between the se-
quence cycles in an autoselect command sequence.
Once in the autoselect mode, the reset command
must be written to return to the read mode. If the de-
vice entered the autoselect mode while in the Erase
Suspend mode, writing the reset command returns the
device to the erase-suspend-read mode.
If DQ5 goes high during a program or erase operation,
writing the reset command returns the device to the
read mode (or erase-suspend-read mode if the device
was in Erase Suspend).
Note that if DQ1 goes high during a Write Buffer Pro-
gramming operation, the system must write the
Write-to-Buffer-Abort Reset command sequence to
reset the device for the next operation. 
Autoselect Command Sequence
The autoselect command sequence allows the host
system to read several identifier codes at specific ad-
dresses:
Note: The device ID is read over three cycles. SA = Sector
Address
Tables  12 and 13 show the address and data require-
ments. This method is an alternative to that shown in
Tabl e  4, which is intended for PROM programmers
and requires VID on address pin A9. The autoselect
command sequence may be written to an address that
is either in the read or erase-suspend-read mode. The
autoselect command may not be written while the de-
vice is actively programming or erasing.
The autoselect command sequence is initiated by first
writing two unlock cycles. This is followed by a third
write cycle that contains the autoselect command. The
device then enters the autoselect mode. The system
may read at any address any number of times without
initiating another autoselect command sequence.
The system must write the reset command to return to
the read mode (or erase-suspend-read mode if the de-
vice was previously in Erase Suspend).
Enter SecSi Sector/Exit SecSi Sector 
Command Sequence
The SecSi Sector region provides a secured data area
containing an 8-word/16-byte random Electronic Serial
Number (ESN). The system can access the SecSi
Sector region by issuing the three-cycle Enter SecSi
Sector command sequence. The device continues to
access the SecSi Sector region until the system is-
sues the four-cycle Exit SecSi Sector command se-
quence. The Exit SecSi Sector command sequence
returns the device to normal operation. Tables 12 and
13 show the address and data requirements for both
command sequences. See also “SecSi (Secured Sili-
con) Sector Flash Memory Region” for further informa-
tion. 
Note that the ACC function and unlock bypass
modes are not available when the SecSi Sector is en-
abled. 
Word/Byte Program Command Sequence
Programming is a four-bus-cycle operation. The pro-
gram command sequence is initiated by writing two
unlock write cycles, followed by the program set-up
command. The program address and data are written
Identifier Code A7:A0
(x16)
A6:A-1
(x8)
Manufacturer ID 00h 00h
Device ID, Cycle 1 01h 02h
Device ID, Cycle 2 0Eh 1Ch
Device ID, Cycle 3 0Fh 1Eh
SecSi Sector Factory Protect 03h 06h
Sector Protect Verify (SA)02h (SA)04h

26518C1 / May 4, 2004

Am29LV320MT/B 27

DATASHEET

next, which in turn initiate the Embedded Program al-

gorithm. The system is

not

required to provide further

controls or timings. The device automatically provides

internally generated program pulses and verifies the

programmed cell margin. Tables 12 and 13 show the

address and data requirements for the word program

command sequence.

When the Embedded Program algorithm is complete,

the device then returns to the read mode and ad-

dresses are no longer latched. The system can deter-

mine the status of the program operation by using

DQ7 or DQ6. Refer to the Write Operation Status sec-

tion for information on these status bits.

Any commands written to the device during the Em-

bedded Program Algorithm are ignored. Note that a

hardware reset immediately terminates the program

operation.

Note that the SecSi Sector, autoselect, and

CFI functions are unavailable when a program opera-

tion is in progress.

The program command sequence

should be reinitiated once the device has returned to

the read mode, to ensure data integrity.

Programming is allowed in any sequence and across

sector boundaries. A bit cannot be programmed

from “0” back to a “1.” Attempting to do so may

cause the device to set DQ5 = 1, or cause the DQ7

and DQ6 status bits to indicate the operation was suc-

cessful. However, a succeeding read will show that the

data is still “0.” Only erase operations can convert a “0”

to a “1.”

Unlock Bypass Command Sequence

The unlock bypass feature allows the system to pro-

gram words to the device faster than using the stan-

dard program command sequence. The unlock bypass

command sequence is initiated by first writing two un-

lock cycles. This is followed by a third write cycle con-

taining the unlock bypass command, 20h. The device

then enters the unlock bypass mode. A two-cycle un-

lock bypass program command sequence is all that is

required to program in this mode. The first cycle in this

sequence contains the unlock bypass program com-

mand, A0h; the second cycle contains the program

address and data. Additional data is programmed in

the same manner. This mode dispenses with the initial

two unlock cycles required in the standard program

command sequence, resulting in faster total program-

ming time. Tables 12 and 13 show the requirements

for the command sequence.

During the unlock bypass mode, only the Unlock By-

pass Program and Unlock Bypass Reset commands

are valid. To exit the unlock bypass mode, the system

must issue the two-cycle unlock bypass reset com-

mand sequence. The first cycle must contain the data

90h. The second cycle must contain the data 00h. The

device then returns to the read mode.

Write Buffer Programming

Write Buffer Programming allows the system write to a

maximum of 16 words/32 bytes in one programming

operation. This results in faster effective programming

time than the standard programming algorithms. The

Write Buffer Programming command sequence is initi-

ated by first writing two unlock cycles. This is followed

by a third write cycle containing the Write Buffer Load

command written at the Sector Address in which pro-

gramming will occur. The fourth cycle writes the sector

address and the number of word locations, minus one,

to be programmed. For example, if the system will pro-

gram 6 unique address locations, then 05h should be

written to the device. This tells the device how many

write buffer addresses will be loaded with data and

therefore when to expect the Program Buffer to Flash

command. The number of locations to program cannot

exceed the size of the write buffer or the operation will

abort.

The fifth cycle writes the first address location and

data to be programmed. The write-buffer-page is se-

lected by address bits AMAX–A4. All subsequent ad-

dress/data pairs must fall within the

selected-write-buffer-page. The system then writes the

remaining address/data pairs into the write buffer.

Write buffer locations may be loaded in any order.

The write-buffer-page address must be the same for

all address/data pairs loaded into the write buffer.

(This means Write Buffer Programming cannot be per-

formed across multiple write-buffer pages. This also

means that Write Buffer Programming cannot be per-

formed across multiple sectors. If the system attempts

to load programming data outside of the selected

write-buffer page, the operation will abort.

Note that if a Write Buffer address location is loaded

multiple times, the address/data pair counter will be

decremented for every data load operation. The host

system must therefore account for loading a

write-buffer location more than once. The counter dec-

rements for each data load operation, not for each

unique write-buffer-address location. Note also that if

an address location is loaded more than once into the

buffer, the final data loaded for that address will be

programmed.

Once the specified number of write buffer locations

have been loaded, the system must then write the Pro-

gram Buffer to Flash command at the sector address.

Any other address and data combination aborts the

Write Buffer Programming operation. The device then

begins programming. Data polling should be used

while monitoring the last address location loaded into

the write buffer. DQ7, DQ6, DQ5, and DQ1 should be

monitored to determine the device status during Write

Buffer Programming.

28 Am29LV320MT/B

26518C1 / May 4, 2004

DATASHEET

The write-buffer programming operation can be sus-

pended using the standard program suspend/resume

commands. Upon successful completion of the Write

Buffer Programming operation, the device is ready to

execute the next command.

The Write Buffer Programming Sequence can be

aborted in the following ways:

■Load a value that is greater than the page buffer

size during the Number of Locations to Program

step.

■Write to an address in a sector different than the

one specified during the Write-Buffer-Load com-

mand.

■Write an Address/Data pair to a different

write-buffer-page than the one selected by the

Starting Address during the write buffer data load-

ing stage of the operation.

■Write data other than the Confirm Command after

the specified number of data load cycles.

The abort condition is indicated by DQ1 = 1, DQ7 =

DATA# (for the last address location loaded), DQ6 =

toggle, and DQ5=0. A Write-to-Buffer-Abort Reset

command sequence must be written to reset the de-

vice for the next operation. Note that the full 3-cycle

Write-to-Buffer-Abort Reset command sequence is re-

quired when using Write-Buffer-Programming features

in Unlock Bypass mode.

Accelerated Program

The device offers accelerated program operations

through the WP#/ACC pin. When the system asserts

VHH on the WP#/ACC pin, the device automatically en-

ters the Unlock Bypass mode. The system may then

write the two-cycle Unlock Bypass program command

sequence. The device uses the higher voltage on the

WP#/ACC pin to accelerate the operation.

Note that

the

WP#/

ACC pin must not be at V

for operations

other than accelerated programming, or device dam-

age may result. In addition, no external pullup is nec-

essary since the WP#/ACC pin has internal pullup to

Figure 5 illustrates the algorithm for the program oper-

ation. Refer to the Erase and Program Operations

table in the AC Characteristics section for parameters,

and Figure 17 for timing diagrams.

26518C1 / May 4, 2004

Am29LV320MT/B 29

DATASHEET

Figure 4. Write Buffer Programming Operation

Write “Write to Buffer”

command and

Sector Address

Write number of addresses

to program minus 1(WC)

and Sector Address

Write program buffer to

flash sector address

Write first address/data

Write to a different

sector address

FAIL or ABORT PASS

Read DQ7 - DQ0 at

Last Loaded Address

Read DQ7 - DQ0 with

address = Last Loaded

Address

Write next address/data pair

WC = WC - 1

WC = 0 ?

Part of “Write to Buffer”

Command Sequence

Ye s

Abort Write to

Buffer Operation?

DQ7 = Data?

DQ5 = 1?DQ1 = 1?

Write to buffer ABORTED.

Must write “Write-to-buffer

Abort Reset” command

sequence to return

to read mode.

Notes:

1. When Sector Address is specified, any address in

the selected sector is acceptable. However, when

loading Write-Buffer address locations with data, all

addresses must fall within the selected Write-Buffer

Page.

2. DQ7 may change simultaneously with DQ5.

Therefore, DQ7 should be verified.

3. If this flowchart location was reached because

DQ5= “1”, then the device FAILED. If this flowchart

location was reached because DQ1= “1”, then the

Write to Buffer operation was ABORTED. In either

case, the proper reset command must be written

before the device can begin another operation. If

DQ1=1, write the

Write-Buffer-Programming-Abort-Reset

command. if DQ5=1, write the Reset command.

4. See Tables 12 and 13 for command sequences

required for write buffer programming.

(Note 3)

(Note 1)

(Note 2)

30 Am29LV320MT/B

26518C1 / May 4, 2004

DATASHEET

Figure 5. Program Operation

Program Suspend/Program Resume

Command Sequence

The Program Suspend command allows the system to

interrupt a programming operation or a Write to Buffer

programming operation so that data can be read from

any non-suspended sector. When the Program Sus-

pend command is written during a programming pro-

cess, the device halts the program operation within 15

µs maximum (5 µs typical) and updates the status bits.

Addresses are not required when writing the Program

Suspend command.

After the programming operation has been sus-

pended, the system can read array data from any

non-suspended sector. The Program Suspend com-

mand may also be issued during a programming oper-

ation while an erase is suspended. In this case, data

may be read from any addresses not in Erase Sus-

pend or Program Suspend. If a read is needed from

the SecSi Sector area (One-time Program area), then

user must use the proper command sequences to

enter and exit this region.

The system may also write the autoselect command

sequence when the device is in the Program Suspend

mode. The system can read as many autoselect codes

as required. When the device exits the autoselect

mode, the device reverts to the Program Suspend

mode, and is ready for another valid operation. See

Autoselect Command Sequence for more information.

After the Program Resume command is written, the

device reverts to programming. The system can deter-

mine the status of the program operation using the

DQ7 or DQ6 status bits, just as in the standard pro-

gram operation. See Write Operation Status for more

information.

The system must write the Program Resume com-

mand (address bits are don’t care) to exit the Program

Suspend mode and continue the programming opera-

tion. Further writes of the Resume command are ig-

nored. Another Program Suspend command can be

written after the device has resume programming.

START

Write Program

Command Sequence

Data Poll

from System

Verify Data? No

Yes

Last Address?

Yes

Programming

Completed

Increment Address

Embedded

Program

algorithm

in progress

Note: See Tables 12 and 13 for program command

sequence.

26518C1 / May 4, 2004

Am29LV320MT/B 31

DATASHEET

Figure 6. Program Suspend/Program Resume

Chip Erase Command Sequence

Chip erase is a six bus cycle operation. The chip erase

command sequence is initiated by writing two unlock

cycles, followed by a set-up command. Two additional

unlock write cycles are then followed by the chip erase

command, which in turn invokes the Embedded Erase

algorithm. The device does

not

require the system to

preprogram prior to erase. The Embedded Erase algo-

rithm automatically preprograms and verifies the entire

memory for an all zero data pattern prior to electrical

erase. The system is not required to provide any con-

trols or timings during these operations. Tables 12 and

13 shows the address and data requirements for the

chip erase command sequence.

Note that the SecSi

Sector, autoselect, and CFI functions are unavailable

when a program operation is in progress.

When the Embedded Erase algorithm is complete, the

device returns to the read mode and addresses are no

longer latched. The system can determine the status

of the erase operation by using DQ7, DQ6, or DQ2.

Refer to the Write Operation Status section for infor-

mation on these status bits.

Any commands written during the chip erase operation

are ignored. However, note that a hardware reset im-

mediately terminates the erase operation. If that oc-

curs, the chip erase command sequence should be

reinitiated once the device has returned to reading

array data, to ensure data integrity.

Figure 7 illustrates the algorithm for the erase opera-

tion. Refer to the Erase and Program Operations ta-

bles in the AC Characteristics section for parameters,

and Figure 19 section for timing diagrams.

Sector Erase Command Sequence

Sector erase is a six bus cycle operation. The sector

erase command sequence is initiated by writing two

unlock cycles, followed by a set-up command. Two ad-

ditional unlock cycles are written, and are then fol-

lowed by the address of the sector to be erased, and

the sector erase command. Tables 12 and 13 shows

the address and data requirements for the sector

erase command sequence.

Note that the SecSi Sec-

tor, autoselect, and CFI functions are unavailable

when a program operation is in progress.

The device does

not

require the system to preprogram

prior to erase. The Embedded Erase algorithm auto-

matically programs and verifies the entire memory for

an all zero data pattern prior to electrical erase. The

system is not required to provide any controls or tim-

ings during these operations.

After the command sequence is written, a sector erase

time-out of 50 µs occurs. During the time-out period,

additional sector addresses and sector erase com-

mands may be written. Loading the sector erase buffer

may be done in any sequence, and the number of sec-

tors may be from one sector to all sectors. The time

between these additional cycles must be less than 50

µs, otherwise erasure may begin. Any sector erase ad-

dress and command following the exceeded time-out

may or may not be accepted. It is recommended that

processor interrupts be disabled during this time to en-

sure all commands are accepted. The interrupts can

be re-enabled after the last Sector Erase command is

written. Any command other than Sector Erase or

Erase Suspend during the time-out period resets

the device to the read mode. The system must re-

write the command sequence and any additional ad-

dresses and commands.

The system can monitor DQ3 to determine if the sec-

tor erase timer has timed out (See the section on DQ3:

Sector Erase Timer.). The time-out begins from the ris-

ing edge of the final WE# pulse in the command

sequence.

When the Embedded Erase algorithm is complete, the

device returns to reading array data and addresses

are no longer latched. The system can determine the

status of the erase operation by reading DQ7, DQ6, or

DQ2 in the erasing sector. Refer to the Write Opera-

tion Status section for information on these status bits.

Program Operation

or Write-to-Buffer

Sequence in Progress

Write Program Suspend

Command Sequence

Command is also valid for

Erase-suspended-program

operations

Autoselect operations are also allowe

Data cannot be read from erase- or

program-suspended sectors

Write Program Resume

Command Sequence

Read data as

required

Done

reading?

Yes

Write address/data

XXXh/30h

Device reverts to

operation prior to

Program Suspend

Write address/data

XXXh/B0h

Wait 15 µs

32 Am29LV320MT/B
26518C1 / May 4, 2004
DATASHEET
Once the sector erase operation has begun, only the
Erase Suspend command is valid. All other com-
mands are ignored. However, note that a hardware
reset immediately terminates the erase operation. If
that occurs, the sector erase command sequence
should be reinitiated once the device has returned to
reading array data, to ensure data integrity.
Figure 7 illustrates the algorithm for the erase opera-
tion. Refer to the Erase and Program Operations ta-
bles in the AC Characteristics section for parameters,
and Figure 19 section for timing diagrams.
Figure 7. Erase Operation
Erase Suspend/Erase Resume 
Commands
The Erase Suspend command, B0h, allows the sys-
tem to interrupt a sector erase operation and then read
data from, or program data to, any sector not selected
for erasure. This command is valid only during the sec-
tor erase operation, including the 50 µs time-out pe-
riod during the sector erase command sequence. The
Erase Suspend command is ignored if written during
the chip erase operation or Embedded Program
algorithm. 
When the Erase Suspend command is written during
the sector erase operation, the device requires a typi-
cal of 5 µs (maximum of 20 µs) to suspend the erase
operation. However, when the Erase Suspend com-
mand is written during the sector erase time-out, the
device immediately terminates the time-out period and
suspends the erase operation. 
After the erase operation has been suspended, the
device enters the erase-suspend-read mode. The sys-
tem can read data from or program data to any sector
not selected for erasure. (The device “erase sus-
pends” all sectors selected for erasure.) Reading at
any address within erase-suspended sectors pro-
duces status information on DQ7–DQ0. The system
can use DQ7, or DQ6 and DQ2 together, to determine
if a sector is actively erasing or is erase-suspended.
Refer to the Write Operation Status section for infor-
mation on these status bits.
After an erase-suspended program operation is com-
plete, the device returns to the erase-suspend-read
mode. The system can determine the status of the
program operation using the DQ7 or DQ6 status bits,
just as in the standard word program operation.
Refer to the Write Operation Status section for more
information.
In the erase-suspend-read mode, the system can also
issue the autoselect command sequence. Refer to the
Autoselect Mode and Autoselect Command Sequence
sections for details.
To resume the sector erase operation, the system
must write the Erase Resume command. Further
writes of the Resume command are ignored. Another
Erase Suspend command can be written after the chip
has resumed erasing. 
Note that during an erase operation, this flash device
performs multiple internal operations that are invisible
to the host system. When an erase operation is sus-
pended, any of the operations that were not fully com-
pleted must be restarted. As such, if this flash device
is continually issued suspend/resume commands in
rapid succession, erase progress will be impeded as a
function of the number of suspends. The result will be
a longer cumulative time than without suspends. The
additional suspends do not affect device reliability or
future performance. In most systems rapid erase/sus-
pend activity occurs only briefly. In this example, erase
performance will not be significantly impacted.
START
Write Erase 
Command Sequence
(Notes 1, 2)
Data Poll to Erasing 
Bank from System
Data = FFh?
No
Yes
Erasure Completed
Embedded 
Erase
algorithm
in progress
Notes:
1. See Tables 12 and 13 for erase command sequence.
2. See the section on DQ3 for information on the sector 
erase timer.

26518C1 / May 4, 2004
Am29LV320MT/B 33
DATASHEET
Command Definitions
Table 12. Command Definitions (x16 Mode, BYTE# = VIH)
Legend:
X = Don’t care
RA = Read Address of the memory location to be read. 
RD = Read Data read from location RA during read operation.
PA = Program Address. Addresses latch on the falling edge of the WE# 
or CE# pulse, whichever happens later.
PD = Program Data for location PA. Data latches on the rising edge of 
WE# or CE# pulse, whichever happens first.
SA = Sector Address of sector to be verified (in autoselect mode) or 
erased. Address bits A20–A15 uniquely select any sector.
WBL = Write Buffer Location. Address must be within the same write 
buffer page as PA.
WC = Word Count. Number of write buffer locations to load minus 1.
Notes:
1. See Tabl e 1 for description of bus operations.
2. All values are in hexadecimal.
3. Except for the read cycle and the fourth cycle of the autoselect 
command sequence, all bus cycles are write cycles.
4. During unlock cycles, when lower address bits are 555 or 2AAh 
as shown in table, address bits higher than A11 (except where BA 
is required) and data bits higher than DQ7 are don’t cares.
5. No unlock or command cycles required when device is in read 
mode.
6. The Reset command is required to return to the read mode (or to 
the erase-suspend-read mode if previously in Erase Suspend) 
when the device is in the autoselect mode, or if DQ5 goes high 
while the device is providing status information.
7. The fourth cycle of the autoselect command sequence is a read 
cycle. Data bits DQ15–DQ8 are don’t care. See the Autoselect 
Command Sequence section for more information.
8. The device ID must be read in three cycles. The data is 2201h for 
top boot and 2200h for bottom boot.
9. If WP# protects the top two address sectors, the data is 98h for 
factory locked and 18h for not factory locked. If WP# protects the 
bottom two address sectors, the data is 88h for factory locked and 
08h for not factor locked.
10. The data is 00h for an unprotected sector group and 01h for a 
protected sector group. 
11. The total number of cycles in the command sequence is 
determined by the number of words written to the write buffer. The 
maximum number of cycles in the command sequence is 21.
12. Command sequence resets device for next command after 
aborted write-to-buffer operation.
13. The Unlock Bypass command is required prior to the Unlock 
Bypass Program command.
14. The Unlock Bypass Reset command is required to return to the 
read mode when the device is in the unlock bypass mode.
15. The system may read and program in non-erasing sectors, or 
enter the autoselect mode, when in the Erase Suspend mode. 
The Erase Suspend command is valid only during a sector erase 
operation.
16. The Erase Resume command is valid only during the Erase 
Suspend mode.
17. Command is valid when device is ready to read array data or when 
device is in autoselect mode.
Command Sequence
(Notes)
Cycles
Bus Cycles (Notes 1–4)
First Second Third  Fourth  Fifth Sixth 
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Read (Note 5) 1 RA RD
Reset (Note 6) 1 XXX F0
Autoselect (Note 7)
Manufacturer ID 4 555 AA 2AA 55 555 90 X00 0001
Device ID (Note 8) 6 555 AA 2AA 55 555 90 X01 227E X0E 221A X0F 2200/
2201
SecSi™ Sector Factory Protect 
(Note 9) 4 555 AA 2AA 55 555 90 X03 (Note 9)
Sector Group Protect Verify 
(Note 10) 4 555 AA 2AA 55 555 90 (SA)X02 00/01
Enter SecSi Sector Region 3 555 AA 2AA 55 555 88
Exit SecSi Sector Region 4 555 AA 2AA 55 555 90 XXX 00
Program 4 555 AA 2AA 55 555 A0 PA PD
Write to Buffer (Note 11) 6 555 AA 2AA 55 SA 25 SA WC PA PD WBL PD
Program Buffer to Flash 1 SA 29
Write to Buffer Abort Reset (Note 12) 3 555 AA 2AA 55 555 F0
Unlock Bypass 3 555 AA 2AA 55 555 20
Unlock Bypass Program (Note 13) 2 XXX A0 PA PD
Unlock Bypass Reset (Note 14) 2 XXX 90 XXX 00
Chip Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 555 10
Sector Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 SA 30
Program/Erase Suspend (Note 15) 1 XXX B0
Program/Erase Resume (Note 16) 1 XXX 30
CFI Query (Note 17) 1 55 98

34 Am29LV320MT/B
26518C1 / May 4, 2004
DATASHEET
Table 13. Command Definitions (x8 Mode, BYTE# = VIL)
Legend:
X = Don’t care
RA = Read Address of the memory location to be read. 
RD = Read Data read from location RA during read operation.
PA = Program Address. Addresses latch on the falling edge of the WE# 
or CE# pulse, whichever happens later.
PD = Program Data for location PA. Data latches on the rising edge of 
WE# or CE# pulse, whichever happens first.
SA = Sector Address of sector to be verified (in autoselect mode) or 
erased. Address bits A20–A15 uniquely select any sector.
WBL = Write Buffer Location. Address must be within the same write 
buffer page as PA.
BC = Byte Count. Number of write buffer locations to load minus 1.
Notes:
1. See Tabl e 1 for description of bus operations.
2. All values are in hexadecimal.
3. Except for the read cycle and the fourth cycle of the autoselect 
command sequence, all bus cycles are write cycles.
4. During unlock cycles, when lower address bits are 555 or AAAh 
as shown in table, address bits higher than A11 (except where BA 
is required) and data bits higher than DQ7 are don’t cares.
5. No unlock or command cycles required when device is in read 
mode.
6. The Reset command is required to return to the read mode (or to 
the erase-suspend-read mode if previously in Erase Suspend) 
when the device is in the autoselect mode, or if DQ5 goes high 
while the device is providing status information.
7. The fourth cycle of the autoselect command sequence is a read 
cycle. Data bits DQ15–DQ8 are don’t care. See the Autoselect 
Command Sequence section for more information.
8. The device ID must be read in three cycles. The data is 01h for 
top boot and 00h for bottom boot 
9. If WP# protects the top two address sectors, the data is 98h for 
factory locked and 18h for not factory locked. If WP# protects the 
bottom two address sectors, the data is 88h for factory locked and 
08h for not factor locked.
10. The data is 00h for an unprotected sector group and 01h for a 
protected sector group. 
11. The total number of cycles in the command sequence is 
determined by the number of words written to the write buffer. The 
maximum number of cycles in the command sequence is 37.
12. Command sequence resets device for next command after 
aborted write-to-buffer operation.
13. The Unlock Bypass command is required prior to the Unlock 
Bypass Program command.
14. The Unlock Bypass Reset command is required to return to the 
read mode when the device is in the unlock bypass mode.
15. The system may read and program in non-erasing sectors, or 
enter the autoselect mode, when in the Erase Suspend mode. 
The Erase Suspend command is valid only during a sector erase 
operation.
16. The Erase Resume command is valid only during the Erase 
Suspend mode.
17. Command is valid when device is ready to read array data or when 
device is in autoselect mode.
Command Sequence
(Notes)
Cycles
Bus Cycles (Notes 1–4)
First Second Third  Fourth  Fifth Sixth 
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Read (Note 5) 1 RA RD
Reset (Note 6) 1 XXX F0
Autoselect (Note 7)
Manufacturer ID 4 AAA AA 555 55 AAA 90 X00 01
Device ID (Note 8) 6 AAA AA 555 55 AAA 90 X02 7E X1C 1A X1E 00/01
SecSi™ Sector Factory Protect 
(Note 9) 4 AAA AA 555 55 AAA 90 X06 (Note 9)
Sector Group Protect Verify 
(Note 10) 4 AAA AA 555 55 AAA 90 (SA)X04 00/01
Enter SecSi Sector Region 3 AAA AA 555 55 AAA 88
Exit SecSi Sector Region 4 AAA AA 555 55 AAA 90 XXX 00
Program 4 AAA AA 555 55 AAA A0 PA PD
Write to Buffer (Note 11) 6 AAA AA 555 55 SA 25 SA BC PA PD WBL PD
Program Buffer to Flash 1 SA 29
Write to Buffer Abort Reset (Note 12) 3 AAA AA 555 55 AAA F0
Unlock Bypass 3 AAA AA 555 55 AAA 20
Unlock Bypass Program (Note 13) 2 XXX A0 PA PD
Unlock Bypass Reset (Note 14) 2 XXX 90 XXX 00
Chip Erase 6 AAA AA 555 55 AAA 80 AAA AA 555 55 AAA 10
Sector Erase 6 AAA AA 555 55 AAA 80 AAA AA 555 55 SA 30
Program/Erase Suspend (Note 15) 1 XXX B0
Program/Erase Resume (Note 16) 1 XXX 30
CFI Query (Note 17) 1 AA 98

26518C1 / May 4, 2004

Am29LV320MT/B 35

DATASHEET

WRITE OPERATION STATUS

The device provides several bits to determine the status of a

program or erase operation: DQ2, DQ3, DQ5, DQ6, and

DQ7. Ta b l e 14 and the following subsections describe the

function of these bits. DQ7 and DQ6 each offer a method for

determining whether a program or erase operation is com-

plete or in progress. The device also provides a hard-

ware-based output signal, RY/BY#, to determine

whether an Embedded Program or Erase operation is

in progress or has been completed.

DQ7: Data# Polling

The Data# Polling bit, DQ7, indicates to the host system

whether an Embedded Program or Erase algorithm is in

progress or completed, or whether the device is in Erase

Suspend. Data# Polling is valid after the rising edge of the

final WE# pulse in the command sequence.

During the Embedded Program algorithm, the device out-

puts on DQ7 the complement of the datum programmed to

DQ7. This DQ7 status also applies to programming during

Erase Suspend. When the Embedded Program algorithm is

complete, the device outputs the datum programmed to

DQ7. The system must provide the program address to

read valid status information on DQ7. If a program address

falls within a protected sector, Data# Polling on DQ7 is ac-

tive for approximately 1 µs, then the device returns to the

read mode.

During the Embedded Erase algorithm, Data# Polling

produces a “0” on DQ7. When the Embedded Erase

algorithm is complete, or if the device enters the Erase

Suspend mode, Data# Polling produces a “1” on DQ7.

The system must provide an address within any of the

sectors selected for erasure to read valid status infor-

mation on DQ7.

After an erase command sequence is written, if all

sectors selected for erasing are protected, Data# Poll-

ing on DQ7 is active for approximately 100 µs, then the

device returns to the read mode. If not all selected

sectors are protected, the Embedded Erase algorithm

erases the unprotected sectors, and ignores the se-

lected sectors that are protected. However, if the sys-

tem reads DQ7 at an address within a protected

sector, the status may not be valid.

Just prior to the completion of an Embedded Program

or Erase operation, DQ7 may change asynchronously

with DQ0–DQ6 while Output Enable (OE#) is asserted

low. That is, the device may change from providing

status information to valid data on DQ7. Depending on

when the system samples the DQ7 output, it may read

the status or valid data. Even if the device has com-

pleted the program or erase operation and DQ7 has

valid data, the data outputs on DQ0–DQ6 may be still

invalid. Valid data on DQ0–DQ7 will appear on suc-

cessive read cycles.

Table 14 shows the outputs for Data# Polling on DQ7.

Figure 8 shows the Data# Polling algorithm. Figure 20

in the AC Characteristics section shows the Data#

Polling timing diagram.

Figure 8. Data# Polling Algorithm

DQ7 = Data? Yes

DQ5 = 1?

Yes

FAIL PASS

Read DQ7–DQ0

Addr = VA

Read DQ7–DQ0

Addr = VA

DQ7 = Data?

START

Notes:

1. VA = Valid address for programming. During a sector

erase operation, a valid address is any sector address

within the sector being erased. During chip erase, a

valid address is any non-protected sector address.

2. DQ7 should be rechecked even if DQ5 = “1” because

DQ7 may change simultaneously with DQ5.

36 Am29LV320MT/B

26518C1 / May 4, 2004

DATASHEET

RY/BY#: Ready/Busy#

The RY/BY# is a dedicated, open-drain output pin

which indicates whether an Embedded Algorithm is in

progress or complete. The RY/BY# status is valid after

the rising edge of the final WE# pulse in the command

sequence. Since RY/BY# is an open-drain output, sev-

eral RY/BY# pins can be tied together in parallel with a

pull-up resistor to VCC.

If the output is low (Busy), the device is actively eras-

ing or programming. (This includes programming in

the Erase Suspend mode.) If the output is high

(Ready), the device is in the read mode, the standby

mode, or in the erase-suspend-read mode. Ta ble 1 4

shows the outputs for RY/BY#.

DQ6: Toggle Bit I

Toggle Bit I on DQ6 indicates whether an Embedded

Program or Erase algorithm is in progress or com-

plete, or whether the device has entered the Erase

Suspend mode. Toggle Bit I may be read at any ad-

dress, and is valid after the rising edge of the final

WE# pulse in the command sequence (prior to the

program or erase operation), and during the sector

erase time-out.

During an Embedded Program or Erase algorithm op-

eration, successive read cycles to any address cause

DQ6 to toggle. The system may use either OE# or

CE# to control the read cycles. When the operation is

complete, DQ6 stops toggling.

After an erase command sequence is written, if all sectors

selected for erasing are protected, DQ6 toggles for approxi-

mately 100 µs, then returns to reading array data. If not all

selected sectors are protected, the Embedded Erase algo-

rithm erases the unprotected sectors, and ignores the se-

lected sectors that are protected.

The system can use DQ6 and DQ2 together to determine

whether a sector is actively erasing or is erase-suspended.

When the device is actively erasing (that is, the Embedded

Erase algorithm is in progress), DQ6 toggles. When the de-

vice enters the Erase Suspend mode, DQ6 stops toggling.

However, the system must also use DQ2 to determine

which sectors are erasing or erase-suspended. Alterna-

tively, the system can use DQ7 (see the subsection on

DQ7: Data# Polling).

If a program address falls within a protected sector,

DQ6 toggles for approximately 1 µs after the program

command sequence is written, then returns to reading

array data.

DQ6 also toggles during the erase-suspend-program

mode, and stops toggling once the Embedded Pro-

gram algorithm is complete.

Table 14 shows the outputs for Toggle Bit I on DQ6.

Figure 9 shows the toggle bit algorithm. Figure 21 in

the “AC Characteristics” section shows the toggle bit

timing diagrams. Figure 22 shows the differences be-

tween DQ2 and DQ6 in graphical form. See also the

subsection on DQ2: Toggle Bit II.

26518C1 / May 4, 2004

Am29LV320MT/B 37

DATASHEET

Figure 9. Toggle Bit Algorithm

DQ2: Toggle Bit II

The “Toggle Bit II” on DQ2, when used with DQ6, indi-

cates whether a particular sector is actively erasing

(that is, the Embedded Erase algorithm is in progress),

or whether that sector is erase-suspended. Toggle Bit

II is valid after the rising edge of the final WE# pulse in

the command sequence.

DQ2 toggles when the system reads at addresses

within those sectors that have been selected for era-

sure. (The system may use either OE# or CE# to con-

trol the read cycles.) But DQ2 cannot distinguish

whether the sector is actively erasing or is erase-sus-

pended. DQ6, by comparison, indicates whether the

device is actively erasing, or is in Erase Suspend, but

cannot distinguish which sectors are selected for era-

sure. Thus, both status bits are required for sector and

mode information. Refer to Table 14 to compare out-

puts for DQ2 and DQ6.

Figure 9 shows the toggle bit algorithm in flowchart

form, and the section “DQ2: Toggle Bit II” explains the

algorithm. See also the RY/BY#: Ready/Busy# sub-

section. Figure 21 shows the toggle bit timing diagram.

Figure 22 shows the differences between DQ2 and

DQ6 in graphical form.

Reading Toggle Bits DQ6/DQ2

Refer to Figure 9 for the following discussion. When-

ever the system initially begins reading toggle bit sta-

tus, it must read DQ7–DQ0 at least twice in a row to

determine whether a toggle bit is toggling. Typically,

the system would note and store the value of the tog-

gle bit after the first read. After the second read, the

system would compare the new value of the toggle bit

with the first. If the toggle bit is not toggling, the device

has completed the program or erase operation. The

system can read array data on DQ7–DQ0 on the fol-

lowing read cycle.

However, if after the initial two read cycles, the system

determines that the toggle bit is still toggling, the sys-

tem also should note whether the value of DQ5 is high

(see the section on DQ5). If it is, the system should

then determine again whether the toggle bit is tog-

gling, since the toggle bit may have stopped toggling

just as DQ5 went high. If the toggle bit is no longer

toggling, the device has successfully completed the

program or erase operation. If it is still toggling, the de-

vice did not completed the operation successfully, and

the system must write the reset command to return to

reading array data.

The remaining scenario is that the system initially de-

termines that the toggle bit is toggling and DQ5 has

not gone high. The system may continue to monitor

the toggle bit and DQ5 through successive read cy-

cles, determining the status as described in the previ-

ous paragraph. Alternatively, it may choose to perform

START

Yes

DQ5 = 1?

Yes

Toggle Bit

= Toggle?

Program/Erase

Operation Not

Complete, Write

Reset Command

Program/Erase

Operation Complete

Read DQ7–DQ0

Toggle Bit

= Toggle?

Read DQ7–DQ0

Twice

Read DQ7–DQ0

Note: The system should recheck the toggle bit even if

DQ5 = “1” because the toggle bit may stop toggling as DQ5

changes to “1.” See the subsections on DQ6 and DQ2 for

more information.

38 Am29LV320MT/B
26518C1 / May 4, 2004
DATASHEET
other system tasks. In this case, the system must start
at the beginning of the algorithm when it returns to de-
termine the status of the operation (top of Figure 9).
DQ5: Exceeded Timing Limits
DQ5 indicates whether the program, erase, or
write-to-buffer time has exceeded a specified internal
pulse count limit. Under these conditions DQ5 produces a
“1,” indicating that the program or erase cycle was not suc-
cessfully completed.
The device may output a “1” on DQ5 if the system tries
to program a “1” to a location that was previously pro-
grammed to “0.” Only an erase operation can
change a “0” back to a “1.” Under this condition, the
device halts the operation, and when the timing limit
has been exceeded, DQ5 produces a “1.”
In all these cases, the system must write the reset
command to return the device to the reading the array
(or to erase-suspend-read if the device was previously
in the erase-suspend-program mode).
DQ3: Sector Erase Timer
After writing a sector erase command sequence, the
system may read DQ3 to determine whether or not
erasure has begun. (The sector erase timer does not
apply to the chip erase command.) If additional
sectors are selected for erasure, the entire time-out
also applies after each additional sector erase com-
mand. When the time-out period is complete, DQ3
switches from a “0” to a “1.” If the time between addi-
tional sector erase commands from the system can be
assumed to be less than 50 µs, the system need not
monitor DQ3. See also the Sector Erase Command
Sequence section.
After the sector erase command is written, the system
should read the status of DQ7 (Data# Polling) or DQ6
(Toggle Bit I) to ensure that the device has accepted
the command sequence, and then read DQ3. If DQ3 is
“1,” the Embedded Erase algorithm has begun; all fur-
ther commands (except Erase Suspend) are ignored
until the erase operation is complete. If DQ3 is “0,” the
device will accept additional sector erase commands.
To ensure the command has been accepted, the sys-
tem software should check the status of DQ3 prior to
and following each subsequent sector erase com-
mand. If DQ3 is high on the second status check, the
last command might not have been accepted.
Table 14 shows the status of DQ3 relative to the other
status bits.
DQ1: Write-to-Buffer Abort
DQ1 indicates whether a Write-to-Buffer operation
was aborted. Under these conditions DQ1 produces a
“1”. The system must issue the
Write-to-Buffer-Abort-Reset command sequence to re-
turn the device to reading array data. See Write Buffer
Table 14. Write Operation Status
Notes:
1. DQ5 switches to ‘1’ when an Embedded Program, Embedded Erase, or Write-to-Buffer operation has exceeded the 
maximum timing limits. Refer to the section on DQ5 for more information.
2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.
3. The Data# Polling algorithm should be used to monitor the last loaded write-buffer address location.
4. DQ1 switches to ‘1’ when the device has aborted the write-to-buffer operation.
Status
DQ7
(Note 2) DQ6
DQ5
(Note 1) DQ3
DQ2
(Note 2) DQ1 RY/BY#
Standard 
Mode
Embedded Program Algorithm DQ7# Toggle 0 N/A No toggle 0 0
Embedded Erase Algorithm 0 Toggle 0 1 Toggle N/A 0
Program 
Suspend 
Mode
Program-
Suspend 
Read
Program-Suspended 
Sector Invalid (not allowed) 1
Non-Program
Suspended Sector Data 1
Erase 
Suspend 
Mode
Erase-
Suspend 
Read
Erase-Suspended 
Sector 1 No toggle 0 N/A Toggle N/A 1
Non-Erase Suspended 
Sector Data 1
Erase-Suspend-Program 
(Embedded Program) DQ7# Toggle 0 N/A N/A N/A 0
Write-to-
Buffer
Busy (Note 3) DQ7# Toggle 0 N/A N/A 0 0
Abort (Note 4) DQ7# Toggle 0 N/A N/A 1 0

26518C1 / May 4, 2004

Am29LV320MT/B 39

DATASHEET

ABSOLUTE MAXIMUM RATINGS

Storage Temperature

Plastic Packages . . . . . . . . . . . . . . . –65°C to +150°C

Ambient Temperature

with Power Applied. . . . . . . . . . . . . . –55°C to +125°C

Voltage with Respect to Ground

VCC (Note 1) . . . . . . . . . . . . . . . . .–0.5 V to +4.0 V

VIO . . . . . . . . . . . . . . . . . . . . . . . . .–0.5 V to +4.0 V

A9, OE#, ACC, and RESET#

(Note 2) . . . . . . . . . . . . . . . . . . . .–0.5 V to +12.5 V

All other pins (Note 1) . . . . . . –0.5 V to VCC +0.5 V

Output Short Circuit Current (Note 3) . . . . . . 200 mA

Notes:

1. Minimum DC voltage on input or I/O pins is –0.5 V.

During voltage transitions, input or I/O pins may

overshoot V

to –2.0 V for periods of up to 20 ns.

Maximum DC voltage on input or I/O pins is V

+0.5 V.

See Figure 10. During voltage transitions, input or I/O

pins may overshoot to V

+2.0 V for periods up to 20 ns.

See Figure 11.

2. Minimum DC input voltage on pins A9, OE#, ACC, and

RESET# is –0.5 V. During voltage transitions, A9, OE#,

ACC, and RESET# may overshoot V

to –2.0 V for

periods of up to 20 ns. See Figure 10. Maximum DC

input voltage on pin A9, OE#, ACC, and RESET# is

+12.5 V which may overshoot to +14.0 V for periods up

to 20 ns.

3. No more than one output may be shorted to ground at a

time. Duration of the short circuit should not be greater

than one second.

Stresses above those listed under “Absolute Maximum

Ratings” may cause permanent damage to the device. This

is a stress rating only; functional operation of the device at

these or any other conditions above those indicated in the

operational sections of this data sheet is not implied.

Exposure of the device to absolute maximum rating

conditions for extended periods may affect device reliability.

OPERATING RANGES

Commercial (C) Devices

Ambient Temperature (TA) . . . . . . . . . . . 0°C to +70°C

Industrial (I) Devices

Ambient Temperature (TA) . . . . . . . . . –40°C to +85°C

Supply Voltages

VCC for full voltage range . . . . . . . . . . . . . . . 2.7–3.6 V

VCC for regulated voltage range . . . . . . . . . . 3.0–3.6 V

Note: Operating ranges define those limits between which

the functionality of the device is guaranteed.

20 ns

+0.8 V

–0.5 V

20 ns

–2.0 V

Figure 10.

Maximum Negative

Overshoot Waveform

20 ns

VCC

+2.0 V

VCC

+0.5 V

20 ns

2.0 V

Figure 11.

Maximum Positive

Overshoot Waveform

40 Am29LV320MT/B
26518C1 / May 4, 2004
DATASHEET
DC CHARACTERISTICS
CMOS Compatible
Notes:
1. On the WP#/ACC pin only, the maximum input load current when WP# = V
IL
 is ± 5.0 µA.
2. The I
CC
 current listed is typically less than 2 mA/MHz, with OE# at V
IH
.
3. Maximum I
CC
 specifications are tested with V
CC
 = V
CC
max.
4. I
CC
 active while Embedded Erase or Embedded Program is in progress.
5. Automatic sleep mode enables the low power mode when addresses remain stable for t
ACC
 + 30 ns. V
CC
 voltage requirements. 
6. Not 100% tested.
Parameter 
Symbol
Parameter Description 
(Notes) Test Conditions  Min Typ Max Unit
ILI Input Load Current (1) VIN = VSS to VCC, 
VCC = VCC max 
±1.0 µA
ILIT A9, ACC Input Load Current VCC = VCC max; A9 = 12.5 V 35 µA
ILR Reset Leakage Current VCC = VCC max; RESET# = 12.5 V 35 µA
ILO Output Leakage Current VOUT = VSS to VCC, 
VCC = VCC max
±1.0 µA
ICC1
VCC Active Read Current 
(2, 3) CE# = VIL, OE# = VIH,  5 MHz 3 34 mA
1 MHz 13 43
ICC2 VCC Initial Page Read Current (2, 3) CE# = VIL, OE# = VIH
1 MHz 4 50
mA10 MHz 40 80
ICC3 VCC Intra-Page Read Current (2, 3) CE# = VIL, OE# = VIH
10 MHz 3 20
33 MHz 6 40 mA
ICC4 VCC Active Write Current (3, 4) CE# = VIL, OE# = VIH 50 60 mA
ICC5 VCC Standby Current (3) CE#, RESET# = VCC ± 0.3 V,
WP# = VIH
15µA
ICC6 VCC Reset Current (3) RESET# = VSS ± 0.3 V, WP# = VIH 15µA
ICC7 Automatic Sleep Mode (3, 5) VIH = VCC ± 0.3 V; 
VIL = VSS ± 0.3 V, WP# = VIH
15µA
VIL Input Low Voltage (5) – 0.5 V 0.8 V
VIH Input High Voltage (5) 1.9 V VCC + 0.5 V
VID
Voltage for Autoselect and Temporary 
Sector Unprotect VCC = 2.7 –3.6 V 11.5 12.5 V
VOL Output Low Voltage IOL = 4.0 mA, VCC = VCC min  0.15 x VCC V
VOH1 Output High Voltage IOH = –2.0 mA, VCC = VCC min 0.85 VCC V
VOH2 IOH = –100 µA, VCC = VCC min V
CC–0.4 V
VLKO Low VCC Lock-Out Voltage (6) 2.3 2.5 V

26518C1 / May 4, 2004

Am29LV320MT/B 41

DATASHEET

TEST CONDITIONS

Table 15. Test Specifications

KEY TO SWITCHING WAVEFORMS

2.7 kΩ

CL6.2 kΩ

3.3 V

Device

Under

Te s t

Note:

Diodes are IN3064 or equivalent

Figure 12. Test Setup

Test Condition All Speeds Unit

Output Load 1 TTL gate

Output Load Capacitance, CL

(including jig capacitance) 30 pF

Input Rise and Fall Times 5 ns

Input Pulse Levels 0.0–3.0 V

Input timing measurement

reference levels 1.5 V

Output timing measurement

reference levels 1.5 V

WAVEFORM INPUTS OUTPUTS

Steady

Changing from H to L

Changing from L to H

Don’t Care, Any Change Permitted Changing, State Unknown

Does Not Apply Center Line is High Impedance State (High Z)

3.0 V

0.0 V

1.5 V 1.5 V OutputMeasurement LevelInput

Figure 13. Input Waveforms and

Measurement Levels

42 Am29LV320MT/B

26518C1 / May 4, 2004

DATASHEET

AC CHARACTERISTICS

Read-Only Operations

Notes:

1. Not 100% tested.

2. See Figure 12 and Table 15 for test specifications.

Parameter

Description Test Setup

Speed Options

JEDEC Std. 90R 95R

100R,

100 110R 110 120R 120 Unit

tAVAV tRC Read Cycle Time (Note 1) Min 90 95 100 110 120 ns

tAVQV tACC Address to Output Delay CE#,

OE# = VIL

Max 90 95 100 110 120 ns

tELQV tCE Chip Enable to Output Delay OE# = VIL Max 90 95 100 110 120 ns

tPAC C Page Access Time Max 25 30 30 30 40 30 40 ns

tGLQV tOE Output Enable to Output Delay Max 25 30 30 30 40 30 40 ns

tEHQZ tDF

Chip Enable to Output High Z

(Note 1) Max 25 ns

tGHQZ tDF

Output Enable to Output High Z

(Note 1) Max 25 ns

tAXQX tOH

Output Hold Time From

Addresses, CE# or OE#,

Whichever Occurs First

Min 0 ns

tOEH

Output Enable

Hold Time

(Note 1)

Read Min 0 ns

Toggle and

Data# Polling Min 10 ns

tOH

tCE

Outputs

WE#

Addresses

CE#

OE#

HIGH Z

Output Valid

HIGH Z

Addresses Stable

tRC

tACC

tOEH

tRH

tOE

tRH

0 V

RY/BY#

RESET#

tDF

Figure 14. Read Operation Timings

26518C1 / May 4, 2004

Am29LV320MT/B 43

DATASHEET

AC CHARACTERISTICS

* Figure shows word mode. Addresses are A1–A-1 for byte mode.

Figure 15. Page Read Timings

A21

CE#

OE#

Data Bus

Same Page

Aa Ab Ac Ad

Qa Qb Qc Qd

ACC

PA C C

44 Am29LV320MT/B

26518C1 / May 4, 2004

DATASHEET

AC CHARACTERISTICS

Hardware Reset (RESET#)

Note: Not 100% tested.

Parameter

Description All Speed Options UnitJEDEC Std.

tReady

RESET# Pin Low (During Embedded Algorithms)

to Read Mode (See Note) Max 20 µs

tReady

RESET# Pin Low (NOT During Embedded

Algorithms) to Read Mode (See Note) Max 500 ns

tRP RESET# Pulse Width Min 500 ns

tRH Reset High Time Before Read (See Note) Min 50 ns

tRPD RESET# Low to Standby Mode Min 20 µs

RESET#

RY/BY#

tRP

tReady

Reset Timings NOT during Embedded Algorithms

tReady

CE#, OE#

tRH

CE#, OE#

Reset Timings during Embedded Algorithms

RESET#

tRP

tRB

Figure 16. Reset Timings

26518C1 / May 4, 2004
Am29LV320MT/B 45
DATASHEET
AC CHARACTERISTICS
Erase and Program Operations
Notes:
1. Not 100% tested.
2. See the “Erase And Programming Performance” section for more 
information.
3. For 1–16 words (or 1–32 bytes) programmed. 
4. Effective write buffer specification is based upon a 16-word (or 
32-byte) write buffer operation.
5. Word/Byte programming specification is based upon a single 
word/byte programming operation not utilizing the write buffer.
6. When using the program suspend/resume feature, if the suspend 
command is issued within tPOLL, tPOLL must be fully re-applied 
upon resuming the programming operation. If the suspend 
command is issued after tPOLL, tPOLL is not required again prior to 
reading the status bits upon resuming.
Parameter Speed Options
JEDEC Std. Description 90R 95R
100,
100R
110,
110R
120,
120R Unit
tAVAV tWC Write Cycle Time (Note 1) Min 90 95 100 110 120 ns
tAVWL tAS Address Setup Time Min 0 ns
tASO
Address Setup Time to OE# Low during Toggle 
Bit Polling  Min 15 ns
tWLAX tAH Address Hold Time Min 45 ns
tAHT
Address Hold Time From CE# or OE#High 
during Toggle Bit Polling Min 0 ns
tDVWH tDS Data Setup Time Min 45 ns
tWHDX tDH Data Hold Time Min 0 ns
tOEPH Output Enable High during Toggle Bit Polling Min 20 ns
tGHWL tGHWL
Read Recovery Time before Write 
(OE# High to WE# Low) Min 0 ns
tELWL tCS CE# Setup Time Min 0 ns
tWHEH tCH CE# Hold Time Min 0 ns
tWLWH tWP Write Pulse Width Min 35 ns
tWHDL tWPH Write Pulse Width High Min 30 ns
tWHWH1 tWHWH1
Write Buffer Program Operation (Notes 2, 3) Typ 240 µs
Effective Write Buffer Program 
Operation (Notes 2, 4)
Per Byte Typ 7.5 µs
Per Word Typ 15 µs
Accelerated Effective Write Buffer 
Program Operation (Notes 2, 4)
Per Byte Typ 6.25 µs
Per Word Typ 12.5 µs
Single Word/Byte Program 
Operation (Note 2, 5)
Byte
Ty p
60 µs
Word 60 µs
Accelerated Single Word/Byte 
Programming Operation (Note 2, 5)
Byte
Ty p
54 µs
Word 54 µs
tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 0.5 sec
tVHH VHH Rise and Fall Time (Note 1) Min 250 ns
tVCS VCC Setup Time (Note 1) Min 50 µs
tBUSY WE# to RY/BY# Min 90 95 100 110 120 ns
tPOLL Program Valid before Status Polling (Note 6) Max 4 µs

46 Am29LV320MT/B

26518C1 / May 4, 2004

DATASHEET

AC CHARACTERISTICS

OE#

WE#

CE#

VCC

Data

Addresses

tDS

tAH

tDH

tWP

tWHWH1

tWC tAS

tWPH

tVCS

555h PA PA

Read Status Data (last two cycles)

A0h

tCS

Status DOUT

Program Command Sequence (last two cycles)

RY/BY#

tRB

tBUSY

tCH

tPOLL

Notes:

1. PA = program address, PD = program data, D

OUT

is the true data at the program address.

2. Illustration shows device in word mode.

Figure 17. Program Operation Timings

ACC

tVHH

VHH

VIL or VIH VIL or VIH

tVHH

Figure 18. Accelerated Program Timing Diagram

26518C1 / May 4, 2004

Am29LV320MT/B 47

DATASHEET

AC CHARACTERISTICS

OE#

CE#

Addresses

VCC

WE#

Data

2AAh SA

tAH

tWP

tWC tAS

tWPH

555h for chip erase

10 for Chip Erase

30h

tDS

tVCS

tCS

tDH

55h

tCH

Progress Complete

tWHWH2

Erase Command Sequence (last two cycles) Read Status Data

RY/BY#

tRB

tBUSY

Notes:

1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status”.

2. These waveforms are for the word mode.

Figure 19. Chip/Sector Erase Operation Timings

48 Am29LV320MT/B

26518C1 / May 4, 2004

DATASHEET

AC CHARACTERISTICS

WE#

CE#

OE#

High Z

tOE

High Z

DQ7

DQ0–DQ6

RY/BY#

tBUSY

Complement Tr u e

Addresses VA

tOEH

tCE

tCH

tOH

tDF

VA VA

Status Data

Complement

Status Data Tr u e

Valid Data

tACC

tPOLL

tRC

Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data

read cycle.

Figure 20. Data# Polling Timings (During Embedded Algorithms)

26518C1 / May 4, 2004

Am29LV320MT/B 49

DATASHEET

AC CHARACTERISTICS

OE#

CE#

WE#

Addresses

OEH

AHT

ASO

OEPH

Valid Data

(first read) (second read) (stops toggling)

CEPH

AHT

DQ6/DQ2 Valid Data

Valid

Status

Valid

Status

Valid

Status

RY/BY#

Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status

read cycle, and array data read cycle

Figure 21. Toggle Bit Timings (During Embedded Algorithms)

Note: DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE# or CE# to toggle

DQ2 and DQ6.

Figure 22. DQ2 vs. DQ6

Enter

Erase

Enter Erase

Suspend Program

Erase Suspend

Read Erase Suspend

Read

Erase

WE#

DQ6

DQ2

Erase

Complete

Erase

Suspend

Program

Resume

Embedded

Erasing

50 Am29LV320MT/B

26518C1 / May 4, 2004

DATASHEET

AC CHARACTERISTICS

Temporary Sector Unprotect

Note: Not 100% tested.

Parameter

All Speed OptionsJEDEC Std Description Unit

tVIDR VID Rise and Fall Time (See Note) Min 500 ns

tRSP

RESET# Setup Time for Temporary Sector

Unprotect Min 4 µs

RESET#

tVIDR

VID

VSS, VIL,

or VIH

VID

VSS, VIL,

or VIH

CE#

WE#

RY/BY#

tVIDR

tRSP

Program or Erase Command Sequence

tRRB

Figure 23. Temporary Sector Group Unprotect Timing Diagram

26518C1 / May 4, 2004

Am29LV320MT/B 51

DATASHEET

AC CHARACTERISTICS

Sector Group Protect: 150 µs,

Sector Group Unprotect: 15 ms

1 µs

RESET#

SA, A6,

A1, A0

Data

CE#

WE#

OE#

60h 60h 40h

Valid* Valid* Valid*

Status

Sector Group Protect or Unprotect Verify

VID

VIH

* For sector group protect, A6–A0 = 0xx0010. For sector group unprotect, A6–A0 = 1xx0010.

Figure 24. Sector Group Protect and Unprotect Timing Diagram

52 Am29LV320MT/B
26518C1 / May 4, 2004
DATASHEET
AC CHARACTERISTICS
Alternate CE# Controlled Erase and Program Operations
Notes:
1. Not 100% tested.
2. See the “Erase And Programming Performance” section for more information.
3. For 1–16 words (or 1–32 bytes in byte mode) programmed.
4. Effective write buffer specification is based upon a 16-word (or 32-byte) write buffer operation.
5. Word/Byte programming specification is based upon a single word/byte programming operation not utilizing the write buffer.
6. When using the program suspend/resume feature, if the suspend command is issued within t
POLL
, t
POLL 
must be fully re-applied 
upon resuming the programming operation. If the suspend command is issued after t
POLL
, t
POLL
 is not required again prior to 
reading the status bits upon resuming.
Parameter Speed Options
JEDEC Std. Description 90R 95R
100,
100R
110,
110R
120,
120R Unit
tAVAV tWC Write Cycle Time (Note 1) Min 90 95 100 110 120 ns
tAVWL tAS Address Setup Time Min 0 ns
tELAX tAH Address Hold Time Min 45 ns
tDVEH tDS Data Setup Time Min 45 ns
tEHDX tDH Data Hold Time Min 0 ns
tGHEL tGHEL
Read Recovery Time Before Write 
(OE# High to WE# Low) Min 0 ns
tWLEL tWS WE# Setup Time Min 0 ns
tEHWH tWH WE# Hold Time Min 0 ns
tELEH tCP CE# Pulse Width Min 45 ns
tEHEL tCPH CE# Pulse Width High Min 30 ns
tWHWH1 tWHWH1
Write Buffer Program Operation (Notes 2, 3) Typ 240 µs
Effective Write Buffer Program 
Operation (Notes 2, 4)
Per Byte Typ 7.5 µs
Per Word Typ 15 µs
Accelerated Effective Write Buffer 
Program Operation (Notes 2, 4)
Per Byte Typ 6.25 µs
Per Word Typ 12.5 µs
Single Word/Byte Program Operation 
(Note 2, 5)
Byte
Typ
60 µs
Word 60 µs
Accelerated Single Word/Byte 
Programming Operation (Note 2, 5)
Byte
Typ
54 µs
Word 54 µs
tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 0.5 sec
tRH RESET# High Time Before Write (Note 1) Min 50 ns
tPOLL Program Valid before Status Polling (Note 6) Max 4 µs

26518C1 / May 4, 2004

Am29LV320MT/B 53

DATASHEET

AC CHARACTERISTICS

tGHEL

tWS

OE#

CE#

WE#

RESET#

tDS

Data

tAH

Addresses

tDH

tCP

DQ7# D

OUT

tWC tAS

tCPH

Data# Polling

A0 for program

55 for erase

tRH

tWHWH1 or 2

tPOLL

RY/BY#

tWH

PD for program

30 for sector erase

10 for chip erase

555 for program

2AA for erase

PA for program

SA for sector erase

555 for chip erase

tBUSY

otes:

. Figure indicates last two bus cycles of a program or erase operation.

. PA = program address, SA = sector address, PD = program data.

. DQ7# is the complement of the data written to the device. D

OUT

is the data written to the device.

. Waveforms are for the word mode.

Figure 25. Alternate CE# Controlled Write (Erase/Program)

Operation Timings

54 Am29LV320MT/B
26518C1 / May 4, 2004
DATASHEET
ERASE AND PROGRAMMING PERFORMANCE
Notes:
1. Typical program and erase times assume the following conditions: 25
°
C, 3.0 V V
CC
, Programming specification assume that 
all bits are programmed to 00h.
2. Maximum values are measured at V
CC
 = 3.0, worst case temperature. Maximum values are valid up to and including 100,000 
program/erase cycles.
3. Word/Byte programming specification is based upon a single word/byte programming operation not utilizing the write buffer.
4. For 1-16 words or 1-32 bytes programmed in a single write buffer programming operation.
5. Effective write buffer specification is calculated on a per-word/per-byte basis for a 16-word/32-byte write buffer operation.
6. In the pre-programming step of the Embedded Erase algorithm, all bits are programmed to 00h before erasure.
7. System-level overhead is the time required to execute the command sequence (s) for the program command. See Tables 12 and 
13 for further information on command definitions.
8. The device has a minimum erase and program cycle endurance of 100,000 cycles.
LATCHUP CHARACTERISTICS
Note: Includes all pins except V
CC
. Test conditions: V
CC
 = 3.0 V, one pin at a time.
Parameter Typ (Note 1) Max (Note 2) Unit Comments
Sector Erase Time 0.5 3.5 sec Excludes 00h programming 
prior to erasure (Note 6)
Chip Erase Time 32 64 sec
Single Word/Byte Program Time (Note 3) 60 600 µs
Excludes system level 
overhead (Note 7)
Accelerated Single Word/Byte Program Time (Note 3) 54 540 µs
Total Write Buffer Program Time (Note 4) 240 1200 µs
Effective Write Buffer Program Time (Note 5)
Per Byte 7.5 38 µs
Per Word 15 75 µs
Total Accelerated Write Buffer Program Time (Note 4) 200 1040 µs
 Effective Accelerated Write Buffer Program Time 
(Note 5)
Per Byte 6.25 33 µs
Per Word 12.5 65 µs
Chip Program Time  31.5 73 sec
Description Min Max
Input voltage with respect to VSS on all pins except I/O pins 
(including A9, OE#, and RESET#) –1.0 V 12.5 V
Input voltage with respect to VSS on all I/O pins –1.0 V VCC + 1.0 V
VCC Current –100 mA +100 mA

26518C1 / May 4, 2004

Am29LV320MT/B 55

DATASHEET

TSOP PIN AND BGA PACKAGE CAPACITANCE

Notes:

1. Sampled, not 100% tested.

2. Test conditions T

= 25°C, f = 1.0 MHz.

DATA RETENTION

Parameter Symbol Parameter Description Test Setup Typ Max Unit

CIN Input Capacitance VIN = 0 TSOP 6 7.5 pF

Fine-Pitch BGA 4.2 5.0 pF

COUT Output Capacitance VOUT = 0 TSOP 8.5 12 pF

Fine-Pitch BGA 5.4 6.5 pF

CIN2 Control Pin Capacitance VIN = 0 TSOP 7.5 9 pF

Fine-Pitch BGA 3.9 4.7 pF

Parameter Description Test Conditions Min Unit

Minimum Pattern Data Retention Time

150°C10Years

125°C20Years

56 Am29LV320MT/B

26518C1 / May 4, 2004

DATASHEET

PHYSICAL DIMENSIONS

TS 048—48-Pin Standard Pinout Thin Small Outline Package (TSOP)

Dwg rev AA; 10/99

26518C1 / May 4, 2004

Am29LV320MT/B 57

DATASHEET

PHYSICAL DIMENSIONS

FBC048—48-Ball Fine-pitch Ball Grid Array (BGA) 9 x 8 mm Package

FBC 048

Dwg rev AF; 10/99

58 Am29LV320MT/B

26518C1 / May 4, 2004

DATASHEET

PHYSICAL DIMENSIONS

LAA064—64-Ball Fortified Ball Grid Array (BGA) 13 x 11 mm Package

26518C1 / May 4, 2004

Am29LV320MT/B 59

DATASHEET

REVISION SUMMARY

Revision A (June 21, 2002)

Initial release.

Revision A+1 (August 9, 2002)

MIRRORBIT 64 MBIT Device Family

Added 64 Fortified BGA to LV640MU device.

Alternate CE# Controlled Erase and Program

Operations

Added tRH parameter to table.

Erase and Program Operations

Added tBUSY parameter to table.

CMOS Compatable

Deleted the IACC specification row in DC Characteris-

tics table.

Figure 16. Program Operation Timings

Added RY/BY# to waveform.

TSOP and BGA PIN Capacitance

Added the FBGA package.

Program Suspend/Program Resume Command

Sequence

Changed 15 µs typical to maximum and added 5 µs

typical.

Erase Suspend/Erase Resume Commands

Changed typical from 20 µs to 5 µs and added a maxi-

mum of 20 µs.

Mirrorbit 32 Mbit Device Family

Changed 48-pin TSOP to 40-pin TSOP.

Product Selector Guide, Valid Combinations Table,

Read-Only Operations, Erase and Program

Operations and Alternate CE# Controlled Erase

and Program Operations

Added regulated OPN to table.

Common Flash Memory Interface

Changed the text in the third paragraph to end with”...

reading array data.”

Command Definitions

Modified the last sentences in the first paragraph.

Revision A+2 (September 19, 2002)

Distinctive Characteristics

Changed the flexible sector architecture from

Sixty-four 32 Kword/64-Kbyte sectors to Sixty-three 32

Kword/64-Kbyte sectors.

Revision A+3 (November 19, 2002)

Product Selector Guide and Read Only Operations

Changed the page access times and TOE

Moved the reverse speed options up into correct row.

Changed VCC range for full speed option to 2.7-3.6.

Ordering Information and Physical Dimensions

Removed FBD048 package.

Added FBC048 package.

Added TS048 package.

Changed order numbers and package markings to re-

flect new package.

Table 7. SecSi Sector Contents

Changed the x8 Secsi Sector Address range to

000010h–0000FFh.

Customer Lockable: SecSi Sector NOT

Programmed or Protected at the factory.

Added second bullet, SecSi sector-protect verify text

and figure 3.

SecSi Sector Flash Memory Region, and Enter

SecSi Sector/Exit SecSi Sector Command

Sequence

Noted that the ACC function and unlock bypass modes

are not available when the SecSi sector is enabled.

Byte/Word Program Command Sequence, Sector

Erase Command Sequence, and Chip Erase Com-

mand Sequence

Noted

that the SecSi Sector, autoselect, and CFI

functions are unavailable when a program or erase

operation is in progress.”

Common Flash Memory Interface (CFI)

Changed wording in last sentence of third paragraph

from, “...the autoselect mode.” to “...reading array

data.”

Changed CFI website address.

60 Am29LV320MT/B
26518C1 / May 4, 2004
DATASHEET
Erase and Programming Performance
Changed the typicals and/or maximums of the Chip
Erase Time, Effective Write Buffer Program Time,
Byte/Word Program Time, and Accelerated Effective
Program Time to TBD.
Revision A+4 (February 16, 2003)
Distinctive Characteristics
Corrected performance characteristics.
Product Selector Guide
Added note 2.
Ordering Information
Corrected Valid Combinations table.
Added Note.
AC Characteristics
Input values in the tWHWH1 and tWHWH2 parameters in
the Erase and Program Options table that were previ-
ously TBD. Also, added note 5.
Input values in the tWHWH1 and tWHWH2 parameters in
the Alternate CE# Controlled Erase and Program Op-
tions table that were previously TBD. Also, added note
5.
Erase and Programming Performance
Input values into table that were previously TBD.
Added note 3 and 4
Revision B (May 16, 2003)
Distinctive Characteristics
Added typical active read current
Global
Converted to full data sheet version.
Modified SecSi Sector Flash Memory Region section
to include ESN references.
CMOS Compatible
Corrected Typ and Max values for the ICC 1, 2, and 3.
Erase and Program Operations and Alternate CE# 
Controlled Erase and Program Operations
Changed Accelerated Effective Write Buffer Program
Operation value.
Erase and Programming Performance
Input values into table that were previously TBD.
Modified notes.
Removed Word references.
Revision C (February 12, 2004)
Global
Added 95R speed option.
Related Documents
Added URL for MirrorBit web content. Deleted list of
application notes.
Ordering Information
Added commercial temperature to 90R speed options
for FBC048 package.
Table 1, Device Bus Operations
Replaced don’t cares with high/low input in ACC col-
umn.
Erase Suspend/Erase Resume Commands
Clarified that address of the erase-suspended sector
is not required for this command. Added note to clarify
behavior of the device when given erase suspend/re-
sume commands in rapid succession.
Tables 12 and 13, Command Definitions
Corrected address requirement for erase suspend and
erase resume commands. Addresses are don’t care.
AC Characteristics
Erase and Program Operations table:
 Added tPOLL
specification.
Added tPOLL timing to Figure 17, Program Operation
Timings; Figure 20, Data# Polling Timings (During
Embedded Algorithms); and Figure 25, Alternate CE#
Controlled Write (Erase/Program)  Operation Timings.
Trademarks
Updated.
Revision C + 1 (May 4, 2004)
Command Definitions table
Corrected information in the first, second, and third
bus cycles for the Program Command sequence.

26518C1 / May 4, 2004

Am29LV320MT/B 61

DATASHEET

Trademarks

AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc.

ExpressFlash is a trademark of Advanced Micro Devices, Inc.

Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.