DS3486
www.ti.com
SNLS354D –MAY 1998–REVISED APRIL 2013
DS3486 Quad RS-422, RS-423 Line Receiver
Check for Samples: DS3486
1FEATURES DESCRIPTION
Texas Instruments' quad RS-422, RS-423 receiver
2• Four Independent Receivers features four independent receivers which comply
• TRI-STATE Outputs with EIA Standards for the electrical characteristics of
• Internal Hysteresis −140 mV (typ) balanced/unbalanced voltage digital interface circuits.
Receiver outputs are 74LS compatible, TRI-STATE
• Fast Propagation Times −19 ns (typ) structures which are forced to a high impedance state
• TTL Compatible Outputs when the appropriate output control pin reaches a
• 5V Supply logic zero condition. A PNP device buffers each
output control pin to assure minimum loading for
• Pin Compatible and Interchangeable with either logic one or logic zero inputs. In addition, each
MC3486 receiver has internal hysteresis circuitry to improve
noise margin and discourage output instability for
slowly changing input waveforms.
Block and Connection Diagrams
Figure 1. Dual-In-Line Package
Top View
D-16 (SOIC) Package or NFG0016E (PDIP)
Package
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 1998–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
DS3486
SNLS354D –MAY 1998–REVISED APRIL 2013
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings(1)(2)
Power Supply Voltage, VCC 8V
Input Common-Mode Voltage, VICM ±25V
Input Differential Voltage, VID ±25V
TRI-STATE Control Input Voltage, VI8V
Output Sink Current, IO50 mA
Storage Temperature, TSTG −65°C to +150°C
Maximum Power Dissipation (3) at 25°C
Molded PDIP Package 1362 mW
SOIC Package 1002 mW
SOIC Package Thermal Resistance
θJA +124.5°C/W
θJC +41.2°C/W
(1) “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be ensured. They are not meant to imply
that the devices should be operated at these limits. The table of “Electrical Characteristics” provides conditions for actual device
operation.
(2) If Military/Aerospace specified devices are required, please contact the TI Sales Office/Distributors for availability and specifications.
(3) Derate PDIP molded package 10.2 mW/°C above 25°C. Derate SOIC package 8.01 mW/°C above 25°C.
Operating Conditions Max Min Units
Power Supply Voltage, VCC 4.75 5.25 V
Operating Temperature, TA0 70 °C
Input Common-Mode Voltage −7.0 7.0 V
Range, VICR
Electrical Characteristics (1)
(Unless otherwise noted, minimum and maximum limits apply over recommended temperature and power supply voltage
ranges. Typical values are for TA= 25°C, VCC = 5V and VIC = 0V.)
Symbol Parameter Conditions Min Typ Max Units
VIH Input Voltage—High Logic State 2.0 V
(TRI-STATE Control)
VIL Input Voltage—Low Logic State 0.8 V
(TRI-STATE Control)
VTH(D) Differential Input Threshold Voltage −7V ≤VIC ≤7V, VIH TRI-STATE = 2V 0.070 0.2 V
IO=−0.4 mA, VOH ≥2.7V
IO= 8 mA, VOL ≥0.5V 0.070 −0.2 V
IIB (D) Input Bias Current VCC = 0V or 5.25V, Other Inputs at 0V
VI=−10V −3.25 mA
VI=−3V −1.50 mA
VI= 3V 1.50 mA
VI= 10V 3.25 mA
Input Balance −7V ≤VIC ≤7V, VIH(3C) = 2V,
(2)
VOH IO=−0.4 mA, VID = 0.4V 2.7 V
VOL IO= 8 mA, VID =−0.4V 0.5 V
(1) All currents into device pins are shown as positive, out of device pins are negative. All voltages referenced to ground unless otherwise
noted.
(2) Refer to EIA RS-422/3 for exact conditions.
2Submit Documentation Feedback Copyright © 1998–2013, Texas Instruments Incorporated
Product Folder Links: DS3486
DS3486
www.ti.com
SNLS354D –MAY 1998–REVISED APRIL 2013
Electrical Characteristics (1) (continued)
(Unless otherwise noted, minimum and maximum limits apply over recommended temperature and power supply voltage
ranges. Typical values are for TA= 25°C, VCC = 5V and VIC = 0V.)
Symbol Parameter Conditions Min Typ Max Units
IOZ Output TRI-STATE Leakage Current VI(D) = 3V, VIL = 0.8V, VOL = 0.5V −40 μA
VI(D) =−3V, VIL = 0.8V, VOH = 2.7V 40 μA
IOS Output Short-Circuit Current VI(D) = 3V, VIHTRI-STATE = 2V, −15 −100 mA
VO= 0V, (3)
IIL Input Current—Low Logic State VIL = 0.5V −100 μA
(TRI-STATE Control)
IIH Input Current—High Logic State VIH = 2.7V 20 μA
(TRI-STATE Control) VIH = 5.25V 100 μA
VIC Input Clamp Diode Voltage IIN =−10 mA −1.5 V
(TRI-STATE Control)
ICC Power Supply Current All Inputs VIL = 0V 85 mA
(3) Only one output at a time should be shorted.
Switching Characteristics
(Unless otherwise noted, VCC = 5V and TA= 25°C.)
Symbol Parameter Min Typ Max Units
tPHL(D) Propagation Delay Time—Differential Inputs to Output 19 35 ns
Output High to Low
tPLH(D) Output Low to High 19 30 ns
tPLZ TRI-STATE Control to Output 23 35 ns
Output Low to TRI-STATE
tPHZ Output High to TRI-STATE 25 35 ns
tPZH Output TRI-STATE to High 18 30 ns
tPZL Output TRI-STATE to Low 20 30 ns
AC TEST CIRCUIT AND SWITCHING TIME WAVEFORMS
Copyright © 1998–2013, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Links: DS3486
DS3486
SNLS354D –MAY 1998–REVISED APRIL 2013
www.ti.com
Input pulse characteristics:
tTLH = tTHL = 6 ns (10% to 90%)
PRR = 1 MHz, 50% duty cycle
Figure 2. Propagation Delay Differential Input to Output
1.5V for tPHZ and tPLZ
1.5V for tPLZ and tPZL
Input pulse characteristics:
tTLH = tTHL = 6 ns (10% to 90%)
PRR = 1 MHz, 50% duty cycle
tPLZ
4Submit Documentation Feedback Copyright © 1998–2013, Texas Instruments Incorporated
Product Folder Links: DS3486
DS3486
SNLS354D –MAY 1998–REVISED APRIL 2013
www.ti.com
REVISION HISTORY
Changes from Revision C (April 2013) to Revision D Page
• Changed layout of National Data Sheet to TI format ............................................................................................................ 5
6Submit Documentation Feedback Copyright © 1998–2013, Texas Instruments Incorporated
Product Folder Links: DS3486
PACKAGE OPTION ADDENDUM
www.ti.com 24-Aug-2018
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
DS3486M/NOPB ACTIVE SOIC D 16 48 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM 0 to 70 DS3486M
DS3486MX/NOPB ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM 0 to 70 DS3486M
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 24-Aug-2018
Addendum-Page 2
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
DS3486MX/NOPB SOIC D 16 2500 330.0 16.4 6.5 10.3 2.3 8.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 18-Aug-2014
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
DS3486MX/NOPB SOIC D 16 2500 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 18-Aug-2014
Pack Materials-Page 2
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