HEF4013BTD-T - NXP Semiconductors / Philips Semiconductors

1. General description

The HEF4013B is a dual D-type ﬂip-ﬂop that features independent set-direct input (SD),

clear-direct input (CD), clock input (CP) and outputs (Q, Q). Data is accepted when CP is

LOW and is transferred to the output on the positive-going edge of the clock. The active

HIGH asynchronous CD and SD inputs are independent and override the D or CP inputs.

The outputs are buffered for best system performance. The clock input’s Schmitt-trigger

action makes the circuit highly tolerant of slower clock rise and fall times.

It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS

(usually ground). Unused inputs must be connected to VDD, VSS, or another input. The

device is suitable for use over both the industrial (−40 °C to +85 °C) and automotive

(−40 °C to +125 °C) temperature ranges.

2. Features

nTolerant of slow clock rise and fall times

nFully static operation

n5 V, 10 V, and 15 V parametric ratings

nStandardized symmetrical output characteristics

nOperates across the automotive temperature range from −40 °C to +125 °C

nComplies with JEDEC standard JESD 13-B

3. Applications

nAutomotive and industrial

nCounters and dividers

nRegisters

nToggle ﬂip-ﬂops

4. Ordering information

HEF4013B

Dual D-type ﬂip-ﬂop

Rev. 05 — 19 June 2009 Product data sheet

Table 1. Ordering information

All types operate from

−

C to +125

Type number Package

Name Description Version

HEF4013BP DIP14 plastic dual in-line package; 14 leads (300 mil) SOT27-1

HEF4013BT SO14 plastic small outline package; 14 leads; body width 3.9 mm SOT108-1

HEF4013BTT TSSOP14 plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1

Product data sheet Rev. 05 — 19 June 2009 2 of 15

NXP Semiconductors HEF4013B

Dual D-type ﬂip-ﬂop

5. Functional diagram

Fig 1. Functional diagram

001aag084

1SD

1CP

1CD

2SD

2D 2Q

2CP

2CD

FF1

CP Q

FF2

CP Q

Fig 2. Logic diagram (one ﬂip-ﬂop)

001aag086

Product data sheet Rev. 05 — 19 June 2009 3 of 15

NXP Semiconductors HEF4013B

Dual D-type ﬂip-ﬂop

6. Pinning information

6.1 Pinning

6.2 Pin description

7. Functional description

[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; ↑ = LOW-to-HIGH clock transition.

Fig 3. Pin conﬁguration

HEF4013B

1Q VDD

1Q 2Q

1CP 2Q

1CD 2CP

1D 2CD

1SD 2D

VSS 2SD

001aag085

7 8

Table 2. Pin description

Symbol Pin Description

1Q, 2Q 1, 13 true output

1Q, 2Q 2, 12 complement output

1CP, 2CP 3, 11 clock input (LOW to HIGH edge-triggered)

1CD, 2CD 4, 10 asynchronous clear-direct input (active HIGH)

1D, 2D 5, 9 data input

1SD, 2SD 6, 8 asynchronous set-direct input (active HIGH)

VSS 7 ground (0 V)

VDD 14 supply voltage

Table 3. Function table[1]

Control Input Output

nSD nCD nCP nD nQ nQ

HLXXHL

LHXXLH

HHXXHH

LL↑LLH

LL↑HHL

Product data sheet Rev. 05 — 19 June 2009 4 of 15

NXP Semiconductors HEF4013B

Dual D-type ﬂip-ﬂop

8. Limiting values

[1] For DIP14 packages: above Tamb = 70 °C, Ptot derates linearly with 12 mW/K.

[2] For SO14 packages: above Tamb = 70 °C, Ptot derates linearly with 8 mW/K.

[3] For TSSOP14 packages: above Tamb = 60 °C, Ptot derates linearly with 5.5 mW/K.

9. Recommended operating conditions

Table 4. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to V

= 0 V (ground).

Symbol Parameter Conditions Min Max Unit

VDD supply voltage −0.5 +18 V

IIK input clamping current VI<−0.5 V or VI>V

DD + 0.5 V - ±10 mA

VIinput voltage −0.5 VDD + 0.5 V

IOK output clamping current VO<−0.5 V or VO>V

DD + 0.5 V - ±10 mA

II/O input/output current - ±10 mA

IDD supply current - 50 mA

Tstg storage temperature −65 +150 °C

Tamb ambient temperature −40 +125 °C

Ptot total power dissipation Tamb = −40 °C to +125 °C

DIP14 [1] - 750 mW

SO14 [2] - 500 mW

TSSOP14 [3] - 500 mW

P power dissipation per output - 100 mW

Table 5. Recommended operating conditions

Symbol Parameter Conditions Min Max Unit

VDD supply voltage 3 15 V

VIinput voltage 0 VDD V

Tamb ambient temperature −40 +125 °C

∆t/∆V input transition rise and fall rate VDD = 5 V - 3.75 ns/V

VDD = 10 V - 0.5 ns/V

VDD = 15 V - 0.08 ns/V

Product data sheet Rev. 05 — 19 June 2009 5 of 15

NXP Semiconductors HEF4013B

Dual D-type ﬂip-ﬂop

10. Static characteristics

Table 6. Static characteristics

= 0 V; V

or V

; unless otherwise speciﬁed.

Symbol Parameter Conditions VDD Tamb = −40 °C Tamb = +25 °C Tamb = +85 °C Tamb = +125 °C Unit

Min Max Min Max Min Max Min Max

VIH HIGH-level

input voltage |IO| < 1 µA 5 V 3.5 - 3.5 - 3.5 - 3.5 - V

10 V 7.0 - 7.0 - 7.0 - 7.0 - V

15 V 11.0 - 11.0 - 11.0 - 11.0 - V

VIL LOW-level

input voltage |IO| < 1 µA 5 V - 1.5 - 1.5 - 1.5 - 1.5 V

10 V - 3.0 - 3.0 - 3.0 - 3.0 V

15 V - 4.0 - 4.0 - 4.0 - 4.0 V

VOH HIGH-level

output voltage |IO| < 1 µA 5 V 4.95 - 4.95 - 4.95 - 4.95 - V

10 V 9.95 - 9.95 - 9.95 - 9.95 - V

15 V 14.95 - 14.95 - 14.95 - 14.95 - V

VOL LOW-level

output voltage |IO| < 1 µA 5 V - 0.05 - 0.05 - 0.05 - 0.05 V

10 V - 0.05 - 0.05 - 0.05 - 0.05 V

15 V - 0.05 - 0.05 - 0.05 - 0.05 V

IOH HIGH-level

output current VO = 2.5 V 5 V −1.7 - −1.4 - −1.1 - −1.1 - mA

VO = 4.6 V 5 V −0.64 - −0.5 - −0.36 - −0.36 - mA

VO = 9.5 V 10 V −1.6 - −1.3 - −0.9 - −0.9 - mA

VO = 13.5 V 15 V −4.2 - −3.4 - −2.4 - −2.4 - mA

IOL LOW-level

output current VO = 0.4 V 5 V 0.64 - 0.5 - 0.36 - 0.36 - mA

VO = 0.5 V 10 V 1.6 - 1.3 - 0.9 - 0.9 - mA

VO = 1.5 V 15 V 4.2 - 3.4 - 2.4 - 2.4 - mA

IIinput leakage

current 15 V - ±0.1 - ±0.1 - ±1.0 - ±1.0 µA

IDD supply current all valid input

combinations;

|IO|=0 A

5 V - 1.0 - 1.0 - 30 - 30 µA

10 V - 2.0 - 2.0 - 60 - 60 µA

15 V - 4.0 - 4.0 - 120 - 120 µA

CIinput

capacitance - - - - 7.5 - - - - pF

Product data sheet Rev. 05 — 19 June 2009 6 of 15

NXP Semiconductors HEF4013B

Dual D-type ﬂip-ﬂop

11. Dynamic characteristics

Table 7. Dynamic characteristics

amb

= 25

C; unless otherwise speciﬁed. For test circuit see Figure 6.

Symbol Parameter Conditions VDD Extrapolation formula Min Typ Max Unit

tPHL HIGH to LOW

propagation delay nCP to nQ, nQ;

see Figure 4 5 V [1] 83 + 0.55 × CL- 110 220 ns

10 V 34 + 0.23 × CL-4590ns

15 V 22 + 0.16 × CL-3060ns

nSD to nQ5 V

[1] 73 + 0.55 × CL- 100 200 ns

10 V 29 + 0.23 × CL-4080ns

15 V 22 + 0.16 × CL-3060ns

nCD to nQ 5 V [1] 73 + 0.55 × CL- 100 200 ns

10 V 29 + 0.23 × CL-4080ns

15 V 22 + 0.16 × CL-3060ns

tPLH LOW to HIGH

propagation delay nCP to nQ, nQ;

see Figure 4 5 V [1] 68 + 0.55 × CL- 95 190 ns

10 V 29 + 0.23 × CL-4080ns

15 V 22 + 0.16 × CL-3060ns

nSD to nQ 5 V [1] 48 + 0.55 × CL- 75 150 ns

10 V 24 + 0.23 × CL-3570ns

15 V 17 + 0.16 × CL-2550ns

nCD to nQ5 V

[1] 33 + 0.55 × CL- 60 120 ns

10 V 19 + 0.23 × CL-3060ns

15 V 12 + 0.16 × CL-2040ns

tttransition time see Figure 4 5 V [1] 10 + 1.00 × CL- 60 120 ns

10 V 9 + 0.42 × CL-3060ns

15 V 6 + 0.28 × CL-2040ns

tsu set-up time nD to nCP;

see Figure 4 5 V 40 20 - ns

10 V 25 10 - ns

15 V 15 5 - ns

thhold time nD to nCP;

see Figure 4 5 V 20 0 - ns

10 V 20 0 - ns

15 V 15 0 - ns

tWpulse width nCP input LOW;

see Figure 4 5 V 60 30 - ns

10 V 30 15 - ns

15 V 20 10 - ns

nSD input HIGH;

see Figure 5 5 V 50 25 - ns

10 V 24 12 - ns

15 V 20 10 - ns

nCD input HIGH;

see Figure 5 5 V 50 25 - ns

10 V 24 12 - ns

15 V 20 10 - ns

Product data sheet Rev. 05 — 19 June 2009 7 of 15

NXP Semiconductors HEF4013B

Dual D-type ﬂip-ﬂop

[1] Typical values of the propagation delays and output transition times can be calculated with the extrapolation formulas. CL is given in pF.

12. Waveforms

trec recovery time nSD input;

see Figure 5 5 V +15 −5- ns

10 V 15 0 - ns

15 V 15 0 - ns

nCD input;

see Figure 5 5 V 40 25 - ns

10 V 25 10 - ns

15 V 25 10 - ns

fclk(max) maximum clock

frequency see Figure 4 5 V 7 14 - MHz

10 V 14 28 - MHz

15 V 20 40 - MHz

Table 7. Dynamic characteristics

…continued

amb

= 25

C; unless otherwise speciﬁed. For test circuit see Figure 6.

Symbol Parameter Conditions VDD Extrapolation formula Min Typ Max Unit

Table 8. Dynamic power dissipation

= 0 V; t

= t

≤

20 ns; T

amb

= 25

Symbol Parameter VDD Typical formula Where

PDdynamic power dissipation 5 V PD = 850 × fi + Σ(fo× CL)× VDD2µWf

i = input frequency in MHz;

fo = output frequency in MHz;

CL = output load capacitance in pF;

Σ(fo× CL) = sum of the outputs;

VDD = supply voltage in V.

10 V PD = 3600 × fi + Σ(fo× CL)× VDD2µW

15 V PD = 9000 × fi + Σ(fo× CL)× VDD2µW

Set-up and hold times are shown as positive values but may be speciﬁed as negative values.

The shaded areas indicate when the input is permitted to change for predictable output performance.

Measurement points are given in Table 9.

Fig 4. Set-up time, hold time, minimum clock pulse width, propagation delays and transition times

001aah016

0 V

tsu

1/fclk(max)

tsu tftr

VOH

VOL

output nQ

input nCP

input nD

tPHL

tPLH

Product data sheet Rev. 05 — 19 June 2009 8 of 15

NXP Semiconductors HEF4013B

Dual D-type ﬂip-ﬂop

Recovery times are shown as positive values but may be speciﬁed as negative values.

Measurement points are given in Table 9.

Fig 5. nSD, nCD recovery time and pulse width

001aag088

input nSD

input nCD

input nCP

0 V

VOL

0 V

VOH

output nQ

trec trec

Table 9. Measurement points

Supply voltage Input Output

VDD VMVMVXVY

5 V to 15 V 0.5VDD 0.5VDD 0.1VDD 0.9VDD

Test and measurement data is given in Table 10;

Deﬁnitions test circuit:

DUT = Device Under Test.

RT = Termination resistance should be equal to output impedance Zo of the pulse generator.

CL = Load capacitance including jig and probe capacitance.

Fig 6. Test circuit for measuring switching times

VDD

VIVO

001aag182

DUT

Table 10. Test data

Supply voltage Input Load

VDD VItr, tfCL

5 V to 15 V VSS or VDD ≤20 ns 50 pF

Product data sheet Rev. 05 — 19 June 2009 9 of 15

NXP Semiconductors HEF4013B

Dual D-type ﬂip-ﬂop

13. Application information

Fig 7. N-stage shift register

Fig 8. Binary ripple up-counter; divide-by-2n

Fig 9. Modiﬁed ring counter; divide-by-(n + 1)

001aag089

DDQ

clock

001aag090

T-type flip-flop

clock CP

001aag091

clock

Product data sheet Rev. 05 — 19 June 2009 10 of 15

NXP Semiconductors HEF4013B

Dual D-type ﬂip-ﬂop

14. Package outline

Fig 10. Package outline SOT27-1 (DIP14)

UNIT A

max. 1 2 (1) (1)

b1cD (1)

Ee M

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

inches

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

SOT27-1 99-12-27

03-02-13

min. A

max. bmax.

1.73

1.13 0.53

0.38 0.36

0.23 19.50

18.55 6.48

6.20 3.60

3.05 0.2542.54 7.62 8.25

7.80 10.0

8.3 2.24.2 0.51 3.2

0.068

0.044 0.021

0.015 0.77

0.73

0.014

0.009 0.26

0.24 0.14

0.12 0.010.1 0.3 0.32

0.31 0.39

0.33 0.0870.17 0.02 0.13

050G04 MO-001 SC-501-14

(e )

seating plane

pin 1 index

0 5 10 mm

scale

Note

1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.

DIP14: plastic dual in-line package; 14 leads (300 mil) SOT27-1

Product data sheet Rev. 05 — 19 June 2009 11 of 15

NXP Semiconductors HEF4013B

Dual D-type ﬂip-ﬂop

Fig 11. Package outline SOT108-1 (SO14)

UNIT A

max. A1A2A3bpcD

(1) E(1) (1)

ELL

pQZywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

inches

1.75 0.25

0.10 1.45

1.25 0.25 0.49

0.36 0.25

0.19 8.75

8.55 4.0

3.8 1.27 6.2

5.8 0.7

0.6 0.7

0.3 8

0.25 0.1

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

Note

1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

1.0

0.4

SOT108-1

detail X

vMA

(A )

076E06 MS-012

pin 1 index

0.069 0.010

0.004 0.057

0.049 0.01 0.019

0.014 0.0100

0.0075 0.35

0.34 0.16

0.15 0.05

1.05

0.041

0.244

0.228 0.028

0.024 0.028

0.012

0.01

0.25

0.01 0.004

0.039

0.016

99-12-27

03-02-19

0 2.5 5 mm

scale

SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1

Product data sheet Rev. 05 — 19 June 2009 12 of 15

NXP Semiconductors HEF4013B

Dual D-type ﬂip-ﬂop

Fig 12. Package outline SOT402-1 (TSSOP14)

UNIT A1A2A3bpcD

(1) E(2) (1)

ELL

pQZywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 0.15

0.05 0.95

0.80 0.30

0.19 0.2

0.1 5.1

4.9 4.5

4.3 0.65 6.6

6.2 0.4

0.3 0.72

0.38 8

0.13 0.10.21

DIMENSIONS (mm are the original dimensions)

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

0.75

0.50

SOT402-1 MO-153 99-12-27

03-02-18

0.25

14 8

detail X

(A )

vMA

0 2.5 5 mm

scale

TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1

max.

1.1

pin 1 index

Product data sheet Rev. 05 — 19 June 2009 13 of 15

NXP Semiconductors HEF4013B

Dual D-type ﬂip-ﬂop

15. Revision history

Table 11. Revision history

Document ID Release date Data sheet status Change notice Supersedes

HEF4013B_5 20090619 Product data sheet - HEF4013B_4

Modiﬁcations: •Section 2 “Features” ESD (ElectroStatic Discharge) values removed.

•Table 4 “Limiting values” the conditions values of VI and VI for IIK and IOK modiﬁed.

•Abbreviations section removed.

•Section 16 “Legal information” export control statement added.

HEF4013B_4 20080515 Product data sheet - HEF4013B_CNV_3

HEF4013B_CNV_3 19950101 Product speciﬁcation - HEF4013B_CNV_2

HEF4013B_CNV_2 19950101 Product speciﬁcation - -

Product data sheet Rev. 05 — 19 June 2009 14 of 15

NXP Semiconductors HEF4013B

Dual D-type ﬂip-ﬂop

16. Legal information

16.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term ‘short data sheet’ is explained in section “Deﬁnitions”.

[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

16.2 Deﬁnitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modiﬁcations or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

ofﬁce. In case of any inconsistency or conﬂict with the short data sheet, the

full data sheet shall prevail.

16.3 Disclaimers

General — Information in this document is believed to be accurate and

reliable. However, NXP Semiconductors does not give any representations or

warranties, expressed or implied, as to the accuracy or completeness of such

information and shall have no liability for the consequences of use of such

information.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation speciﬁcations and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in medical, military, aircraft,

space or life support equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors accepts no liability for inclusion and/or use of

NXP Semiconductors products in such equipment or applications and

therefore such inclusion and/or use is at the customer’s own risk.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

speciﬁed use without further testing or modiﬁcation.

Limiting values — Stress above one or more limiting values (as deﬁned in

the Absolute Maximum Ratings System of IEC 60134) may cause permanent

damage to the device. Limiting values are stress ratings only and operation of

the device at these or any other conditions above those given in the

Characteristics sections of this document is not implied. Exposure to limiting

values for extended periods may affect device reliability.

Terms and conditions of sale — NXP Semiconductors products are sold

subject to the general terms and conditions of commercial sale, as published

at http://www.nxp.com/proﬁle/terms, including those pertaining to warranty,

intellectual property rights infringement and limitation of liability, unless

explicitly otherwise agreed to in writing by NXP Semiconductors. In case of

any inconsistency or conﬂict between information in this document and such

terms and conditions, the latter will prevail.

No offer to sell or license — Nothing in this document may be interpreted

or construed as an offer to sell products that is open for acceptance or the

grant, conveyance or implication of any license under any copyrights, patents

or other industrial or intellectual property rights.

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from national authorities.

16.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

17. Contact information

For more information, please visit: http://www.nxp.com

For sales ofﬁce addresses, please send an email to: salesaddresses@nxp.com

Document status[1][2] Product status[3] Deﬁnition

Objective [short] data sheet Development This document contains data from the objective speciﬁcation for product development.

Preliminary [short] data sheet Qualiﬁcation This document contains data from the preliminary speciﬁcation.

Product [short] data sheet Production This document contains the product speciﬁcation.

NXP Semiconductors HEF4013B

Dual D-type ﬂip-ﬂop

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 19 June 2009

Document identifier: HEF4013B_5

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

18. Contents

1 General description. . . . . . . . . . . . . . . . . . . . . . 1

2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

4 Ordering information. . . . . . . . . . . . . . . . . . . . . 1

5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2

6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 3

6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3

7 Functional description . . . . . . . . . . . . . . . . . . . 3

8 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4

9 Recommended operating conditions. . . . . . . . 4

10 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5

11 Dynamic characteristics . . . . . . . . . . . . . . . . . . 6

12 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

13 Application information. . . . . . . . . . . . . . . . . . . 9

14 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10

15 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 13

16 Legal information. . . . . . . . . . . . . . . . . . . . . . . 14

16.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 14

16.2 Deﬁnitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

16.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 14

16.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 14

17 Contact information. . . . . . . . . . . . . . . . . . . . . 14

18 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15