2018-2019 Microchip Technology Inc. DS00002670D-page 1
USB7002
Highlights
• 4-Port USB Smart Hub with:
- Native USB Type-C™ support on upstream port
- Native USB Type-C support on downstream ports
1 and 2
- Two Standard USB 2.0 downstream ports
- Internal Hub Feature Controller device which
enables:
-USB to I
2C/SPI/UART/I2S/GPIO bridge endpoint
support
- USB to internal hub register write and read
• USB-IF Certified - TID 1212. Testing includes:
- USB3.1 Gen1 Hub with BC1.2 support
- Power Delivery 2.0 using UPD350 PD Transceiver
(TID 330000077)
- Billboard endpoint device for Alternate Mode nego-
tiation status
- Advanced multi-port system policy management
• USB Link Power Management (LPM) support
• USB-IF Battery Charger revision 1.2 support on
downstream ports (DCP, CDP, SDP)
• Enhanced OEM configuration options available
through either OTP or SPI ROM
• Commercial and industrial grade temperature
support
• Automotive/AEC-Q100 qualified
Target Applications
• Standalone USB Hubs
• Laptop Docks
• PC Motherboards
• PC Monitor Docks
• Multi-function USB 3.1 Gen 1 Peripherals
• Automotive integrated head unit and breakout box
Key Benefits
• USB 3.1 Gen 1 compliant 5 Gbps, 480 Mbps, 12
Mbps, and 1.5Mbps operation
- 5V tolerant USB 2.0 pins
- 1.32V tolerant USB 3.1 Gen 1 pins
- Integrated termination and pull-up/down resistors
• Native USB Type-C Support
- Type-C CC Pin with integrated Rp and Rd
- Integrated multiplexer on USB Type-C enabled
ports. USB 3.1 Gen 1 PHYs are disabled until a
valid Type-C attach is detected, saving idle power.
- Control for external VCONN supply
• Supports battery charging of most popular battery
powered devices on all ports
- USB-IF Battery Charging rev. 1.2 support
(DCP, CDP, SDP)
- Apple® portable product charger emulation
- Chinese YD/T 1591-2006 charger emulation
- Chinese YD/T 1591-2009 charger emulation
- European Union universal mobile charger support
- Supports additional portable devices
• On-chip Microcontroller
- Manages I/Os, VBUS, and other signals
• 64kB RAM, 256kB ROM
• 8kB One-Time-Programmable (OTP) ROM
- Includes on-chip charge pump
• Configuration programming via OTP ROM, SPI
ROM, or SMBus
• FlexConnect
- The roles of the upstream and any downstream
port are reversible on command
• Multi-Host Endpoint Reflector
- Integrated host-controller endpoint reflector via
CDC/NCM device class for automotive applications
• USB Bridging
- USB to I2C, SPI, UART, I2S, and GPIO
•PortSwap
- Configurable USB 2.0 differential pair signal swap-
ping
• PHYBoost
- Programmable USB 2.0 transceiver drive strength
for recovering signal integrity
• VariSense
- Programmable USB 2.0 receiver sensitivity
• Compatible with Microsoft Windows 10, 8, 7, XP,
Apple OS X 10.4+, and Linux hub drivers
• Optimized for low-power operation and low ther-
mal dissipation
• Package: 100-pin RoHS compliant VQFN
(12mm x 12mm)
* USB Type-C™ and USB-C™ are trademarks of USB
Implementers Forum.
4-Port SS/HS USB Type-C™ PD Smart Hub
USB7002
DS00002670D-page 2 2018-2019 Microchip Technology Inc.
TO OUR VALUED CUSTOMERS
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An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may
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2018-2019 Microchip Technology Inc. DS00002670D-page 3
USB7002
Table of Contents
1.0 Preface ............................................................................................................................................................................................ 4
2.0 Introduction ..................................................................................................................................................................................... 6
3.0 Pin Descriptions and Configuration ................................................................................................................................................. 8
4.0 Device Connections ...................................................................................................................................................................... 23
5.0 Modes of Operation ...................................................................................................................................................................... 26
6.0 Device Configuration ..................................................................................................................................................................... 29
7.0 Device Interfaces .......................................................................................................................................................................... 30
8.0 Functional Descriptions ................................................................................................................................................................. 34
9.0 Operational Characteristics ........................................................................................................................................................... 40
10.0 Package Outline .......................................................................................................................................................................... 49
Appendix A: Revision History .............................................................................................................................................................. 52
Product Identification System ............................................................................................................................................................. 53
The Microchip Web Site ...................................................................................................................................................................... 54
Customer Change Notification Service ............................................................................................................................................... 54
Customer Support ............................................................................................................................................................................... 54
USB7002
DS00002670D-page 4 2018-2019 Microchip Technology Inc.
1.0 PREFACE
1.1 General Terms
TABLE 1-1: GENERAL TERMS
Term Description
ADC Analog-to-Digital Converter
Byte 8 bits
CDC Communication Device Class
CSR Control and Status Registers
DFP Downstream Facing Port
DWORD 32 bits
EOP End of Packet
EP Endpoint
FIFO First In First Out buffer
FS Full-Speed
FSM Finite State Machine
GPIO General Purpose I/O
HS Hi-Speed
HSOS High Speed Over Sampling
Hub Feature Controller The Hub Feature Controller, sometimes called a Hub Controller for short is the internal
processor used to enable the unique features of the USB Controller Hub. This is not to
be confused with the USB Hub Controller that is used to communicate the hub status
back to the Host during a USB session.
I2C Inter-Integrated Circuit
LS Low-Speed
lsb Least Significant Bit
LSB Least Significant Byte
msb Most Significant Bit
MSB Most Significant Byte
N/A Not Applicable
NC No Connect
OTP One Time Programmable
PCB Printed Circuit Board
PCS Physical Coding Sublayer
PHY Physical Layer
PLL Phase Lock Loop
RESERVED Refers to a reserved bit field or address. Unless otherwise noted, reserved bits must
always be zero for write operations. Unless otherwise noted, values are not guaran-
teed when reading reserved bits. Unless otherwise noted, do not read or write to
reserved addresses.
SDK Software Development Kit
SMBus System Management Bus
UFP Upstream Facing Port
UUID Universally Unique IDentifier
WORD 16 bits
2018-2019 Microchip Technology Inc. DS00002670D-page 5
USB7002
1.2 Buffer Types
1.3 Reference Documents
1. Universal Serial Bus Revisi on 3.1 Specification, http://www.usb.org
2. Battery Charging Specification, Revision 1.2, Dec. 07, 2010, http://www.usb.org
3. I2C-Bus Specification, Version 1.1, http://www.nxp.com/documents/user_manual/UM10204.pdf
4. I2S-Bus Specification, http://www.nxp.com/acrobat_download/various/I2SBUS.pdf
5. System Management Bus Specification, Version 1.0, http://smbus.org/specs
TABLE 1-2: BUFFER TYPES
Buffer Type Description
I Input.
IS Input with Schmitt trigger.
O12 Output buffer with 12 mA sink and 12 mA source.
OD12 Open-drain output with 12 mA sink
PU 50 μA (typical) internal pull-up. Unless otherwise noted in the pin description, internal pull-
ups are always enabled.
Internal pull-up resistors prevent unconnected inputs from floating. Do not rely on internal
resistors to drive signals external to the device. When connected to a load that must be
pulled high, an external resistor must be added.
PD 50 μA (typical) internal pull-down. Unless otherwise noted in the pin description, internal
pull-downs are always enabled.
Internal pull-down resistors prevent unconnected inputs from floating. Do not rely on
internal resistors to drive signals external to the device. When connected to a load that
must be pulled low, an external resistor must be added.
ICLK Crystal oscillator input pin
OCLK Crystal oscillator output pin
I/O-U Analog input/output defined in USB specification.
I-R RBIAS.
A Analog.
P Power pin.
Note: Additional USB7002 resources can be found on the Microchip USB7002 product page at www.micro-
chip.com/USB7002.
USB7002
DS00002670D-page 6 2018-2019 Microchip Technology Inc.
2.0 INTRODUCTION
2.1 General Description
The Microchip USB7002 hub is low-power, OEM configurable, USB 3.1 Gen 1 hub controller with 4 downstream ports
and advanced features for embedded USB applications. The USB7002 is fully compliant with the Universal Serial Bus
Revision 3.1 Specification and USB 2.0 Link Power Management Addendum. The USB7002 supports 5 Gbps Super-
Speed (SS), 480 Mbps Hi-Speed (HS), 12 Mbps Full-Speed (FS), and 1.5 Mbps Low-Speed (LS) USB downstream
devices on two standard USB 3.1 Gen 1 downstream ports and only legacy speeds (HS/FS/LS) on two standard USB
2.0 downstream ports.
The USB7002 supports native Type-C connectivity on the upstream port and two of the downstream ports. The hub
includes internal Type-C CC pin logic and an internal USB 3.1 Gen 1 multiplexer to support both Type-C insertion ori-
entations.
The USB7002 supports the legacy USB speeds (HS/FS/LS) through a dedicated USB 2.0 hub controller that is the cul-
mination of six generations of Microchip hub feature controller design and experience with proven reliability, interoper-
ability, and device compatibility. The SuperSpeed hub controller operates in parallel with the USB 2.0 controller,
decoupling the 5 Gbps SS data transfers from bottlenecks due to the slower USB 2.0 traffic.
The USB7002 enables OEMs to configure their system using “Configuration Straps.” These straps simplify the config-
uration process assigning default values to USB 3.1 Gen 1 ports and GPIOs. OEMs can disable ports, enable battery
charging and define GPIO functions as default assignments on power up.
The USB7002 supports downstream battery charging. The USB7002 integrated battery charger detection circuitry sup-
ports the USB-IF Battery Charging (BC1.2) detection method and most Apple devices. The USB7002 provides the bat-
tery charging handshake and supports the following USB-IF BC1.2 charging profiles:
• DCP: Dedicated Charging Port (Power brick with no data)
• CDP: Charging Downstream Port (1.5A with data)
• SDP: Standard Downstream Port (0.5A with data)
• Custom profiles loaded via SPI EEPROM or OTP
Additionally, the USB7002 includes many powerful and unique features such as:
The Hub Feature Controller, an internal USB device dedicated for use as a USB to I2C/UART/SPI/GPIO interface that
allows external circuits or devices to be monitored, controlled, or configured via the USB interface.
Multi-Host Endpoint Reflector, which provides unique USB functionality whereby USB data can be “mirrored” between
two USB hosts (Multi-Host) in order to perform a single USB transaction.This capability is fully covered by Microchip
intellectual property (U.S. Pat. Nos. 7,523,243 and 7,627,708) and is instrumental in enabling Apple CarPlay™, where
the Apple iPhone® becomes a USB Host.
FlexConnect, which provides flexible connectivity options. Any one of the USB7002’s downstream ports can be recon-
figured to become the upstream port, allowing master capable devices to control other devices on the hub.
AEC-Q100 compliance:, which tailors the device for use in automotive applications requiring automotive grade robust-
ness, starting with the comprehension of proprietary design for reliability techniques within the silicon IC itself, as well
as for the package design.
• Automotive qualified technologies and processes are used to fabricate the products with enhanced monitors to
continuously drive improvements in accordance with Microchip's zero-dpm methodology.
• Product qualification is focused on customer expectations and exceeds many of the automotive reliability stan-
dards including AEC-Q100.
• Microchip automotive services are provided during the life of the product from a dedicated organization of opera-
tions, quality, and product support personnel specialized in meeting the requirements of the automotive customer.
PortSwap, which adds per-port programmability to USB differential-pair pin locations. PortSwap allows direct alignment
of USB signals (D+/D-) to connectors to avoid uneven trace length or crossing of the USB differential signals on the
PCB.
PHYBoost, which provides programmable levels of Hi-Speed USB signal drive strength
in the downstream port transceivers. PHYBoost attempts to restore USB signal integrity
in a compromised system environment. The graphic on the right shows an example of
Hi-Speed USB eye diagrams before and after PHYBoost signal integrity restoration. in
a compromised system environment.
2018-2019 Microchip Technology Inc. DS00002670D-page 7
USB7002
VariSense, which controls the Hi-Speed USB receiver sensitivity enabling programmable levels of USB signal receive
sensitivity. This capability allows operation in a sub-optimal system environment, such as when a captive USB cable is
used.
The USB7002 can be configured for operation through internal default settings. Custom OEM configurations are sup-
ported through external SPI ROM or internal OTP ROM. All port control signal pins are under firmware control in order
to allow for maximum operational flexibility and are available as GPIOs for customer specific use.
The USB7002 is available in commercial (0°C to +70°C) and industrial (-40°C to +85°C) temperature ranges. An internal
block diagram of the USB7002 in an upstream Type-C application is shown in Figure 2-1.
FIGURE 2-1: USB7002 INTERNAL BLOCK DIAGRAM - UPSTREAM TYPE-C APPLICATION
Hub Controller Logic
I2C/SMB
I2C from Master
25 Mhz
USB3 USB2
P4
A
USB7002
PHY0
+3.3 V
+1.2 V
P3
A
PHY4PHY2PHY1
PHY2
B
PHY1
A
P1
C
CC PHY3
PHY4
B
PHY3
A
P2
C
CC
Hub Feature Controller
GPIO SMB
OTP
SPI
HFC
PHY
I2SUART
PHY5
B
PHY0
A
CC
P0
C
Mux
USB7002
DS00002670C-page 8 2018-2019 Microchip Technology Inc.
3.0 PIN DESCRIPTIONS AND CONFIGURATION
The pin assignments for the USB7002 are detailed in Section 3.1, Pin Assignments. Pin descriptions are provided in
Section 3.2, Pin Descriptions.
3.1 Pin Assignments
The device pin diagram for the USB7002 can be seen in Figure 3-1. Table 3-1 provides a USB7002 pin assignments
table. Pin descriptions are provided in Section 3.2, Pin Descriptions.
FIGURE 3-1: USB7002 100-VQFN PIN ASSIGNMENTS
Note: Configuration straps are identified by an underlined symbol name. Signals that function as configuration
straps must be augmented with an external resistor when connected to a load.
Thermal slug connects to VSS
100
99
98
97
96
95
94
93
92
90
89
88
87
86
85
91
16
15
14
13
12
11
10
9
8
6
5
4
3
2
1
7
41
40
39
37
36
35
34
33
32
31
30
29
28
27
26
75
74
73
72
71
70
68
67
66
65
69
64
63
62
61
60
38
RESET_N
DP1_VBUS_MON
PF31
DP1_CC1
USB3DN_RXDM1A
USB3DN_RXDP1A
VDD12
USB3DN_TXDM1A
USB3DN_TXDP1A
USB2DN_DM1/PRT_DIS_M1
DP2_CC1
DP2_VBUS_MON
USB3DN_RXDM2A
USB2DN_DM4/PRT_DIS_M4
USB2DN_DP4/PRT_DIS_P4
DP2_CC2
USB3DN_RXDP2A
VDD12
USB3DN_TXDP2A
USB2DN_DM2/PRT_DIS_M2
USB2DN_DP2/PRT_DIS_P2
VDD33
USB3DN_TXDM2A
PF17
PF25
PF22/CFG_BC_EN
PF21
VDD33
PF23
PF19
PF26
TEST3
PF20/CFG_NON_REM
TEST1
25
24
23
22
21
20
19
18
17
50
49
48
46
45
44
43
42
47
PF9
USB3DN_TXDP2B
59
58
57
56
55
54
53
52
51 PF10
PF13
VDD33
TEST2
PF24
PF18
PF15
84
83
81
80
79
78
77
76
82
PF30/VBUS_DET
USB3DN_RXDM1B
VDD12
USB3DN_TXDM2B
PF16
PF27
USB2DN_DP1/PRT_DIS_P1
USB3DN_RXDP1B
VDD12
USB3DN_TXDM1B
USB3DN_TXDP1B
USB2DN_DM3/PRT_DIS_M3
USB2DN_DP3/PRT_DIS_P3
DP1_CC2
CFG_STRAP1
CFG_STRAP2
CFG_STRAP3
TESTEN
VDD12
PF28
VDD12
USB3UP_RXDMB
USB3UP_RXDPB
VDD12
USB3UP_TXDMB
USB3UP_TXDPB
VBUS_MON_UP
VDD33
USB3UP_TXDMA
USB3UP_TXDPA
USB2UP_DM
USB2UP_DP
CC2_UP
CC1_UP
VDD33
RBIAS
VDD33
XTALI/CLK_IN
XTALO
ATEST
USB3UP_RXDMA
USB3UP_RXDPA
VDD12
VDD33
USB3DN_RXDM2B
PF5
PF4
PF6
PF8
PF7
USB3DN_RXDP2B
VDD33
VDD12
PF12
PF29
PF11
PF14
Microchip
USB7002
(Top V iew 1 00-VQFN)
2018-2019 Microchip Technology Inc. DS00002670C-page 9
USB7002
Pin
Num Pin Name Pin
Num Pin Name
1RESET_N 51 PF10
2PF30/VBUS_DET 52 PF11
3PF31 53 VDD33
4DP1_VBUS_MON 54 PF12
5USB2DN_DP1/PRT_DIS_P1 55 VDD12
6USB2DN_DM1/PRT_DIS_M1 56 PF13
7USB3DN_TXDP1A 57 PF14
8USB3DN_TXDM1A 58 PF15
9VDD12 59 PF16
10 USB3DN_RXDP1A 60 PF17
11 USB3DN_RXDM1A 61 PF18
12 DP1_CC1 62 VDD33
13 DP1_CC2 63 TEST1
14 USB2DN_DP3/PRT_DIS_P3 64 TEST2
15 USB2DN_DM3/PRT_DIS_M3 65 TEST3
16 USB3DN_TXDP1B 66 PF19
17 USB3DN_TXDM1B 67 VDD33
18 VDD12 68 PF21
19 USB3DN_RXDP1B 69 PF20/CFG_NON_REM
20 USB3DN_RXDM1B 70 PF22/CFG_BC_EN
21 CFG_STRAP1 71 PF23
22 CFG_STRAP2 72 PF24
23 CFG_STRAP3 73 PF25
24 TESTEN 74 PF29
25 VDD12 75 PF26
26 VDD33 76 PF27
27 DP2_CC1 77 PF28
28 DP2_CC2 78 VDD12
29 USB2DN_DP2/PRT_DIS_P2 79 VDD33
30 USB2DN_DM2/PRT_DIS_M2 80 VBUS_MON_UP
31 USB3DN_TXDP2A 81 USB3UP_TXDPB
32 USB3DN_TXDM2A 82 USB3UP_TXDMB
33 VDD12 83 VDD12
34 USB3DN_RXDP2A 84 USB3UP_RXDPB
35 USB3DN_RXDM2A 85 USB3UP_RXDMB
36 DP2_VBUS_MON 86 VDD33
37 USB2DN_DP4/PRT_DIS_P4 87 CC1_UP
38 USB2DN_DM4/PRT_DIS_M4 88 CC2_UP
39 USB3DN_TXDP2B 89 USB2UP_DP
40 USB3DN_TXDM2B 90 USB2UP_DM
41 VDD12 91 USB3UP_TXDPA
42 USB3DN_RXDP2B 92 USB3UP_TXDMA
43 USB3DN_RXDM2B 93 VDD12
44 VDD33 94 USB3UP_RXDPA
USB7002
DS00002670C-page 10 2018-2019 Microchip Technology Inc.
3.2 Pin Descriptions
This section contains descriptions of the various USB7002 pins. The “_N” symbol in the signal name indicates that the
active, or asserted, state occurs when the signal is at a low voltage level. For example, RESET_N indicates that the
reset signal is active low. When “_N” is not present after the signal name, the signal is asserted when at the high voltage
level.
The terms assertion and negation are used exclusively. This is done to avoid confusion when working with a mixture of
“active low” and “active high” signal. The term assert, or assertion, indicates that a signal is active, independent of
whether that level is represented by a high or low voltage. The term negate, or negation, indicates that a signal is inac-
tive.
Buffer type definitions are detailed in Section 1.2, Buffer Types.
45 PF4 95 USB3UP_RXDMA
46 PF5 96 ATEST
47 PF6 97 XTALO
48 PF7 98 XTALI/CLK_IN
49 PF8 99 VDD33
50 PF9 100 RBIAS
Exposed Pad (VSS) must be connected to ground.
TABLE 3-1: PIN DESCRIPTIONS
Name Symbol Buffer
Type Description
USB 3.1 Gen 1 Interfaces
Upstream USB
3.1 Gen 1 TX D+
Orientation A
USB3UP_TXDPA I/O-U Upstream USB Type-C™ “Orientation A” USB 3.1 Gen 1
Transmit Data Plus.
Upstream USB
3.1 Gen 1 TX D-
Orientation A
USB3UP_TXDMA I/O-U Upstream USB Type-C “Orientation A” USB 3.1 Gen 1
Transmit Data Minus.
Upstream USB
3.1 Gen 1 RX D+
Orientation A
USB3UP_RXDPA I/O-U Upstream USB Type-C “Orientation A” USB 3.1 Gen 1
Receive Data Plus.
Upstream USB
3.1 Gen 1 RX D-
Orientation A
USB3UP_RXDMA I/O-U Upstream USB Type-C “Orientation A” USB 3.1 Gen 1
Receive Data Minus.
Upstream USB
3.1 Gen 1 TX D+
Orientation B
USB3UP_TXDPB I/O-U Upstream USB Type-C “Orientation B” USB 3.1 Gen 1
Transmit Data Plus.
Upstream USB
3.1 Gen 1 TX D-
Orientation B
USB3UP_TXDMB I/O-U Upstream USB Type-C “Orientation B” USB 3.1 Gen 1
Transmit Data Minus.
Upstream USB
3.1 Gen 1 RX D+
Orientation B
USB3UP_RXDPB I/O-U Upstream USB Type-C “Orientation B” USB 3.1 Gen 1
Receive Data Plus.
Pin
Num Pin Name Pin
Num Pin Name
2018-2019 Microchip Technology Inc. DS00002670C-page 11
USB7002
Upstream USB
3.1 Gen 1 RX D-
Orientation B
USB3UP_RXDMB I/O-U Upstream USB Type-C “Orientation B” USB 3.1 Gen 1
Receive Data Minus.
Downstream
Port 1 USB 3.1
Gen 1 TX D+
Orientation A
USB3DN_TXDP1A I/O-U Downstream USB Type-C “Orientation A” Super Speed
Transmit Data Plus, port 1.
Downstream
Port 1 USB 3.1
Gen 1 TX D- Ori-
entation A
USB3DN_TXDM1A I/O-U Downstream USB Type-C “Orientation A” Super Speed
Transmit Data Minus, port 1.
Downstream
Port 1 USB 3.1
Gen 1 RX D+
Orientation A
USB3DN_RXDP1A I/O-U Downstream USB Type-C “Orientation A” Super Speed
Receive Data Plus, port 1.
Downstream
Port 1 USB 3.1
Gen 1 RX D- Ori-
entation A
USB3DN_RXDM1A I/O-U Downstream USB Type-C “Orientation A” Super Speed
Receive Data Minus, port 1.
Downstream
Port 1 USB 3.1
Gen 1 TX D+
Orientation B
USB3DN_TXDP1B I/O-U Downstream USB Type-C “Orientation B” Super Speed
Transmit Data Plus, port 1.
Downstream
Port 1 USB 3.1
Gen 1 TX D- Ori-
entation B
USB3DN_TXDM1B I/O-U Downstream USB Type-C “Orientation B” Super Speed
Transmit Data Minus, port 1.
Downstream
Port 1 USB 3.1
Gen 1 RX D+
Orientation B
USB3DN_RXDP1B I/O-U Downstream USB Type-C “Orientation B” Super Speed
Receive Data Plus, port 1.
Downstream
Port 1 USB 3.1
Gen 1 RX D- Ori-
entation B
USB3DN_RXDM1B I/O-U Downstream USB Type-C “Orientation B” Super Speed
Receive Data Minus, port 1.
Downstream
Port 2 USB 3.1
Gen 1 TX D+
Orientation A
USB3DN_TXDP2A I/O-U Downstream USB Type-C “Orientation A” Super Speed
Transmit Data Plus, port 2.
Downstream
Port 2 USB 3.1
Gen 1 TX D-
Orientation A
USB3DN_TXDM2A I/O-U Downstream USB Type-C “Orientation A” Super Speed
Transmit Data Minus, port 2.
TABLE 3-1: PIN DESCRIPTIONS (CONTINUED)
Name Symbol Buffer
Type Description
USB7002
DS00002670C-page 12 2018-2019 Microchip Technology Inc.
Downstream
Port 2 USB 3.1
Gen 1 RX D+
Orientation A
USB3DN_RXDP2A I/O-U Downstream USB Type-C “Orientation A” Super Speed
Receive Data Plus, port 2.
Downstream
Port 2 USB 3.1
Gen 1 RX D-
Orientation A
USB3DN_RXDM2A I/O-U Downstream USB Type-C “Orientation A” Super Speed
Receive Data Minus, port 2.
Downstream
Port 2 USB 3.1
Gen 1 TX D+
Orientation B
USB3DN_TXDP2B I/O-U Downstream USB Type-C “Orientation B” Super Speed
Transmit Data Plus, port 2.
Downstream
Port 2 USB 3.1
Gen 1 TX D-
Orientation B
USB3DN_TXDM2B I/O-U Downstream USB Type-C “Orientation B” Super Speed
Transmit Data Minus, port 2.
Downstream
Port 2 USB 3.1
Gen 1 RX D+
Orientation B
USB3DN_RXDP2B I/O-U Downstream USB Type-C “Orientation B” Super Speed
Receive Data Plus, port 2.
Downstream
Port 2 USB 3.1
Gen 1 RX D-
Orientation B
USB3DN_RXDM2B I/O-U Downstream USB Type-C “Orientation B” Super Speed
Receive Data Minus, port 2.
USB 2.0 Interfaces
Upstream USB
2.0 D+
USB2UP_DP I/O-U Upstream USB 2.0 Data Plus (D+).
Upstream USB
2.0 D-
USB2UP_DM I/O-U Upstream USB 2.0 Data Minus (D-).
Downstream
Ports 1-4 USB
2.0 D+
USB2DN_DP[1:4] I/O-U Downstream USB 2.0 Ports 1-4 Data Plus (D+).
Downstream
Ports 1-4 USB
2.0 D-
USB2DN_DM[1:4] I/O-U Downstream USB 2.0 Ports 1-4 Data Minus (D-)
TABLE 3-1: PIN DESCRIPTIONS (CONTINUED)
Name Symbol Buffer
Type Description
2018-2019 Microchip Technology Inc. DS00002670C-page 13
USB7002
VBUS Detect VBUS_DET IS This signal detects the state of the upstream bus power
in legacy Type-B upstream implementations.
When designing a detachable hub, this pin must be con-
nected to the VBUS power pin of the upstream USB port
through a resistor divider (50 kΩ by 100 kΩ) to provide
3.3 V.
For self-powered applications with a permanently
attached host, this pin must be connected to either 3.3 V
or 5.0 V through a resistor divider to provide 3.3 V.
In embedded applications, VBUS_DET may be con-
trolled (toggled) when the host desires to renegotiate a
connection without requiring a full reset of the device.
USB Type-C Connector Control
Downstream
Port 1 Type-C
Voltage Monitor
DP1_VBUS_MON I/O12 Used to detect Type-C VBUS vSafe5V and vSafe0V
states on Port 1. A potential divider is needed for this pin
(44.2 k to 49.9 k , 1.0%).
Downstream
Port 1 Type-C
CC1
DP1_CC1 I/O12 Used for Type-C attach and orientation detection on Port
1. Includes configurable Rp/Ra selection. Connect this
pin directly to the CC1 pin of the respective Type-C con-
nector.
Downstream
Port 1 Type-C
CC2
DP1_CC2 I/O12 Used for Type-C attach and orientation detection on Port
1. Includes configurable Rp/Ra selection. Connect this
pin directly to the CC2 pin of the respective Type-C con-
nector.
Downstream
Port 2 Type-C
Voltage Monitor
DP2_VBUS_MON I/O12 Used for detect Type-C VBUS vSafe5V and vSafe0V
states on Port 2. A potential divider is needed for this pin
(44.2 k to 49.9 k , 1.0%).
Downstream
Port 2 Type-C
CC1
DP2_CC1 I/O12 Used for Type-C attach and orientation detection on Port
2. Includes configurable Rp/Ra selection. Connect this
pin directly to the CC1 pin of the respective Type-C con-
nector.
Downstream
Port 2 Type-C
CC2
DP2_CC2 I/O12 Used for Type-C attach and orientation detection on Port
2. Includes configurable Rp/Ra selection. Connect this
pin directly to the CC2 pin of the respective Type-C con-
nector.
Upstream
Type-C CC1
CC1_UP I/O12 Used for Type-C attach and orientation detection.
Includes configurable Rp/Ra selection.
Upstream
Type-C CC2
CC2_UP I/O12 Used for Type-C attach and orientation detection.
Includes configurable Rp/Ra selection.
Upstream
Type-C Voltage
Monitor
VBUS_MON_UP I/O12 Used to detect Type-C VBUS vSafe5V and vSafe0V
states on the upstream port. A potential divider is
needed for this pin (44.2 k to 49.9 k , 1.0%).
TABLE 3-1: PIN DESCRIPTIONS (CONTINUED)
Name Symbol Buffer
Type Description
USB7002
DS00002670C-page 14 2018-2019 Microchip Technology Inc.
Miscellaneous
Programmable
Function Pins
PF[31:4] I/O12 Programmable function pins.
Refer to Section 3.3, Configuration Straps and Program-
mable Functions for details.
Reset Input RESET_N IS This active low signal is used by the system to reset the
device.
Bias Resistor RBIAS I-R A 12.0 k 1.0% resistor is attached from ground to this
pin to set the transceiver’s internal bias settings. Place
the resistor as close the device as possible with a dedi-
cated, low impedance connection to the ground plane.
Test 1 TEST1 A Test 1 pin.
This signal is used for test purposes and must always
be pulled-up to 3.3V via a 4.7 k resistor.
Test 2 TEST2 A Test 2 pin.
This signal is used for test purposes and must always
be pulled-down to ground via a 4.7 k resistor.
Test 3 TEST3 A Test 3 pin.
This signal is used for test purposes and must always
be pulled-down to ground via a 4.7 k resistor.
Test TESTEN I/O12 Test pin.
This signal is used for test purposes and must always
be connected to ground.
Analog Test ATEST A Analog test pin.
This signal is used for test purposes and must either be
left unconnected or tied to ground.
External 25 MHz
Crystal Input
XTALI ICLK External 25 MHz crystal input
External 25 MHz
Reference Clock
Input
CLKIN ICLK External reference clock input.
The device may alternatively be driven by a single-
ended clock oscillator. When this method is used,
XTALO should be left unconnected.
External 25 MHz
Crystal Output
XTALO OCLK External 25 MHz crystal output
TABLE 3-1: PIN DESCRIPTIONS (CONTINUED)
Name Symbol Buffer
Type Description
2018-2019 Microchip Technology Inc. DS00002670C-page 15
USB7002
Note 3-1 Configuration strap values are latched on Power-On Reset (POR) and the rising edge of RESET_N
(external chip reset). Configuration straps are identified by an underlined symbol name. Signals that
function as configuration straps must be augmented with an external resistor when connected to a
load. For additional information, refer to Section 3.3, Configuration Straps and Programmable
Functions.
Configuration Straps
Port 4-1 D+
Disable
Configuration
Strap
PRT_DIS_P[4:1] I Port 4-1 D+ Disable Configuration Strap.
These configuration straps are used in conjunction with
the corresponding PRT_DIS_M[4:1] straps to disable
the related port (4-1). See Note 3-1.
Both USB data pins for the corresponding port must be
tied to 3.3V to disable the associated downstream port.
Port 4-1 D-
Disable
Configuration
Strap
PRT_DIS_M[4:1] I Port 4-1 D- Disable Configuration Strap.
These configuration straps are used in conjunction with
the corresponding PRT_DIS_P[4:1] straps to disable the
related port (4-1). See Note 3-1.
Both USB data pins for the corresponding port must be
tied to 3.3V to disable the associated downstream port.
Non-Removable
Ports
Configuration
Strap
CFG_NON_REM I Non-Removable Ports Configuration Strap.
This configuration strap controls the number of reported
non-removable ports. See Note 3-1.
Battery Charging
Configuration
Strap
CFG_BC_EN I/O12 Battery Charging Configuration Strap.
This configuration strap controls the number of BC 1.2
enabled downstream ports. See Note 3-1.
Device Mode
Configuration
Straps 3-1
CFG_STRAP[3:1] I Device Mode Configuration Straps 3-1.
These configuration straps are used to select the
device’s mode of operation. See Note 3-1.
Power/Ground
+3.3V I/O Power
Supply Input
VDD33 P +3.3 V power and internal regulator input.
+1.2V Core
Power Supply
Input
VDD12 P +1.2 V digital core power supply input.
Ground VSS P Common ground.
This exposed pad must be connected to the ground
plane with a via array.
TABLE 3-1: PIN DESCRIPTIONS (CONTINUED)
Name Symbol Buffer
Type Description
USB7002
DS00002670C-page 16 2018-2019 Microchip Technology Inc.
3.3 Configuration Straps and Programmable Functions
Configuration straps are multi-function pins that are used during Power-On Reset (POR) or external chip reset
(RESET_N) to determine the default configuration of a particular feature. The state of the signal is latched following
deassertion of the reset. Configuration straps are identified by an underlined symbol name. This section details the var-
ious device configuration straps and associated programmable pin functions.
3.3.1 PORT DISABLE CONFIGURATION (PRT_DIS_P[4:1] / PRT_DIS_M[4:1])
The PRT_DIS_P[4:1] / PRT_DIS_M[4:1] configuration straps are used in conjunction to disable the related port (4-1)
For PRT_DIS_Px (where x is the corresponding port 4-1):
0 = Port x D+ Enabled
1 = Port x D+ Disabled
For PRT_DIS_Mx (where x is the corresponding port 4-1):
0 = Port x D- Enabled
1 = Port x D- Disabled
3.3.2 NON-REMOVABLE PORT CONFIGURATION (CFG_NON_REM)
The CFG_NON_REM configuration strap is used to configure the non-removable port settings of the device to one of
five settings. These modes are selected by the configuration of an external resistor on the CFG_NON_REM pin. The
resistor options are a 200 kΩ pull-down, 200 kΩ pull-up, 10 kΩ pull-down, 10 kΩ pull-up, and 10 Ω pull-down, as shown
in Table 3-2.
Note: The system designer must ensure that configuration straps meet the timing requirements specified in
Section 9.6.2, Power-On and Configuration Strap Timing and Section 9.6.3, Reset and Configuration Strap
Timing. If configuration straps are not at the correct voltage level prior to being latched, the device may
capture incorrect strap values.
Note: Both PRT_DIS_Px and PRT_DIS_Mx (where x is the corresponding port) must be tied to 3.3 V to disable
the associated downstream port. Disabling the USB 2.0 port will also disable the corresponding USB 3.0
port.
TABLE 3-2: CFG_NON_REM RESISTOR ENCODING
CFG_NON_REM Resistor Value Setting
200 kΩ Pull-Down All ports removable
200 kΩ Pull-Up Port 1 non-removable
10 kΩ Pull-Down Ports 1, 2 non-removable
10 kΩ Pull-Up Ports 1, 2, 3 non-removable
10 Ω Pull-Down Ports 1, 2, 3, 4 non-removable
2018-2019 Microchip Technology Inc. DS00002670C-page 17
USB7002
3.3.3 BATTERY CHARGING CONFIGURATION (CFG_BC_EN)
The CFG_BC_EN configuration strap is used to configure the battery charging port settings of the device to one of
five settings. These modes are selected by the configuration of an external resistor on the CFG_BC_EN pin. The resistor
options are a 200 kΩ pull-down, 200 kΩ pull-up, 10 kΩ pull-down, 10 kΩ pull-up, and 10 Ω pull-down, as shown in
Table 3-3.
3.3.4 PF[31:4] CONFIGURATION (CFG_STRAP[2:1])
The USB7002 provides 28 programmable function pins (PF[31:4]). These pins can be configured to 4 predefined con-
figurations via the CFG_STRAP[2:1] pins. These configurations are selected via external resistors on the
CFG_STRAP[2:1] pins, as detailed in Ta bl e 3-4. Resistor values and combinations not detailed in Table 3-4 are reserved
and should not be used.
TABLE 3-3: CFG_BC_EN RESISTOR ENCODING
CFG_BC_EN Resistor Value Setting
200 kΩ Pull-Down Battery charging not enable on any port
200 kΩ Pull-Up BC1.2 DCP and CDP battery charging enabled on Port 1
10 kΩ Pull-Down BC1.2 DCP and CDP battery charging enabled on Ports 1, 2
10 kΩ Pull-Up BC1.2 DCP and CDP battery charging enabled on Ports 1, 2, 3
10 Ω Pull-Down BC1.2 DCP and CDP battery charging enabled on Ports 1, 2, 3, 4
Note: CFG_STRAP3 is not used and can be left unconnected.
TABLE 3-4: CFG_STRAP[2:1] RESISTOR ENCODING
Mode CFG_STRAP2
Resistor Value CFG_STRAP1
Resistor Value
Configuration 1 200 kΩ Pull-Down 200 kΩ Pull-Down
Configuration 2 200 kΩ Pull-Down 200 kΩ Pull-Up
Configuration 3 200 kΩ Pull-Down 10 kΩ Pull-Down
Configuration 4 200 kΩ Pull-Down 10 kΩ Pull-Up
USB7002
DS00002670C-page 18 2018-2019 Microchip Technology Inc.
A summary of the configuration pin assignments for each of the 4 configurations is provided in Table 3-5. For details on
behavior of each programmable function, refer to Ta b l e 3-6 .
TABLE 3-5: PF[31:4] FUNCTION ASSIGNMENT
Pin Configuration 1
(SMBus/I2C) Configuratio n 2
(I2S) Configuration 3
(UART) Configuration 4
(Flex)
PF4 DP2_DISCHARGE DP2_DISCHARGE DP2_DISCHARGE DP2_DISCHARGE
PF5 DP1_DISCHARGE DP1_DISCHARGE DP1_DISCHARGE DP1_DISCHARGE
PF6 GPIO70 GPIO70 UART_RX GPIO70
PF7 GPIO71 MIC_DET UART_TX GPIO71
PF8 DP1_VCONN1 DP1_VCONN1 DP1_VCONN1 DP1_VCONN1
PF9 DP1_VCONN2 DP1_VCONN2 DP1_VCONN2 DP1_VCONN2
PF10 DP2_VCONN1 DP2_VCONN1 DP2_VCONN1 DP2_VCONN1
PF11 DP2_VCONN2 DP2_VCONN2 DP2_VCONN2 DP2_VCONN2
PF12 GPIO76 GPIO76 GPIO76 GPIO76
PF13 PRT_CTL4 PRT_CTL4 PRT_CTL4 PRT_CTL4
PF14 GPIO78 I2S_SDI UART_nCTS GPIO78
PF15 PRT_CTL2 PRT_CTL2 PRT_CTL2 PRT_CTL2
PF16 PRT_CTL3 PRT_CTL3 PRT_CTL3 PRT_CTL3
PF17 PRT_CTL1 PRT_CTL1 PRT_CTL1 PRT_CTL1
PF18 MSTR_I2C_CLK I2S_LRCK UART_nDCD GPIO82
PF19 MSTR_I2C_DATA I2S_SDO UART_nRTS GPIO83
PF20 SPI_CE_N SPI_CE_N SPI_CE_N SPI_CE_N
PF21 SPI_CLK SPI_CLK SPI_CLK SPI_CLK
PF22 SPI_D0 SPI_D0 SPI_D0 SPI_D0
PF23 SPI_D1 SPI_D1 SPI_D1 SPI_D1
PF24 SPI_D2 SPI_D2 SPI_D2 SPI_D2
PF25 SPI_D3 SPI_D3 SPI_D3 SPI_D3
PF26 SLV_I2C_CLK I2S_SCK UART_nDSR GPIO90
PF27 SLV_I2C_DATA I2S_MCLK UART_nDTR GPIO91
PF28 GPIO92 GPIO92 GPIO92 GPIO92
PF29 GPIO93 GPIO93 GPIO93 GPIO93
PF30 GPIO94 MSTR_I2C_CLK GPIO94 GPIO94
PF31 GPIO95 MSTR_I2C_DATA GPIO95 GPIO95
Note: The default PFx pin functions can be overridden with additional configuration by modification of the pin mux
registers. These changes can be made during the SMBus configuration stage, by programming to OTP
memory, or during runtime (after hub has attached and enumerated) by register writes via the SMBus slave
interface or USB commands to the internal Hub Feature Controller Device.
2018-2019 Microchip Technology Inc. DS00002670C-page 19
USB7002
TABLE 3-6: PROGRAMMABLE FUNCTIONS DESCRIPTIONS
Function Buffer
Type Description
Master SMBus/I2C Interface
MSTR_I2C_CLK I/O12 Bridging Master SMBus/I2C controller clock (SMBus/I2C controller 1)
MSTR_I2C_DATA I/O12 Bridging Master SMBus/I2C controller data (SMBus/I2C controller 1)
Slave SMBus/I2C Interface
SLV_I2C_CLK I/O12 Slave SMBus/I2C controller clock (SMBus/I2C controller 2)
SLV_I2C_DATA I/O12 Slave SMBus/I2C controller data (SMBus/I2C controller 2)
SPI Interface
SPI_CLK I/O-U SPI clock. If the SPI interface is enabled, this pin must be driven low during
reset.
SPI_D[3:0] I/O-U SPI Data 3-0. If the SPI interface is enabled, these signals function as Data
3 through 0.
SPI_CE_N I/O12 Active low SPI chip enable input. If the SPI interface is enabled, this pin
must be driven high in powerdown states.
UART Interface
UART_TX O12 UART Transmit
UART_RX I UART Receive
UART_nCTS I UART Clear To Send
UART_nRTS O12 UART Request To Send
UART_nDCD I UART Data Carrier Detect
UART_nDSR I UART Data Set Ready
UART_nDTR O12 UART Data Terminal Ready
I2S Interface
I2S_SDI I I2S Serial Data In
I2S_SDO O12 I2S Serial Data Out
I2S_SCK O12 I2S Continuous Serial Clock
I2S_LRCK O12 I2S Word Select / Left-Right Clock
I2S_MCLK O12 I2S Master Clock
MIC_DET I I2S Microphone Plug Detect
0 = No microphone plugged into the audio jack
1 = Microphone plugged into the audio jack
Miscellaneous
DP2_VCONN1 I/O12 Port 2 VCONN1 enable
DP2_VCONN2 I/O12 Port 2 VCONN2 enable
USB7002
DS00002670C-page 20 2018-2019 Microchip Technology Inc.
DP2_DISCHARGE I/O12 Port 2 DISCHARGE enable
DP1_VCONN1 I/O12 Port 1 VCONN1 enable
DP1_VCONN2 I/O12 Port 1 VCONN2 enable
DP1_DISCHARGE I/O12 Port 1 DISCHARGE enable
PRT_CTL4 I/O12
(PU)
Port 4 power enable / overcurrent sense
When the downstream port is enabled, this pin is set as an input with an
internal pull-up resistor applied. The internal pull-up enables power to the
downstream port while the pin monitors for an active low overcurrent signal
assertion from an external current monitor on USB port 4.
This pin will change to an output and be driven low when the port is dis-
abled by configuration or by the host control.
Note: This signal controls both the USB 2.0 and USB 3.1 portions of
the port.
PRT_CTL3 I/O12
(PU)
Port 3 power enable / overcurrent sense
When the downstream port is enabled, this pin is set as an input with an
internal pull-up resistor applied. The internal pull-up enables power to the
downstream port while the pin monitors for an active low overcurrent signal
assertion from an external current monitor on USB port 3.
This pin will change to an output and be driven low when the port is dis-
abled by configuration or by the host control.
Note: This signal controls both the USB 2.0 and USB 3.1 portions of
the port.
PRT_CTL2 I/O12
(PU)
Port 2 power enable / overcurrent sense
When the downstream port is enabled, this pin is set as an input with an
internal pull-up resistor applied. The internal pull-up enables power to the
downstream port while the pin monitors for an active low overcurrent signal
assertion from an external current monitor on USB port 2.
This pin will change to an output and be driven low when the port is dis-
abled by configuration or by the host control.
Note: This signal controls both the USB 2.0 and USB 3.1 portions of
the port.
TABLE 3-6: PROGRAMMABLE FUNCTIONS DESCRIPTIONS (CONTIN UED)
Function Buffer
Type Description
2018-2019 Microchip Technology Inc. DS00002670C-page 21
USB7002
3.4 Physical and Logical Port Mapping
The USB70xx family of devices are based upon a common architecture, but all have different modifications and/or pin
bond outs to achieve the various device configurations. The base chip is composed of a total of 6 USB3 PHYs and 7
USB2 PHYs. These PHYs are physically arranged on the chip in a certain way, which is referred to as the PHYSICAL
port mapping.
The actual port numbering is remapped by default in different ways on each device in the family. This changes the way
that the ports are numbered from the USB host’s perspective. This is referred to as LOGICAL mapping.
The various configuration options available for these devices may, at times, be with respect to PHYSICAL mapping or
LOGICAL mapping. Each individual configuration option which has a PHYSICAL or LOGICAL dependency is declared
as such within the register description.
The PHYSICAL vs. LOGICAL mapping is described for all port related pins in Table 3-7. A system design in schematics
and layout is generally performed using the pinout in Section 3.1, Pin Assignments, which is assigned by the default
LOGICAL mapping. Hence, it may be necessary to cross reference the PHYSICAL vs. LOGICAL look up tables when
determining the hub configuration.
PRT_CTL1 I/O12
(PU)
Port 1 power enable / overcurrent sense
When the downstream port is enabled, this pin is set as an input with an
internal pull-up resistor applied. The internal pull-up enables power to the
downstream port while the pin monitors for an active low overcurrent signal
assertion from an external current monitor on USB port 1.
This pin will change to an output and be driven low when the port is dis-
abled by configuration or by the host control.
Note: This signal controls both the USB 2.0 and USB 3.1 portions of
the port.
GPIOxI/O12 General Purpose Inputs/Outputs
(x = 70-71, 76, 78, 82-83, 90-95)
Note: The MPLAB Connect tool makes configuration simple; the settings can be selected by the user with respect
to the LOGICAL port numbering. The tool handles the necessary linking to the PHYSICAL port settings.
Refer to Section 6.0, Device Configuration for additional information.
TABLE 3-6: PROGRAMMABLE FUNCTIONS DESCRIPTIONS (CONTINUED)
Function Buffer
Type Description
USB7002
DS00002670C-page 22 2018-2019 Microchip Technology Inc.
TABLE 3-7: USB7002 PHYSICAL VS. LOGICAL PORT MAPPING
Device
Pin Pin Name LOGICAL PORT NUMBER PHYSICAL PORT NUMBER
0123450123456
5 USB2DN_DP1 X X
6 USB2DN_DM1 X X
7 USB3DN_TXDP1A X X
8 USB3DN_TXDM1A X X
10 USB3DN_RXDP1A X X
11 USB3DN_RXDM1A X X
14 USB2DN_DP3 X X
15 USB2DN_DM3 X X
16 USB3DN_TXDP1B X X
17 USB3DN_TXDM1B X X
19 USB3DN_RXDP1B X X
20 USB3DN_RXDM1B X X
29 USB2DN_DP2 X X
30 USB2DN_DM2 X X
31 USB3DN_TXDP2A X X
32 USB3DN_TXDM2A X X
34 USB3DN_RXDP2A X X
35 USB3DN_RXDM2A X X
37 USB2DN_DP4 X X
38 USB2DN_DM4 X X
39 USB3DN_TXDP2B X X
40 USB3DN_TXDM2B X X
42 USB3DN_RXDP2B X X
43 USB3DN_RXDM2B X X
81 USB3UP_TXDPB X X
82 USB3UP_TXDMB X X
84 USB3UP_RXDPB X X
85 USB3UP_RXDMB X X
89 USB2UP_DP X X
90 USB2UP_DM X X
91 USB3UP_TXDPA X X
92 USB3UP_TXDMA X X
94 USB3UP_RXDPA X X
95 USB3UP_RXDMA X X
2018-2019 Microchip Technology Inc. DS00002670D-page 23
USB7002
4.0 DEVICE CONNECTIONS
4.1 Power Connections
Figure 4-1 illustrates the device power connections.
4.2 SPI/SQI Flash Connections
Figure 4-2 illustrates the Quad-SPI flash connections.
FIGURE 4-1: POWER CONNECTIONS
FIGURE 4-2: QUAD-SPI FLASH CONNECTIONS
+3.3V
Supply
USB7002
3.3V Internal Logic
VDD33 (x8)
VSS(exposed pad)
1.2V Internal Logic VDD12 (x9)
+1.2V
Supply
+3.3V
0.1uF
0.001uF
x8
+3.3V
4.7uF
+1.2V
0.1uF
0.001uF
x9
+1.2V
4.7uF
USB7002
SPI_CE_N
SPI_CLK
SPI_D0
SPI_D1
Quad-SPI Flash
CE#
CLK
SIO0
SIO1
SPI_D2
SPI_D3
SIO2/WPn
SIO3/HOLDn
+3.3V
10K
USB7002
DS00002670D-page 24 2018-2019 Microchip Technology Inc.
4.3 SMBus/I2C Connections
Figure 4-3 illustrates the SMBus/I2C connections.
4.4 I2S Connections
Figure 4-4 illustrates the I2S connections.
FIGURE 4-3: SMBUS/I2C CONNECTIONS
Note: Resistor values detailed in Figure 4-3 are suggestions. Optimal pull-up values may vary dependent on
external factors.
FIGURE 4-4: I2S CONNECTIONS
+3.3V
USB7002
x_I2C_CLK
x_I2C_DAT
SMBus/I
2
C
Clock
Data
R
+3.3V
R
R = 4.7K for 400/100KHz Master I2C interfaces,
1.0K for 1MHz Master I2C interfaces,
10K for Slave I2C interfaces
USB7002
I2S_LRCK
I2S_SDO
I2S_SD
I2S_MCLK
CODEC
I2S_SCK
+3.3V
10K
10K
I2S
MSTR_I2C_CLK
MSTR_I2C_DAT I2C
Audio Jack
MIC_DET
USB7002
DS00002670D-page 26 2018-2019 Microchip Technology Inc.
5.0 MODES OF OPERATION
The device provides two main modes of operation: Standby Mode and Hub Mode. These modes are controlled via the
RESET_N pin, as shown in Tab l e 5-1 .
The flowchart in Figure 5-1 details the modes of operation and details how the device traverses through the Hub Mode
stages (shown in bold). The remaining sub-sections provide more detail on each stage of operation.
TABLE 5-1: MODES OF OPERATION
RESET_N Input Summary
0Standby Mode: This is the lowest power mode of the device. No functions are active other
than monitoring the RESET_N input. All port interfaces are high impedance and the PLL is
halted. Refer to Section 8.11, Resets for additional information on RESET_N.
1Hub (Normal) Mode: The device operates as a configurable USB hub. This mode has vari-
ous sub-modes of operation, as detailed in Figure 5-1. Power consumption is based on the
number of active ports, their speed, and amount of data received.
FIGURE 5-1: HUB MODE FLOWCHART
Combine OTP
Config Data
In SPI Mode
& Ext. SPI ROM
present?
YES
NO
Run From
External SPI ROM
(SPI_INIT)
SMBus Slave Pull-ups?
RESET_N deasserted
Modify Config
Based on Config
Straps
(CFG_ROM)
Load Config from
Internal ROM
YES
NO
(SMBUS_CHECK)
Perform SMBus/I2C
Initialization
SOC Done?
YES
NO
(CFG_SMBUS)
(CFG_OTP)
Hub Connect
(USB_ATTACH)
Normal O perat ion
(NORMAL_MODE)
(CFG_STRAP)
Configuration 1?
YES
NO
2018-2019 Microchip Technology Inc. DS00002670D-page 27
USB7002
5.1 Boot Sequence
5.1.1 STANDBY MODE
If the RESET_N pin is asserted, the hub will be in Standby Mode. This mode provides a very low power state for maxi-
mum power efficiency when no signaling is required. This is the lowest power state. In Standby Mode all downstream
ports are disabled, the USB data pins are held in a high-impedance state, all transactions immediately terminate (no
states saved), all internal registers return to their default state, the PLL is halted, and core logic is powered down in order
to minimize power consumption. Because core logic is powered off, no configuration settings are retained in this mode
and must be re-initialized after RESET_N is negated high.
5.1.2 SPI INITIALIZATION STAGE (SPI_INIT)
The first stage, the initialization stage, occurs on the deassertion of RESET_N. In this stage, the internal logic is reset,
the PLL locks if a valid clock is supplied, and the configuration registers are initialized to their default state. The internal
firmware then checks for an external SPI ROM. The firmware looks for an external SPI flash device that contains a valid
signature of “2DFU” (device firmware upgrade) beginning at address 0x3FFFA. If a valid signature is found, then the
external SPI ROM is enabled and the code execution begins at address 0x0000 in the external SPI device. If a valid
signature is not found, then execution continues from internal ROM (CFG_ROM stage).
The required SPI ROM must be a minimum of 1 Mbit, and 60 MHz or faster. Both 1, 2, and 4-bit SPI operation is sup-
ported. For optimum throughput, a 2-bit SPI ROM is recommended. Both mode 0 and mode 3 SPI ROMs are also sup-
ported.
If the system is not strapped for SPI Mode, code execution will continue from internal ROM (CFG_ROM stage).
5.1.3 CONFIGURATION FROM INTERNAL ROM STAGE (CFG_ROM)
In this stage, the internal firmware loads the default values from the internal ROM. Most of the hub configuration regis-
ters, USB descriptors, electrical settings, etc. will be initialized in this state.
5.1.4 CONFIGURATION STRAP READ STAGE (CFG_STRAP)
In this stage, the firmware reads the following configuration straps to override the default values:
•CFG_STRAP[3:1]
•PRT_DIS_P[4:1]
•PRT_DIS_M[4:1]
•CFG_NON_REM
•CFG_BC_EN
If the CFG_STRAP[3:1] pins are set to Configuration 1, the device will move to the SMBUS_CHECK stage, otherwise
it will move to the CFG_OTP stage. Refer to Section 3.3, Configuration Straps and Programmable Functions for infor-
mation on usage of the various device configuration straps.
5.1.5 SMBUS CHECK STAGE (SMBUS_CHECK)
Based on the PF[31:4] configuration selected (refer to Section 3.3.4, PF[31:4] Configuration (CFG_STRAP[2:1])), the
firmware will check for the presence of external pull up resistors on the SMBus slave programmable function pins. If
pull-ups are detected on both pins, the device will be configured as an SMBus slave, and the next state will be CFG_SM-
BUS. If a pull-up is not detected in either of the pins, the next state is CFG_OTP.
5.1.6 SMBUS CONFIGURATION STAGE (CFG_SMBUS)
In this stage, the external SMBus master can modify any of the default configuration settings specified in the integrated
ROM, such as USB device descriptors, port electrical settings, and control features such as downstream battery
charging.
There is no time limit on this mode. In this stage the firmware will wait indefinitely for the SMBus/I2C configuration. The
external SMBus master writes to register 0xFF to end the configuration in legacy mode. In non-legacy mode, the SMBus
command USB_ATTACH (opcode 0xAA55) or USB_ATTACH_WITH_SMBUS (opcode 0xAA56) will finish the configu-
ration.
USB7002
DS00002670D-page 28 2018-2019 Microchip Technology Inc.
5.1.7 OTP CONFIGURATION STAGE (CFG_OTP)
Once the SOC has indicated that it is done with configuration, all configuration data is combined in this stage. The
default data, the SOC configuration data, and the OTP data are all combined in the firmware and the device is pro-
grammed.
5.1.8 HUB CONNECT STAGE (USB_ATTACH)
Once the hub registers are updated through default values, SMBus master, and OTP, the device firmware will enable
attaching the USB host by setting the USB_ATTACH bit in the HUB_CMD_STAT register (for USB 2.0) and the
USB3_HUB_ENABLE bit (for USB 3.1). The device will remain in the Hub Connect stage indefinitely.
5.1.9 NORMAL MODE (NORMAL_MODE)
Lastly, the hub enters Normal Mode of operation. In this stage full USB operation is supported under control of the USB
Host on the upstream port. The device will remain in the normal mode until the operating mode is changed by the sys-
tem.
If RESET_N is asserted low, then Standby Mode is entered. The device may then be placed into any of the designated
hub stages. Asserting a soft disconnect on the upstream port will cause the hub to return to the Hub Connect stage until
the soft disconnect is negated.
2018-2019 Microchip Technology Inc. DS00002670D-page 29
USB7002
6.0 DEVICE CONFIGURATION
The device supports a large number of features (some mutually exclusive), and must be configured in order to correctly
function when attached to a USB host controller. Microchip provides a comprehensive software programming tool,
MPLAB Connect Configurator (formerly ProTouch2), for OTP configuration of various USB7002 functions and registers.
All configuration is to be performed via the MPLAB Connect Configurator programming tool. For additional information
on this tool, refer to the MPLAB Connect Configurator programming tool product page at http://www.microchip.com/
design-centers/usb/mplab-connect-configurator.
Additional information on configuring the USB7002 is also provided in the “Configuration of the USB7002/USB705x”
application note, which contains details on the hub operational mode, SOC configuration stage, OTP configuration, USB
configuration, and configuration register definitions. This application note, along with additional USB7002 resources,
can be found on the Microchip USB7002 product page at www.microchip.com/USB7002.
Note: The USB7002 requires external firmware to operate. Refer to the “Configuration of the USB7002/
USB705x” application note for additional information.
Note: Device configuration straps and programmable pins are detailed in Section 3.3, Configuration Straps and
Programmable Functions.
Refer to Section 7.0, Device Interfaces for detailed information on each device interface.
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7.0 DEVICE INTERFACES
The USB7002 provides multiple interfaces for configuration, external memory access, etc.. This section details the var-
ious device interfaces:
•SPI/SQI Master Interface
•SMBus/I2C Master/Slave Interfaces
•I2S Interface
•UART Interface
7.1 SPI/SQI Master Interface
The SPI/SQI controller has two basic modes of operation: execution of an external hub firmware image, or the USB to
SPI bridge. On power up, the firmware looks for an external SPI flash device that contains a valid signature of 2DFU
(device firmware upgrade) beginning at address 0x3FFFA. If a valid signature is found, then the external ROM mode is
enabled and the code execution begins at address 0x0000 in the external SPI device. If a valid signature is not found,
then execution continues from internal ROM and the SPI interface can be used as a USB to SPI bridge.
The second mode of operation is the USB to SPI bridge operation. Additional details on this feature can be found in
Section 8.8, USB to SPI Bridging.
Table 7-1 details how the associated pins are mapped in SPI vs. SQI mode.
7.2 SMBus/I2C Master/Slave Interfaces
The device provides two independent SMBus/I2C controllers (Slave, and Master) which can be used to access internal
device run time registers or program the internal OTP memory. The device contains two 128 byte buffers to enable
simultaneous master/slave operation and to minimize firmware overhead in processed I2C packets. The I2C interfaces
support 100KHz Standard-mode (Sm) and 400KHz Fast Mode (Fm) operation.
The SMBus/I2C interfaces are assigned to programmable pins (PFx) and therefore the device must be programmed into
specific configurations to enable specific interfaces. Refer to Section 3.3.4, PF[31:4] Configuration (CFG_STRAP[2:1])
for additional information.
Note: For details on how to enable each interface, refer to Section 3.3, Configuration Straps and Programmable
Functions.
For information on device connections, refer to Section 4.0, Device Connections. For information on device
configuration, refer to Section 6.0, Device Configuration.
Microchip provides a comprehensive software programming tool, MPLAB Connect Configurator (formerly
ProTouch2), for configuring the USB7002 functions, registers and OTP memory. All configuration is to be
performed via the MPLAB Connect Configurator programming tool. For additional information on this tool,
refer to th MPLAB Connect Configurator programming tool product page at http://www.microchip.com/
design-centers/usb/mplab-connect-configurator.
TABLE 7-1: SPI/SQI PIN USAGE
SPI Mode SQI Mode Description
SPI_CE_N SPI_CE_N SPI/SQI Chip Enable (Active Low)
SPI_CLK SPI_CLK SPI/SQI Clock
SPI_D0 SPI_D0 SPI Data Out; SQI Data I/O 0
SPI_D1 SPI_D1 SPI Data In; SQI Data I/O 1
- SPI_D2 SQI Data I/O 2
- SPI_D3 SQI Data I/O 3
Note: For SPI/SQI master timing information, refer to Section 9.6.8, SPI/SQI Master Timing.
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USB7002
7.3 I2S Interface
The device provides an integrated I2S interface to facilitate the connection of digital audio devices. The I2S interface
conforms to the voltage, power, and timing characteristics/specifications as set forth in the I2S-Bus Specification, and
consists of the following signals:
•I2S_SDI: Serial Data Input
•I2S_SDO: Serial Data Output
•I2S_SCK: Serial Clock
•I2S_LRCK: Left/Right Clock (SS/FSYNC)
•I2S_MCLK: Master Clock
•MIC_DET: Microphone Plug Detect
Each audio connection is half-duplex, so I2S_SDO exists only on the transmit side and I2S_SDI exists only on the
receive side of the interface. Some codecs refer to the Serial Clock (I2S_SCK) as Baud/Bit Clock (BCLK). Also, the Left/
Right Clock is commonly referred to as LRC or LRCK. The I2S and other audio protocols refer to LRC as Word Select
(WS).
The following codec is supported by the default settings:
• Analog Devices ADAU1961 (24-bit 48kHz)
Additional codecs are also supported with modifications to the configuration register settings. Use the following table as
a guide for assessing I2S codec compatibility. For additional details on how to implement the necessary configuration
settings, refer to the application note, “USB7002/USB705x I2S Operation” .
Note: For SMBus/I2C timing information, refer to Section 9.6.5, SMBus Timing and Section 9.6.6, I2C Timing.
TABLE 7-2: USB TO I2S
Parameter Supported Values
Sampling Frequency (fs) 8kHz, 11.025kHz, 12kHz, 16kHz, 22.05kHz, 24kHz, 32kHz, 44.1kHz, 48kHz
MCLK Frequency.
(Multiple of Sampling frequency)
From 1*fs to 1024*fs.
MCLK can take continuous values also. However, the I2S LRCLK signal is derived
from the MCLK source, so it is advisable to keep MCLK signal frequency “Even
integer Multiple of Sampling frequency”.
Audio Sample size 16-bits/sample, 24-bits/sample, 32-bits/sample
I2S Audio Interface Format I2S Mode, Left Justified Mode, Right Justified Mode
I2C Master Control Interface
Frequency
100kHz and 400kHz
Audio channels Mono Mode and Stereo Mode
Enabling disabling the I2S-
Bridge Interfaces
Audio Out only (Speaker Interface) Mode (Or) Audio IN only (Mic Interface) (Or)
Enable both Audio IN and OUT interfaces (Or) Disable both Audio IN and Audio
Out interfaces.
Enabling Disabling of Jack-
Detection interface
Enable the Audio Jack-Insert detection HID interface / Disable the Jack detection
interface.
Note: For I2S timing information, refer to Section 9.6.7, I2S Timing. For detailed information on utilizing the I2S
interface, refer to the application note “USB7002/USB705x I2S Operation”, which can be found on the
Microchip USB7002 product page at www.microchip.com/USB7002.
USB7002
DS00002670D-page 32 2018-2019 Microchip Technology Inc.
7.3.1 MODES OF OPERATION
The USB audio class operates in three ways: Asynchronous, Synchronous and Adaptive. There are also multiple oper-
ating modes, such as hi-res, streaming, etc.. Typically for USB devices, inputs such as microphones are Asynchronous,
and output devices such as speakers are Adaptive. The hardware is set up to handle all three modes of operation. It is
recommended that the following configuration be used: Asynchronous IN; Adaptive OUT; 48Khz streaming mode; Two
channels: 16 bits per channel.
7.3.1.1 Asynchronous IN 48KHz Streaming
In this mode, the codec sampling clock is set to 48Khz based on the local oscillator. This clock is never changed. The
data from the codec is fed into the input FIFO. Since the sampling clock is asynchronous to the host clock, the amount
of data captured in every USB frame will vary. This issue is left for the host to handle. The input FIFO has two markers,
a low water mark (THRESHOLD_LOW_VAL), and a high water mark (THRESHOLD_HIGH_VAL). There are three reg-
isters to determine how much data to send back in each frame. If the amount of data in the FIFO exceeds the high water
mark, then HI_PKT_SIZE worth of data is sent. If the data is between the high and low water mark, the normal MID_P-
KT_SIZE amount of data is sent. If the data is below the low water mark, LO_PKT_SIZE worth of data is sent.
7.3.1.2 Adaptive OUT 48KHz Streaming
In this mode, the codec sampling clock is initially set to 48Khz based on the local oscillator. The host data is fed into the
OUT FIFO. The host will send the same amount of data on every frame, i.e. 48KHz of data based on the host clock. The
codec sampling clock is asynchronous to the host clock. This will cause the amount of data in the OUT FIFO to vary. If
the amount of data in the FIFO exceeds the high water mark, then the sampling clock is increased. If the data is between
the high and low water mark, the sampling clock does not change. If the data is below the low water mark, the sampling
clock is decreased.
7.3.1.3 Synchronous Operation
For synchronous operation, the internal clock must be synchronized with the host SOF. The Frame SOF is nominally
1mS. Since there is significant jitter in the SOFs, there is circuitry provided to measure the SOFs over a long period of
time to get a more accurate reading. The calculated host frequency is used to calculate the codec sampling clock.
7.4 UART Interface
The device incorporates a configurable universal asynchronous receiver/transmitter (UART) that is functionally compat-
ible with the NS 16550AF, 16450, 16450 ACE registers and the 16C550A. The UART performs serial-to-parallel con-
version on received characters and parallel-to-serial conversion on transmit characters. Two sets of baud rates are
provided: 24 Mhz and 16 MHz. When the 24 Mhz source clock is selected, standard baud rates from 50 to 115.2 K are
available. When the source clock is 16 MHz, baud rates from 125 K to 1,000 K are available. The character options are
programmable for the transmission of data in word lengths of from five to eight, 1 start bit; 1, 1.5 or 2 stop bits; even,
odd, sticky or no parity; and prioritized interrupts. The UART contains a programmable baud rate generator that is capa-
ble of dividing the input clock or crystal by a number from 1 to 65535. The UART is also capable of supporting the MIDI
data rate.
The UART interface is assigned to programmable pins (PFx) and therefore the device must be programmed into specific
configurations to enable the interface. Refer to Section 3.3.4, PF[31:4] Configuration (CFG_STRAP[2:1]) for additional
information.
7.4.1 TRANSMIT OPERATION
Transmission is initiated by writing the data to be sent to the TX Holding Register or TX FIFO (if enabled). The data is
then transferred to the TX Shift Register together with a start bit and parity and stop bits as determined by settings in
the Line Control Register. The bits to be transmitted are then shifted out of the TX Shift Register in the order Start bit,
Data bits (LSB first), Parity bit, Stop bit, using the output from the Baud Rate Generator (divided by 16) as the clock.
If enabled, a TX Holding Register Empty interrupt will be generated when the TX Holding Register or the TX FIFO (if
enabled) becomes empty.
When FIFOs are enabled (i.e. bit 0 of the FIFO Control Register is set), the UART can store up to 16 bytes of data for
transmission at a time. Transmission will continue until the TX FIFO is empty. The FIFO’s readiness to accept more data
is indicated by interrupt.
2018-2019 Microchip Technology Inc. DS00002670D-page 33
USB7002
7.4.2 RECEIVE OPERATION
Data is sampled into the RX Shift Register using the Receive clock, divided by 16. The Receive clock is provided by the
Baud Rate Generator. A filter is used to remove spurious inputs that last for less than two periods of the Receive clock.
When the complete word has been clocked into the receiver, the data bits are transferred to the RX Buffer Register or
to the RX FIFO (if enabled) to be read by the CPU. (The first bit of the data to be received is placed in bit 0 of this reg-
ister.) The receiver also checks that the parity bit and stop bits are as specified by the Line Control Register.
If enabled, an RX Data Received interrupt will be generated when the data has been transferred to the RX Buffer Reg-
ister or, if FIFOs are enabled, when the RX Trigger Level has been reached. Interrupts can also be generated to signal
RX FIFO Character Timeout, incorrect parity, a missing stop bit (frame error) or other Line Status errors.
When FIFOs are enabled (i.e. bit 0 of the FIFO Control Register is set), the UART can store up to 16 bytes of received
data at a time. Depending on the selected RX Trigger Level, interrupt will go active to indicate that data is available when
the RX FIFO contains 1, 4, 8 or 14 bytes of data.
USB7002
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8.0 FUNCTIONAL DESCRIPTIONS
This section details various USB7002 functions, including:
•Downstream Battery Charging
•Port Power Control
•CC Pin Orientation and Detection
•FlexConnect
•Multi-Host Endpoint Reflector
•USB to GPIO Bridging
•USB to I2C Bridging
•USB to SPI Bridging
•USB to UART Bridging
•Link Power Management (LPM)
•Resets
8.1 Downstream Battery Charging
The device can be configured by an OEM to have any of the downstream ports support battery charging. The hub’s role
in battery charging is to provide acknowledgment to a device’s query as to whether the hub system supports USB battery
charging. The hub silicon does not provide any current or power FETs or any additional circuitry to actually charge the
device. Those components must be provided externally by the OEM.
If the OEM provides an external supply capable of supplying current per the battery charging specification, the hub can
be configured to indicate the presence of such a supply from the device. This indication, via the PRT_CTLx pins, is on
a per port basis. For example, the OEM can configure two ports to support battery charging through high current power
FETs and leave the other two ports as standard USB ports.
The port control signals are assigned to programmable pins (PFx) and therefore the device must be programmed into
specific configurations to enable the signals. Refer to Section 3.3.4, PF[31:4] Configuration (CFG_STRAP[2:1]) for addi-
tional information.
For detailed information on utilizing the battery charging feature, refer to the application note “USB Battery Chargi ng
with Microchip USB7002 and USB705x Hubs”, which can be found on the Microchip USB7002 product page www.micro-
chip.com/USB7002.
FIGURE 8-1: BATTERY CHARGING EXTERNAL POWER SUPPLY
SOC
VBUS[n]
PRT_CTLx
INT
SCL
SDA
Microchip
Hub
DC Power
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USB7002
8.2 Port Power Control
Port power and over-current sense share the same pin (PRT_CTLx) for each port. These functions can be controlled
directly from the USB hub, or via the processor.
8.2.1 PORT POWER CONTROL USING USB POWER SWITCH
When operating in combined mode, the device will have one port power control and over-current sense pin for each
downstream port. When disabling port power, the driver will actively drive a '0'. To avoid unnecessary power dissipation,
the pull-up resistor will be disabled at that time. When port power is enabled, it will disable the output driver and enable
the pull-up resistor, making it an open drain output. If there is an over-current situation, the USB Power Switch will assert
the open drain OCS signal. The Schmidt trigger input will recognize that as a low. The open drain output does not inter-
fere. The over-current sense filter handles the transient conditions such as low voltage while the device is powering up.
Note: The PRT_CTLx function is assigned to programmable function pins (PFx) via configuration straps. Refer
to Section 3.3.4, PF[31:4] Configuration (CFG_STRAP[2:1]) for additional information.
FIGURE 8-2: PORT POWER CONTROL WITH USB POWER SWITCH
USB Power
Switch
50k
PRTPWR
EN
OCS
OCS
Pull‐UpEnable
5V
USB
Device
FILTER
PRT_CTLx
USB7002
DS00002670D-page 36 2018-2019 Microchip Technology Inc.
8.2.1.1 Port Power Control Using Poly Fuse
When using the device with a poly fuse, there is no need for an output power control. A single port power control and
over-current sense for each downstream port is still used from the Hub's perspective. When disabling port power, the
driver will actively drive a '0'. This will have no effect as the external diode will isolate pin from the load. When port power
is enabled, it will disable the output driver and enable the pull-up resistor. This means that the pull-up resistor is providing
3.3 volts to the anode of the diode. If there is an over-current situation, the poly fuse will open. This will cause the cath-
ode of the diode to go to 0 volts. The anode of the diode will be at 0.7 volts, and the Schmidt trigger input will register
this as a low resulting in an over-current detection. The open drain output does not interfere.
8.3 CC Pin Orientation and Detection
The device provides CC1 and CC2 pins on all Type-C ports for cable plug orientation and detection of a USB Type-C
receptacle. The device also integrates a comparator and DAC circuit to implement Type-C attach and detach functions,
which supports up to eight programmable thresholds for attach detection between a UFP and DFP. When operating as
a UFP, the device supports detecting changes in the DFP’s advertised thresholds. Default nominal values for the thresh-
olds detected by the CC comparator are:
•0.20V
•0.40V
•0.66V
•0.80V
•1.23V
•1.60V
•2.60V
When operating as a DFP, the device implements current sources to advertise current charging capabilities on both CC
pins. When a UFP connection is established, the current driven across the CC pins creates a voltage across the UFP’s
Rd pull-down that can be detected by the integrated CC comparator. When connected to an active cable, an alternative
pull-down, Ra, appears on the CC pin.
When operating as a UFP, the device applies an Rd pull-down on both CC lines and waits for a DFP connection from
the assertion of VBUS. The CC comparator is used to determine the advertised current charger capabilities supported
by the DFP.
FIGURE 8-3: PORT POWER CONTROL USING A POLY FUSE
PRT_CTLx
50k
PRTPWR
OCS
USB
Device
Pull-Up Enable
5V
Poly Fuse
FILTER
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USB7002
VCONN is a 5V supply used to power circuitry in the USB Type-C plug that is required to implement Electronically
Marked Cables. By default the DFP always sources VCONN when connected to an active cable. The USB7002 requires
the use of two external VCONN FETs. The device provides the enables for these FETs, and can detect an OCS by mon-
itoring the output voltage of the FET via the CC pins.
The device also implements a comparator for determining when a VBUS is within a programmed range, vSafe5V or
vSafe0V. VBUS is divided down externally to provide a nominal 3.3V at the VBUS_MON pin. For a DFP, the VBUS com-
parator is useful to detect when VBUS is within the desired range per power delivery negotiations. For a UFP, the VBUS
comparator is utilized to determine when a DFP is attached or detached. It may also use the comparator to determine
when VBUS is within a new voltage range per power delivery negotiations.
8.4 FlexConnect
The device allows the upstream port to be swapped with any downstream port, enabling any USB port to assume the
role of USB host at any time during hub operation. This host role exchange feature is called FlexConnect. Additionally,
the USB 2.0 ports can be flexed independently of the USB 3.1 ports.
This functionality can be used in two primary ways:
1. Host Swapping: This functionality can be achieved through a hub wherein a host and device can agree to swap
the host/device relationship; The host becomes a device, and the device becomes a host.
2. Host Sharing: A USB ecosystem can be shared between multiple hosts. Note that only 1 host may access to
the USB tree at a time.
FlexConnect can be enabled through any of the following three methods:
•I2C Control: The embedded I2C slave can be used to control the state of the FlexConnect feature through basic
write/read operations.
•USB Command: FlexConnect can be initiated via a special USB command directed to the hub’s internal Hub
Feature Controller device.
•Direct Pin Control: Any available GPIO pin on the hub can be assigned the role of a FlexConnect control pin.
For detailed information on utilizing the FlexConnect feature, refer to the application note “USB7002/USB705x FlexCon-
nect Operation”, which can be found on the Microchip USB7002 product page at www.microchip.com/USB7002.
8.5 Multi-Host Endpoint Reflector
The internal Multi-Host Endpoint Reflector allows for smart-phone automotive mode sessions to be entered on the
downstream ports. The device supports the Multi-Host Endpoint Reflector on downstream ports.
The Multi-Host Endpoint Reflector uses standard Network Control Model (NCM) device protocol, which is a sub-class
of Communication Device Class (CDC) group of protocols. Standard NCM USB drivers may be utilized; No custom driv-
ers are required.
A Multi-Host Endpoint Reflector session may be entered on only 1 downstream port at a time. Entry into Multi-Host mode
is initiated via a no data Control USB transfer addressed to the internal Multi-Host Endpoint Reflector device in the hub.
The USB7002 has two internal USB devices. The Multi-Host Endpoint Reflector is a Composite WinUSB and NCM
device. The Hub Feature Controller is a WinUSB device which enables the USB bridging functions.
The hub ports which are connected to both the Multi-Host Endpoint Reflector and Hub Feature Controller are both con-
figured as non-removable.
For detailed information on utilizing the multi-host endpoint reflector feature, refer to the application note “USB7002/
USB705x Multi-Host Endpoint Reflector Operation”, which can be found on the Microchip USB7002 product page at
www.microchip.com/USB7002.
Note: The native USB Type-C functionality (including CC pin orientation and detection features) is managed
autonomously by the USB7002.
USB7002
DS00002670D-page 38 2018-2019 Microchip Technology Inc.
8.6 USB to GPIO Bridging
The USB to GPIO bridging feature provides system designers expanded system control and potential BOM reduction.
General Purpose Input/Outputs (GPIOs) may be used for any general 3.3V level digital control and input functions.
Commands may be sent from the USB Host to the internal Hub Feature Controller device in the Microchip hub to per-
form the following functions:
• Set the direction of the GPIO (input or output)
• Enable a pull-up resistor
• Enable a pull-down resistor
• Read the state
• Set the state
For detailed information on utilizing the USB to GPIO bridging feature, refer to the application note “USB to GPIO Bridg-
ing with Microchip USB7002 and USB705x Hubs”, which can be found on the Microchip USB7002 product page at
www.microchip.com/USB7002.
8.7 USB to I2C Bridging
The USB to I2C bridging feature provides system designers expanded system control and potential BOM reduction. The
use of a separate USB to I2C device is no longer required and a downstream USB port is not lost, as occurs when a
standalone USB to I2C device is implemented.
Commands may be sent from the USB Host to the internal Hub Feature Controller device in the Microchip hub to per-
form the following functions:
•Configure I
2C Pass-Through Interface
•I
2C Write
•I
2C Read
For detailed information on utilizing the USB to I2C bridging feature, refer to the application note “USB to I2C Bridging
with Microchip USB7002 and USB705x Hubs”, which can be found on the Microchip USB7002 product page at
www.microchip.com/USB7002.
8.8 USB to SPI Bridging
The USB to SPI bridging feature provides system designers expanded system control and potential BOM reduction. The
use of a separate USB to SPI device is no longer required and a downstream USB port is not lost, as occurs when a
standalone USB to SPI device is implemented.
Commands may be sent from the USB Host to the internal Hub Feature Controller device in the Microchip hub to per-
form the following functions:
• Enable SPI Pass-Through Interface
• SPI Write/Read
• Disable SPI Pass-Through Interface
For detailed information on utilizing the USB to SPI bridging feature, refer to the application note “USB to SPI Bridging
with Microchip USB7002 and USB705x Hubs”, which can be found on the Microchip USB7002 product page at
www.microchip.com/USB7002.
8.9 USB to UART Bridging
The USB to UART bridging feature provides system designers with expanded system control and potential BOM reduc-
tion. When using Microchip’s USB hubs, a separate USB to UART device is no longer required and a downstream USB
port is not lost, as occurs when a standalone USB to UART device is implemented.
Commands may be sent from the USB Host to the internal Hub Feature Controller device in the Microchip hub to per-
form the following functions:
• Enable/Disable UART Interface
• Set UART Interface Baud Rate
•UART Write
•UART Read
2018-2019 Microchip Technology Inc. DS00002670D-page 39
USB7002
For detailed information on utilizing the USB to UART bridging feature, refer to the application note “USB to UART Bridg-
ing with Microchip USB7002 and USB705x Hubs”, which can be found on the Microchip USB7002 product page at
www.microchip.com/USB7002.
8.10 Link Power Management (LPM)
The device supports the L0 (On), L1 (Sleep), and L2 (Suspend) link power management states. These supported LPM
states offer low transitional latencies in the tens of microseconds versus the much longer latencies of the traditional USB
suspend/resume in the tens of milliseconds. The supported LPM states are detailed in Tab l e 8 - 1.
8.11 Resets
The device includes the following chip-level reset sources:
•Power-On Reset (POR)
•External Chip Reset (RESET_N)
•USB Bus Reset
8.11.1 POWER-ON RESET (POR)
A power-on reset occurs whenever power is initially supplied to the device, or if power is removed and reapplied to the
device. A timer within the device will assert the internal reset per the specifications listed in Section 9.6.2, Power-On
and Configuration Strap Timing.
8.11.2 EXTERNAL CHIP RESET (RESET_N)
A valid hardware reset is defined as assertion of RESET_N, after all power supplies are within operating range, per the
specifications in Section 9.6.3, Reset and Configuration Strap Timing. While reset is asserted, the device (and its asso-
ciated external circuitry) enters Standby Mode and consumes minimal current.
Assertion of RESET_N causes the following:
1. The PHY is disabled and the differential pairs will be in a high-impedance state.
2. All transactions immediately terminate; no states are saved.
3. All internal registers return to the default state.
4. The external crystal oscillator is halted.
5. The PLL is halted.
8.11.3 USB BUS RESET
In response to the upstream port signaling a reset to the device, the device performs the following:
1. Sets default address to 0.
2. Sets configuration to Unconfigured.
3. Moves device from suspended to active (if suspended).
4. Complies with the USB Specification for behavior after completion of a reset sequence.
The host then configures the device in accordance with the USB Specification.
TABLE 8-1: LPM STATE DEFINITIONS
State Description Entry/Exit Time to L0
L2 Suspend Entry: ~3 ms
Exit: ~2 ms (from start of RESUME)
L1 Sleep Entry: <10 us
Exit: <50 us
L0 Fully Enabled (On) -
Note: All power supplies must have reached the operating levels mandated in Section 9.2, Operating Condi-
tions**, prior to (or coincident with) the assertion of RESET_N.
Note: The device does not propagate the upstream USB reset to downstream devices.
USB7002
DS00002670D-page 40 2018-2019 Microchip Technology Inc.
9.0 OPERATIONAL CHARACTERISTICS
9.1 Absolute Maximum Ratings*
+1.2 V Supply Voltage (VDD12) (Note 1) ...............................................................................................-0.5 V to +1.32 V
+3.3 V Supply Voltage (VDD33) (Note 1) ................................................................................................. -0.5 V to +4.6 V
Positive voltage on input signal pins, with respect to ground (Note 2)................................................................... +4.6 V
Negative voltage on input signal pins, with respect to ground ................................................................................ -0.5 V
Positive voltage on XTALI/CLK_IN, with respect to ground................................................................................+3.63 V
Positive voltage on USB DP/DM signal pins, with respect to ground......................................................................+6.0 V
Positive voltage on USB 3.1 Gen 1 USB3UP_xxxx and USB3DN_xxxx signal pins, with respect to ground..........1.32 V
Storage Temperature.............................................................................................................................. -55oC to +150oC
Junction Temperature............................................................................................................................................+125oC
Lead Temperature Range............................................................................................Refer to JEDEC Spec. J-STD-020
HBM ESD Performance ........................................................................................................................................ +/-3 kV
1: When powering this device from laboratory or system power supplies, it is important that the absolute max-
imum ratings not be exceeded or device failure can result. Some power supplies exhibit voltage spikes on
their outputs when AC power is switched on or off. In addition, voltage transients on the AC power line may
appear on the DC output. If this possibility exists, it is suggested that a clamp circuit be used.
2: This rating does not apply to the following pins: All USB DM/DP pins, XTAL1/CLK_IN, and XTALO
*Stresses exceeding those listed in this section could cause permanent damage to the device. This is a stress rating
only. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Functional
operation of the device at any condition exceeding those indicated in Section 9.2, Operating Conditions**, Section 9.5,
DC Specifications, or any other applicable section of this specification is not implied.
9.2 Operating Conditions**
+1.2 V Supply Voltage (VDD12) .......................................................................................................... +1.08 V to +1.32 V
+3.3 V Supply Voltage (VDD33) .............................................................................................................. +3.0 V to +3.6 V
Input Signal Pins Voltage (Note 2) ...........................................................................................................-0.3 V to +3.6 V
XTALI/CLK_IN Voltage...........................................................................................................................-0.3 V to +3.6 V
USB 2.0 DP/DM Signal Pins Voltage ....................................................................................................... -0.3 V to +5.5 V
USB 3.1 Gen 1 USB3UP_xxxx and USB3DN_xxxx Signal Pins Voltage ...............................................-0.3 V to +1.32 V
Ambient Operating Temperature in Still Air (TA) ..................................................................................................... Note 3
+1.2 V Supply Voltage Rise Time (TRT in Figure 9-1) ............................................................................................ 400 µs
+3.3 V Supply Voltage Rise Time (TRT in Figure 9-1) ............................................................................................ 400 µs
3: 0oC to +70oC for commercial version, -40oC to +85oC for industrial version.
**Proper operation of the device is ensured only within the ranges specified in this section.
Note: Do not drive input signals without power supplied to the device.
2018-2019 Microchip Technology Inc. DS00002670D-page 41
USB7002
9.3 Package Thermal Specifications
FIGURE 9-1: SUPPLY RISE TIME MODEL
TABLE 9-1: PACKAGE THERMAL PARAMETERS
Symbol °C/W Velocity (Meters/s)
JA 19 0
16 1
JT 0.1 0
0.1 1
JC 1.3 0
1.3 1
Note: Thermal parameters are measured or estimated for devices in a multi-layer 2S2P PCB per JESDN51. For
industrial applications, the USB7002 requires multi-layer 2S4P PCB power dissipation.
t10%
10%
90%
Voltage TRT
t90% Time
100%
3.3 V
VSS
VDD33
90%
100%
1.2 V
VDD12
USB7002
DS00002670D-page 42 2018-2019 Microchip Technology Inc.
9.4 Power Consumption
This section details the power consumption of the device as measured during various modes of operation. Power dis-
sipation is determined by temperature, supply voltage, and external source/sink requirements.
TABLE 9-2: DEVICE POWER CONSUMPTION
Typical (mA) Typical Power
VDD12 VDD33 (mW)
Global Suspend 10 11 48.3
No VBUS 9 11 47.1
Reset/Standby 3 0 5
Idle 63 20 140
Active Idle 447 62 741
SuperSpeed Active Operation
2 SuperSpeed Active Ports 465 56 743
1 SuperSpeed Active Port 358 44 576
Hi-Speed Active Operation
4 Hi-Speed Active Ports 67 49 241
3 Hi-Speed Active Ports 66 41 215
2 Hi-Speed Active Ports 64 32 181
1 Hi-Speed Active Port 63 28 168
Full-Speed Active Operation
4 Full-Speed Active Ports 62 31 178
3 Full-Speed Active Ports 62 30 174
2 Full-Speed Active Ports 62 30 173
1 Full-Speed Active Port 62 29 172
Mixed SuperSpeed / Hi-Speed Active Operation
2 SS / 2 HS Active Ports 440 64 738
2018-2019 Microchip Technology Inc. DS00002670D-page 43
USB7002
9.5 DC Specifications
4: 0.42V for interface using open drain with pull-ups to voltages up to 2.1V, 0.34V for interface using open drain
with pull-ups to voltages greater than 2.1V.
5: XTALI can optionally be driven from a 25 MHz singled-ended clock oscillator.
6: Refer to the USB 3.1 Gen 1 Specification for USB DC electrical characteristics.
TABLE 9-3: I/O DC ELECTRICAL CHARACTERISTICS
Parameter Symbol Min Typical Max Units Notes
I Type Input Buffer
Low Input Level
High Input Level
VIL
VIH 1.25
Note 4 V
V
IS Type Input Buffer
Low Input Level
High Input Level
Schmitt Trigger Hysteresis
(VIHT - VILT)
VIL
VIH
VHYS
1.25
100 160
Note 4
240
V
V
mV
O12 Type Output Buffer
Low Output Level
High Output Level
VOL
VOH VDD33-0.4
0.4 V
V
IOL = 12 mA
IOH = -12 mA
OD12 Type Output Buffer
Low Output Level VOL 0.4 V IOL = 12 mA
ICLK Type Input Buffer
(XTALI Input)
Low Input Level
High Input Level
VIL
VIH 0.9
0.35
1.2
V
V
Note 5
IO-U Type Buffer
(See Note 6)Note 6
USB7002
DS00002670D-page 44 2018-2019 Microchip Technology Inc.
9.6 AC Specifications
This section details the various AC timing specifications of the device.
9.6.1 POWER SUPPLY AND RESET_N SEQUENCE TIMING
Figure 9-2 illustrates the recommended power supply sequencing and timing for the device. VDD33 should rise after or
at the same rate as VDD12. Similarly, RESET_N and/or VBUS_DET should rise after or at the same rate as VDD33.
VBUS_DET and RESET_N do not have any other timing dependencies.
9.6.2 POWER-ON AND CONFIGURATION STRAP TIMING
Figure 9-3 illustrates the configuration strap valid timing requirements in relation to power-on, for applications where
RESET_N is not used at power-on. In order for valid configuration strap values to be read at power-on, the following
timing requirements must be met. The operational levels (Vopp) for the external power supplies are detailed in
Section 9.2, Operating Conditions**.
Device configuration straps are also latched as a result of RESET_N assertion. Refer to Section 9.6.3, Reset and Con-
figuration Strap Timing for additional details.
FIGURE 9-2: POWER SUPPLY AND RESET_N SEQU ENCE TIMING
TABLE 9-4: POWER SUPPLY AND RESET_N SEQUENCE TIMING
Symbol Description Min Typ Max Units
tVDD33 VDD12 to VDD33 rise time 0 ms
treset VDD33 to RESET_N/VBUS_DET rise time 0 ms
FIGURE 9-3: POWER-ON CONFIGURATION STRAP VALID TIMING
TABLE 9-5: POWER-ON CONFIGURATION STRAP LATCHING TIMING
Symbol Description Min Typ Max Units
tcsh Configuration strap hold after external power supplies at opera-
tional levels
1ms
VDD12
tVDD33
VDD33
RESET_N/
VBUS_DET
treset
All External
Power Supplies
Vopp
Configuration
Straps
tcsh
2018-2019 Microchip Technology Inc. DS00002670D-page 45
USB7002
9.6.3 RESET AND CONFIGURATION STRAP TIMING
Figure 9-4 illustrates the RESET_N pin timing requirements and its relation to the configuration strap pins. Assertion of
RESET_N is not a requirement. However, if used, it must be asserted for the minimum period specified. Refer to
Section 8.11, Resets for additional information on resets. Refer to Section 3.3, Configuration Straps and Programmable
Functions for additional information on configuration straps.
9.6.4 USB TIMING
All device USB signals conform to the voltage, power, and timing characteristics/specifications as set forth in the Uni-
versal Serial Bus Specification. Please refer to the Universal Seria l Bus Revision 3.1 Specification, available at http://
www.usb.org/developers/docs.
9.6.5 SMBUS TIMING
All device SMBus signals conform to the voltage, power, and timing characteristics/specifications as set forth in the Sys-
tem Management Bus Specification. Please refer to the System Management Bus Specification, Version 1.0, available
at http://smbus.org/specs.
9.6.6 I2C TIMING
All device I2C signals conform to the 100KHz Standard-mode (Sm) and 400KHz Fast Mode (Fm) voltage, power, and
timing characteristics/specifications as set forth in the I2C-Bus Specification. Please refer to the I2C-Bus Specification,
available at http://www.nxp.com/documents/user_manual/UM10204.pdf.
9.6.7 I2S TIMING
All device I2S signals conform to the voltage, power, and timing characteristics/specifications as set forth in the I2S-Bus
Specification. Please refer to the I2S-Bus Specification, available at http://www.nxp.com/acrobat_download/various/
I2SBUS.pdf.
FIGURE 9-4: RESET_N CONFIGURATION STRAP TIMING
TABLE 9-6: RESET_N CONFIGURATION STRAP TIMING
Symbol Description Min Typ Max Units
trstia RESET_N input assertion time 5 s
tcsh Configuration strap pins hold after RESET_N deassertion 1 ms
Note: The clock input must be stable prior to RESET_N deassertion.
Configuration strap latching and output drive timings shown assume that the Power-On reset has finished
first otherwise the timings in Section 9.6.2, Power-On and Configuration Strap Timing apply.
RESET_N
Configuration
Straps
trstia
tcsh
USB7002
DS00002670D-page 46 2018-2019 Microchip Technology Inc.
9.6.8 SPI/SQI MASTER TIMING
This section specifies the SPI/SQI master timing requirements for the device.
FIGURE 9-5: SPI/SQI MASTER TIMING
TABLE 9-7: SPI/SQI MASTER TIMING (30 MHZ OPERATION)
Symbol Description Min Typ Max Units
tfc Clock frequency 30 MHz
tceh Chip enable (SPI_CE_N) high time 100 ns
tclq Clock to input data 13 ns
tdh Input data hold time 0 ns
tos Output setup time 5 ns
toh Output hold time 5 ns
tov Clock to output valid 4 ns
tcel Chip enable (SPI_CE_N) low to first clock 12 ns
tceh Last clock to chip enable (SPI_CE_N) high 12 ns
TABLE 9-8: SPI/SQI MASTER TIMING (60 MHZ OPERATION)
Symbol Description Min Typ Max Units
tfc Clock frequency 60 MHz
tceh Chip enable (SPI_CE_N) high time 50 ns
tclq Clock to input data 9 ns
tdh Input data hold time 0 ns
tos Output setup time 5 ns
toh Output hold time 5 ns
tov Clock to output valid 4 ns
tcel Chip enable (SPI_CE_N) low to first clock 12 ns
tceh Last clock to chip enable (SPI_CE_N) high 12 ns
SPI_CLK
SPI_D[3:0] (in)
SPI _D[3:0] (out)
SPI_CE_N
tcel tfc
Output
data valid
tclq
tceh
tdh
toh
tos tov toh
Output
data valid
Input
data valid
tceh
2018-2019 Microchip Technology Inc. DS00002670D-page 47
USB7002
9.7 Clock Specifications
The device can accept either a 25MHz crystal or a 25MHz single-ended clock oscillator input. If the single-ended clock
oscillator method is implemented, XTALO should be left unconnected and XTALI/CLK_IN should be driven with a
nominal 0-3.3V clock signal. The input clock duty cycle is 40% minimum, 50% typical and 60% maximum.
It is recommended that a crystal utilizing matching parallel load capacitors be used for the crystal input/output signals
(XTALI/XTALO). The following circuit design (Figure 9-6) and specifications (Ta b le 9- 9 ) are required to ensure proper
operation.
FIGURE 9-6: 25MHZ CR YSTAL CIRCUIT
USB7002
XTALO
XTALI
Y1
C1C2
USB7002
DS00002670D-page 48 2018-2019 Microchip Technology Inc.
9.7.1 CRYSTAL SPECIFICATIONS
It is recommended that a crystal utilizing matching parallel load capacitors be used for the crystal input/output signals
(XTALI/XTALO). Refer to Table 9-9 for the recommended crystal specifications.
7: Frequency Deviation Over Time is also referred to as Aging.
8: 0 °C for commercial version, -40 °C for industrial version.
9: +70 °C for commercial version, +85 °C for industrial version.
10: This number includes the pad, the bond wire and the lead frame. PCB capacitance is not included in this
value. The XTALI/CLK_IN pin, XTALO pin and PCB capacitance values are required to accurately calcu-
late the value of the two external load capacitors. These two external load capacitors determine the accu-
racy of the 25.000 MHz frequency.
9.7.2 EXTERNAL REFERENCE CLOCK (CLK_IN)
When using an external reference clock, the following input clock specifications are suggested:
•25MHz
• 50% duty cycle ±10%, ±100 ppm
• Jitter < 100 ps RMS
TABLE 9-9: CRYSTAL SPECIFICATIONS
Parameter Symbol Min Nom Max Units Notes
Crystal Cut AT, typ
Crystal Oscillation Mode Fundamental Mode
Crystal Calibration Mode Parallel Resonant Mode
Frequency Ffund - 25.000 - MHz
Frequency Tolerance @ 25oCF
tol - - ±50 PPM
Frequency Stability Over Temp Ftemp - - ±50 PPM
Frequency Deviation Over Time Fage - ±3 to 5 - PPM Note 7
Total Allowable PPM Budget - - ±100 PPM
Shunt Capacitance CO- 7 typ - pF
Load Capacitance CL- 20 typ - pF
Drive Level PW100 - - uW
Equivalent Series Resistance R1--60Ω
Operating Temperature Range Note 8 -Note 9 oC
XTALI/CLK_IN Pin Capacitance - 3 typ - pF Note 10
XTALO Pin Capacitance - 3 typ - pF Note 10
2018-2019 Microchip Technology Inc. DS00002670D-page 49
USB7002
10.0 PACKAGE OUTLINE
Note: For the most current package drawings, see the Microchip Packaging Specification at:
http://www.microchip.com/packaging.
FIGURE 10-1: 100-VQFN PACKAGE (DRAWING)
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USB7002
DS00002670D-page 50 2018-2019 Microchip Technology Inc.
Note: For the most current package drawings, see the Microchip Packaging Specification at:
http://www.microchip.com/packaging.
FIGURE 10-2: 100-VQFN PACKAGE (DIMENSIONS)
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Notes:
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3DFNDJHLVVDZVLQJXODWHG
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2018-2019 Microchip Technology Inc. DS00002670D-page 51
USB7002
Note: For the most current package drawings, see the Microchip Packaging Specification at:
http://www.microchip.com/packaging.
FIGURE 10-3: 100-VQFN PACKAGE (LAND-PATTERN)
RECOMMENDED LAND PATTERN
Dimension Limits
Units
C2
Optional Center Pad Width
Contact Pad Spacing
Optional Center Pad Length
Contact Pitch
Y2
X2
8.10
8.10
MILLIMETERS
0.40 BSC
MIN
E
MAX
11.70
Contact Pad Length (X100)
Contact Pad Width (X100)
Y1
X1
1.05
0.20
Microchip Technology Drawing C04-2407A
NOM
SILK SCREEN
12
100
C1
C2
E
X1
Y1
G1
Y2
X2
C1Contact Pad Spacing 11.70
Contact Pad to Center Pad (X100) G1 0.20
Thermal Via Diameter V
Thermal Via Pitch EV
0.33
1.20
ØV
EV
EV
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Notes:
Dimensioning and tolerancing per ASME Y14.5M
For best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss during
reflow process
1.
2.
USB7002
DS00002670D-page 52 2018-2019 Microchip Technology Inc.
APPENDIX A: REVISION HIST OR Y
TABLE A-1: REVISION HISTOR Y
Revision Level & Date Section/Figure/Entry Correction
DS00002670D (08-09-19) Section 2.1, General Description
Document Title
Key Benefits on cover
• Updated last sentence of the first para-
graph for greater clarity.
• Title modified changing “Controller” to
“PD Smart”
• “USB Power Delivery Billboard Device
Support” bullet removed
Cover Added TID data
Tabl e 3 - 5 , Table 3-6 • Changed PF15 from PRT_CTL3 to
PRT_CTL2
• Changed PF16 from PRT_CTL2 to
PRT_CTL3
• Updated programmable functions
descriptions table to match new assigned
PRT_CTLx and PRT_CTLx_U3 numbers.
Section 3.4, Physical and Logical Port
Mapping
Added new section with physical and logical
port mapping.
Figure 2-1 Updated internal PHY numbering to match
physical port numbering detailed in new
Section 3.4, Physical and Logical Port Map-
ping.
Figure 4-3, SMBus/I2C Connections Updated suggested nominal external resistor
values. Added note under figure: “Resistor
values detailed in Figure 4-3 are suggestions.
Optimal pull-up values may vary dependent
on external factors.”
Section 5.1.5, SMBus Check Stage
(SMBUS_CHECK)
Updated second sentence: “If pull-ups are
detected on both pins...”
DS00002670C (02-20-19) All Public Release
DS00002670B (09-07-18) All Initial Release
2018-2019 Microchip Technology Inc. DS00002670D-page 53
USB7002
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO. [X] XXX
PackageTemperature
Range
Device
Device: USB7002
Tape and Reel
Option: Blank = Standard packaging (tray)
T = Tape and Reel (Note 1)
Temperature
Range: Blank = 0C to +70C (Commercial)
I= -40C to +85C (Industrial/Automotive Grade 3)
Package: KDX = 100-pin VQFN
Automotive Code: Vxx = 3 character code with “V” prefix,
specifying automotive product.
Examples:
a) USB7002/KDX
Tray, 0°C to +70°C, 100-pin VQFN
b) USB7002T/KDX
Tape & reel, 0°C to +70°C, 100-pin VQFN
c) USB7002-I/KDX
Tray, -40°C to +85°C, 100-pin VQFN
d) USB7002T-I/KDX
Tape & reel, -40°C to +85°C, 100-pin VQFN
e) USB7002-I/KDXVAO
Tray, -40°C to +85°C, Automotive Grade 3,
100-pin VQFN
f) USB7002T-I/KDXVAO
Tape & reel, -40°C to +85°C, Automotive Grade 3,
100-pin VQFN
Note 1: Tape and Reel identifier only appears in
the catalog part number description. This
identifier is used for ordering purposes and
is not printed on the device package.
Check with your Microchip Sales Office
for package availability with the Tape and
Reel option.
[X](1)
Tape and Reel
Option
-
/
XXX
Automotive
Code
USB7002
DS00002670D-page 54 2018-2019 Microchip Technology Inc.
THE MICROCHIP WEB SITE
Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make
files and information easily available to customers. Accessible by using your favorite Internet browser, the web site con-
tains the following information:
•Product Support – Data sheets and errata, application notes and sample programs, design resources, user’s
guides and hardware support documents, latest software releases and archived software
•General Technical Support – Frequently Asked Questions (FAQ), technical support requests, online discussion
groups, Microchip consultant program member listing
•Business of Micr oc hip – Product selector and ordering guides, latest Microchip press releases, listing of semi-
nars and events, listings of Microchip sales offices, distributors and factory representatives
CUSTOMER CHANGE NOTIFICATION SERVICE
Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive
e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or
development tool of interest.
To register, access the Microchip web site at www.microchip.com. Under “Support”, click on “Customer Change Notifi-
cation” and follow the registration instructions.
CUSTOMER SUPPORT
Users of Microchip products can receive assistance through several channels:
• Distributor or Representative
• Local Sales Office
• Field Application Engineer (FAE)
• Technical Support
Customers should contact their distributor, representative or Field Application Engineer (FAE) for support. Local sales
offices are also available to help customers. A listing of sales offices and locations is included in the back of this docu-
ment.
Technical support is available through the web site at: http://microchip.com/support
2018-2019 Microchip Technology Inc. DS00002670D-page 55
USB7002
Information contained in this publication regarding device applications and the like is provided only for your convenience and may be
superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO
REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE,
MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Micro-
chip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold
harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or
otherwise, under any Microchip intellectual property rights unless otherwise stated.
Trademarks
The Microchip name and logo, the Microchip logo, Adaptec, AnyRate, AVR, AVR logo, AVR Freaks, BesTime, BitCloud, chipKIT, chipKIT logo,
CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR, HELDO, IGLOO, JukeBlox, KeeLoq, Kleer, LANCheck, LinkMD, maXStylus, maXTouch,
MediaLB, megaAVR, Microsemi, Microsemi logo, MOST, MOST logo, MPLAB, OptoLyzer, PackeTime, PIC, picoPower, PICSTART, PIC32 logo,
PolarFire, Prochip Designer, QTouch, SAM-BA, SenGenuity, SpyNIC, SST, SST Logo, SuperFlash, Symmetricom, SyncServer, Tachyon,
TempTrackr, TimeSource, tinyAVR, UNI/O, Vectron, and XMEGA are registered trademarks of Microchip Technology Incorporated in the U.S.A. and
other countries.
APT, ClockWorks, The Embedded Control Solutions Company, EtherSynch, FlashTec, Hyper Speed Control, HyperLight Load, IntelliMOS, Libero,
motorBench, mTouch, Powermite 3, Precision Edge, ProASIC, ProASIC Plus, ProASIC Plus logo, Quiet-Wire, SmartFusion, SyncWorld, Te m u x ,
TimeCesium, TimeHub, TimePictra, TimeProvider, Vite, WinPath, and ZL are registered trademarks of Microchip Technology Incorporated in the
U.S.A.
Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BlueSky, BodyCom, CodeGuard,
CryptoAuthentication, CryptoAutomotive, CryptoCompanion, CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM,
ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP, INICnet, Inter-Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, memBrain,
Mindi, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net,
PICkit, PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE, Ripple Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI, SuperSwitcher,
SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.
The Adaptec logo, Frequency on Demand, Silicon Storage Technology, and Symmcom are registered trademarks of Microchip Technology Inc. in
other countries.
GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other
countries.
All other trademarks mentioned herein are property of their respective companies.
© 2018-2019, Microchip Technology Incorporated, All Rights Reserved.
ISBN: 9781522448501
Note the following deta ils of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
For information regarding Microchip’s Quality Managemen t Systems,
please visit www.microchip.com/quality.
2018-2019 Microchip Technology Inc. DS00002670D-page 56
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