5-8
File Number
2220.3
CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures.
http://www.intersil.com or 407-727-9207 |Copyright © Intersil Corporation 1999
IRF9130
-12A, -100V, 0.30 Ohm, P-Channel Power
MOSFET
These are P-Channel enhancement mode silicon gate
power field effect transistors. They are advanced power
MOSFETs designed, tested, and guaranteed to withstand a
specified level of energy in the breakdown avalanche mode
of operation. All of these power MOSFETs are designed for
applications such as switching regulators, switching
convertors, motor drivers, relay drivers, and drivers for high
power bipolar switching transistors requiring high speed and
low gate drive power. They can be operated directly from
integrated circuits.
Formerly developmental type TA17511.
Features
• -12A, -100V
•r
DS(ON) = 0.30Ω
• Single Pulse Avalanche Energy Rated
• SOA is Power Dissipation Limited
• Nanosecond Switching Speeds
• Linear Transfer Characteristics
• High Input Impedance
Symbol
Packaging
JEDEC TO-204AA
Ordering Information
PART NUMBER PACKAGE BRAND
IRF9130 TO-204AA IRF9130
NOTE: When ordering, use the entire part number.
G
D
S
DRAIN
(FLANGE)
SOURCE (PIN 2)
GATE (PIN 1)
Data Sheet February 1999
5-9
Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified IRF9130 UNITS
Drain to Source Breakdown Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDS -100 V
Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR -100 V
Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID
TC= 100oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID-12
-7.5 A
A
Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .IDM -48 A
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS ±20 V
Maximum Power Dissipation (Figure 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD75 W
Linear Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.6 W/oC
Single Pulse Avalanche Energy Rating (Note 4). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS 500 mJ
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TJ, TSTG -55 to 150 oC
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TL300 oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operationofthe
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. TJ = 25oC to TJ = 125oC.
Electrical Specifications TC = 25oC, Unless Otherwise Specified
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Drain to Source Breakdown Voltage BVDSS ID = -250µA, VGS = 0V, (Figure 10) -100 - - V
Gate Threshold Voltage VGS(TH) VGS = VDS, ID = -250µA -2 - -4 V
Zero Gate Voltage Drain Current IDSS VDS = Rated BVDSS, VGS = 0V - - -25 µA
VDS = 0.8 x Rated BVDSS, VGS = 0V, TC = 125oC - - 250 µA
On-State Drain Current (Note 2) ID(ON) VDS > ID(ON) x rDS(ON)MAX, VGS = -10V -12 - - A
Gate to Source Leakage Current IGSS VGS = ±20V - - ±100 nA
Drain to Source On Resistance (Note 2) rDS(ON) ID = -6.5A, VGS = -10V, (Figures 8, 9) - 0.25 0.30 Ω
Forward Transconductance (Note 2) gfs VDS > ID(ON) x rDS(ON)MAX, ID = -6.5A
(Figure 12) 2 3.7 - S
Turn-On Delay Time td(ON) VDD = 0.5 x Rated BVDSS, ID≈ -6.5A, RG = 50Ω
RL = 5.7Ω (Figures 17, 18)
MOSFET Switching Times are Essentially
Independent of Operating Temperature
-3060ns
Rise Time tr- 70 140 ns
Turn-Off Delay Time td(OFF) - 70 140 ns
Fall Time tf- 70 140 ns
Total Gate Charge
(Gate to Source + Gate to Drain) Qg(TOT) VGS = -10V, ID = -15A, VDS = 0.8 x Rated BVDSS
Ig(REF) = -1.5mA (Figures 14, 19, 20)
Gate Charge is Essentially Independent of
Operating Temperature
-2545nC
Gate to Source Charge Qgs -13-nC
Gate to Drain “Miller” Charge Qgd -12-nC
Input Capacitance CISS VDS = -25V, VGS = 0V, f = 1MHz
(Figure 11) - 500 - pF
Output Capacitance COSS - 300 - pF
Reverse Transfer Capacitance CRSS - 100 - pF
Internal Drain Inductance LDMeasured Between the
Contact Screw on the
Flange that is Closer to
SourceandGatePinsand
the Center of Die
Modified MOSFET
Symbol Showing the
Internal Devices
Inductances
- 5.0 - nH
Internal Source Inductance LSMeasured From the
Source Lead, 6mm
(0.25in) From the Flange
and the Source
Bonding Pad
- 12.5 - nH
Thermal Resistance Junction to Case RθJC - - 1.67 oC/W
Thermal Resistance Junction to Ambient RθJA Typical Socket Mount - - 30 oC/W
LS
LD
G
D
S
IRF9130
5-10
Source to Drain Diode Specifications
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Continuous Source to Drain Current ISD Modified MOSFET Symbol
Showing the Integral Re-
verse P-N Junction Diode
- - -12 A
Pulse Source to Drain Current
(Note 3) ISDM - - -48 A
Source to Drain Diode Voltage (Note 2) VSD TC = 25oC, ISD = -12A, VGS = 0V (Figure 13) - - -1.5 V
Reverse Recovery Time trr TJ =150oC, ISD = -12A, dISD/dt = 100A/µs - 300 - ns
Reverse Recovery Charge QRR TJ = 150oC, ISD = -12A, dISD/dt = 100A/µs - 1.8 - µC
NOTES:
2. Pulse test: pulse width ≤300µs, duty cycle ≤2%.
3. Repetitive rating: pulse width limited by maximum junction temperature. See Transient Thermal Impedance curve (Figure 3).
4. VDD = 25V, starting TJ= 25oC, L = 5.2mH, RG= 25Ω, peak IAS = 12A. See Figures 15, 16.
G
D
S
Typical Performance Curves
Unless Otherwise Specified
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE
TEMPERATURE FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPERATURE
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
TA, CASE TEMPERATURE (oC)
POWER DISSIPATION MULTIPLIER
00 25 50 75 100 150
0.2
0.4
0.6
0.8
1.0
1.2
125 050 100
ID, DRAIN CURRENT (A)
TC, CASE TEMPERATURE (oC)
150
25 75 125
-12.0
-9.6
-7.2
-4.8
-2.4
t1, RECTANGULAR PULSE DURATION (s)
ZθJC, NORMALIZED TRANSIENT
THERMAL IMPEDANCE (oC/W)
10-3 10-2
1
10-5 10-4
0.01
0.1
10
10-1 1
PDM
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJC x RθJC + TC
t1
t2
SINGLE PULSE
0.1
0.02
0.2
0.5
0.01
0.05
IRF9130
5-11
FIGURE 4. FORWARD BIAS SAFE OPERATING AREA FIGURE 5. OUTPUT CHARACTERISTICS
FIGURE 6. SATURATION CHARACTERISTICS FIGURE 7. TRANSFER CHARACTERISTICS
NOTE: Heating effect of 2µs pulse is minimal.
FIGURE 8. DRAIN TO SOURCE ON RESISTANCE vs GATE
VOLTAGE AND DRAIN CURRENT FIGURE 9. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
Typical Performance Curves
Unless Otherwise Specified (Continued)
VDS, DRAIN TO SOURCE VOLTAGE (V)
10
ID, DRAIN CURRENT (A)
100
1
101
100µs
1ms
10ms
DC
100
SINGLE PULSE
TJ = MAX RATED
TC = 25oC
0.1
OPERATION IN THIS AREA
IS LIMITED BY rDS(ON) 100ms
10µs
ID, DRAIN CURRENT (A)
0 -10 -20 -30 -40
-4
-8
-12
-16
-20
-50
VGS = -10V VGS = -9V
VGS = -8V
VGS = -7V
VGS = -6V
VGS = -5V
VDS, DRAIN TO SOURCE VOLTAGE (V)
VGS = -4V
0
PULSE DURATION = 80µs
0
-2
0-1 -2 -3 -5
-4
-6
ID, DRAIN CURRENT (A)
VDS, DRAIN TO SOURCE VOLTAGE (V)
-8
-4
-10
VGS = -7V
VGS = -10V
VGS = -9V
VGS = -4V
VGS = -5V
VGS = -6V
VGS = -8V
PULSE DURATION = 80µs-20
-16
-12
-8
-4
00 -2-4 -6-8-10
VGS, GATE TO SOURCE VOLTAGE (V)
PULSE DURATION = 80µs
VDS ≥ID(ON) x rDS(ON)MAX
ID(ON), ON-STATE DRAIN CURRENT (A)
TJ = 125oC
TJ = 25oC
TJ = -55oC
0
0.6
-10 -20 -30 -40
rDS(ON), DRAIN TO SOURCE
ID, DRAIN CURRENT (A) -50
0.8
0
0.2
0.4
VGS = -20V
PULSE DURATION = 2µs
VGS = -10V
1.0
ON RESISTANCE (Ω)
NORMALIZED DRAIN TO SOURCE
2.2
1.4
1.0
0.6
0.2 -40 0 40
TJ, JUNCTION TEMPERATURE (oC)
120
1.8
80
VGS = -10V, ID = -4A
ON RESISTANCE
IRF9130
5-12
FIGURE 10. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE FIGURE 11. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
FIGURE 12. TRANSCONDUCTANCE vs DRAIN CURRENT FIGURE 13. SOURCE TO DRAIN DIODE VOLTAGE
FIGURE 14. GATE TO SOURCE VOLTAGE vs GATE CHARGE
Typical Performance Curves
Unless Otherwise Specified (Continued)
1.25
0.95
0.85
0.75
-40 0 40
TJ, JUNCTION TEMPERATURE (oC)
NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE
80 120 160
1.05
1.15
1000
200
00-20 -50
C, CAPACITANCE (pF)
600
VDS, DRAIN TO SOURCE VOLTAGE (V)
800
400
CISS
COSS
CRSS
-10 -30 -40
CISS = CGS + CGD
CRSS = CGD
COSS ≈ CDS + CGD
VGS = 0V, f = 1MHz
ID, DRAIN CURRENT (A)
gfs, TRANSCONDUCTANCE (S)
0 -4 -8 -12 -16
1
2
3
4
5
-20
TJ = 125oC
TJ = 25oC
TJ = -55oC
PULSE DURATION = 80µs
-0.4 -1.0 -1.2 -1.6 -1.8-0.6 VSD, SOURCE TO DRAIN VOLTAGE (V)
-0.8 -1.4
-0.1
-1.0
-10
ISD, SOURCE TO DRAIN CURRENT (A)
-100
TJ = 25oC
TJ = 150oC
0
-5
-10
-15 0 8 16 24 32 40
VDS = -80V
VDS = -50V
VDS = -20V
ID = 15A
Qg(TOT), TOTAL GATE CHARGE (nC)
VGS, GATE TO SOURCE VOLTAGE (V)
IRF9130
5-13
Test Circuits and Waveforms
FIGURE 15. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 16. UNCLAMPED ENERGY WAVEFORMS
FIGURE 17. SWITCHING TIME TEST CIRCUIT FIGURE 18. RESISTIVE SWITCHING WAVEFORMS
FIGURE 19. GATE CHARGE TEST CIRCUIT FIGURE 20. GATE CHARGE WAVEFORMS
tP
0.01Ω
L
IAS
+
-
VDS
VDD
RG
DUT
VARY tP TO OBTAIN
REQUIRED PEAK IAS
0V
VGS
VDD
VDS
BVDSS
tP
IAS
tAV
0
VGS
RL
RG
DUT
+
-VDD
td(ON)
tr
90%
10%
VDS 90%
tf
td(OFF)
tOFF
90%
50%
50%
10%
PULSE WIDTH
VGS
tON
10%
0
0
0.3µF
12V
BATTERY 50kΩ
+VDS
S
DUT
D
G
Ig(REF)
0
(ISOLATED
-VDS
0.2µF
CURRENT
REGULATOR
ID CURRENT
SAMPLING
IG CURRENT
SAMPLING
SUPPLY)
RESISTOR RESISTOR
DUT
Qg(TOT)
Qgd
Qgs
VDS
0
VGS
VDD
0
IG(REF)
IRF9130
5-14
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is gr anted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see w eb site http://www.intersil.com
Sales Office Headquarters
NORTH AMERICA
Intersil Corporation
P. O. Box 883, Mail Stop 53-204
Melbourne, FL 32902
TEL: (407) 724-7000
FAX: (407) 724-7240
EUROPE
Intersil SA
Mercure Center
100, Rue de la Fusee
1130 Brussels, Belgium
TEL: (32) 2.724.2111
FAX: (32) 2.724.22.05
ASIA
Intersil (Taiwan) Ltd.
7F-6, No. 101 Fu Hsing North Road
Taipei, Taiwan
Republic of China
TEL: (886) 2 2716 9310
FAX: (886) 2 2715 3029
IRF9130
