R[7:0]
HS
VS
PCLK
PDB Serializer Deserializer
DE
RGB Display
QVGA to XGA
24-bit color depth
RGB Digital Display Interface
HOST
Graphics
Processor
FPD-Link II
1 Pair / AC Coupled
DS90UR905Q DS90UR906Q
100 STP CableΩ
PASS
V
DDIO
PDB
SCL
SDA
CONFIG [1:0]
RFB
VODSEL
DeEmph
BISTEN BISTEN
LOCK
ID[x]
DAP DAP
CMF
100 nF 100 nF
G[7:0]
B[7:0]
SCL
SDA
ID[x]
R[7:0]
HS
VS
PCLK
DE
G[7:0]
B[7:0]
STRAP pins
not shown
RIN+
RIN-
DOUT+
DOUT-
Optional Optional
(1.8 V or 3.3 V)(1.8 V or 3.3 V) 1.8 V 1.8 V
VDDIO
VDDn VDDn
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Folder
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Design
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
DS90UR905Q-Q1
,
DS90UR906Q-Q1
SNLS313I –SEPTEMBER 2009–REVISED OCTOBER 2019
DS90UR90xQ-Q1 5- to 65-MHz, 24-bit Color FPD-Link II Serializer and Deserializer
1
1 Features
1• 5- to 65-MHz PCLK support (140 Mbps to
1.82 Gbps)
• AC-Coupled STP interconnect cable up to 10
meters
• Integrated terminations on serializer and
deserializer
• At speed link BIST mode and reporting pin
• Optional I2C-compatible serial control bus
• RGB888 + VS, HS, DE support
• Power down mode minimizes power dissipation
• 1.8-V or 3.3-V compatible LVCMOS I/O interface
• Automotive-grade product: AEC-Q100 grade 2
qualified
• >8-kV HBM and ISO 10605 ESD rating
• Backward compatible mode for operation with
older generation devices
•SERIALIZER — DS90UR905Q-Q1
– RGB888 + VS/HS/DE serialized to 1 Pair FPD-
Link II
– Randomizer/scrambler — DC-balanced data
stream
– Selectable output VOD and adjustable de-
emphasis
•DESERIALIZER — DS90UR906Q-Q1
– FAST random data lock; no reference clock
required
– Adjustable input receiver equalization
– LOCK (real time link status) reporting pin
– EMI minimization on output parallel bus
(SSCG)
– Output slew control (OS)
2 Applications
• Automotive display for navigation
• Automotive display for entertainment
3 Description
The DS90UR90xQ-Q1 chipset translates a parallel
RGB video interface into a high-speed serialized
interface over a single pair. This serial bus scheme
makes system design easy by eliminating skew
problems between clock and data, reducing the
number of connector pins, reducing the interconnect
size, weight, cost, and easing overall PCB layout. In
addition, internal DC-balanced decoding is used to
support AC-coupled interconnects.
The DS90UR905Q-Q1 serializer embeds the clock,
balances the data payload, and level shifts the
signals to high-speed, low voltage differential
signaling. Up to 24 inputs are serialized, along with
the three video control signals. This supports full
24-bit color or 18-bit color and 6 general-purpose
signals (for example, Audio I2S applications).
The DS90UR906Q-Q1 deserializer recovers the data
(RGB) and control signals and extracts the clock from
the serial stream. The DS90UR906Q-Q1 is able to
lock to the incoming data stream without the use of a
training sequence or special SYNC patterns and does
not require a reference clock. A link status (LOCK)
output signal is provided.
Device Information(1)
PART NUMBER PACKAGE BODY SIZE (NOM)
DS90UR905Q-Q1 WQFN (48) 7.00 mm × 7.00 mm
DS90UR906Q-Q1 WQFN (60) 9.00 mm × 9.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Application Diagram
2
DS90UR905Q-Q1
,
DS90UR906Q-Q1
SNLS313I –SEPTEMBER 2009–REVISED OCTOBER 2019
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Table of Contents
1 Features.................................................................. 1
2 Applications ........................................................... 1
3 Description............................................................. 1
4 Revision History..................................................... 2
5 Description (continued)......................................... 4
6 Pin Configuration and Functions......................... 5
7 Specifications....................................................... 10
7.1 Absolute Maximum Ratings .................................... 10
7.2 ESD Ratings............................................................ 10
7.3 Recommended Operating Conditions..................... 11
7.4 Thermal Information................................................ 11
7.5 Serializer DC Electrical Characteristics ................. 11
7.6 Deserializer DC Electrical Characteristics ............. 12
7.7 DC and AC Serial Control Bus Characteristics....... 14
7.8 Timing Requirements for DC and AC Serial Control
Bus........................................................................... 14
7.9 Timing Requirements for Serializer PCLK.............. 14
7.10 Timing Requirements for Serial Control Bus ........ 14
7.11 Switching Characteristics: Serializer..................... 15
7.12 Switching Characteristics: Deserializer................. 16
7.13 Typical Characteristics.......................................... 22
8 Detailed Description............................................ 23
8.1 Overview................................................................. 23
8.2 Functional Block Diagrams ..................................... 23
8.3 Feature Description................................................. 24
8.4 Device Functional Modes........................................ 38
8.5 Register Maps......................................................... 39
9 Application and Implementation ........................ 42
9.1 Application Information............................................ 42
9.2 Typical Applications ................................................ 43
10 Power Supply Recommendations ..................... 48
10.1 Power Up Requirements and PDB Pin................. 48
11 Layout................................................................... 48
11.1 Layout Guidelines ................................................. 48
11.2 Layout Example .................................................... 49
12 Device and Documentation Support................. 51
12.1 Documentation Support ........................................ 51
12.2 Related Links ........................................................ 51
12.3 Community Resource............................................ 51
12.4 Trademarks........................................................... 51
12.5 Electrostatic Discharge Caution............................ 51
12.6 Glossary................................................................ 51
13 Mechanical, Packaging, and Orderable
Information........................................................... 51
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision H (July 2015) to Revision I Page
• Fixed typo in power down supply current units - changed mA to uA .................................................................................. 12
Changes from Revision G (April 2013) to Revision H Page
• Added ESD Ratings table, Feature Description section, Device Functional Modes,Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................ 1
Changes from Revision F (January 2011) to Revision G Page
• Changed layout of National Data Sheet to TI format ............................................................................................................ 1
Changes from Revision E (August 2010) to Revision F Page
• Modified ESD to include IEC condition (330 Ohm, 150pF).................................................................................................. 10
• Updated deserializer parameters: IDD1, IDDZ, IDDIOZ, IDDR, VOH, VOL, tROS, tRDC .................................................. 11
• Updated Figure 14 and Figure 15 to reflect data measurement at VDDIO/2 ...................................................................... 20
• Updated Figure 38 – C13 changed to 4.7uF ....................................................................................................................... 44
3
DS90UR905Q-Q1
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Changes from Revision D (May 2010) to Revision E Page
• Removed ”Data Randomization & Scrambling ”, "Noise Margin” and “Typical Performance Curves” sections ................... 1
• Modified order information to include NOPB designation in NSPN column (replaced NSID column) .................................. 1
• Corrected ESD Ratings to IEC 61000 – 4 – 2 from ISO 10605 (duplication). .................................................................... 10
• Added RPU = 10k Ωcondition for the Serial Control Bus Characteristics of tR and tF. ..................................................... 14
Changes from Revision C (March 2010) to Revision D Page
• DS90UR906Q-Q1 data sheet limits have been updated per characterization results ........................................................ 11
• Corrected register 5 from RFB to VODSEL and register 4 from VODSEL to RFB in Table 14 .......................................... 39
Changes from Revision B (Feburary 2010) to Revision C Page
• Added reference to soldering profile..................................................................................................................................... 10
• Added ESD CDM and ESD MM values................................................................................................................................ 10
• Updated RθAvalue ............................................................................................................................................................... 11
Changes from Revision A (September 2009) to Revision B Page
• Removed IDDT3 and IDDIOT3 (RANDOM pattern) because the limits are the same as checker board pattern ................ 1
• DS90UR905Q data sheet limits have been updated per characterization result and are the final limits ............................. 1
• Updated DS90UR905Q-Q1 Typical Connection Diagram — Pin Control. Ref 30102044 .................................................... 5
• Updated DS90UR906Q-Q1 Pin Diagram: strap changes on pin11, pin14, and pin42 .......................................................... 7
• Added strap to pin 11 “ OS_PCLK ” (Output Slew_PCLK) ................................................................................................... 7
• Changed strap pin 14 feature from “ RDS ” to “ OS_DATA ” (Output Slew_DATA) ............................................................. 7
• Added strap to pin 42 “ OP_LOW ” (Output LOW) ................................................................................................................ 8
• Updated DS90UR906Q-Q1 Typical Connection Diagram — Pin Control. Ref 30102045 .................................................... 8
• Updated DS90UR906Q-Q1 Deserializer Pin Descriptions: RDS feature changed to OS_PCLK and OS_DATA.
Added OP_LOW feature ........................................................................................................................................................ 8
• Created OP_LOW timing Figure 28. Ref 30102065 ............................................................................................................ 31
• Created OP_LOW timing Figure 29. Ref 30102066 ............................................................................................................ 32
• Updated Table 12: deleted ID[x] Address 7'b 110 1000 (h'68) (8'b 1101 0000 (h'D0))....................................................... 38
• Updated Table 13: deleted ID[x] Address 7'b 111 0000 (h'70) (8'b 1110 0000 (h'E0)) ....................................................... 39
• Changed Table 14 ADD \ 1 \ bit \ 6:0 \ ID[x]: deleted Device ID 7b'1101 00 (h'68). Only four (4) IDs will be available...... 39
• Changed Table 15: ADD \ 0 \ bit \ 6 \ OSS_SEL: “ OSS_SEL ” changed feature to “ OS_PCLK ” (Output
Slew_PCLK). OSS_SEL moved to ADD \ 2 \ bit \ 6 \........................................................................................................... 40
• Changed Table 15: ADD \ 0 \ bit \ 5 \ RDS: changed “ RDS ” feature to OS_DATA (Output Slew_DATA) ....................... 40
• Changed Table 15: ADD \ 1\ bit \ 6:0 \ ID[x]: deleted Device ID 7b'1110 00 (h'70). Only four (4) IDs will be available. .... 40
• Changed Table 15: ADD \ 2 \ bit \ 7 \ Reserved: changed “ Reserved ” to “ OP_LOW ”..................................................... 40
• Changed Table 15: ADD \ 2 \ bit \ 6 \ Reserved: changed “ Reserved ” to “ OSS_SEL ”.................................................... 40
4
DS90UR905Q-Q1
,
DS90UR906Q-Q1
SNLS313I –SEPTEMBER 2009–REVISED OCTOBER 2019
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5 Description (continued)
Serial transmission is optimized by a user-selectable de-emphasis, differential output level select features, and
receiver equalization. EMI is minimized by the use of low voltage differential signaling, receiver drive strength
control, and spread spectrum clocking compatibility. The deserializer may be configured to generate spread
spectrum clock and data on its parallel outputs.
The DS90UR905Q-Q1 serializer is offered in a 48-pin WQFN and the DS90UR906Q-Q1 (deserializer) is offered
in a 60-pin WQFN package. They are specified over the automotive AEC-Q100 grade 2 temperature range of
–40°C to +105°C.
37
38
39
40
41
42
43
44
45
46
47
48
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
36
35
34
33
32
31
30
29
28
27
26
25
DS90UR905Q
TOP VIEW
DAP = GND
B[5]
B[4]
B[2]
B[1]
G[6]
G[5]
G[3]
G[2]
CONFIG[1]
VDDP
RES1
VDDHS
DOUT+
PDB
De-Emph
VODSEL
G[4]
G[7]
B[0]
B[3] RES0
RES2
DOUT-
VDDTX
B[6]
HS
PCLK
CONFIG[0]
B[7] G[0]
R[7]
R[6]
R[5]
BISTEN
VDDIO
R[4]
R[3]
R[2]
R[1]
G[1]
VDDL
SCL
RFB
R[0]
SDA
VS
DE
ID[x]
5
DS90UR905Q-Q1
,
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(1) 1 = HIGH, 0 = LOW
6 Pin Configuration and Functions
RHS Package
48-Pin WQFN
Top View
DS90UR905Q-Q1 Serializer Pin Functions(1)
PIN I/O, TYPE DESCRIPTION
NAME NO.
LVCMOS PARALLEL INTERFACE
B[7:0] 2, 1, 48, 47, 46,
45, 44, 43 I, LVCMOS
with pulldown BLUE parallel interface data input pins
(MSB = 7, LSB = 0)
DE 5 I, LVCMOS
with pulldown
Data enable input
Video control signal pulse width must be 3 PCLKs or longer to be transmitted when the
control signal filter is enabled (CONFIG[1:0] = 01). There is no restriction on the
minimum transition pulse when the control signal filter is disabled (CONFIG[1:0] = 00).
The signal is limited to 2 transitions per 130 PCLKs.
G[7:0] 42, 41, 40, 39,
38, 37, 36, 35 I, LVCMOS
with pulldown GREEN parallel interface data input pins
(MSB = 7, LSB = 0)
HS 3 I, LVCMOS
with pulldown
Horizontal Sync Input
Video control signal pulse width must be 3 PCLKs or longer to be transmitted when the
control signal filter is enabled (CONFIG[1:0] = 01). There is no restriction on the
minimum transition pulse when the control signal filter is disabled (CONFIG[1:0] = 00).
The signal is limited to 2 transitions per 130 PCLKs.
PCLK 10 I, LVCMOS
with pulldown Pixel clock input
Latch edge set by RFB function.
R[7:0] 34, 33, 32, 29,
28, 27, 26, 25 I, LVCMOS
with pulldown RED parallel interface data input pins
(MSB = 7, LSB = 0)
VS 4 I, LVCMOS
with pulldown Vertical sync input
Video control signal is limited to 1 transition per 130 PCLKs. Thus, the minimum pulse
width is 130 PCLKs.
6
DS90UR905Q-Q1
,
DS90UR906Q-Q1
SNLS313I –SEPTEMBER 2009–REVISED OCTOBER 2019
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DS90UR905Q-Q1 Serializer Pin Functions(1) (continued)
PIN I/O, TYPE DESCRIPTION
NAME NO.
(2) The VDD (VDDn and VDDIO) supply ramp should be faster than 1.5 ms with a monotonic rise. If slower then 1.5 ms, then a capacitor on
the PDB pin is needed to ensure PDB arrives after all the VDD have settled to the recommended operating voltage.
CONTROL AND CONFIGURATION
BISTEN 31 I, LVCMOS
with pulldown BIST mode — optional
BISTEN = 1, BIST is enabled
BISTEN = 0, BIST is disabled
CONFIG[1:0] 13, 12 I, LVCMOS
with pulldown
Operating modes — pin or register control
Determine the operating mode of the DS90UR905 and interfacing device.
CONFIG[1:0] = 00: interfacing to DS90UR906Q-Q1, control signal filter DISABLED
CONFIG[1:0] = 01: interfacing to DS90UR906Q-Q1, control signal filter ENABLED
CONFIG[1:0] = 10: interfacing to DS90UR124, DS99R124
CONFIG[1:0] = 11: interfacing to DS90C124
De-Emph 23 I, Analog
with pullup
De-emphasis control — pin or register control
De-emph = open (float) - disabled
To enable de-emphasis, tie a resistor from this pin to GND or control via register (see
Table 2).
ID[x] 6 I, Analog Serial control bus device ID address select — optional
Resistor-to-ground and 10-kΩpullup to 1.8-V rail (see Table 11).
PDB 21 I, LVCMOS
with pulldown
Power-down mode input
PDB = 1, serializer is enabled (normal operation).
Refer to Power Up Requirements and PDB Pin.
PDB = 0, serializer is powered down
When the serializer is in the power-down state, the driver outputs (DOUT±) are both
logic high, the PLL is shutdown, IDD is minimized. Control registers are RESET.
RES[2:0] 18, 16, 15 I, LVCMOS
with pulldown Reserved - tie LOW
RFB 11 I, LVCMOS
with pulldown
Pixel clock input latch edge select — pin or register control
RFB = 1, parallel interface data and control signals are latched on the rising clock
edge.
RFB = 0, parallel interface data and control signals are latched on the falling clock
edge.
SCL 8 I, LVCMOS Serial control bus clock input - optional
SCL requires an external pullup resistor to VDDIO.
SDA 9 I/O, LVCMOS
Open-Drain Serial control bus data input/output - optional
SDA requires an external pullup resistor VDDIO.
VODSEL 24 I, LVCMOS
with pulldown
Differential driver output voltage select — pin or register control
VODSEL = 1, LVDS VOD is ±420 mV, 840 mVp-p (typical) — long cable / de-emp
applications
VODSEL = 0, LVDS VOD is 280 mV, 560 mVp-p (typical)
FPD-LINK II SERIAL INTERFACE
DOUT+ 20 O, LVDS True output
The output must be AC-coupled with a 100-nF capacitor.
DOUT- 19 O, LVDS Inverting output
The output must be AC-coupled with a 100-nF capacitor.
POWER AND GROUND(2)
GND DAP Ground DAP is the large metal contact at the bottom side, located at the center of the WQFN
package. Connect to the ground plane (GND) with at least 9 vias.
VDDHS 17 Power TX high-speed logic power, 1.8 V ±5%
VDDL 7 Power Logic power, 1.8 V ±5%
VDDP 14 Power PLL power, 1.8 V ±5%
VDDIO 30 Power LVCMOS I/O power, 1.8 V ±5% or 3.3 V ±10%
VDDTX 22 Power Output Driver power, 1.8 V ±5%
50
51
52
53
54
55
56
57
58
59
60
1
2
3
4
5
6
7
8
9
10
11
12
27
26
25
24
23
22
21
20
19
18
17
16
45
44
43
42
41
40
39
38
37
36
35
34
DS90UR906Q
TOP VIEW
DAP = GND
NC
PDB
VDDPR
ID[x]
CMLOUTN
CMLOUTP
RIN-
RIN+
NC
B[2]/OSS_SEL
B[0]
G[7]/EQ[3]
G[4]/EQ[0]
VDDIO
G[2]/OSC_SEL[2]
G[1]/OSC_SEL[1]
CMF
VDDCMLO
VDDR
VDDSC B[1]/RFB
G[6]/EQ[2]
G[5]/EQ[1]
G[3]
NC
SCL
B[6]/CONFIG[1]
B[4]/LF_MODE
SDA BISTEN
VDDR
PASS/OP_LOW
R[0]/MAP_SEL[0]
R[1]/MAP_SEL[1]
R[2]
VDDIO
R[3]/SSC[0]
R[4]/SSC[1]
R[5]/SSC[2]
NC
VS
HS
B[5]/OS_PCLK
R[6]/SSC[3]
B[7]/CONFIG[0]
VDDSC
PCLK
DE
VDDIO
NC
B[3]/OS_DATA
33
32
31
R[7]
LOCK
NC
30
29
28
VDDL
NC
G[0]/OSC_SEL[0]
46
47
48
RES
NC
VDDIR
BOLD PIN NAME ± indicates I/O strap
pin associated with output pin
13
14
15
49
7
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(1) 1 = HIGH, 0 = LOW
NKB Package
60-Pin WQFN
Top View
DS90UR906Q-Q1 Deserializer Pin Functions(1)
PIN I/O, TYPE DESCRIPTION
NAME NO.
LVCMOS PARALLEL INTERFACE
B[7:0] 9, 10, 11,
12, 14, 17,
18, 19 I, STRAP,
O, LVCMOS BLUE parallel interface data output pins (MSB = 7, LSB = 0)
In power-down (PDB = 0), outputs are controlled by the OSS_SEL (see Table 6). These pins
are inputs during power up (see Deserializer Strap Input Pins).
DE 6 O, LVCMOS
Data enable output
In power down (PDB = 0), output is controlled by the OSS_SEL pin (see Table 6). Video
control signal pulse width must be 3 PCLKs or longer to be transmitted when the control
signal filter is enabled (CONFIG[1:0] = 01). There is no restriction on the minimum transition
pulse when the control signal filter is disabled
(CONFIG[1:0] = 00). The signal is limited to 2 transitions per 130 PCLKs.
G[7:0] 20, 21, 22,
23, 25, 26,
27, 28 I, STRAP,
O, LVCMOS GREEN parallel interface data output pins (MSB = 7, LSB = 0)
In power down (PDB = 0), outputs are controlled by the OSS_SEL (see Table 6). These pins
are inputs during power up (see Deserializer Strap Input Pins).
HS 8 O, LVCMOS
Horizontal sync output
In power down (PDB = 0), output is controlled by the OSS_SEL pin (see Table 6). Video
control signal pulse width must be 3 PCLKs or longer to be transmitted when the control
signal filter is enabled (CONFIG[1:0] = 01). There is no restriction on the minimum transition
pulse when the control signal filter is disabled
(CONFIG[1:0] = 00). The signal is limited to 2 transitions per 130 PCLKs.
8
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DS90UR906Q-Q1 Deserializer Pin Functions(1) (continued)
PIN I/O, TYPE DESCRIPTION
NAME NO.
(2) It is not recommended to use any other strap options with this strap function
(3) Before the device is powered up, the outputs are in tri-state.
(4) OSS_SEL strap cannot be used if OP_LOW =1
LOCK 32 O, LVCMOS LOCK status output
LOCK = 1, PLL is Locked, outputs are active LOCK = 0, PLL is unlocked, RGB[7:0], HS, VS,
DE and PCLK output states are controlled by OSS_SEL (see Table 6). May be used as link
status or to flag when video data is active (ON/OFF).
PASS 42 O, LVCMOS PASS output (BIST mode)
PASS = 1, error free transmission
PASS = 0, one or more errors were detected in the received payload
Route to test point for monitoring, or leave open if unused.
PCLK 5 O, LVCMOS Pixel clock output
In power down (PDB = 0), output is controlled by the OSS_SEL pin (see Table 6). Strobe
edge set by RFB function.
R[7:0] 33, 34, 35,
36, 37, 39,
40, 41 I, STRAP,
O, LVCMOS RED parallel interface data output pins (MSB = 7, LSB = 0)
In power down (PDB = 0), outputs are controlled by the OSS_SEL (see Table 6). These pins
are inputs during power up (see Deserializer Strap Input Pins).
VS 7 O, LVCMOS Vertical sync output
In power down (PDB = 0), output is controlled by the OSS_SEL pin (see Table 6). Video
control signal is limited to 1 transition per 130 PCLKs. Thus, the minimum pulse width is 130
PCLKs.
CONTROL AND CONFIGURATION — STRAP PINS
For a HIGH state, use a 10-kΩpullup to VDDIO; for a LOW state, the IO includes an internal pulldown. The STRAP pins are read upon
power up and set device configuration. Pin Number listed along with shared RGB output name in square brackets.
CONFIG[1:0] 10 [B6],
9 [B7] STRAP
I, LVCMOS
with pulldown
Operating modes — pin or register control
These pins determine the operating mode of the DS90UR906 and interfacing device.
CONFIG[1:0] = 00: interfacing to DS90UR905Q-Q1, control signal filter DISABLED
CONFIG[1:0] = 01: interfacing to DS90UR905Q-Q1, control signal filter ENABLED
CONFIG[1:0] = 10: interfacing to DS90UR241
CONFIG[1:0] = 11: interfacing to DS90C241
EQ[3:0] 20 [G7],
21 [G6],
22 [G5],
23 [G4]
STRAP
I, LVCMOS
with pulldown Receiver input equalization — pin or register control (see Table 3).
LF_MODE 12 [B4] STRAP
I, LVCMOS
with pulldown
SSCG low-frequency mode — pin or register control
Only required when SSCG is enabled, otherwise LF_MODE condition is a DON’T CARE (X).
LF_MODE = 1, SSCG in low-frequency mode (PCLK = 5 to 20 MHz)
LF_MODE = 0, SSCG in high-frequency mode (PCLK = 20 to 65 MHz)
MAP_SEL[1:0] 40 [R1],
41 [R0] STRAP
I, LVCMOS
with pulldown Bit mapping backward compatibility / DS90UR241 options — pin or register control
Normal setting to b'00 (see Table 9).
OP_LOW 42 PASS STRAP
I, LVCMOS
with pulldown
Outputs held LOW when LOCK = 1 — pin or register control
See (2)
OP_LOW = 1: all outputs are held LOW during power up until released by programming
OP_LOW release / set register HIGH
See (3)
See Figure 30 and Figure 31.
OP_LOW = 0: all outputs toggle normally as soon as LOCK goes HIGH (default).
OS_DATA 14 [B3] STRAP
I, LVCMOS
with pulldown
Data output slew select — pin or register control
OS_DATA = 1, increased DATA slew
OS_DATA = 0, normal (default)
OSC_SEL[2:0] 26 [G2],
27 [G1],
28 [G0]
STRAP
I, LVCMOS
with pulldown Oscillator select — pin or register control (see Table 7 and Table 8).
OS_PCLK 11 [B5] STRAP
I, LVCMOS
with pulldown
PCLK output slew select — pin or register control
OS_PCLK = 1, increased PCLK slew
OS_PCLK = 0, normal (default)
OSS_SEL 17 [B2] STRAP
I, LVCMOS
with pulldown
Output sleep state select — pin or register control
See (4)
OSS_SEL is used in conjunction with PDB to determine the state of the outputs in power
down (Sleep) (see Table 6).
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DS90UR906Q-Q1 Deserializer Pin Functions(1) (continued)
PIN I/O, TYPE DESCRIPTION
NAME NO.
(5) The VDD (VDDn and VDDIO) supply ramp should be faster than 1.5 ms with a monotonic rise. If slower then 1.5 ms, then a capacitor on
the PDB pin is needed to ensure PDB arrives after all the VDD have settled to the recommended operating voltage.
RFB 18 [B1] STRAP
I, LVCMOS
with pulldown
Pixel clock output strobe edge select — pin or register control
RFB = 1, parallel interface data and control signals are strobed on the rising clock edge.
RFB = 0, parallel interface data and control signals are strobed on the falling clock edge.
SSC[3:0] 34 [R6],
35 [R5],
36 [R4],
37 R[3]
STRAP
I, LVCMOS
with pulldown Spread spectrum clock generation (SSCG) range select — pin or register control
See Table 4 and Table 5.
CONTROL AND CONFIGURATION
BISTEN 44 I, LVCMOS
with pulldown BIST enable input — optional
BISTEN = 1, BIST is enabled
BISTEN = 0, BIST is disabled
ID[x] 56 I, Analog Serial control bus device ID address select — optional
Resistor-to-ground and 10-kΩpullup to 1.8-V rail (see Table 10).
NC 1, 15, 16,
30, 31, 45,
46, 60 —Not connected
Leave pin open (float)
PDB 59 I, LVCMOS
with pulldown
Power-down mode input
PDB = 1, deserializer is enabled (normal operation).
Refer to Power Up Requirements and PDB Pin.
PDB = 0, deserializer is in power down.
When the deserializer is in the power-down state, the LVCMOS output state is determined by
Table 6. Control Registers are RESET.
RES 47 I, LVCMOS
with pulldown Reserved - tie LOW
SCL 3 I, LVCMOS Serial control bus clock input — optional
SCL requires an external pullup resistor to VDDIO.
SDA 2 I/O, LVCMOS
Open-Drain Serial control bus data input/output — optional
SDA requires an external pullup resistor to VDDIO.
FPD-LINK II SERIAL INTERFACE
CMF 51 I, Analog Common-mode filter
VCM center-tap is a virtual ground which may be AC coupled to ground to increase receiver
common-mode noise immunity. Recommended value is 0.1 μF or higher.
CMLOUTN 53 O, LVDS Test monitor pin — EQ waveform
NC or connect to test point. Requires serial bus control to enable.
CMLOUTP 52 O, LVDS Test monitor pin — EQ waveform
NC or connect to test point. Requires serial bus control to enable.
RIN+ 49 I, LVDS True input. The input must be AC coupled with a 100-nF capacitor.
RIN- 50 I, LVDS Inverting input. The input must be AC coupled with a 100-nF capacitor.
POWER AND GROUND(5)
GND DAP Ground DAP is the large metal contact at the bottom side, located at the center of the WQFN
package. Connected to the ground plane (GND) with at least 9 vias.
VDDCMLO 54 Power RX high-speed logic power, 1.8 V ±5%
VDDL 29 Power Logic power, 1.8 V ±5%
VDDIO 13, 24, 38 Power LVCMOS I/O power, 1.8 V ±5% or 3.3 V ±10% (VDDIO)
VDDIR 48 Power Input power, 1.8 V ±5%
VDDPR 57 Power PLL power, 1.8 V ±5%
VDDR 43, 55 Power RX high-speed logic power, 1.8 V ±5%
VDDSC 4, 58 Power SSCG power, 1.8 V ±5%
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(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office or Distributors for availability and
specifications.
(3) For soldering specifications see product folder at www.ti.com and SNOA549.
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)(2)(3).MIN MAX UNIT
Supply voltage – VDDn (1.8 V) –0.3 2.5 V
Supply voltage – VDDIO –0.3 4 V
LVCMOS I/O voltage –0.3 VDDIO + 0.3 V
Receiver input voltage –0.3 VDD + 0.3 V
Driver output voltage –0.3 VDD + 0.3 V
Junction temperature 150 °C
48L RHS package Maximum power dissipation capacity at 25°C 215 mW
Derate above 25°C 1/θJA mW/°C
60L NKB package Maximum power dissipation capacity at 25°C 470 mW
Derate above 25°C 1/θJA mW/°C
Storage temperature –65 150 °C
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
(2) RD= 2 kΩ, CS= 150 pF or RD= 2 kΩ, CS= 330 pF or RD= 330 Ω, CS= 150 pF
(3) RD= 330 Ω, CS= 330 pF
7.2 ESD Ratings VALUE UNIT
V(ESD) Electrostatic discharge
Human body model (HBM), per AEC Q100-002(1) ±8000
V
Charged-device model (CDM), per AEC Q100-011 ±1000
Machine Model (MM) ±250
ISO10605(2)
Air Discharge (DOUT+, DOUT−)≥±30000
Contact Discharge (DOUT+, DOUT−)≥±10000
Air Discharge (RIN+, RIN−)≥±30000
Contact Discharge (RIN+, RIN−)≥±10000
ISO10605(3)
Air Discharge (DOUT+, DOUT−)≥±15000
Contact Discharge (DOUT+, DOUT−)≥±10000
Air Discharge (RIN+, RIN−)≥±15000
Contact Discharge (RIN+, RIN−)≥±10000
IEC 61000-4-2(3)
Air Discharge (DOUT+, DOUT−)≥±25000
Contact Discharge (DOUT+, DOUT−)≥±8000
Air Discharge (RIN+, RIN−)≥±25000
Contact Discharge (RIN+, RIN−)≥±8000
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(1) Supply noise testing was done with minimum capacitors on the PCB. A sinusoidal signal is AC coupled to the VDDn (1.8-V) supply with
amplitude = 100 mVp-p measured at the device VDDn pins. Bit error rate testing of input to the serializer and output of the deserializer
with 10 meter cable shows no error when the noise frequency on the serializer is less than 750 kHz. The deserializer on the other hand
shows no error when the noise frequency is less than 400 kHz.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT
Supply voltage (VDDn) 1.71 1.8 1.89 V
LVCMOS supply voltage (VDDIO) 1.71 1.8 1.89 V
OR LVCMOS supply voltage (VDDIO) 3 3.3 3.6
Operating free-air temperature (TA)−40 25 105 °C
PCLK clock frequency 5 65 MHz
Supply noise(1) 50 mVP-P
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
(2) Based on nine thermal vias.
7.4 Thermal Information
THERMAL METRIC(1) DS90UR905Q-Q1 DS90UR906Q-Q1
UNITRHS (WQFN) NKB (WQFN)
48 PINS 60 PINS
RθJA Junction-to-ambient thermal resistance(2) 30.3 26.9 °C/W
RθJC(top) Junction-to-case (top) thermal resistance(2) 11.5 9.1 °C/W
RθJB Junction-to-board thermal resistance 7.3 6.0 °C/W
ψJT Junction-to-top characterization parameter 0.1 0.1 °C/W
ψJB Junction-to-board characterization parameter 7.3 6.0 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 2.7 1.5 °C/W
(1) The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not ensured.
(2) Typical values represent most likely parametric norms at VDD = 3.3 V, TA= 25°C, and at the Recommended Operating Conditions at the
time of product characterization and are not ensured.
(3) Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground
except VOD, ΔVOD, VTH and VTL which are differential voltages.
7.5 Serializer DC Electrical Characteristics
over recommended operating supply and temperature ranges unless otherwise specified.(1)(2)(3)
PARAMETER TEST CONDITIONS PIN / FREQ MIN TYP MAX UNIT
LVCMOS INPUT DC SPECIFICATIONS
VIH High-level input voltage VDDIO = 3.0 to 3.6 V
R[7:0],
G[7:0],
B[7:0],
HS, VS, DE,
PCLK, PDB,
VODSEL,
RFB,
CONFIG[1:0],BIS
TEN
2.2 VDDIO V
VDDIO = 1.71 to 1.89 V 0.65 ×
VDDIO VDDIO V
VIL Low-level input voltage VDDIO = 3.0 to 3.6 V GND 0.8 V
VDDIO = 1.71 to 1.89 V GND 0.35 ×
VDDIO V
IIN Input current VIN = 0 V or VDDIO
VDDIO = 3.0
to 3.6 V –15 ±1 +15 μA
VDDIO = 1.7
to 1.89 V –15 ±1 +15 μA
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Serializer DC Electrical Characteristics (continued)
over recommended operating supply and temperature ranges unless otherwise specified.(1)(2)(3)
PARAMETER TEST CONDITIONS PIN / FREQ MIN TYP MAX UNIT
LVDS DRIVER DC SPECIFICATIONS
VOD Differential output
voltage RL= 100 Ω,
De-emph = disabled,
Figure 2
VODSEL = 0 DOUT+, DOUT– ±205 ±280 ±355 mV
VODSEL = 1 ±320 ±420 ±520
VODp-p Differential output
voltage
(DOUT+) – (DOUT-)
VODSEL = 0 DOUT+, DOUT– 560 mVp-p
VODSEL = 1 840
ΔVOD Output voltage
unbalance RL= 100 Ω, De-emph = disabled, VODSEL = L
DOUT+, DOUT–
1 50 mV
VOS Offset voltage – single-
ended
at TP A and B, Figure 1 RL= 100 Ω,
De-emph = disabled VODSEL = 0 1.65 V
VODSEL = 1 1.575
ΔVOS
Offset voltage
unbalance
Single-ended
at TP A and B, Figure 1 RL= 100 Ω, De-emph = disabled
DOUT+, DOUT–
1 mV
IOS Output short circuit
current DOUT± = 0 V,
De-emph = disabled VODSEL = 0 –36 mA
RTInternal termination
resistor 80 100 120 Ω
SUPPLY CURRENT
IDDT1 Serializer
supply current
(includes load current)
RL= 100 Ω, f = 65 MHz
Checker Board Pattern,
De-emph = 3 KΩ
VODSEL = H, Figure 9
VDD = 1.89 V All VDD pins 75 85 mAVDDIO = 1.89 V VDDIO 3 5
IDDIOT1 VDDIO = 3.6 V 11 15
IDDT2 Checker Board Pattern,
De-emph = 6 KΩ,
VODSEL = L, Figure 9
VDD = 1.89 V All VDD pins 65 75 mAVDDIO = 1.89 V VDDIO 3 5
IDDIOT2 VDDIO = 3.6 V 11 15
IDDZ Serializer
cupply current power
down PDB = 0 V , (All other
LVCMOS Inputs = 0 V)
VDD = 1.89 V All VDD pins 40 1000
μAVDDIO = 1.89 V VDDIO 5 10
IDDIOZ VDDIO = 3.6 V 10 20
7.6 Deserializer DC Electrical Characteristics
over recommended operating supply and temperature ranges unless otherwise specified.
PARAMETER TEST CONDITIONS PIN / FREQ MIN TYP MAX UNIT
3.3 V I/O LVCMOS DC SPECIFICATIONS – VDDIO = 3.0 to 3.6 V
VIH High-level input voltage PDB, BISTEN 2.2 VDDIO V
VIL Low-level input voltage GND 0.8 V
IIN Input current VIN = 0 V or VDDIO −15 ±1 15 μA
VOH High-level output voltage IOH =−2 mA,
OS_PCLK/DATA = L
R[7:0], G[7:0],
B[7:0], HS,VS,
DE, PCLK,
LOCK, PASS 2.4 VDDIO V
VOL Low-level output voltage IOL = +2 mA,
OS_PCLK/DATA = L
R[7:0], G[7:0],
B[7:0], HS, VS,
DE,PCLK,
LOCK, PASS GND 0.4 V
IOS
Output short circuit current VDDIO = 3.3 V
VOUT = 0 V,
OS_PCLK/DATA = L/H PCLK 36 mA
Output short circuit current VDDIO = 3.3 V
VOUT = 0 V,
OS_PCLK/DATA = L/H Deserializer
Outputs 37 mA
IOZ TRI-STATE output current PDB = 0 V, OSS_SEL = 0
V, VOUT = H Outputs −15 15 µA
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Deserializer DC Electrical Characteristics (continued)
over recommended operating supply and temperature ranges unless otherwise specified.
PARAMETER TEST CONDITIONS PIN / FREQ MIN TYP MAX UNIT
1.8 V I/O LVCMOS DC SPECIFICATIONS – VDDIO = 1.71 to 1.89 V
VIH High-level input voltage PDB, BISTEN 1.235 VDDIO V
VIL Low-level input voltage GND 0.595 V
IIN Input current VIN = 0 V or VDDIO −15 ±1 15 μA
VOH High-level output voltage IOH =−2 mA,
OS_PCLK/DATA = L/H R[7:0], G[7:0],
B[7:0], HS, VS,
DE, PCLK,
LOCK, PASS
VDDIO −
0.45 VDDIO V
VOL Low-level output voltage IOL = +2 mA,
OS_PCLK/DATA = L/H GND 0.45 V
IOS Output short circuit current
VDDIO = 1.8 V
VOUT = 0 V,
OS_PCLK/DATA = L/H PCLK 18 mA
VDDIO = 1.8 V
VOUT = 0 V,
OS_PCLK/DATA = L/H DATA 18 mA
IOZ TRI-STATE output current PDB = 0 V, OSS_SEL = 0
V, VOUT = 0 V or VDDIO Outputs –15 15 µA
LVDS RECEIVER DC SPECIFICATIONS
VTH Differential input threshold high
voltage VCM = +1.2 V (Internal
VBIAS)RIN+, RIN-
50 mV
VTL Differential input threshold low
voltage –50 mV
VCM Common-mode voltage, internal
VBIAS 1.2 V
IIN Input current VIN = 0 V or VDDIO –15 15 µA
RTInternal termination resistor RIN+, RIN- 80 100 120 Ω
CMLOUTP/N DRIVER OUTPUT DC SPECIFICATIONS – EQ TEST PORT
VOD Differential output voltage RL= 100 ΩCMLOUTP,
CMLOUTN
542 mV
VOS Offset voltage
Single-ended RL= 100 Ω1.4 V
RTInternal termination resistor CMLOUTP,
CMLOUTN 80 100 120 Ω
SUPPLY CURRENT
IDD1 Deserializer
supply current
(includes load current)
Checker Board Pattern,
OS_PCLK/DATA = H,
EQ = 001,
SSCG=ON
CMLOUTP/N = enabled
CL= 4 pF, Figure 9
All VDD pins 93 110 mA
IDDIO1 VDDIO
33 45 mA
62 75 mA
IDDZ Deserializer supply current power
down PDB = 0 V, All other
LVCMOS Inputs = 0 V
All VDD pins 40 3000 µA
IDDIOZ VDDIO 5 50 µA
10 100 µA
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(1) Specification is ensured by characterization and is not tested in production.
7.7 DC and AC Serial Control Bus Characteristics
over 3.3-V supply and temperature ranges unless otherwise specified.
PARAMETERS TEST CONDITIONS MIN TYP MAX UNIT
VIH Input high-level voltage SDA and SCL 2.2 VDDIO V
VIL Input low-level voltage SDA and SCL GND 0.8 V
VHY Input hysteresis >50 mV
VOL Output low-level voltage(1) SDA, IOL = 1.25 mA 0 0.4 V
Iin SDA or SCL, Vin = VDDIO or GND –15 15 µA
Cin Input capacitance SDA or SCL <5 pF
7.8 Timing Requirements for DC and AC Serial Control Bus
over recommended operating supply and temperature ranges unless otherwise specified.
TEST CONDITIONS MIN NOM MAX UNIT
tRSDA rise time – READ SDA, RPU = 10 kΩ, Cb ≤400 pF 40 ns
tFSDA fall time – READ 25 ns
tSU;DAT Set-up time – READ 520 ns
tHD;DAT Hold up time – READ 55 ns
tSP Input filter 50 ns
7.9 Timing Requirements for Serializer PCLK
over recommended operating supply and temperature ranges unless otherwise specified.
TEST CONDITIONS MIN NOM MAX UNIT
tTCP Transmit input PCLK period
5 MHz to 65 MHz, Figure 4
15.38 T 200 ns
tTCIH Transmit input PCLK high time 0.4T 0.5T 0.6T ns
tTCIL Transmit input PCLK low time 0.4T 0.5T 0.6T ns
tCLKT PCLK input transition time 0.5 2.4 ns
SSCIN PCLK input – spread spectrum
at PCLK = 65 MHz fmod 35 kHz
fdev ±2%
7.10 Timing Requirements for Serial Control Bus
over 3.3-V supply and temperature ranges unless otherwise specified.
TEST CONDITIONS MIN NOM MAX UNIT
fSCL SCL clock frequency Standard Mode >0 100 kHz
Fast Mode >0 400 kHz
tLOW SCL low period Standard Mode 4.7 µs
Fast Mode 1.3 µs
tHIGH SCL high period Standard Mode 4 µs
Fast Mode 0.6 µs
tHD;STA Hold time for a start or a
repeated start condition,
Figure 18
Standard Mode 4 us
Fast Mode 0.6 µs
tSU:STA Set-up time for a start or a
repeated start condition,
Figure 18
Standard Mode 4.7 µs
Fast Mode 0.6 µs
tHD;DAT Data hold time,
Figure 18 Standard Mode 0 3.45 µs
Fast Mode 0 0.9 µs
tSU;DAT Data set-up time,
Figure 18 Standard Mode 250 ns
Fast Mode 100 ns
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Timing Requirements for Serial Control Bus (continued)
over 3.3-V supply and temperature ranges unless otherwise specified.
TEST CONDITIONS MIN NOM MAX UNIT
tSU;STO Set-up time for STOP condition,
Figure 18 Standard Mode 4 µs
Fast Mode 0.6 µs
tBUF Bus free time between STOP
and START, Figure 18 Standard Mode 4.7 µs
Fast Mode 1.3 µs
trSCL and SDA rise time,
Figure 18 Standard Mode 1000 µs
Fast Mode 300 ns
tfSCL and SDA fall time,
Figure 18 Standard Mode 300 ns
Fast mode 300 ns
(1) Specification is ensured by characterization and is not tested in production.
(2) tPLD is the time required by the serializer to obtain lock when exiting power-down state with an active PCLK.
(3) When the serializer output is at TRI-STATE the deserializer will lose PLL lock. Resynchronization / Relock must occur before data
transfer require tPLD
(4) UI – Unit Interval is equivalent to one serialized data bit width (1UI = 1 / [28 × PCLK]). The UI scales with PCLK frequency.
7.11 Switching Characteristics: Serializer
over recommended operating supply and temperature ranges unless otherwise specified.
PARAMETERS TEST CONDITIONS MIN TYP MAX UNIT
tLHT Serializer output low-to-high
transition time, Figure 3 RL= 100 Ω, De-emphasis = disabled, VODSEL = 0 200 ps
RL= 100 Ω, De-emphasis = disabled, VODSEL = 1 200 ps
tHLT Serializer output high-to-low
transition time, Figure 3 RL= 100 Ω, De-emphasis = disabled, VODSEL = 0 200 ps
RL= 100 Ω, De-emphasis = disabled, VODSEL = 1 200 ps
tDIS Input data – set-up time,
Figure 4 RGB[7:0], HS, VS, DE to PCLK 2 ns
tDIH Input data – hold time,
Figure 4 PCLK to RGB[7:0], HS, VS, DE 2 ns
tXZD Serializer output active to OFF
delay, Figure 6(1) 8 15 ns
tPLD(2) Serializer PLL lock time,
Figure 5(1)(3) RL= 100 Ω1.4 10 ms
tSD Serializer delay – latency,
Figure 7(1) RL= 100 Ω144 × T 145 × T ns
tDJIT Serializer output total jitter,
Figure 8
RL= 100 Ω, De-Emph = disabled,
RANDOM pattern, PCLK = 65 MHz 0.28 UI(4)
RL= 100 Ω, De-Emph = disabled,
RANDOM pattern, PCLK = 43 MHz 0.27 UI
RL= 100 Ω, De-Emph = disabled,
RANDOM pattern, PCLK = 5 MHz 0.35 UI
λSTXBW Serializer jitter transfer
Function –3-dB bandwidth
PCLK = 65 MHz 3 MHz
PCLK = 43 MHz 2.3 MHz
PCLK = 20 MHz 1.3 MHz
PCLK = 5 MHz 650 kHz
δSTX Serializer jitter transfer
function peaking
PCLK = 65 MHz 0.838 dB
PCLK = 43 MHz 0.825 dB
PCLK = 20 MHz 0.826 dB
PCLK = 5 MHz 0.278 dB
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(1) tDDLT is the time required by the deserializer to obtain lock when exiting power-down state with an active PCLK.
(2) tPLD is the time required by the serializer to obtain lock when exiting power-down state with an active PCLK.
(3) tDPJ is the maximum amount the period is allowed to deviate over many samples.
(4) Specification is ensured by characterization and is not tested in production.
(5) Specification is ensured by design and is not tested in production.
(6) Specification is ensured by characterization and is not tested in production.
(7) tDCCJ is the maximum amount of jitter between adjacent clock cycles.
7.12 Switching Characteristics: Deserializer
over recommended operating supply and temperature ranges unless otherwise specified.
PARAMETERS TEST CONDITIONS PIN / FREQ MIN TYP MAX UNIT
tRCP PCLK output period tRCP = tTCP PCLK 15.38 T 200 ns
tRDC PCLK output duty cycle SSCG=OFF, 5–65 MHz PCLK 43% 50% 57%
SSCG=ON, 5–20 MHz 35% 59% 65%
SSCG=ON, 20–65 MHz 40% 53% 60%
tCLH LVCMOS
Low-to-high transition time,
Figure 10
VDDIO = 1.8 V, CL= 4 pF PCLK/RGB[7:0], HS,
VS, DE 2.1 ns
VDDIO = 3.3 V, CL= 4 pF 2.0 ns
tCHL LVCMOS
High-to-low transition time,
Figure 10
VDDIO = 1.8 V
CL= 4 pF, OS_PCLK/DATA = L PCLK/RGB[7:0], HS,
VS, DE
1.6 ns
VDDIO = 3.3 V
CL= 4 pF, OS_PCLK/DATA = H 1.5 ns
tROS Data valid before PCLK –
set-up time Figure 14 VDDIO = 1.71 to 1.89 V or 3.0 to
3.6 V
CL= 4pF (lumped load) RGB[7:0], HS, VS, DE 0.27 0.45 T
tROH Data valid after PCLK – hold
time Figure 14 VDDIO = 1.71 to 1.89 V or 3.0 to
3.6 V
CL= 4pF (lumped load) RGB[7:0], HS, VS, DE 0.4 0.55 T
tDDLT(1) Deserializer lock time,
Figure 13
SSC[3:0] = 0000 (OFF)(2) PCLK = 5 MHz 3 ms
SSC[3:0] = 0000 (OFF)(2) PCLK = 65 MHz 4 ms
SSC[3:0] = ON(2) PCLK = 5 MHz 30 ms
SSC[3:0] = ON(2) PCLK = 65 MHz 6 ms
tDD Deserializer delay – latency,
Figure 11 SSC[3:0] = 0000 (OFF)(2) 139 × T 140 × T ns
tDPJ Deserializer period jitter SSC[3:0] = OFF(3)(4)(5) PCLK = 5 MHz 975 1700 ps
PCLK = 10 MHz 500 1000 ps
PCLK = 65 MHz 550 1250 ps
tDCCJ Deserializer cycle-to-cycle
jitter SSC[3:0] = OFF(6)(7)(5) PCLK = 5 MHz 675 1150 ps
PCLK = 10 MHz 375 900 ps
PCLK = 65 MHz 500 1150 ps
tIJT Deserializer input jitter
tolerance, Figure 16 EQ = OFF,
SSCG = OFF,
PCLK = 65 MHz
for jitter freq < 2 MHz 0.9 UI
for jitter freq > 6 MHz 0.5 UI
BIST Mode
tPASS BIST PASS valid time,
BISTEN = 1, Figure 17 1 10 µs
SSCG Mode
fDEV Spread spectrum clocking
deviation frequency Under typical conditions PCLK = 5 to 65 MHz,
SSC[3:0] = ON ±0.5% ±2%
fMOD Spread spectrum clocking
modulation frequency Under typical conditions PCLK = 5 to 65 MHz,
SSC[3:0] = ON 8 100 kHz
tDIH
tDIS
tTCP
1/2 VDDIO
GND
VDDIO
GND
VDDIO
RGB[n],
VS, HS, DE
PCLK
w/ RFB = L
tTCIH tTCIL
tCLKT tCLKT
20%
80%
VIHmin
VILmax
0V
+VOD
-VOD
tLHLT
tLLHT
(DOUT+) - (DOUT-)
20%
80%
DOUT+
DOUT-
(DOUT+) - (DOUT+)
GND
0V
VOD+
VOD-
VOS
VODp-p
VOD+ VOD-
Single-EndedDifferential
A
B
A'
B'
CA
CB
50:
50:
50:50:
Scope
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Figure 1. Serializer Test Circuit
Figure 2. Serializer Output Waveforms
Figure 3. Serializer Output Transition Times
Figure 4. Serializer Input PCLK Waveform and Set and Hold Times
SYMBOL N
27210
START
BIT
STOP
BIT
SYMBOL N
27210
START
BIT
STOP
BIT
SYMBOL N-1
DOUT
(Diff.)
PCLK
(RFB = L)
tSD
RGB[7:0],
HS, VS, DE SYMBOL N+1
PDB 1/2 VDDIO
PCLK
DOUT
(Diff.)
"X"active
tXZD
active
Driver OFF, VOD = 0V
PDB 1/2 VDDIO
PCLK
DOUT
(Diff.)
"X" active
tPLD
Driver OFF, VOD = 0V Driver On
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Figure 5. Serializer Lock Time
Figure 6. Serializer Disable Time
Figure 7. Serializer Latency Delay
27210
START
BIT
STOP
BIT
SYMBOL N+1
27210
START
BIT
STOP
BIT
SYMBOL N
RIN
(Diff.)
PCLK
(RFB = L)
tDD
RGB[7:0],
HS, VS, DE
SYMBOL N-1 SYMBOL NSYMBOL N-2
80%
VDDIO
20%
tCLH tCHL
GND
GND
VDDIO
GND
VDDIO
RGB[n] (odd),
VS, HS
PCLK
w/ RFB = L
RGB[n] (even),
DE GND
VDDIO
DOUT
(Diff.)
tDJIT
VOD (+)
tBIT (1 UI)
TxOUT_E_O
VOD (-)
0V
tDJIT
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Figure 8. Serializer Output Jitter
Figure 9. Checkerboard Data Pattern
Figure 10. Deserializer LVCMOS Transition Times
Figure 11. Deserializer Delay – Latency
1/2 VDDIO
GND
VDDIO
GND
VDDIO
tROS tROH
PCLK
w/ RFB = H
RGB[n],
VS, HS, DE 1/2 VDDIO
RIN
(Diff.)
Z or L or PU
Z or L
Z or L
TRI-STATE or LOW or Pulled Up
TRI-STATE or LOW
RGB[7:0],
HS, VS, DE
PCLK
(RFB = L)
TRI-STATE
or LOW
LOCK
'RQ¶W&DUH
tRxZ
tDDLT
PDB 2.0V
0.8V
IN LOCK TIMEOFF ACTIVE OFF
PDB 1/2 VDDIO
RIN
(Diff.)
PCLK,
RGB[7:0],
DE, HS, VS,
PASS, LOCK
"X"active
tXZR
active Z (TRI-STATE)
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Figure 12. Deserializer Disable Time (OSS_SEL = 0)
Figure 13. Deserializer PLL Lock Times and PDB TRI-STATE Delay
Figure 14. Deserializer Output Data Valid (Set-up and Hold) Times With SSCG = Off
SCL
SDA
tHD;STA
tLOW
tr
tHD;DAT
tHIGH
tf
tSU;DAT
tSU;STA tSU;STO
tf
START REPEATED
START
STOP
tHD;STA
START
tSP
tr
tBUF
BISTEN 1/2 VDDIO
PASS
(w/ errors)
tPASS
1/2 VDDIO
Prior BIST Result Current BIST Test - Toggle on Error Result Held
tBIT (1 UI)
Sampling
Window
Ideal Data
Bit End
Ideal Data Bit
Beginning
RxIN_TOL
Left
RxIN_TOL
Right
Ideal Center Position (tBIT/2)
tRJIT = RxIN_TOL (Left + Right)
VTH
VTL
0V
Sampling Window = 1 UI - tRJIT
1/2 VDDIO
GND
VDDIO
GND
VDDIO
tROS tROH
PCLK
w/ RFB = H
RGB[n],
VS, HS, DE 1/2 VDDIO 1/2 VDDIO
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Figure 15. Deserializer Output Data Valid (Set-up and Hold) Times With SSCG = On
Figure 16. Receiver Input Jitter Tolerance
Figure 17. BIST PASS Waveform
Figure 18. Serial Control Bus Timing Diagram
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7.13 Typical Characteristics
Figure 19. Differential Output Voltage vs Ambient
Temperature Figure 20. CMLOUT VOD vs Ambient Temperature
RFB
24
PCLK
PDB
PLL
Timing and
Control
DOUT-
DOUT+
Input Latch
Parallel to Serial
DC Balance Encoder
De-Emph
VODSEL
RGB[7:0]
HS
VS
DE
SCL
SCA
ID[x]
CONFIG[1:0]
BISTEN
Pattern
Generator
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8 Detailed Description
8.1 Overview
The DS90UR90xQ-Q1 chipset transmits and receives 27-bits of data (24-high speed color bits and 3 low speed
video control signals) over a single serial FPD-Link II pair operating at 140Mbps to 1.82Gbps. The serial stream
also contains an embedded clock, video control signals and the DC-balance information which enhances signal
quality and supports AC coupling. The pair is intended for use with each other but is backward-compatible with
previous generations of FPD-Link II as well.
The deserializer can attain lock to a data stream without the use of a separate reference clock source, which
greatly simplifies system complexity and overall cost. The deserializer also synchronizes to the serializer
regardless of the data pattern, delivering true automatic plug and lock performance. It can lock to the incoming
serial stream without the need of special training patterns or sync characters. The deserializer recovers the clock
and data by extracting the embedded clock information, validating and then deserializing the incoming data
stream providing a parallel LVCMOS video bus to the display.
The DS90UR90xQ-Q1 chipset can operate in 24-bit color depth (with VS,HS,DE encoded in the DCA bit) or in
18-bit color depth (with VS, HS, DE encoded in DCA or mapped into the high-speed data bits). In 18–bit color
applications, the three video signals maybe sent encoded via the DCA bit (restrictions apply) or sent as data bits
along with three additional general-purpose signals.
Functional Block Diagrams shows the diagrams for the chipsets.
8.2 Functional Block Diagrams
Figure 21. DS90UR905Q-Q1 – Serializer
C
1
C
0
D
C
A
D
C
B
b
0
b
1
b
2
b
3
b
4
b
5
b
6
b
7
b
8
b
9
b
1
0
b
1
1
b
1
2
b
1
3
b
1
4
b
1
5
b
1
6
b
1
7
b
1
8
b
1
9
b
2
0
b
2
1
b
2
2
b
2
3
RIN-
RIN+
Clock and
Data
Recovery
Timing and
Control
24
LOCK
PCLK
SSCG
Output Latch
Serial to Parallel
DC Balance Decoder
PASS
RGB [7:0]
HS
VS
DE
Error
Detector
PDB
BISTEN
CMF
SCL
SCA
ID[x]
STRAP INPUT
CONFIG [1:0]
LF_MODE
OS_PCLK/DATA
OSS_SEL
RFB
EQ [3:0]
OSC_SEL [2:0]
SSC [3:0]
MAPSEL [1:0]
STRAP INPUT
OP_LOW
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Functional Block Diagrams (continued)
Figure 22. DS90UR906Q-Q1 – Deserializer
8.3 Feature Description
8.3.1 Data Transfer
The DS90UR90xQ-Q1 chipset will transmit and receive a pixel of data in the following format: C1 and C0
represent the embedded clock in the serial stream. C1 is always HIGH and C0 is always LOW. b[23:0] contain
the scrambled RGB data. DCB is the DC-Balanced control bit. DCB is used to minimize the short and long-term
DC bias on the signal lines. This bit determines if the data is unmodified or inverted. DCA is used to validate data
integrity in the embedded data stream and can also contain encoded control (VS, HS, DE). Both DCA and DCB
coding schemes are generated by the serializer and decoded by the deserializer automatically. Figure 23
illustrates the serial stream per PCLK cycle.
NOTE
The figure only illustrates the bits but does not actually represent the bit location as the
bits are scrambled and balanced continuously.
Figure 23. FPD-Link II Serial Stream (DS90UR90xQ-Q1)
PCLK
IN
PCLK
OUT
HS/VS/DE
IN
HS/VS/DE
OUT
Latency
Pulses 1 or 2
PCLKs wide
Filetered OUT
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Feature Description (continued)
8.3.2 Video Control Signal Filter — Serializer and Deserializer
When operating the devices in Normal Mode, the Video Control Signals (DE, HS, VS) have the following
restrictions:
• Normal Mode with Control Signal Filter Enabled:
– DE and HS: Only 2 transitions per 130 clock cycles are transmitted, the transition pulse must be 3 PCLK
or longer.
• Normal Mode with Control Signal Filter Disabled:
– DE and HS: Only 2 transitions per 130 clock cycles are transmitted, no restriction on minimum transition
pulse.
• VS: Only 1 transition per 130 clock cycles are transmitted, minimum pulse width is 130 clock cycles.
Video Control Signals are defined as low frequency signals with limited transitions. Glitches of a control signal
can cause a visual display error. This feature allows for the chipset to validate and filter out any high frequency
noise on the control signals (see Figure 24).
Figure 24. Video Control Signal Filter Waveform
8.3.3 Serializer Functional Description
The serializer converts a wide parallel input bus to a single serial output data stream, and also acts as a signal
generator for the chipset Built-In Self Test (BIST) mode. The device can be configured via external pins or
through the optional serial control bus. The serializer features enhance signal quality on the link by supporting: a
selectable VOD level, a selectable de-emphasis signal conditioning and also the FPD-Link II data coding that
provides randomization, scrambling, and DC balancing of the video data. The serializer includes multiple features
to reduce EMI associated with display data transmission. This includes the randomization and scrambling of the
data and also the system spread spectrum PCLK support. The serializer features power saving features with a
sleep mode, auto stop clock feature, and optional LVCMOS (1.8 V) parallel bus compatibility.
See also the Functional Description of the chipset's serial control bus and BIST modes.
8.3.3.1 EMI Reduction Features
8.3.3.1.1 Serializer Spread Spectrum Compatibility
The serializer PCLK is capable of tracking spread spectrum clocking (SSC) from a host source. The PCLK will
accept spread spectrum tracking up to 35 kHz modulation and ±0.5, ±1 or ±2% deviations (center spread). The
maximum conditions for the PCLK input are: a modulation frequency of 35 kHz and amplitude deviations of ±2%
(4% total).
1.0E+02
R VALUE - LOG SCALE (:)
-14.00
-12.00
-10.00
-8.00
-6.00
-4.00
-2.00
0.00
DE-EMPH (dB)
VDD = 1.8V,
TA = 25oC
1.0E+03 1.0E+04 1.0E+05 1.0E+06
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Feature Description (continued)
8.3.3.2 Signal Quality Enhancers
8.3.3.2.1 Serializer VOD Select (VODSEL)
The serializer differential output voltage may be increased by setting the VODSEL pin High. When VODSEL is
Low, the VOD is at the standard (default) level. When VODSEL is High, the DC VOD is increased in level. The
increased VOD is useful in extremely high noise environments and also on extra long cable length applications.
When using de-emphasis it is recommended to set VODSEL = H to avoid excessive signal attenuation especially
with the larger de-emphasis settings. This feature may be controlled by the external pin or by register.
Table 1. Differential Output Voltage
INPUT EFFECT
VODSEL VOD (mV) VOD (mVp-p)
H ±420 840
L ±280 560
8.3.3.2.2 Serializer De-Emphasis (De-Emph)
The De-Emph pin controls the amount of de-emphasis beginning one full bit time after a logic transition that the
serializer drives. This is useful to counteract loading effects of long or lossy cables. This pin should be left open
for standard switching currents (no de-emphasis) or if controlled by register. De-emphasis is selected by
connecting a resistor on this pin to ground, with R value between 0.5 kΩto 1 MΩ, or by register setting. When
using De-Emphasis, TI recommends to set VODSEL = H.
Table 2. De-Emphasis Resistor Value
RESISTOR VALUE (KΩ) DE-EMPHASIS SETTING
Open Disabled
0.6 –12 dB
1.0 –9 dB
2.0 –6 dB
5.0 –3 dB
Figure 25. De-Emph vs. R value
8.3.3.3 Power-Saving Features
8.3.3.3.1 Serializer Power-down Feature (PDB)
The serializer has a PDB input pin to ENABLE or POWER DOWN the device. This pin is controlled by the host
and is used to save power, disabling the link when the display is not needed. In the power-down mode, the high-
speed driver outputs are both pulled to VDD and present a 0-V VOD state.
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NOTE
In power down, the optional Serial Bus Control Registers are RESET.
8.3.3.3.2 Serializer Stop Clock Feature
The serializer will enter a low power SLEEP state when the PCLK is stopped. A STOP condition is detected
when the input clock frequency is less than 3 MHz. The clock should be held at a static LOW or HIGH state.
When the PCLK starts again, the Ser will then lock to the valid input PCLK and then transmits the RGB data to
the deserializer.
NOTE
In STOP CLOCK SLEEP, the optional Serial Bus Control Registers values are
RETAINED.
8.3.3.3.3 1.8-V or 3.3-V VDDIO Operation
The serializer parallel bus and serial bus interface can operate with 1.8 V or 3.3 V levels (VDDIO) for host
compatibility. The 1.8 V levels will offer lower noise (EMI) and also a system power savings.
8.3.3.4 Serializer Pixel Clock Edge Select (RFB)
The RFB pin determines the edge that the data is latched on. If RFB is High, input data is latched on the Rising
edge of the PCLK. If RFB is Low, input data is latched on the Falling edge of the PCLK. serializer and
deserializer maybe set differently. This feature may be controlled by the external pin or by register.
8.3.3.5 Optional Serial Bus Control
See Optional Serial Bus Control.
8.3.3.6 Optional BIST Mode
See Built-In Self Test (BIST).
8.3.4 Deserializer Functional Description
The deserializer converts a single input serial data stream to a wide parallel output bus, and also provides a
signal check for the chipset Built-In Self Test (BIST) mode. The device can be configured via external pins and
strap pins or through the optional serial control bus. The deserializer features enhance signal quality on the link
by supporting: an equalizer input and also the FPD-Link II data coding that provides randomization, scrambling,
and DC balanacing of the data. The deserializer includes multiple features to reduce EMI associated with display
data transmission. This includes the randomization and scrambling of the data and also the output spread
spectrum clock generation (SSCG) support. The deserializer features power saving features with a power-down
mode, and optional LVCMOS (1.8 V) interface compatibility.
8.3.4.1 Signal Quality Enhancers
8.3.4.1.1 Deserializer Input Equalizer Gain (EQ)
The deserializer can enable receiver input equalization of the serial stream to increase the eye opening to the
deserializer input.
NOTE
This function cannot be seen at the RxIN± input but can be observed at the serial test port
(CMLOUTP/N) enabled through the Serial Bus control registers. The equalization feature
may be controlled by the external pin or by register.
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(1) Default Setting is EQ = Off
Table 3. Receiver Equalization Configuration Table
INPUTS EFFECT
EQ3 EQ2 EQ1 EQ0
L L L H ≈1.5 dB
L L H H ≈3 dB
L H L H ≈4.5 dB
L H H H ≈6 dB
H L L H ≈7.5 dB
H L H H ≈9 dB
H H L H ≈10.5 dB
HHHH≈12 dB
X X X L OFF(1)
8.3.4.2 EMI Reduction Features
8.3.4.2.1 Deserializer Output Slew (OS_PCLK/DATA)
The parallel bus outputs (RGB[7:0], VS, HS, DE and PCLK) of the deserializer feature a selectable output slew.
The DATA (RGB[7:0], VS, HS, DE) are controlled by strap pin or register bit OS_DATA. The PCLK is controlled
by strap pin or register bit OS_PCLK. When the OS_PCLK/DATA = HIGH, the maximum slew rate is selected.
When the OS_PCLK/DATA = LOW, the minimum slew rate is selected. Use the higher slew rate setting when
driving longer traces or a heavier capacitive load.
8.3.4.2.2 Deserializer Common-Mode Filter Pin (CMF) — Optional
The deserializer provides access to the center tap of the internal termination. A capacitor may be placed on this
pin for additional common-mode filtering of the differential pair. This can be useful in high noise environments for
additional noise rejection capability. A 0.1-µF capacitor may be connected to this pin to Ground.
8.3.4.2.3 Deserializer SSCG Generation — Optional
The deserializer provides an internally generated spread spectrum clock (SSCG) to modulate its outputs. Both
clock and data outputs are modulated. This will aid to lower system EMI. Output SSCG deviations to ±2.0% (4%
total) at up to 35kHz modulations nominally are available (see Table 4). This feature may be controlled by
external STRAP pins or by register.
Table 4. SSCG Configuration (LF_MODE = L) — Deserializer Output
SSC[3:0] INPUTS
LF_MODE = L (20 to 65 MHz) RESULT
SSC3 SSC2 SSC1 SSC0 FDEV (%) FMOD (kHz)
L L L L Off Off
L L L H ±0.5
PCLK/2168
L L H L ±1.0
L L H H ±1.5
L H L L ±2.0
L H L H ±0.5
PCLK/1300
L H H L ±1.0
L H H H ±1.5
H L L L ±2.0
H L L H ±0.5
PCLK/868
H L H L ±1.0
H L H H ±1.5
H H L L ±2.0
fdev(max)
FPCLK+
Frequency
Time
FPCLK-
FPCLK
fdev(min)
1/fmod
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Table 4. SSCG Configuration (LF_MODE = L) — Deserializer Output (continued)
SSC[3:0] INPUTS
LF_MODE = L (20 to 65 MHz) RESULT
SSC3 SSC2 SSC1 SSC0 FDEV (%) FMOD (kHz)
H H L H ±0.5 PCLK/650H H H L ±1.0
H H H H ±1.5
Table 5. SSCG Configuration (LF_MODE = H) — Deserializer Output
SSC[3:0] INPUTS
LH_MODE = H (5 to 20 MHz) RESULT
SSC3 SSC2 SSC1 SSC0 FDEV (%) FMOD (kHz)
L L L L Off Off
L L L H ±0.5
PCLK/620
L L H L ±1.0
L L H H ±1.5
L H L L ±2.0
L H L H ±0.5
PCLK/370
L H H L ±1.0
L H H H ±1.5
H L L L ±2.0
H L L H ±0.5
PCLK/258
H L H L ±1.0
H L H H ±1.5
H H L L ±2.0
H H L H ±0.5 PCLK/192H H H L ±1.0
H H H H ±1.5
Figure 26. SSCG Waveform
8.3.4.2.4 1.8-V or 3.3-V VDDIO Operation
The deserializer parallel bus and Serial Bus Interface can operate with 1.8 V or 3.3 V levels (VDDIO) for target
(Display) compatibility. The 1.8-V levels will offer a lower noise (EMI) and also a system power-savings.
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(1) If pin is strapped HIGH, output will be pulled up
8.3.4.3 Power-Saving Features
8.3.4.3.1 Deserializer Power-Down Feature (PDB)
The deserializer has a PDB input pin to ENABLE or POWER DOWN the device. This pin can be controlled by
the system to save power, disabling the deserializer when the display is not needed. An auto detect mode is also
available. In this mode, the PDB pin is tied High and the deserializer will enter power down when the serial
stream stops. When the serial stream starts up again, the deserializer will lock to the input stream and assert the
LOCK pin and output valid data. In power-down mode, the Data and PCLK output states are determined by the
OSS_SEL status.
NOTE
In power down, the optional Serial Bus Control Registers are RESET.
8.3.4.3.2 Deserializer Stop Stream SLEEP Feature
The deserializer will enter a low power SLEEP state when the input serial stream is stopped. A STOP condition
is detected when the embedded clock bits are not present. When the serial stream starts again, the deserializer
will then lock to the incoming signal and recover the data.
NOTE
In STOP STREAM SLEEP, the optional Serial Bus Control Registers values are
RETAINED.
8.3.4.4 Deserializer CLOCK-DATA RECOVERY STATUS FLAG (LOCK) and OUTPUT STATE SELECT
(OSS_SEL)
When PDB is driven HIGH, the CDR PLL begins locking to the serial input and LOCK goes from TRI-STATE to
LOW (depending on the value of the OSS_SEL setting). After the DS90UR906Q-Q1 completes its lock sequence
to the input serial data, the LOCK output is driven HIGH, indicating valid data and clock recovered from the serial
input is available on the parallel bus and PCLK outputs. The PCLK output is held at its current state at the
change from OSC_CLK (if this is enabled via OSC_SEL) to the recovered clock (or vice versa).
If there is a loss of clock from the input serial stream, LOCK is driven Low and the state of the RGB/VS/HS/DE
outputs are based on the OSS_SEL setting (STRAP PIN configuration or register).
8.3.4.5 Deserializer Oscillator Output (Optional)
The deserializer provides an optional PCLK output when the input clock (serial stream) has been lost. This is
based on an internal oscillator. The frequency of the oscillator may be selected. This feature may be controlled
by the external pin or by register (see Table 7 and Table 8).
Table 6. OSS_SEL and PDB Configuration — Deserializer Outputs(1)
INPUTS OUTPUTS
SERIAL
INPUT PDB OSS_SEL PCLK RGB/HS/VS/DE LOCK PASS
X L X Z Z Z Z
Static H L L L L L
Static H H Z Z* L L
Active H X Active Active H H
active serial stream X
PDB
(DES)
RIN
(Diff.)
LOCK
PCLK*
(DES)
PASS
OFF
OFF Active ActiveLocking
ZL
H
L
H
Z
H
Z Z Z
Z Z Z
Z Z
CONDITIONS: * RFB = L, and OSS_SEL = H
RGB[7:0],
HS, VS, DE
C0 or C1 Error
In Bit Stream
(Loss of LOCK)
L L
H
active serial stream X
PDB
(DES)
RIN
(Diff.)
LOCK
RGB[7:0],
HS, VS, DE
PCLK*
(DES)
PASS
OFF
OFF Active Active
C0 or C1 Error
In Bit Stream
(Loss of LOCK)
Locking
L
H
Z
H
Z
Z
L L L
L L L
CONDITIONS: * RFB = L, and OSS_SEL = L
L
LL
HH
Z
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(1) Absent and OSC_SEL ≠000
Table 7. OSC (Oscillator) Mode — Deserializer Output(1)
INPUTS OUTPUTS
EMBEDDED PCLK PCLK RGB/HS/VS/DE LOCK PASS
NOTE * OSC
Output LLL
Present Toggling Active H H
Figure 27. Deserializer Outputs With Output State Select Low (OSS_SEL = L)
Figure 28. Deserializer Outputs With Output State Select High (OSS_SEL = H)
active serial stream X
PDB
(DES)
RIN
(Diff.)
LOCK
RGB[7:0],
HS, VS, DE
PCLK*
(DES)
PASS
OFF
OFF Active ActiveLocking
L
H
Z
H
Z
L L L
L L
CONDITIONS: * RFB = L, OSS_SEL = H , and OSC_SEL not equal to 000.
ff
C0 or C1 Error
In Bit Stream
(Loss of LOCK)
Z
H
L
L
H
L
Z
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Table 8. OSC_SEL (Oscillator) Configuration
OSC_SEL[2:0] INPUTS PCLK OSCILLATOR OUTPUT
OSC_SEL2 OSC_SEL1 OSC_SEL0
L L L Off – Feature Disabled – Default
L L H 50 MHz ±40%
L H L 25 MHz ±40%
L H H 16.7 MHz ±40%
H L L 12.5 MHz ±40%
H L H 10 MHz ±40%
H H L 8.3 MHz ±40%
H H H 6.3 MHz ±40%
Figure 29. Deserializer Outputs with Output State High and PCLK Output Oscillator Option Enabled
8.3.4.6 Deserializer OP_LOW (Optional)
The OP_ LOW feature is used to hold the LVCMOS outputs (except the LOCK output) at a LOW state. The user
must toggle the OP_LOW Set / Reset register bit to release the outputs to the normal toggling state.
NOTE
The release of the outputs can only occur when LOCK is HIGH. When the OP_LOW
feature is enabled, anytime LOCK = LOW, the LVCMOS outputs will toggle to a LOW
state again. The OP_ LOW strap pin feature is assigned to output PASS pin 42.
Restrictions on other straps:
1. Other straps should not be used in order to keep RGB[7:0], HS, VS, DE, and PCLK at a true LOW state.
Other features should be selected through I2C.
2. OSS_SEL function is not available when O/P_LOW is tied H.
Outputs RGB[7:0], HSYNC, VSYNC, DE, and PCLK are in TRI-STATE before PDB toggles HIGH because the
OP_LOW strap value has not been recognized until the DS90UR906Q-Q1 powers up. Figure 30 shows the user
controlled release of OP_LOW and automatic reset of OP_LOW set on the falling edge of LOCK. Figure 31
shows the user controlled release of OP_LOW and manual reset of OP_LOW set.
PDB 2.0V
LOCK
OP_LOW
SET
(Strap pin)
RGB[7:0],
HS, VS, DE
OP_ LOW
RELEASE/SET
(Register)
TRI-
STATE
PCLK
User
controlled
TRI-
STATE
ACTIVE
ACTIVE
User
controlled
PDB 2.0V
LOCK
OP_ LOW
SET
(Strap pin)
RGB[7:0],
HS, VS, DE
OP_ LOW
RELEASE/SET
(Register)
TRI-
STATE
PCLK
User
controlled
User
controlled
TRI-
STATE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
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NOTE
Manual reset of OP_LOW can only occur when LOCK is H.
Figure 30. OP_LOW Auto Set
Figure 31. OP_LOW Manual Set/Reset
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8.3.4.7 Deserializer Pixel Clock Edge Select (RFB)
The RFB pin determines the edge that the data is strobed on. If RFB is High, output data is strobed on the Rising
edge of the PCLK. If RFB is Low, data is strobed on the Falling edge of the PCLK. This allows for inter-
operability with downstream devices. The deserializer output does not need to use the same edge as the
serializer input. This feature may be controlled by the external pin or by register.
8.3.4.8 Deserializer Control Signal Filter (Optional)
The deserializer provides an optional Control Signal (VS, HS, DE) filter that monitors the three video control
signals and eliminates any pulses that are 1 or 2 PCLKs wide. Control signals must be 3 pixel clocks wide (in its
HIGH or LOW state, regardless of which state is active). This is set by the CONFIG[1:0] or by the Control
Register. This feature may be controlled by the external pin or by Register.
8.3.4.9 Deserializer Low Frequency Optimization (LF_Mode)
This feature may be controlled by the external pin or by Register.
8.3.4.10 Deserializer Map Select
This feature may be controlled by the external pin or by register.
Table 9. Map Select Configuration
INPUTS Effect
MAPSEL1 MAPSEL0
L L Bit 4, Bit 5 on LSB
DEFAULT
L H LSB 0 or 1
H H or L LSB 0
8.3.4.11 Deserializer Strap Input Pins
Configuration of the device maybe done through configuration input pins and the STRAP input pins, or through
the Serial Control Bus. The STRAP input pins share select parallel bus output pins. They are used to load in
configuration values during the initial power-up sequence of the device. Only a pullup on the pin is required when
a HIGH is desired. By default the pad has an internal pulldown, and will bias Low by itself. The recommended
value of the pullup is 10 kΩto VDDIO; open (NC) for Low, no pulldown is required (internal pulldown). If using the
Serial Control Bus, no pullups are required.
8.3.4.12 Optional Serial Bus Control
See Optional Serial Bus Control.
8.3.4.13 Optional BIST Mode
See Built-In Self Test (BIST).
8.3.5 Built-In Self Test (BIST)
An optional At-Speed Built In Self Test (BIST) feature supports the testing of the high-speed serial link. This is
useful in the prototype stage, equipment production, in-system test and also for system diagnostics. In the BIST
mode only a input clock is required along with control to the serializer and deserializer BISTEN input pins. The
Ser outputs a test pattern (PRBS7) and drives the link at speed. The deserializer detects the PRBS7 pattern and
monitors it for errors. A PASS output pin toggles to flag any payloads that are received with 1 to 24 errors. Upon
completion of the test, the result of the test is held on the PASS output until reset (new BIST test or power
down). A high on PASS indicates NO ERRORS were detected. A Low on PASS indicates one or more errors
were detected. The duration of the test is controlled by the pulse width applied to the deserializer BISTEN pin.
During the BIST duration the deserializer data outputs toggle with a checkerboard pattern.
Inter-operability is supported between this FPD-Link II device and all FPD-Link II generations (Gen 1, 2, 3). See
Sample BIST Sequence for entering BIST mode and control.
Normal
BIST
start
BIST
stop
BIST
Wait
Step 1: SER in BIST
Step 2: Wait, DES in BIST
Step 3: DES in Normal
Mode - check PASS
Step 4: SER in Normal
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8.3.5.1 Sample BIST Sequence
See Figure 32 for the BIST mode flow diagram.
Step 1: Place the DS90UR905Q-Q1 serializer in BIST Mode by setting serializer BISTEN = H. For the
DS90UR905Q-Q1 serializer or DS99R421 FPD-Link II serializer BIST Mode is enabled through the BISTEN pin.
For the DS90C241 serializer or DS90UR241 serializer, BIST mode is enetered by setting all the input data of the
device to LOW state. A PCLK is required for all the serializer options. When the deserializer detects the BIST
mode pattern and command (DCA and DCB code) the RGB and control signal outputs are shut off.
Step 2: Place the DS90UR906Q-Q1 deserializer in BIST mode by setting the BISTEN = H. The deserializer is
now in the BIST mode and checks the incoming serial payloads for errors. If an error in the payload (1 to 24) is
detected, the PASS pin will switch low for one half of the clock period. During the BIST test, the PASS output can
be monitored and counted to determine the payload error rate.
Step 3: To Stop the BIST mode, the deserializer BISTEN pin is set Low. The deserializer stops checking the
data and the final test result is held on the PASS pin. If the test ran error free, the PASS output will be High. If
there was one or more errors detected, the PASS output will be Low. The PASS output state is held until a new
BIST is run, the device is RESET, or Powered Down. The BIST duration is user controlled by the duration of the
BISTEN signal.
Step 4: To return the link to normal operation, the serializer BISTEN input is set Low. The Link returns to normal
operation.
Figure 33 shows the waveform diagram of a typical BIST test for two cases. Case 1 is error free, and Case 2
shows one with multiple errors. In most cases it is difficult to generate errors due to the robustness of the link
(differential data transmission etc.), thus they may be introduced by greatly extending the cable length, faulting
the interconnect, reducing signal condition enhancements (De-Emphasis, VODSEL, or Rx Equalization).
Figure 32. BIST Mode Flow Diagram
8.3.5.2 BER Calculations
It is possible to calculate the approximate Bit Error Rate (BER). The following is required:
• Pixel Clock Frequency (MHz)
• BIST Duration (seconds)
• BIST test Result (PASS)
The BER is less than or equal to one over the product of 24 times the PCLK rate times the test duration. If we
assume a 65-MHz PCLK, a 10 minute (600 seconds) test, and a PASS, the BERT is ≤1.07 × 10E-12.
The BIST mode runs a check on the data payload bits. The LOCK pin also provides a link status. It the recovery
of the C0 and C1 bits does not reconstruct the expected clock signal, the LOCK pin will switch Low. The
combination of the LOCK and At-Speed BIST PASS pin provides a powerful tool for system evaluation and
performance monitoring.
X XX
PCLK
(RFB = L)
BISTEN
(DES)
PASS
DATA
(internal)
PASS
BIST Duration
Prior Result
BIST
Result
Held
PASS
FAIL
X = bit error(s)
BISTEN
(SER)
RGB[7:0]
HS, VS, DE
DATA
(internal)
Case 1 - Pass Case 2 - Fail
Prior Result
Normal PRBS BIST Test Normal
DES Outputs
SER
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Figure 33. BIST Waveforms
SDA
SCL
S P
START condition, or
START repeat condition
STOP condition
HOST
SER
or
DES
SCL
SDA
4.7k 4.7k
10 k
RID
SCL
SDA
To other
Devices
ID[X]
1.8V
VDDIO
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8.3.6 Optional Serial Bus Control
The serializer and deserializer may also be configured by the use of a serial control bus that is I2C protocol
compatible. By default, the I2C reg_0x00'h is set to 00'h and all configuration is set by control/strap pins. A write
of 01'h to reg_0x00'h will enable or allow configuration by registers; this will override the control/strap pins.
Multiple devices may share the serial control bus since multiple addresses are supported (see Figure 34).
The serial bus is comprised of three pins. The SCL is a serial bus clock Input. The SDA is the serial bus data
input/output signal. Both SCL and SDA signals require an external pullup resistor to VDDIO. For most applications
a 4.7-k pullup resistor to VDDIO may be used. The resistor value may be adjusted for capacitive loading and data
rate requirements. The signals are either pulled High, or driven Low.
Figure 34. Serial Control Bus Connection
The third pin is the ID[X] pin. This pin sets one of four possible device addresses. Two different connections are
possible. The pin may be pulled to VDD (1.8V, NOT VDDIO) with a 10 kΩresistor; or a 10-kΩpullup resistor (to
VDD1.8V, NOT VDDIO) and a pulldown resistor of the recommended value to set other three possible addresses
may be used. See Table 10 for the serializer and Table 11 for the deserializer. Do not tie ID[x] directly to VSS.
The Serial Bus protocol is controlled by START, START-Repeated, and STOP phases. A START occurs when
SCL transitions Low while SDA is High. A STOP occurs when SDA transition High while SCL is also HIGH (see
Figure 35).
Figure 35. START and STOP Conditions
To communicate with a remote device, the host controller (master) sends the slave address and listens for a
response from the slave. This response is referred to as an acknowledge bit (ACK). If a slave on the bus is
addressed correctly, it Acknowledges (ACKs) the master by driving the SDA bus low. If the address doesn't
match a device's slave address, it Not-acknowledges (NACKs) the master by letting SDA be pulled High. ACKs
also occur on the bus when data is being transmitted. When the master is writing data, the slave ACKs after
every data byte is successfully received. When the master is reading data, the master ACKs after every data
byte is received to let the slave know it wants to receive another data byte. When the master wants to stop
reading, it NACKs after the last data byte and creates a stop condition on the bus. All communication on the bus
begins with either a Start condition or a Repeated Start condition. All communication on the bus ends with a Stop
condition. A READ is shown in Figure 36 and a WRITE is shown in Figure 37.
NOTE
During initial power-up, a delay of 10 ms will be required before the I2C will respond.
Slave Address Register Address Data
S0a
c
k
a
c
k
a
c
kP
A
0
A
1
A
2
Slave Address Register Address Slave Address Data
S01
a
c
k
a
c
k
a
c
k
a
c
k
S P
A
0
A
1
A
2A
1
A
2
A
0
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(1) RID ≠0Ω, do not connect directly to VSS (GND), this is not a valid address.
If the Serial Bus is not required, the three pins may be left open (NC).
Table 10. ID[x] Resistor Value – DS90UR905Q-Q1 Serializer
RESISTOR
RID(1) kΩ(5% TOL) ADDRESS
7'b ADDRESS
8'b
0 APPENDED
(WRITE)
0.47 7b' 110 1001 (h'69) 8b' 1101 0010 (h'D2)
2.7 7b' 110 1010 (h'6A) 8b' 1101 0100 (h'D4)
8.2 7b' 110 1011 (h'6B) 8b' 1101 0110 (h'D6)
Open 7b' 110 1110 (h'6E) 8b' 1101 1100 (h'DC)
(1) RID ≠0Ω, do not connect directly to VSS (GND), this is not a valid address.
Table 11. ID[x] Resistor Value – DS90UR906Q-Q1 Deserializer
RESISTOR
RID(1) kΩ(5% TOL) ADDRESS
7'b ADDRESS
8'b
0 APPENDED
(WRITE)
0.47 7b' 111 0001 (h'71) 8b' 1110 0010 (h'E2)
2.7 7b' 111 0010 (h'72) 8b' 1110 0100 (h'E4)
8.2 7b' 111 0011 (h'73) 8b' 1110 0110 (h'E6)
Open 7b' 111 0110 (h'76) 8b' 1110 1100 (h'EC)
Figure 36. Serial Control Bus — READ
Figure 37. Serial Control Bus — WRITE
8.4 Device Functional Modes
8.4.1 Serializer and Deserializer Operating Modes and Backward Compatibility (CONFIG[1:0])
The DS90UR90xQ-Q1 chipset is also backward-compatible with previous generations of FPD-Link II.
Configuration modes are provided for backwards compatibility with the DS90C241 / DS90C124 FPD-Link II
Generation 1, and also the DS90UR241 / DS90UR124 FPD-Link II Generation 2 chipset by setting the respective
mode with the CONFIG[1:0] pins on the serializer or deserializer as shown in Table 12 and Table 13. The
selection also determine whether the Video Control Signal filter feature is enabled or disabled in Normal mode.
This feature may be controlled by pin or by Register.
Table 12. DS90UR905Q-Q1 Serializer Modes
CONFIG1 CONFIG0 MODE DESERIALIZER DEVICE
L L Normal Mode, Control Signal Filter disabled DS90UR906Q-Q1
L H Normal Mode, Control Signal Filter enabled DS90UR906Q-Q1
H L Backwards-Compatible GEN2 DS90UR124, DS99R124
H H Backwards-Compatible GEN1 DS90C124
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Table 13. DS90UR906Q Deserializer Modes
CONFIG1 CONFIG0 MODE SERIALIZER DEVICE
L L Normal Mode, Control Signal Filter disabled DS90UR905Q-Q1
L H Normal Mode, Control Signal Filter enabled DS90UR905Q-Q1
H L Backwards-Compatible GEN2 DS90UR241
H H Backwards-Compatible GEN1 DS90C241
8.5 Register Maps
Table 14. SERIALIZER — Serial Bus Control Registers
ADD
(DEC) ADD
(HEX) REGISTER
NAME BIT(S) R/W DEFAULT
(BIN) FUNCTION DESCRIPTION
0 0 Serializer
Config 1
7 R/W 0 Reserved Reserved
6 R/W 0 Reserved Reserved
5 R/W 0 VODSEL 0: Low
1: High
4 R/W 0 RFB 0: Data latched on Falling edge of PCLK
1: Data latched on Rising edge of PCLK
3:2 R/W 00 CONFIG 00: Control Signal Filter Disabled
01: Control Signal Filter Enabled
10: DS90UR124, DS99R124 Mode
11: DS90C124 Mode
1 R/W 0 SLEEP Note – not the same function as PowerDown (PDB)
0: normal mode
1: Sleep Mode – Register settings retained.
0 R/W 0 REG 0: Configurations set from control pins
1: Configuration set from registers (except I2C_ID)
1 1 Device ID
7 R/W 0 REG ID 0: Address from ID[x] Pin
1: Address from Register
6:0 R/W 1101000 ID[X]
Serial Bus Device ID, Four IDs are:
7b '1101 001 (h'69)
7b '1101 010 (h'6A)
7b '1101 011 (h'6B)
7b '1101 110 (h'6E)
All other addresses are Reserved.
2 2 De-Emphasis
Control
7:5 R/W 000 De-E Setting
000: set by external Resistor
001: –1 dB
010: –2 dB
011: –3.3 dB
100: –5 dB
101: –6.7 dB
110: –9 dB
111: –12 dB
4 R/W 0 De-E EN 0: De-Emphasis Enabled
1: De-Emphasis Disabled
3:0 R/W 000 Reserved Reserved
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Table 15. DESERIALIZER — Serial Bus Control Registers
ADD
(DEC) ADD
(HEX) REGISTER
NAME BIT(S) R/W DEFAULT
(BIN) FUNCTION DESCRIPTION
0 0 Deserializer
Config 1
7 R/W 0 LFMODE 0: 20 to 65 MHz Operation
1: 5 to 20 MHz Operation
6 R/W 0 OS_PCLK 0: Normal PCLK Output Slew
1: Increased PCLK Slew
5 R/W 0 OS_DATA 0: Normal DATA OUTPUT Slew
1: Increased Data Slew
4 R/W 0 RFB 0: Data strobed on Falling edge of PCLK
1: Data strobed on Rising edge of PCLK
3:2 R/W 00 CONFIG 00: Normal Mode, Control Signal Filter Disabled
01: Normal Mode, Control Signal Filter Enabled
10: Backwards-Compatible (DS90UR241)
11: Backwards-Compatible (DS90C241)
1 R/W 0 SLEEP Note – not the same function as PowerDown (PDB)
0: normal mode
1: Sleep Mode – Register settings retained.
0 R/W 0 REG Control 0: Configurations set from control pins / STRAP pins
1: Configurations set from registers (except I2C_ID)
1 1 Slave ID
7 R/W 0 0: Address from ID[X] Pin
1: Address from Register
6:0 R/W 1110000 ID[X]
Serial Bus Device ID, Four IDs are:
7b '1110 001 (h'71)
7b '1110 010 (h'72)
7b '1110 011 (h'73)
7b '1110 110 (h'76)
All other addresses are Reserved.
2 2 Deserializer
Features 1
7 R/W 0 OP_LOW
Release/Set
0: set outputs state LOW (except LOCK)
1: release output LOW state, outputs toggling
normally
Note: This register only works during LOCK = 1.
6 R/W 0 OSS_SEL
Output Sleep State Select
0: PCLK/RGB[7:0]/HS/VS/DE = L, LOCK = Normal,
PASS = H
1: PCLK/RGB[7:0]/HS/VS/DE = Tri-State, LOCK =
Normal, PASS = H
5:4 R/W 00 MAP_SEL
Special for Backwards-Compatible Mode
00: bit 4, 5 on LSB
01: LSB zero if all data is zero; one if any data is one
10: LSB zero
11: LSB zero
3 R/W 0 OP_LOW
strap bypass 0: strap will determine whether OP_LOW feature is
ON or OFF
1: Turns OFF OP_LOW feature
2:0 R/W 00 OSC_SEL
000: OFF
001: 50 MHz ±40%
010: 25 MHz ±40%
011: 16.7 MHz ±40%
100: 12.5 MHz ±40%
101: 10 MHz ±40%
110: 8.3 MHz ±40%
111: 6.3 MHz ±40%
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Table 15. DESERIALIZER — Serial Bus Control Registers (continued)
ADD
(DEC) ADD
(HEX) REGISTER
NAME BIT(S) R/W DEFAULT
(BIN) FUNCTION DESCRIPTION
3 3 Deserializer
Features 2
7:5 R/W 000 EQ Gain
000: ≈1.625 dB
001: ≈3.25 dB
010: ≈4.87 dB
011: ≈6.5 dB
100: ≈8.125 dB
101: ≈9.75 dB
110: ≈11.375 dB
111: ≈13 dB
4 R/W 0 EQ Enable 0: EQ = disabled
1: EQ = enabled
3:0 R/W 0000 SSC
IF LF_MODE = 0, then:
000: SSCG OFF
0001: fdev = ±0.5%, fmod = PCLK/2168
0010: fdev = ±1.0%, fmod = PCLK/2168
0011: fdev = ±1.5%, fmod = PCLK/2168
0100: fdev = ±2.0%, fmod = PCLK/2168
0101: fdev = ±0.5%, fmod = PCLK/1300
0110: fdev = ±1.0%, fmod = PCLK/1300
0111: fdev = ±1.5%, fmod = PCLK/1300
1000: fdev = ±2.0%, fmod = PCLK/1300
1001: fdev = ±0.5%, fmod = PCLK/868
1010: fdev = ±1.0%, fmod = PCLK/868
1011: fdev = ±1.5%, fmod = PCLK/868
1100: fdev = ±2.0%, fmod = PCLK/868
1101: fdev = ±0.5%, fmod = PCLK/650
1110: fdev = ±1.0%, fmod = PCLK/650
1111: fdev = ±1.5%, fmod = PCLK/650
IF LF_MODE = 1, then:
000: SSCG OFF
0001: fdev = ±0.5%, fmod = PCLK/620
0010: fdev = ±1.0%, fmod = PCLK/620
0011: fdev = ±1.5%, fmod = PCLK/620
0100: fdev = ±2.0%, fmod = PCLK/620
0101: fdev = ±0.5%, fmod = PCLK/370
0110: fdev = ±1.0%, fmod = PCLK/370
0111: fdev = ±1.5%, fmod = PCLK/370
1000: fdev = ±2.0%, fmod = PCLK/370
1001: fdev = ±0.5%, fmod = PCLK/258
1010: fdev = ±1.0%, fmod = PCLK/258
1011: fdev = ±1.5%, fmod = PCLK/258
1100: fdev = ±2.0%, fmod = PCLK/258
1101: fdev = ±0.5%, fmod = PCLK/192
1110: fdev = ±1.0%, fmod = PCLK/192
1111: fdev = ±1.5%, fmod = PCLK/192
4 4 CMLOUT Config 7 R/W 0 Repeater
Enable 0: Output CMLOUTP/N = disabled
1: Output CMLOUTP/N = enabled
6:0 R/W 0000000 Reserved Reserved
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
9.1.1 Display Application
The DS90UR90xQ-Q1 chipset is intended for interface between a host (graphics processor) and a display. It
supports an 24-bit color depth (RGB888) and up to 1024 × 768 display formats. In a RGB888 application, 24
color bits (R[7:0], G[7:0], B[7:0]), Pixel Clock (PCLK) and three control bits (VS, HS and DE) are supported
across the serial link with PCLK rates from 5 to 65 MHz. The chipset may also be used in 18-bit color
applications. In this application three to six general-purpose signals may also be sent from host to display.
The deserializer is expected to be located close to its target device. The interconnect between the deserializer
and the target device is typically in the 1 to 3 inch separation range. The input capacitance of the target device is
expected to be in the 5 to 10 pF range. Care should be taken on the PCLK output trace as this signal is edge
sensitive and strobes the data. It is also assumed that the fanout of the deserializer is one. If additional loads
need to be driven, a logic buffer or mux device is recommended.
9.1.2 Live Link Insertion
The serializer and deserializer devices support live pluggable applications. The automatic receiver lock to
random data “plug & go” hot insertion capability allows the DS90UR906Q-Q1 to attain lock to the active data
stream during a live insertion event.
9.1.3 Alternate Color / Data Mapping
Color Mapped data Pin names are provided to specify a recommended mapping for 24-bit Color Applications.
Seven [7] is assumed to be the MSB, and Zero [0] is assumed to be the LSB. While this is recommended it is not
required. When connecting to earlier generations of FPD-Link II serializer and deserializer devices, a color
mapping review is recommended to ensure the correct connectivity is obtained. Table 16 provides examples for
interfacing to 18-bit applications with or without the video control signals embedded. The DS90UR906Q-Q1
deserializer also provides additional flexibility with the MAP_SEL feature as well.
Table 16. Alternate Color / Data Mapping
18-BIT RGB 18-BIT RGB 24-BIT RGB 905 PIN NAME 906 PIN NAME 24-BIT RGB 18-BIT RGB 18-BIT RGB
LSB R0 GP0 RO RO R0 R0 GP0 LSB R0
R1 GP1 R1 R1 R1 R1 GP1 R1
R2 R0 R2 R2 R2 R2 R0 R2
R3 R1 R3 R3 R3 R3 R1 R3
R4 R2 R4 R4 R4 R4 R2 R4
MSB R5 R3 R5 R5 R5 R5 R3 MSB R5
LSB G0 R4 R6 R6 R6 R6 R4 LSB G0
G1 R5 R7 R7 R7 R7 R5 G1
G2 GP2 G0 G0 G0 G0 GP2 G2
G3 GP3 G1 G1 G1 G1 GP3 G3
G4 GO G2 G2 G2 G2 G0 G4
MSB G5 G1 G3 G3 G3 G3 G1 MSB G5
LSB B0 G2 G4 G4 G4 G4 G2 LSB0
B1 G3 G5 G5 G5 G5 G3 B1
B2 G4 G6 G6 G6 G6 G4 B2
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Application Information (continued)
Table 16. Alternate Color / Data Mapping (continued)
18-BIT RGB 18-BIT RGB 24-BIT RGB 905 PIN NAME 906 PIN NAME 24-BIT RGB 18-BIT RGB 18-BIT RGB
(1) Scenario 3 supports an 18-bit RGB color mapping, 3 un-embedded video control signals, and up to three general-purpose signals.
(2) Scenario 2 supports an 18-bit RGB color mapping, 3 embedded video control signals, and up to six general-purpose signals.
(3) Scenario 1 supports the 24-bit RGB color mapping, along with the 3 embedded video control signals. This is the native mode for the
chipset.
B3 G5 G7 G7 G7 G7 G5 B3
B4 GP4 B0 B0 B0 B0 GP4 B4
MSB B5 GP5 B1 B1 B1 B1 GP5 MSB B5
HS B0 B2 B2 B2 B2 B0 HS
VS B1 B3 B3 B3 B3 B1 VS
DE B2 B4 B4 B4 B4 B2 DE
GP0 B3 B5 B5 B5 B5 B3 GP0
GP1 B4 B6 B6 B6 B6 B4 GP1
GP2 B5 B7 B7 B7 B7 B5 GP2
GND HS HS HS HS HS HS GND
GND VS VS VS VS VS VS GND
GND DE DE DE DE DE DE GND
Scenario 3(1) Scenario 2(2) Scenario 1(3) 905 Pin Name 906 Pin Name Scenario 1(3) Scenario 2(2) Scenario 3(1)
9.2 Typical Applications
9.2.1 DS90UR905Q-Q1 Typical Connection
Figure 38 shows a typical application of the DS90UR905Q-Q1 serializer in Pin control mode for a 65 MHz 24-bit
Color Display Application. The LVDS outputs require 100-nF AC-coupling capacitors to the line. The line driver
includes internal termination. Bypass capacitors are placed near the power supply pins. At a minimum, four 0.1
µF capacitors and a 4.7-µF capacitor should be used for local device bypassing. System GPO (General-Purpose
Output) signals control the PDB and BISTEN pins. In this application the RFB pin is tied Low to latch data on the
falling edge of the PCLK. The application assumes the companion deserializer (DS90UR906Q-Q1) therefore the
configuration pins are also both tied Low. In this example the cable is long, therefore the VODSEL pin is tied
High and a De-Emphasis value is selected by the resistor R1. The interface to the host is with 1.8-V LVCMOS
levels, thus the VDDIO pin is connected also to the 1.8-V rail. The Optional Serial Bus Control is not used in this
example, thus the SCL, SDA and ID[x] pins are left open. A delay cap is placed on the PDB signal to delay the
enabling of the device until power is stable.
R7
R6
R5
R4
R3
R2
R1
R0
G7
G6
G5
G4
G3
G2
G1
G0
B7
B6
B5
B4
B3
B2
B1
B0
PCLK
PDB
DOUT+
DOUT-
VDDL
R1
De-Emph
DAP (GND)
VDDP
VDDHS
VDDTX
VDDIO
1.8V
DS90UR905Q (SER)
C4
C11 C5
C6
C1
C2
NOTE:
C1-C2 = 0.1 PF (50 WV)
C3-C8 = 0.1 PF
C9-11 = 4.7 PF
C12 = >10 PF
R1 (cable specific)
RID (see ID[x] Resistor Value Table 12)
FB1-FB4: Impedance = 1 k:,
low DC resistance (<1:)
LVCMOS
Parallel
Video
Interface
Serial
FPD-Link II
Interface
VS
DE
HS
BISTEN
CONFIG1
CONFIG1
RFB
VODSEL
SCL
SDA
ID[X]
VDDIO
RES2
RES1
RES0
C3
C12
LVCMOS
Control
Interface
VDDIO
1.8V
RID
10k
C8
C7
C9 C10
FB1 FB2
FB3
FB4
44
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Typical Applications (continued)
Figure 38. DS90UR905Q-Q1 Typical Connection Diagram – Pin Control
9.2.1.1 Design Requirements
For this example, use the parameters listed in Table 17.
Table 17. Design Parameters
DESIGN PARAMETERS EXAMPLE VALUE
VDDIO 1.8 V to 3.3 V
VDDL, VDDP, VDDHS, VDDTX 1.8 V
AC-Coupling Capacitor for DOUT± 100 nF
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9.2.1.2 Detailed Design Procedure
The DOUT± outputs require 100-nF AC-coupling capacitors to the line. The power supply filter capacitors are
placed near the power supply pins. A smaller capacitance capacitor should be located closer to the power supply
pins.
The VODSEL pin is tied to VDDIO for the long cable application. The De-Emph pin may connect a resistor to
ground. Refer to Table 2. The PDB and BISTEN pins are assumed controlling by a microprocessor. The PDB
has to be LOW state until all power supply voltages reach the final voltage. The RFB pin is tied Low to latch data
on the falling edge of the PCLK, High for the rising clock edge. The CNFIG[1:0] pins are set depending on
operating modes and backward compatibility. The SCL, SDA and ID[x] pins are left open when these Serial Bus
Control pins are unused. The RES[2:0] pins and DAP should be tied to ground.
9.2.1.3 Application Curves
Figure 39. Eye Diagram at PCLK = 5 MHz Figure 40. Eye Diagram at PCLK = 20 MHz
9.2.2 DS90UR906Q-Q1 Typical Connection
Figure 41 shows a typical application of the DS90UR906Q-Q1 deserializer in Pin/STRAP control mode for a 65-
MHz 24-bit Color Display Application. The LVDS inputs utilize 100-nF coupling capacitors to the line and the
receiver provides internal termination. Bypass capacitors are placed near the power supply pins. At a minimum,
seven 0.1-µF capacitors and two 4.7-µF capacitors should be used for local device bypassing. System GPO
(General-Purpose Output) signals control the PDB and the BISTEN pins. In this application the RRFB pin is tied
Low to strobe the data on the falling edge of the PCLK.
Since the device in the Pin/STRAP mode, four 10-kΩpullup resistors are used on the parallel output bus to
select the desired device features. CONFIG[1:0] is set to 01'b for Normal Mode and Control Signal Filter ON, this
is accomplished with the STRAP pullup on B7. The receiver input equalizer is also enabled and set to provide
7.5 dB of gain, this is accomplished with EQ[3:0] set to 1001'b with STRAP pullups on G4 and G7. To reduce
parallel bus EMI, the SSCG feature is enabled and set to 30 kHz and ±1% with SSC[3:0] set to 0010'b and a
STRAP pullup on R4. The desired features are set with the use of the four pullup resistors.
The interface to the target display is with 3.3V LVCMOS levels, thus the VDDIO pin is connected to the 3.3 V rail.
The optional Serial Bus Control is not used in this example, thus the SCL, SDA and ID[x] pins are left open. A
delay cap is placed on the PDB signal to delay the enabling of the device until power is stable.
R7
R6
R5
R4
R3
R2
R1
R0
G7
G6
G5
G4
G3
G2
G1
G0
B7
B6
B5
B4
B3
B2
B1
B0
HS
PDB
NC
DAP (GND)
ID[X]
SDA
SCL
8
RIN+
RIN-
VDDSC
VDDIO
VDDIO
VDDIO
LVCMOS
Parallel
Video
Interface
VDDIO
DS90UR906Q (DES)
C9
C10
C1
C2
C3
VDDL
BISTEN
RES
VS
DE
C4
1.8V
Serial
FPD-Link II
Interface
PCLK
LOCK
PASS
C8
C16 C6
C17 C7
CMF
VDDR
VDDIR
VDDCMLO
VDDPR
CMLOUTP
CMLOUTN
EXAMPLE:
STRAP
Input
Pull-Ups
(10k)
VDDIO
C13
TP_A
TP_B
Host
Control
C18
C1 - C2 = 0.1 PF (50 WV)
C3 - C12 = 0.1 PF
C13 - C17 = 4.7 PF
C18 = >10 PF
RID (see ID[x] Resistor Value Table 13)
FB1-FB6: Impedance = 1 k:,
low DC resistance (<1:)
C5
C14 C11 C12 C15
1.8V
RID
10k
FB1 FB2
FB3
FB4
FB5
FB6
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Figure 41. DS90UR906Q-Q1 Typical Connection Diagram — Pin Control
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9.2.2.1 Design Requirements
For this example, use the parameters listed in Table 18.
Table 18. Design Parameters
DESIGN PARAMETERS EXAMPLE VALUE
VDDIO 1.8 V to 3.3 V
VDDL, VDDSC, VDDPR, VDDR,
VDDIR, VDDCMLO 1.8 V
AC-Coupling Capacitor for DOUT± 100 nF
9.2.2.2 Detailed Design Procedure
The RIN± input require 100-nF AC-coupling capacitors to the line. The power supply filter capacitors are placed
near the power supply pins. A smaller capacitance capacitor should be located closer to the power supply pins.
The device has twenty-two Control and Configuration pins which are called STARTP pins. These pins include an
internal pulldown. For a HIGH state, use a 10-KΩresistor pulled up to VDDIO.
The PDB and BISTEN pins are assumed controlling by a microprocessor. The PDB has to be LOW state until all
power supply voltages reach the final voltage. The SCL, SDA and ID[x] pins are left open when these Serial Bus
Control pins are unused.
The RES pins and DAP should be tied to ground.
9.2.2.3 Application Curves
Figure 42. Eye Diagram at PCLK = 45 MHz Figure 43. Eye Diagram at PCLK = 65 MHz
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10 Power Supply Recommendations
10.1 Power Up Requirements and PDB Pin
The VDD (VDDn and VDDIO) supply ramp should be faster than 1.5 ms with a monotonic rise. If slower then 1.5 ms
then a capacitor on the PDB pin is needed to ensure PDB arrives after all the VDD have settled to the
recommended operating voltage. When PDB pin is pulled to VDDIO, it is recommended to use a 10-kΩpullup and
a > 10 µF capacitor to GND to delay the PDB input signal.
11 Layout
11.1 Layout Guidelines
Circuit board layout and stack-up for the LVDS serializer and deserializer devices should be designed to provide
low-noise power feed to the device. Good layout practice will also separate high frequency or high-level inputs
and outputs to minimize unwanted stray noise pickup, feedback and interference. Power system performance
may be greatly improved by using thin dielectrics (2 to 4 mils) for power / ground sandwiches. This arrangement
provides plane capacitance for the PCB power system with low-inductance parasitics, which has proven
especially effective at high frequencies, and makes the value and placement of external bypass capacitors less
critical. External bypass capacitors should include both RF ceramic and tantalum electrolytic types. RF capacitors
may use values in the range of 0.01 µF to 0.1 µF. Tantalum capacitors may be in the 2.2 µF to 10 µF range.
Voltage rating of the tantalum capacitors should be at least 5× the power supply voltage being used.
Surface mount capacitors are recommended due to their smaller parasitics. When using multiple capacitors per
supply pin, locate the smaller value closer to the pin. A large bulk capacitor is recommend at the point of power
entry. This is typically in the 50 µF to 100 µF range and will smooth low frequency switching noise. It is
recommended to connect power and ground pins directly to the power and ground planes with bypass capacitors
connected to the plane with via on both ends of the capacitor. Connecting power or ground pins to an external
bypass capacitor will increase the inductance of the path.
A small body size X7R chip capacitor, such as 0603, is recommended for external bypass. Its small body size
reduces the parasitic inductance of the capacitor. The user must pay attention to the resonance frequency of
these external bypass capacitors, usually in the range of 20-30 MHz. To provide effective bypassing, multiple
capacitors are often used to achieve low impedance between the supply rails over the frequency of interest. At
high frequency, it is also a common practice to use two vias from power and ground pins to the planes, reducing
the impedance at high frequency.
Some devices provide separate power and ground pins for different portions of the circuit. This is done to isolate
switching noise effects between different sections of the circuit. Separate planes on the PCB are typically not
required. Pin Description tables typically provide guidance on which circuit blocks are connected to which power
pin pairs. In some cases, an external filter many be used to provide clean power to sensitive circuits such as
PLLs.
Use at least a four layer board with a power and ground plane. Locate LVCMOS signals away from the LVDS
lines to prevent coupling from the LVCMOS lines to the LVDS lines. Closely-coupled differential lines of 100
Ohms are typically recommended for LVDS interconnect. The closely coupled lines help to ensure that coupled
noise will appear as common-mode and thus is rejected by the receivers. The tightly coupled lines will also
radiate less.
Information on the WQFN style package is provided in Leadless Leadframe Package (LLP) Application Report
(SNOA401).
11.1.1 Transmission Media
The serializer and deserializer chipset is intended to be used in a point-to-point configuration, through a PCB
trace, or through twisted pair cable. The serializer and deserializer provide internal terminations providing a clean
signaling environment. The interconnect for LVDS should present a differential impedance of 100 Ohms. Use
cables and connectors that have matched differential impedance to minimize impedance discontinuities. Shielded
or un-shielded cables may be used depending upon the noise environment and application requirements.
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Layout Guidelines (continued)
11.1.2 LVDS Interconnect Guidelines
See AN-1108 Channel-Link PCB and Interconnect Design-In Guidelines (SNLA008) and AN-905 Transmission
Line RAPIDESIGNER Operation and Applications Guide (SNLA035) for full details.
• Use 100-Ωcoupled differential pairs
• Use the S, 2S, 3S rule in spacings
– S = space between the pair
– 2S = space between pairs
– 3S = space to LVCMOS signal
• Minimize the number of Vias
• Use differential connectors when operating above 500-Mbps line speed
• Maintain balance of the traces
• Minimize skew within the pair
• Terminate as close to the TX outputs and RX inputs as possible
Additional general guidance can be found in the LVDS Owner’s Manual - available in PDF format from the TI
web site at: www.ti.com/lvds
11.2 Layout Example
Figure 44 and Figure 45 show the PCB layout example derived from the layout design of the DS90UR905Q-Q1
and DS90UR906Q-Q1 Evaluation Boards. The graphic and layout description are used to determine both proper
routing and proper solder techniques for designing the board.
Figure 44. DS90UR905Q-Q1 Serializer Example Layout
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation, see the following:
• AN-1108 Leadless Leadframe Package (LLP) Application Report (SNOA401)
•Channel-Link PCB and Interconnect Design-In Guidelines (SNLA008)
• AN-905 Transmission Line RAPIDESIGNER Operation and Applications Guide (SNLA035)
12.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 19. Related Links
PARTS PRODUCT FOLDER SAMPLE & BUY TECHNICAL
DOCUMENTS TOOLS &
SOFTWARE SUPPORT &
COMMUNITY
DS90UR905Q-Q1 Click here Click here Click here Click here Click here
DS90UR906Q-Q1 Click here Click here Click here Click here Click here
12.3 Community Resource
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.6 Glossary
SLYZ022 —TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
PACKAGE OPTION ADDENDUM
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Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
DS90UR905QSQ/NOPB ACTIVE WQFN RHS 48 1000 RoHS & Green SN Level-3-260C-168 HR -40 to 105 UR905QSQ
DS90UR905QSQE/NOPB ACTIVE WQFN RHS 48 250 RoHS & Green SN Level-3-260C-168 HR -40 to 105 UR905QSQ
DS90UR905QSQX/NOPB ACTIVE WQFN RHS 48 2500 RoHS & Green SN Level-3-260C-168 HR -40 to 105 UR905QSQ
DS90UR906QSQ/NOPB ACTIVE WQFN NKB 60 1000 RoHS & Green SN Level-3-260C-168 HR -40 to 105 UR906QSQ
DS90UR906QSQE/NOPB ACTIVE WQFN NKB 60 250 RoHS & Green SN Level-3-260C-168 HR -40 to 105 UR906QSQ
DS90UR906QSQX/NOPB ACTIVE WQFN NKB 60 2000 RoHS & Green SN Level-3-260C-168 HR -40 to 105 UR906QSQ
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
Addendum-Page 2
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
DS90UR905QSQ/NOPB WQFN RHS 48 1000 330.0 16.4 7.3 7.3 1.3 12.0 16.0 Q1
DS90UR905QSQE/NOPB WQFN RHS 48 250 178.0 16.4 7.3 7.3 1.3 12.0 16.0 Q1
DS90UR905QSQX/NOPB WQFN RHS 48 2500 330.0 16.4 7.3 7.3 1.3 12.0 16.0 Q1
DS90UR906QSQ/NOPB WQFN NKB 60 1000 330.0 16.4 9.3 9.3 1.3 12.0 16.0 Q1
DS90UR906QSQE/NOPB WQFN NKB 60 250 178.0 16.4 9.3 9.3 1.3 12.0 16.0 Q1
DS90UR906QSQX/NOPB WQFN NKB 60 2000 330.0 16.4 9.3 9.3 1.3 12.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 2-Oct-2019
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
DS90UR905QSQ/NOPB WQFN RHS 48 1000 367.0 367.0 38.0
DS90UR905QSQE/NOPB WQFN RHS 48 250 210.0 185.0 35.0
DS90UR905QSQX/NOPB WQFN RHS 48 2500 367.0 367.0 38.0
DS90UR906QSQ/NOPB WQFN NKB 60 1000 367.0 367.0 38.0
DS90UR906QSQE/NOPB WQFN NKB 60 250 210.0 185.0 35.0
DS90UR906QSQX/NOPB WQFN NKB 60 2000 367.0 367.0 38.0
PACKAGE MATERIALS INFORMATION
www.ti.com 2-Oct-2019
Pack Materials-Page 2
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PACKAGE OUTLINE
C
9.1
8.9
9.1
8.9
0.8
0.7
0.05
0.00
2X 7
56X 0.5
2X 7
60X 0.7
0.5
60X 0.3
0.2
6.3 0.1
(0.1) TYP
VQFN - 0.8 mm max heightNKB0060B
PLASTIC QUAD FLATPACK - NO LEAD
4214995/A 03/2018
0.08 C
0.1 C A B
0.05
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
PIN 1 INDEX AREA
SEATING PLANE
PIN 1 ID
SYMM
EXPOSED
THERMAL PAD
SYMM
1
15
16 30
31
45
46
60
61
SCALE 1.500
A
B
www.ti.com
EXAMPLE BOARD LAYOUT
56X (0.5)
(R0.05) TYP
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
60X (0.8)
60X (0.25)
(8.6)
(8.6)
( 6.3)
( 0.2) TYP
VIA
(0.6) TYP
(1.2) TYP
(1.1) TYP
(0.6) TYP
(1.2) TYP (1.1) TYP
VQFN - 0.8 mm max heightNKB0060B
PLASTIC QUAD FLATPACK - NO LEAD
4214995/A 03/2018
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
SYMM
SYMM
SEE SOLDER MASK
DETAIL
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 8X
1
15
16 30
31
45
46
60
61
METAL EDGE
SOLDER MASK
OPENING
EXPOSED METAL
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
EXPOSED
METAL
NON SOLDER MASK
DEFINED
(PREFERRED) SOLDER MASK DEFINED
SOLDER MASK DETAILS
www.ti.com
EXAMPLE STENCIL DESIGN
60X (0.8)
60X (0.25)
56X (0.5)
(8.6)
(8.6)
25X ( 1)
(R0.05) TYP
(1.2) TYP
(1.2) TYP
VQFN - 0.8 mm max heightNKB0060B
PLASTIC QUAD FLATPACK - NO LEAD
4214995/A 03/2018
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
SOLDER PASTE EXAMPLE
BASED ON 0.125 MM THICK STENCIL
SCALE: 8X
EXPOSED PAD 61
63% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SYMM
SYMM
1
15
16 30
31
45
46
60
61
www.ti.com
PACKAGE OUTLINE
C
SEE TERMINAL
DETAIL
48X 0.30
0.18
5.1 0.1
48X 0.5
0.3
0.8
0.7
(A) TYP
0.05
0.00
44X 0.5
2X
5.5
2X 5.5
A7.15
6.85 B
7.15
6.85
0.30
0.18
0.5
0.3
(0.2)
WQFN - 0.8 mm max heightRHS0048A
PLASTIC QUAD FLATPACK - NO LEAD
4214990/B 04/2018
DIM A
OPT 1 OPT 2
(0.1) (0.2)
PIN 1 INDEX AREA
0.08 C
SEATING PLANE
1
12 25
36
13 24
48 37
(OPTIONAL)
PIN 1 ID 0.1 C A B
0.05
EXPOSED
THERMAL PAD
49 SYMM
SYMM
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
SCALE 1.800
DETAIL
OPTIONAL TERMINAL
TYPICAL
www.ti.com
EXAMPLE BOARD LAYOUT
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
48X (0.25)
48X (0.6)
( 0.2) TYP
VIA
44X (0.5)
(6.8)
(6.8)
(1.25) TYP
( 5.1)
(R0.05)
TYP
(1.25)
TYP
(1.05) TYP
(1.05)
TYP
WQFN - 0.8 mm max heightRHS0048A
PLASTIC QUAD FLATPACK - NO LEAD
4214990/B 04/2018
SYMM
1
12
13 24
25
36
37
48
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:12X
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
49
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
EXPOSED
METAL
METAL EDGE
SOLDER MASK
OPENING
SOLDER MASK DETAILS
NON SOLDER MASK
DEFINED
(PREFERRED)
EXPOSED
METAL
www.ti.com
EXAMPLE STENCIL DESIGN
48X (0.6)
48X (0.25)
44X (0.5)
(6.8)
(6.8)
16X
( 1.05)
(0.625) TYP
(R0.05) TYP
(1.25)
TYP
(1.25)
TYP
(0.625) TYP
WQFN - 0.8 mm max heightRHS0048A
PLASTIC QUAD FLATPACK - NO LEAD
4214990/B 04/2018
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
49
SYMM
METAL
TYP
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 49
68% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:15X
SYMM
1
12
13 24
25
36
37
48
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