®
Alt er a Cor pora t ion 1
MAX 7000
Programmable Logic
Device Family
Dec emb er 2002, ver. 6.5 Data Sheet
DS-MAX7000-6.5
Features... ■High-performance, EEPROM-ba sed progra mmab le logic devices
(PLDs) based on second-generation MAX® architecture
■5.0-V in-system programmability (ISP) through the built-in
IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface available in
MAX 7000S devices
– ISP circuitry compatible with IEEE S td. 1532
■Includes 5.0-V MAX 7000 devices and 5.0-V ISP-based MAX 7000S
devices
■Built-in JTAG boundary-scan test (BST) circuitry in MAX 7000S
devices with 128 or more macrocells
■Complete EPLD family with logic densities ranging from 600 to
5,000 u sable gates (see Tables 1 and 2)
■5-ns pin-to-pin logic delays with up to 175.4-MHz counter
frequencies (including interconnect)
■PCI-complia nt devic es availabl e
fFor information on in-system programmable 3.3-V MAX 7000A or 2.5-V
MAX 700 0B devi ces, see th e MAX 7000A Programma ble Logic De vice Fami ly
Data Sheet or the MAX 7000B Programmable Logic Device Family Data
Sheet.
Table 1. MAX 7000 Device Featu res
Feature EPM7032 EPM7064 EPM7096 EPM7128E EPM7160E EPM7192E EPM7256E
Usable
gates 600 1,250 1,800 2,500 3,200 3,750 5,000
Macrocells 32 64 96 128 160 192 256
Logic array
blocks 2468101216
Maximum
user I/O pins 36 68 76 100 104 124 164
tPD (ns ) 6 6 7.5 7.5 10 12 12
tSU (ns)5566777
tFSU (ns)2.5 2.533333
tCO1 (ns)444.54.5566
fCNT (MHz) 151.5 151.5 125.0 125.0 100.0 90.9 90.9
2Altera Corporation
MAX 7000 Programmable Logic D evi ce F ami l y Da ta Sh eet
...and More
Features
■Open-drain output option in MAX 7000S devices
■Programmable macrocell flipflops with individual clear, preset,
clock, and clock enable controls
■Programmab le power- saving mode for a reduction o f over 50% in
each macrocell
■Configurable expander product-term distribution, allowing up to
32 product terms per macrocell
■44 to 208 pi ns availabl e in plastic J-l ea d chi p car r ier (P LCC ), ceramic
pin-grid array (PGA), pl astic quad fla t pack (PQFP), p ower q uad flat
pack ( RQFP), and 1.0 -mm th in qu ad flat pack (TQF P) pa ckage s
■Programmable security bit for protection of proprietary designs
■3.3-V or 5.0-V operation
– MultiVoltTM I/O interface operation, allowing devices to
inte rface with 3.3 -V or 5.0-V device s (MultiVolt I /O operati on is
not available in 44-pin packages)
– Pin compatible with low-voltage MAX 7000A and MAX 7000B
devices
■Enhanced featu r es availab le in M AX 7000E and MA X 7000S devices
– Six pin- or logic-driven output enable signals
– Two global clock signals with optional inversion
– Enhanced interconnect resources for improved routability
– Fast input setup times provided by a dedicated path from I/O
pin to macrocell registers
– Programmable output slew-rate control
■Software d esign suppor t and automa tic place- and-route provided by
Altera’s devel opm ent system for Win dows -based P Cs and Sun
SPARCstation, and HP 9000 Series 700/800 workstations
Table 2. MAX 7000S Device Features
Feature EPM7032S EPM7064S EPM7128S EPM7160S EPM7192S EPM7256S
Usable gat es 600 1,250 2, 500 3, 200 3, 750 5,000
Macrocells 32 64 128 160 192 256
Logic arra y
blocks 2 4 8 10 12 16
Maximum
user I/O pins 36 68 100 104 124 164
tPD (ns)55667.57.5
tSU (ns) 2.9 2.9 3.4 3.4 4.1 3.9
tFSU (ns) 2.5 2.5 2.5 2.5 3 3
tCO1 (ns) 3.2 3.2 4 3.9 4.7 4.7
fCNT (MHz) 175.4 175.4 147.1 149.3 125.0 128.2
Altera Corporation 3
MAX 7000 Pr o grammable Log i c Dev ic e Fam ily D ata Sh eet
■Additi ona l design entry and simula tion support pr ovide d by EDIF
2 0 0 and 3 0 0 netlist files, library of parameterized modules (LPM),
Verilog HDL, VHDL, an d othe r interf aces to popular EDA tools fr om
manufacturers such as Cadence, Exemplar Logic, Mentor Graphics,
OrCAD, Syno psys, and VeriBes t
■Programming support
– Altera’s Master Programming Unit (MPU) and programming
hardware from third-party manufacturers program all
MAX 7000 devices
–The BitBlaster
TM serial download cable, Byte BlasterMVTM
parallel port download cable, and MasterBlasterTM
serial/universal serial bus (USB) download cable program MAX
7000S devices
General
Description
The MAX 7000 family of high-density, high-performance PLDs is based
on Altera’s second-generation MAX architecture. Fabricated with
advanced CMOS technology, the EEPROM-based MAX 7000 family
provides 600 to 5,000 usable gates, ISP, pin-to-pin delays as fast as 5 ns,
and counter speeds of up to 175.4 MHz. MAX 7 000S devices in the -5, -6,
-7, and -1 0 spe ed grades as wel l as MAX 7000 and MAX 700 0E dev ic es in
-5, -6, -7, -10P, and -12P speed grades comply with the PCI Special Interest
Group (PCI SIG) PCI Local Bus Specification, Revision 2.2. See Table 3
for available speed grades.
Table 3. MAX 7000 Speed Grades
Device Speed Grade
-5 -6 -7 -10P -10 -12P -12 -15 -15T -20
EPM7032 vv v vvv
EPM7032S vvv v
EPM7064 vvvvv
EPM7064S vvv v
EPM7096 vvvv
EPM7128E vvvvvv
EPM7128S vv v v
EPM7160E vv vv v
EPM7160S vv v v
EPM7192E vvv v
EPM7192S vv v
EPM7256E vvv v
EPM7256S vv v
4Altera Corporation
MAX 7000 Programmable Logic D evi ce F ami l y Da ta Sh eet
The MAX 7000E devices—including the EPM7128E, EPM7160E,
EPM71 92 E, and EPM7256E devices—have several enhanced features:
additional global clocking, additional output enable controls, enhanced
interconnect res ources, fast input registe rs, a nd a programmable slew
rate.
In-system programmable MAX 7000 devices—called MAX 7000S
devi ce s—include the EPM7032S, EPM7064S, EPM7 128S, EPM716 0S ,
EPM7192S, and EPM7256S devices. MAX 7000S devices have the
enhan ced featur es of MAX 700 0E de vices as well as JTAG BST cir cuitry in
devices with 128 or more macrocells, ISP, and an open-drain output
option. See Table 4.
Notes:
(1) Available only in EPM7128S, EPM7160S, EPM7192S, and EPM7256S devices only.
(2) The MultiV olt I/ O in t e r face is not ava ilable in 4 4- p in pac kages .
Table 4. MAX 7000 Device Features
Feature EPM7032
EPM7064
EPM7096
All
MAX 7000E
Devices
All
MAX 7000S
Devices
ISP via JTAG int erf ac e v
JTAG BST circuit ry v(1)
Open-drain output option v
Fast inpu t reg isters vv
Six global output enables vv
Two global clocks vv
Slew-rate control vv
MultiVolt int erf ac e (2) vvv
Programmable register vvv
Parallel ex panders vvv
Shared ex panders vvv
Power - saving mode vvv
Security bit vvv
PCI-co mp liant dev ic es avai lable vvv
Altera Corporation 5
MAX 7000 Pr o grammable Log i c Dev ic e Fam ily D ata Sh eet
The MAX 7000 architecture supports 100% TTL emulation and
high-density integration of SSI, MSI, and LSI logic functions. The
MAX 7000 architecture easily integrates multiple devices ranging from
PALs, GALs, and 22V10s to MACH and pLSI devices. MAX 7000 devices
are available in a wide ran ge of package s, includin g PLCC, PGA, PQ FP ,
RQFP , and TQFP pac kages. See Table 5.
Notes:
(1) Whe n the JTA G interface in MA X 7000S dev ices is u sed for ei ther bounda ry -scan t estin g or fo r IS P, four I/O pins
become JTAG pins.
(2) Perform a complete thermal analysis before committing a design to this device package. For more information, see
the Operating Requirements for Altera Devices Data Sheet.
MAX 7000 devices use CMOS EEPROM cells to implement logic
functions. The user-configurable MAX 7000 architecture accommodates a
varie ty o f ind epende nt c omb inat orial and se qu ent ial l ogic func tions . T he
devices can be reprogrammed for quick and efficient iterations during
design development and debug cycles, an d can be programmed and
erased up to 100 times.
Table 5. MAX 7000 Maximum User I/O Pins Note (1)
Device 44-
Pin
PLCC
44-
Pin
PQFP
44-
Pin
TQFP
68-
Pin
PLCC
84-
Pin
PLCC
100-
Pin
PQFP
100-
Pin
TQFP
160-
Pin
PQFP
160-
Pin
PGA
192-
Pin
PGA
208-
Pin
PQFP
208-
Pin
RQFP
EPM7032 36 36 36
EPM7032S 36 36
EPM7064 36 36 52 68 68
EPM7064S 36 36 68 68
EPM7096 52 64 76
EPM7128E 68 84 100
EPM7128S 68 84 84 (2) 100
EPM7160E 64 84 104
EPM7160S 64 84 (2) 104
EPM7192E 124 124
EPM7192S 124
EPM7256E 132 (2) 164 164
EPM7256S 164 (2) 164
6Altera Corporation
MAX 7000 Programmable Logic D evi ce F ami l y Da ta Sh eet
MAX 7000 devi ces cont ain fr om 32 to 256 macro cells that are combined
into groups of 16 macrocells, called logic array blocks (LABs). Each
macrocell has a programmable-AND/fixed-OR array and a confi g urab le
regist er with indepe ndently programma ble clock , cloc k enable, clea r, and
preset funct ions. To build compl ex log ic fun ction s, e ac h macro cel l can be
supplemented with both shareable expander product terms and high-
speed pa rallel expa nder prod uct terms to pr ovide up to 32 product terms
per macroc ell .
The MAX 7000 family provides programmable speed/power
optimization. Speed-critical portions of a design can run at high
speed/full power, while the remaining portions run at reduced
speed/low power. This speed/power optimization feature enables the
designer to configure one or more macrocells to operate at 50% or lower
power while adding only a nominal timing delay. MAX 7000E and
MAX 7000S devices also provide an option that reduces the slew rate of
the output buffers, minimizing noise transients when non-speed-critical
signals a re switc hing. T he output d rivers of a ll MAX 7000 de vices (exc ept
44-pin devices) can be set for either 3.3-V or 5.0-V operation, allowing
MAX 7000 devices to be used in mixed-voltage systems.
The MAX 7000 family is supported byAltera development systems, which
are integrated packages that offer schematic, text—including VHDL,
Verilog HDL, and the Altera Hardware Description Language (AHDL)—
and waveform design entry, compilation and logic synthesis, simulation
and timing analysis, and device programming. The software provides
EDIF 2 0 0 and 3 0 0, LPM, VHDL, Verilog HDL, and other interfaces for
additional design entry and simulation support from other industry-
standa rd PC- an d UNIX-workstation-b ased EDA tools. T he softw are runs
on Wind ows -base d PCs, as well a s Sun SPARC station, and H P 9000 Series
700/800 workstations.
fFor more information on development tools, see the MAX+PLUS II
Programmable Logic Development System & Software Data Sheet and the
Quartus Programmable Logic Development System & Software Data Sheet.
Functional
Description
The MAX 7000 architecture includes the following elements:
■Lo gic array blo cks
■Macrocells
■Expander product terms (shareable and parallel)
■Programmab le inter conn ec t array
■I/O control blocks
Altera Corporation 7
MAX 7000 Pr o grammable Log i c Dev ic e Fam ily D ata Sh eet
The MAX 7000 architecture includes four dedicated inputs that can
be used as general-purpose inputs or as high-speed, global control
signals (clock, clear, and two output enable signals) for each
macroce ll and I/O pin. Figure 1 sh ows the arch itectu re of EPM 7032,
EPM7064, an d EP M7096 devices.
Figure 1. EPM7032, EPM7064 & EPM7096 Device Block Diagram
I/O
Control
Block
8 to 16
I/O pins
8 to 16
8 to 16
16
36 I/O
Control
Block
8 to 16 8 to 16
I/O pins
36
8 to 16
16
8 to 16 8 to 16
I/O pins
36
8 to 16
16
I/O
Control
Block
I/O
Control
Block
8 to 16
I/O pins
8 to 16
8 to 16
16
36
LAB A LAB B
LAB C
Macrocells
33 to 48
LAB D
INPUT/GCLRn
INPUT/OE1
INPUT/OE2
Macrocells
17 to 32
Macrocells
49 to 64
PIA
INPUT/GLCK1
Macrocells
1 to 16
8Altera Corporation
MAX 7000 Programmable Logic D evi ce F ami l y Da ta Sh eet
Figure 2 shows the architecture of MAX 7000E and MAX 7000S devices.
Figure 2. MAX 7000E & MAX 7000S Device Block Diagram
Logic Array Blocks
The MAX 7000 device architecture is based on the linking of high-
performance, flexible, logic array modules called logic array blocks
(LABs) . LABs consi st of 16-mac rocell ar rays, as sho wn in Figures 1 and 2.
Multiple LABs are linked together via the programmable interconnect
array (PIA), a global bus that is fed by all dedicated inputs, I/O pins, and
macrocells.
6
6
INPUT/GCLRn
6 Output Enables 6 Output Enables
16
36 36
16
I/O
Control
Block
LAB C LAB D
I/O
Control
Block
6
16
36 36
16
I/O
Control
Block
LAB A LAB B
I/O
Control
Block
6
6 to16
INPUT/GCLK1
I
NPUT/OE2/GCLK2
INPUT/OE1
6 to 16 I/O Pins
6 to 16 I/O Pins
6 to 16 I/O Pin
s
6 to 16 I/O Pin
s
6 to16
6 to16
6 to16
6 to16
6 to16
6 to16
6 to16
6 to16
6 to16
6 to16
6 to16
Macrocells
1 to 16 Macrocells
17 to 32
Macrocells
33 to 48 Macrocells
49 to 64
PIA
Altera Corporation 9
MAX 7000 Pr o grammable Log i c Dev ic e Fam ily D ata Sh eet
Each LAB is fed by the following signals:
■36 signals from the PIA that are used for general logic inputs
■Global controls that are used for secondary register functions
■Direct input paths from I/O pins to the registers that are used
for fast setup times for MAX 7000E and MAX 7000S devices
Macrocells
The MA X 7000 m acroc ell can be indiv idually configu r ed for either
sequential or combinatorial logic operation. The macrocell consists
of three functional blocks: the logic array, the product-term select
matrix, and the programmable register. The macrocell of EPM7032,
EPM7064, an d EP M7096 devices is shown in Figure 3.
Figure 3. EPM7032, EPM7064 & EPM7096 Device Macrocell
Product
-
T
er
TT
m
S
elect
M
atri
x
36
S
ignals
f
rom PIA 16 Expander
Product
T
er
T
T
ms
Logic Arra
y
P
a
rallel Lo
g
ic
Expanders
(
from other
macrocells
)
S
hared Lo
g
ic
Expanders
Clear
Select
Global
Clear Global
Clocks
Clock/
Enable
Select
2
PRN
CLRN
D/T Q
ENA
Register
Bypass To I/O
Control
Block
to PIA
Programmable
Register
From
I/O pin
Fast Input
Select
VCC
10 Altera Corporation
MAX 7000 Programmable Logic D evi ce F ami l y Da ta Sh eet
Figure 4 sho ws a MAX 7000E and MAX 7000S device macrocell.
Figure 4. MAX 7000E & MAX 7000S Device Macrocell
Combinatorial logic is implemented in the logic array, which provides
five product terms per macrocell. The product-term select matrix allocates
these product terms for use as either primary logic inputs (to the OR and
XOR gates) to implement combinatorial functions, or as secondary inputs
to the ma crocell’s reg ister clea r, preset, clo ck, and clo ck enable cont rol
functions. Two kinds of expander product terms (“expanders”) are
available to supplement macrocell logic resources:
■Sh area ble expanders, which are inverted product term s that are f ed
back into the logic array
■Parallel expanders, which are product terms borrowed from adjacent
macrocells
The Alte ra development syste m aut om at ica lly opti m ize s pro du ct- t erm
allocation according to the logic requirements of the design.
For registered functions, each macrocell flipflop can be individually
programmed t o impl eme nt D, T , JK, or SR op erat ion w ith prog rammable
clock control. The flipflop can be bypassed for combinatorial operation.
During design entry, the designer specifies the desired flipflop type; the
Altera development software then selects the most efficient flipflop
operation for each registered function to optimize resource utilization.
Product-
Term
Select
Matrix
36 Signals
from PIA 16 Expander
Product Terms
Logic Array
Parallel Logic
Expanders
(from other
macrocells)
Shared Logic
Expanders
Clear
Select
Global
Clear Global
Clocks
Clock/
Enable
Select
2
PRN
CLRN
D/T Q
ENA
Register
Bypass to I/O
Control
Block
to PIA
Programmable
Register
from
I/O pin
Fast Input
Select
VCC
Altera Corporation 11
MAX 7000 Pr o grammable Log i c Dev ic e Fam ily D ata Sh eet
Each progra mmable regi ster c an be cl ocked in three different modes:
■By a global cloc k signal. This mod e achieves the fast est clock-to -
output performance.
■By a global clock signal and enabl e d by an activ e-h igh cl ock
enable. This mode provides an enable on each flipflop while still
achieving the fast clock-to-output performance of the global
clock.
■By an array clock implemented with a product term. In this
mode, the flipflop can be clocked by signals from buried
macroce lls or I/O pins.
In EPM7032, EPM7064, and EPM7096 devices, the global clock signal
is available from a dedic ated clock pin, GCLK1, as shown in Figure 1.
In MA X 70 00E and M AX 70 00S devices, two glob al cloc k signals ar e
ava ilable. As shown in Figure 2, these global clock signals can be the
true or the complement of either of the global clock pins, GCLK1 or
GCLK2.
Each r egister al so supports asy nchronous pr eset and clea r functions .
As shown in Figures 3 and 4, the product-term select matrix allocates
product terms to control these operations. Althoug h the
product -term-driven pres et and clear of the regis te r are ac tiv e high,
act ive-low contr ol can be obtaine d by invertin g the sig nal wit hin the
logic array. In addi tio n, each register cl ea r function can be
individ ua lly driven by the active -low dedica te d global clea r pin
(GCLRn). Upon power-up, each register in the device will be set to a
low state.
All M AX 700 0E a nd M AX 7000 S I /O pi ns have a f a st in pu t path to a
macroce ll r e gi ster . T his ded ica te d pat h a llows a s ig nal to b ypas s t he
PIA and combinatorial logic and be driven to an input D flipflop with
an extremely fast (2.5 ns) input setup time.
Expande r Pro duc t Terms
Although most logic functions can be implemented with the five
product terms available in each macrocell, the more complex logic
functions require additional product terms. Another macrocell can
be used to supply the required logic resources; however, the
MAX 7000 architecture also allows both shareable and parallel
expander product terms (“expanders”) that provide additional
product terms directly to any macrocell in the same LAB. These
expanders help ensure that logic is synthesized with the fewest
possible logic resources to obtain the fastest possible speed.
12 Altera Corporation
MAX 7000 Programmable Logic D evi ce F ami l y Da ta Sh eet
Shareable Expanders
Each LAB has 16 shareable expanders that can be viewed as a pool of
uncommitted single product terms (one from each macrocell) with
inverted outputs that feed back into the logic array. Each shareable
expander can be used and shared by any or all macrocells in the LAB to
build complex logic functions. A small delay (tSEXP) is incurred when
shareable expanders are used. Figure 5 shows how shar ea bl e exp anders
can feed multiple macrocells.
Figure 5. Shareable Expanders
Shareable expanders can be shared by any or all macrocells in an LAB.
Parallel Expanders
Parallel expanders are unused product terms that can be allocated to a
neighboring macrocell to implement fast, complex logic functions.
Parallel expanders allow up to 20 product terms to directly feed the
macrocell OR logic, with five product terms provided by the macrocell and
15 parallel expanders provided by neighboring macrocells in the LAB.
Macrocell
Product-Ter
m
Logic
Product-Term Select Matrix
Macrocell
Product-Ter
m
Logic
36 Signals
from PIA 16 Shared
Expanders
Altera Corporation 13
MAX 7000 Pr o grammable Log i c Dev ic e Fam ily D ata Sh eet
The co mp ile r can al loca te up t o th r ee se ts of up to fiv e p ar al lel expanders
automatically to the macrocells that require additional product terms.
Each set of five parallel expanders incurs a small, incremental timing
delay (tPEXP). For example, if a macrocell requires 14 product terms, the
Comp iler use s the f i ve dedica te d prod uc t te rms w i thi n t he m ac roce ll a nd
alloc ates two se ts of parallel exp ande r s; t he first se t in clud e s fiv e p ro duct
term s and th e se cond set inc ludes four prod uct te rms, inc rea sing th e total
delay by 2 ×tPEXP.
Two groups of 8 macrocells within each LAB (e.g., macrocells
1 through 8 and 9 through 16) form two chains to lend or borrow parallel
expanders. A macrocell borrows parallel expanders from lower-
numbered macrocells. For example, macrocell 8 can borrow parallel
expan ders from macroce ll 7, from macrocells 7 and 6, or from macrocells
7, 6, and 5. Within each group of 8, the lowest-numbered macrocell can
only lend parallel expanders and the highest-numbered macrocell can
only borrow them. Figure 6 shows how parallel expander s ca n be
borrowed from a neighboring macrocell.
Figure 6. Parallel Expa nders
Unused product terms in a macrocell can be allocated to a neighboring macrocell.
Preset
Clock
Clear
Product-
Term
Select
Matrix
Preset
Clock
Clear
Product-
Term
Select
Matrix
Macrocell
Product-
Term Logic
From
Previous
Macrocell
To Next
Macrocell
Macrocell
Product-
Term Logic
36 Signals
from PIA 16 Shared
Expanders
14 Altera Corporation
MAX 7000 Programmable Logic D evi ce F ami l y Da ta Sh eet
Programmable Int er co nnec t Array
Logic is routed between LABs via the programmable interconnect array
(PIA). This global bus is a programmable path that connects any signal
source to any destination on the device. All MAX 7000 dedicated inputs,
I/O pins, and macrocell outputs feed the PIA, which makes the signals
availa bl e th ro ugh out the ent i re d ev ice . O nly the sign al s r eq uired b y eac h
LAB are actually routed from the PIA into the LAB. Figure 7 shows how
the PIA signals are routed into the LAB. An EEPROM cell controls one
input to a 2-input AND gate, which selects a PIA signal to drive into the
LAB.
Fig ur e 7. PI A Ro ut i n g
While the r out ing dela ys of cha nne l-b as ed routing scheme s in ma sk ed or
FPGAs ar e cumula tive, va riable , and path- depen dent , the MAX 7000 PIA
has a fixed delay. The PIA thus eliminates skew between signals and
makes timing performance easy to predict.
I/O Contr ol B loc k s
The I/O control block allows each I/O pin to be individually configured
for input, output, or bidirectional operation. All I/O pins have a tri-state
buffer that is individually controlled by one of the global output enable
signals or directly connected to ground or VCC. Figure 8 shows the I/O
control block for the MAX 7000 family. The I/O control block of EPM7032,
EPM7064, and EPM7096 devices has two global output enable signals that
are dr iven by two dedicated active-low ou tput enab le pins ( OE1 and OE2).
The I/O control block of MAX 7000E and MAX 7000S devices has six
global output ena ble signa ls that ar e driv en by the tr ue or comple ment of
two out put enab le sig na ls, a s ubse t of t he I /O pin s, o r a sub set of the I /O
macrocells.
To LAB
PIA Signals
Altera Corporation 15
MAX 7000 Pr o grammable Log i c Dev ic e Fam ily D ata Sh eet
Figure 8. I/O Control Block of MAX 7000 Devices
Note:
(1) Th e o p en-dra in output o pt ion is av a il a ble only in M A X 70 00S devices.
E
PM7032, EPM7064 & EPM7096 Devices
M
AX 7000E & MAX 7000S Devices
To PIA
GND
VCC
F
rom Macrocell
OE1
OE2
From
Macrocell
Fast Input to
Macrocell
Register
Slew-Rate Control
To PIA
To Other I/O Pins
Six Global Output Enable Signals
PIA
GND
VCC
Open-Drain Output (1)
16 Altera Corporation
MAX 7000 Programmable Logic D evi ce F ami l y Da ta Sh eet
When the tri-state buffer control is connected to ground, the output is
tri-stated (high impedance) and the I/O pin can be used as a dedicated
input. Whe n th e tri-s ta te buffe r cont r ol is con ne cted to VCC, t he ou tput is
enabled.
The MAX 7000 architecture provides dual I/O feedback, in which
macrocell and pin feedbacks are independent. When an I/O pin is
configured as an input, the associated macrocell can be used for buried
logic.
In-System
Programma-
bility (ISP)
MAX 7000S devices are in-system programmable via an
industry-standard 4-pin Joint Test Action Group (JTAG) interface (IEEE
Std. 1149.1-1990). ISP allows quick, efficient iterations during design
development and debugging cycles. The MAX 7000S architecture
internally generates the high programming voltage required to program
EEPROM cells, allowing in-sy stem progr amming with only a si ngle 5.0 V
power supply. During in-system programming, the I/O pins are tri-stated
and pulled-up to eliminate board conflicts. The pull-up value is nominally
50 k¾.
ISP simplifie s the manufacturin g flow by a llowing d evices to be mounted
on a printed circuit board with standard in-circuit test equipment before
they are programmed. MAX 7000S devices can be programmed by
downloading the informat ion via in-circ uit teste rs (ICT), embedded
processors, or the Altera MasterBlaster, ByteBlasterMV, ByteBlaster,
BitBlaster download cables. (The ByteBlaster cable is obsolete and is
replaced by the ByteBlasterMV cable, which can program and co nfigure
2.5-V, 3.3-V, an d 5.0 -V device s.) Programming the devices after they are
placed on the boar d elimina tes lead d amage on high-p in-cou nt pa ck ages
(e.g., QFP packages) due to device handling and allows devices to be
reprogrammed after a system has already shipped to the field. For
example, product upgrades can be performed in the field via software or
modem.
In-system programming can be accomplished with either an adaptive or
constant algorithm. An adaptive algorithm reads information from the
unit and adapts subsequent programming steps to achieve the fastest
possible programming time for that unit. Because some in-circuit testers
cannot su ppor t an a da pt ive algorithm , A lte r a o f fer s d evic es te st ed w ith a
constant algorithm. Devices tested to the constant algorithm have an “F”
suffix in the ordering code.
The J am TM Standard Test and Progra mmi ng Language (STAPL) c an be
used to program MAX 7000S devices with in-circuit testers, PCs, or
em bedded processor.
Altera Corporation 17
MAX 7000 Pr o grammable Log i c Dev ic e Fam ily D ata Sh eet
fFor more information on using the Jam language, see Application Note 88
(Using the Jam Language for ISP & ICR via an Embedded Processor).
The I SP circuit ry in MAX 7000S devices is compa tible wit h IEEE Std . 1532
specification. The IEEE Std. 1532 is a standard developed to allow
concurrent ISP between multiple PLD vendors.
Programmable
Speed/Power
Control
MAX 7000 dev ices offer a power-saving mode that supports low- power
operation across user-defined signal paths or the entire device. This
feature allows total power dissipation to be reduced by 50% or more,
becau se most logic a pplications r equir e o nly a small fract ion of all gates to
operate at maximum frequency.
The designer can program each individual macrocell in a MAX 7000
device for either high-speed (i.e., with the Turbo BitTM option turned on)
or low-power (i.e., with the Turbo Bit option turned off) operation. As a
result, speed-critical paths in the design can run at high speed, while the
remain ing paths can operate at red uced power. Macr ocells that run at low
power incur a nominal timing delay adder (tLPA) for the tLAD, tLAC, tIC,
tEN, and tSEXP, tACL, and tCPPW parameters.
Output
Configuration
MAX 7000 device outputs can be programmed to meet a variety of
system -level requirements.
MultiVol t I/O Interface
MAX 7000 devices—except 44-pin devices—support the MultiVolt I/O
interface feature, which allows MAX 7000 devices to interface with
system s that have differi ng suppl y volt ages . The 5.0- V dev ices in al l
packages ca n be set for 3.3-V or 5.0-V I/O pin operation. These devices
have one set of VCC pins for internal operation and input buffers
(VCCINT), and another set for I/O output drivers (VCCIO).
The VCCINT pins must always be connected to a 5.0-V power supply.
With a 5.0-V VCCINT level , input volt age thres holds are a t TTL levels, a nd
are therefore compatib le with bo th 3.3-V and 5.0- V inputs.
The VCCIO pins can be connected to either a 3.3-V or a 5.0-V power
supp ly, depend ing o n the output req uirements . When the VCCIO pins ar e
connected to a 5.0-V supply, the output levels are compatible with 5.0-V
systems. When VCCIO is connected to a 3.3-V supply, the output high is
3.3 V and is therefo r e compatible with 3 .3-V or 5.0- V system s. Device s
operating with VCCIO levels lower than 4.75 V incur a nominally greater
tim ing delay o f tOD2 instead of tOD1.
18 Altera Corporation
MAX 7000 Programmable Logic D evi ce F ami l y Da ta Sh eet
Open-Dr ain Out put Option (MAX 7000S Dev ices Only )
MAX 7000S devices provide an optional open-drain (functionally
equivalent to open-collector) output for each I/O pin. This open-drain
output enables the device to provide system-level control signals (e.g.,
interrupt and write enable signals) that can be asserted by any of several
devices. It can also provide an additional wired-OR plane.
By using an external 5.0-V pull-up resistor, output pins on MAX 7000S
devices can be set to meet 5.0-V CMOS input voltages. When VCCIO is
3.3 V, setting the open drain option will turn off the output pull-up
transistor, allowing the external pull-up resistor to pull the output high
enough to meet 5 .0-V CMOS inp ut volt ages . When VCCIO is 5.0 V, setting
the output drain option is not necessary because the pull-up transistor will
already turn off when the pin exceeds approximately 3.8 V, allowing the
external pull-up resistor to pull the output high enough to meet 5.0-V
CMOS input voltages.
Slew-Rate Control
The out put buffer for each MAX 7000E and MAX 7000 S I/O pin has an
adjustable output slew rate that can be configured for low-noise or high-
speed performance. A faster slew rate provides high-speed transitions for
high-performance systems. However, these fast transitions may introduce
noise transients into the system. A slow slew rate reduces system noise,
but adds a nominal delay of 4 to 5 ns. In MAX 7000E devices, when the
Turbo Bit is turne d of f, the sle w ra te is set f or low noise perfor ma nce . F or
MAX 7000S devi ces, each I/O pin has an indiv i dual EEPROM bit that
controls the slew rate, allowing designers to specify the slew rate on a
pin-by-pin basis.
Programming
with External
Hardware
MAX 7000 dev ices can b e pro gram med on Windo ws-based PCs with the
Altera Logic Programmer card, the Master Programmi ng Unit (MPU),
and the appropriate device adapter. The MPU performs a continuity
check to ensure adequate electrical contact between the adapter and the
device.
fFor more information, see the Altera Programming Hardware Data Sheet.
The Altera development system can use text- or waveform-format test
vectors created with the Text Editor or Waveform Editor to test the
progr amme d dev i ce. For added design verification, de signers can
perform functional testing to compare the functional behavior of a
MAX 7000 device with the result s of simula tion . More ove r, Data I /O, BP
Microsystems, and other programming hardware manufacturers also
provide programming support for Altera devices.
fFor more information, see the Programming Hardware Manufacturers.
Altera Corporation 19
MAX 7000 Pr o grammable Log i c Dev ic e Fam ily D ata Sh eet
IEEE Std.
1149.1 (JTAG)
Boundary-Scan
Support
MAX 7000 devi ce s support JTAG BST circuitry as spec i f ied by IEEE Std.
1149.1-1990. Table 6 describes the JTAG instructions supported by the
MAX 7000 family. The pin -out tables (see the Altera web site
(http://www.altera.com) or the Altera Digital Libra ry for pin-out
information) show the location of the JTAG control pins for each device.
If the JTAG interface is not required, the JTAG pins are available as user
I/O pins.
Table 6. MAX 7000 JTAG Instructions
JTAG Instruc tion Devices Descript ion
SAMPLE/PRELOAD EPM7128S
EPM7160S
EPM7192S
EPM7256S
Allow s a snaps hot of signals at the dev ic e pins to be capt ured and
examined during normal device operat ion, and perm it s an init ial dat a
pattern output at the device pins.
EXTEST EPM7128S
EPM7160S
EPM7192S
EPM7256S
Allow s the ex te rnal c irc uit ry and board-level interc onnections to be
teste d by forc ing a t est pat te rn at the ou tpu t pin s and capturing test
resul ts at the input pins.
BYPASS EPM7032S
EPM7064S
EPM7128S
EPM7160S
EPM7192S
EPM7256S
Place s the 1-bit byp as s regist er bet w een th e TDI and TDO pins, which
allow s the BST dat a to pass sync hronously th rough a selected de vice
to adjacent devices during normal device operation.
IDCODE EPM7032S
EPM7064S
EPM7128S
EPM7160S
EPM7192S
EPM7256S
Selec ts th e IDC OD E regis t er and places it betwe en TDI and TDO,
allow ing th e IDC OD E to be ser ially shift ed out of TDO.
ISP Instructions EPM7032S
EPM7064S
EPM7128S
EPM7160S
EPM7192S
EPM7256S
These ins t ruc tio ns are us ed wh en programming M AX 7000S devices
via the JTAG ports with the Maste rBlaster, ByteB las te rM V, BitBlaster
download cable, or using a Jam File (.jam), Ja m Byte-Code file (.jbc),
or Serial Vec t or Fo rm at file (.svf) v ia an em bedded proce ssor or test
equipment.
20 Altera Corporation
MAX 7000 Programmable Logic D evi ce F ami l y Da ta Sh eet
The instruction register length of MAX 7000S devices is 10 bits. Tables 7
and 8 show the boundary-scan register length and device IDCODE
information for MAX 7000S devices.
Note:
(1) This device does not support JTAG boundary-scan testing. Selecting either the
EXTEST or SAMPLE/PRELOAD instruction will select the one-bit bypass register.
Notes:
(1) The most sign ifi can t bit (M SB) is on the left.
(2) The least sign ifi c an t bit (LSB) for all JTAG IDC OD Es is 1.
Table 7. M A X 7000S Boundary-Scan Re gister Length
Device Boundar y-Scan Register Length
EPM7032S 1 (1)
EPM7064S 1 (1)
EPM7128S 288
EPM7160S 312
EPM7192S 360
EPM7256S 480
Table 8. 32-Bit MAX 7000 D evice IDCODE Note (1)
Devic e IDCODE (32 Bits )
Version
(4 Bits) Par t N umber (16 Bits) Manufacturer’ s
Identity (11 Bits) 1 (1 Bit)
(2)
EPM7032S 0000 0111 0000 0011 0010 00001101110 1
EPM7064S 0000 0111 0000 0110 0100 00001101110 1
EPM7128S 0000 0111 0001 0010 1000 00001101110 1
EPM7160S 0000 0111 0001 0110 0000 00001101110 1
EPM7192S 0000 0111 0001 1001 0010 00001101110 1
EPM7256S 0000 0111 0010 0101 0110 00001101110 1
Altera Corporation 21
MAX 7000 Pr o grammable Log i c Dev ic e Fam ily D ata Sh eet
Figure 9 sh ows the ti ming requ irements for the JTAG signals.
Figure 9. MAX 7000 JTAG Waveforms
Table 9 shows the JTAG timing parameters and values for
MAX 7000S devices.
T
DO
T
CK
t
JPZX
t
JPCO
t
JPH
t
JPXZ
t
JCP
t
JPSU
t
JCL
t
JCH
TDI
T
MS
g
nal
o
Be
u
red
g
nal
o
Be
iven
t
JSZX
t
JSSU
t
JSH
t
JSCO
t
JSXZ
Table 9. J TAG Timing Parameters & Values for M A X 7000S Dev i ces
Symbol Parameter Min Max Unit
tJCP TCK clock period 100 ns
tJCH TCK clock high time 50 ns
tJCL TCK clock low time 50 ns
tJPSU J T AG port setup time 20 ns
tJPH JTAG port ho ld time 45 ns
tJPCO JTAG port clock to output 25 ns
tJPZX JTAG port high impedance to valid outpu t 25 ns
tJPXZ J T AG port valid output to high impedance 2 5 ns
tJSSU C apture regist er se tu p time 20 ns
tJSH Capture regis t er hold time 45 ns
tJSCO Up dat e regis t er clo ck to outp ut 25 ns
tJSZX Up dat e regis t er high im pedance to vali d out put 25 ns
tJSXZ U pdate regist er va lid out put to hig h imp edance 25 ns
22 Altera Corporation
MAX 7000 Programmable Logic D evi ce F ami l y Da ta Sh eet
fFor more information, see Application Note 39 (IEEE 11 49.1 (JTAG)
Boundary-Scan Testing in Altera Devices).
Design Se cu ri ty All MAX 7000 devices contain a programmable security bit that controls
access to the data programmed into the device. When this bit is
programmed, a proprietary design implemented in the device cannot be
copied or retrieved. This feature provides a high level of design security
because pr ogrammed data withi n EE PROM c ells is invisi bl e. The secur ity
bit that controls this function, as well as all other programmed data, is
reset only when the device is reprogrammed.
Generic Testin g Each MAX 7000 device is functionally tested. Complete testing of each
programmable EE PROM bit an d all inte rna l log ic ele men ts ens ur es 10 0%
programming yield. AC test measurements are taken under conditions
equivalent to those shown in Figure 10. Test patterns can be used and then
erased during early stages of the production flow.
Figure 10. MAX 7000 A C Test Conditions
QFP Ca rrier &
Development
Socket
MAX 7000 and MAX 7000E devices in QFP packages with 100 or more
pins are shipped in special plastic carriers to protect the QFP leads. The
carrier is used with a prototype development socket and special
programming hardware availa ble from Alter a. This carri er te chno logy
makes it possi ble to progra m, test , era se, an d repr ogram a d evice withou t
exposing the leads to mechanical stress.
fFor detaile d information and carr ie r dimensions, refer to the QFP Carrier
& Development Socket Data Sheet.
1MAX 7000S device s are not shi pped in carrier s.
VCC
To Test
System
C1 (includes JIG
capacitance)
Device input
rise and fall
times < 3 ns
Device
Output
464 Ω
[703 Ω]
250
[8.06 ]
Ω
KΩ
Power supply transie nts can affec t AC
measurements. Simultaneous
tr ansit ions of m ulti pl e out put s shoul d be
avoided for accurate measu reme nt.
Thr eshold tes ts must not be performed
unde r AC conditions. Large-ampl itude,
fa st ground- current transients norma lly
occur as the device outputs discharge
the load capacitances. W hen these
transients flow through the parasitic
in ductance be tween the device ground
pin and the test system ground,
significant reductions in observable
noise immunity can result. Numbers in
brackets are for 2.5-V devices and
outputs. Numbers without brackets are
for 3.3-V devices and outputs.
Altera Corporation 23
MAX 7000 Pr o grammable Log i c Dev ic e Fam ily D ata Sh eet
Operating
Conditions
Tables 10 through 15 provide information about absolute maximum
ratings, recommended operating conditions, operating conditions, and
capa ci t ance for 5.0- V MAX 700 0 de vi c es .
Table 10. MAX 7000 5.0-V Device Absolute Maximum Ratings Note (1)
Symbol Parameter Conditions Min Max Unit
VCC Supply voltage With respect to ground (2) –2.0 7.0 V
VIDC input voltage –2.0 7.0 V
IOUT DC output current, per pin –25 25 mA
TSTG Storage temperature No bias –65 150 ° C
TAMB A mbient temperature Under bias –65 135 ° C
TJJunction temperature Ceram ic packages, unde r bias 150 ° C
PQFP and RQFP packages, under bias 135 ° C
Table 1 1. MAX 7000 5 . 0-V Device Reco mm ended Oper ating Cond itions
Symbol Parameter Conditions Min Max Unit
VCCINT Supply voltage for internal logic and
input buffers (3), (4), (5) 4.75
(4.50) 5.25
(5.50) V
VCCIO Supply voltage for output drivers,
5.0-V operation (3), (4) 4.75
(4.50) 5.25
(5.50) V
Supply voltage for output drivers,
3.3-V operation (3), (4), (6) 3.00
(3.00) 3.60
(3.60) V
VCCISP Supply voltage during ISP (7) 4.75 5.25 V
VIInput voltage –0.5 (8) VCCINT + 0.5 V
VOOutput voltage 0V
CCIO V
TAAmbient temperature For commercial use 0 70 ° C
For industrial use –40 85 ° C
TJJunction temperature For commercial use 0 90 ° C
For industrial use –40 105 ° C
tRInput rise time 40 ns
tFInput fall time 40 ns
24 Altera Corporation
MAX 7000 Programmable Logic D evi ce F ami l y Da ta Sh eet
Table 12. MAX 7000 5.0- V Device DC Oper ating Conditions Note (9)
Symbol Parameter Conditions Min Max Unit
VIH High-level input voltage 2.0 VCCINT + 0.5 V
VIL Low-level input voltage –0.5 (8) 0.8 V
VOH 5.0-V high-level TTL output voltage IOH = –4 mA DC, VCCIO = 4.75 V (10) 2.4 V
3.3-V high-level TTL output voltage IOH = –4 mA DC, VCCIO = 3.00 V (10) 2.4 V
3.3-V high-level CMOS output
voltage IOH = –0.1 mA DC, VCCIO = 3.0 V (10) VCCIO – 0.2 V
VOL 5.0-V low-level TTL output voltage IOL = 12 mA DC, VCCIO = 4.75 V (11) 0.45 V
3.3-V low-level TTL output voltage IOL = 12 mA DC, VCCIO = 3.00 V (11) 0.45 V
3.3-V low-level CMOS output
voltage IOL = 0.1 mA DC, VCCIO = 3.0 V(11) 0.2 V
IILeakage current of dedicated input
pins VI = –0.5 to 5.5 V (11) –10 10 µA
IOZ I/O pin tri-state output off-state
current VI = –0.5 to 5.5 V (11), (12) –40 40 µA
Table 13. MAX 7000 5. 0-V Device Capacitance: EPM7032, EPM 7064 & EPM7096 Devices Note (13)
Symbol Parameter Conditions Min Max Unit
CIN Input pin capacitance VIN = 0 V, f = 1.0 MHz 12 pF
CI/O I/O pin capacitance VOUT = 0 V, f = 1.0 MHz 12 pF
Table 14. M AX 70 00 5.0-V De vice Capaci t ance: MA X 7000E Devices Note (13)
Symbol Parameter Conditions Min Max Unit
CIN Input pin capacitance VIN = 0 V, f = 1.0 MHz 15 pF
CI/O I/O pin capacitance VOUT = 0 V, f = 1.0 MHz 15 pF
Table 15. M AX 70 00 5.0-V De vice Capaci t ance: MA X 7000S D evi ces Note (13 )
Symbol Parameter Conditions Min Max Unit
CIN Dedicated input pin capacitance VIN = 0 V, f = 1.0 MHz 10 pF
CI/O I/O pin capacitance VOUT = 0 V, f = 1.0 MHz 10 pF
Altera Corporation 25
MAX 7000 Pr o grammable Log i c Dev ic e Fam ily D ata Sh eet
Notes to table s:
(1) See the Operat ing Requirement s f o r Alt era Devices Data Sh eet.
(2) Minimu m DC input vol tage on I/O pins is –0.5 V and on 4 dedica ted inpu t pins is –0 .3 V. Du ri n g tran sitions, the
inputs may undershoot to –2.0 V or overshoot to 7.0 V for input currents less than 100 mA and periods shorter than
20 ns.
(3) Numbers in parentheses are for industrial-temperature-range devices.
(4) VCC must rise monoton ically.
(5) The POR time for all 7000S devices does not exceed 300 µs. The sufficient VCCINT voltage level for POR is 4.5 V. The
device is fully init iali zed within the POR time after VCCINT reaches the s ufficie nt P OR v o ltage lev el.
(6) 3.3-V I/O operation is not available for 44-pin packages.
(7) The VCCISP parameter applies only to MAX 7000S devices.
(8) Duri n g in-sy s tem progr amm in g, the min im um DC inpu t vol t ag e is –0. 3 V .
(9) Thes e values are spec ifi ed under th e M A X 7000 reco mmen d ed operatin g con d i ti ons in Tabl e 11 on pag e 23.
(10) The parameter is measured with 50% of the ou t pu t s each sourcing the sp ec i fied cur re n t. The IOH parameter refers
to high-leve l TTL or CMOS output current.
(11) The parameter is measured with 5 0% of the outputs each sinking the specified current. The IOL parameter refers to
low-leve l T T L , P CI, or CM OS o u t put current.
(12) When the JTAG interface is enabled in MAX 7000S devices, the input leakage current on the JTAG pins is typically
–60 µA.
(1 3) Ca pa c i t a n ce is m ea sur ed at 2 5° C and is sample-tested only. The OE1 pin has a maximum capacitance of 20 pF.
Figure 11 shows the typical output drive characteristics of MAX 7000
devices.
Figure 11. Output Drive Characteristics of 5 .0-V MAX 7000 Devi ces
T i mi ng Model MAX 70 00 device ti ming can be ana lyzed wit h the Alte ra software , wi th a
vari e ty of popular industry-s tan d ard EDA simulator s and timing
analyzers, or with the timing model shown in Figure 12. MAX 7 000
devices have fixed internal delays that enabl e the designe r to determine
the worst-c ase timing of any desig n. The Altera soft ware provides timing
simulation, point-to-point delay prediction, and detailed timing analysis
for a device-wide performance evaluation.
VO Output Voltage (V)
12345
30
60
90
150
120
VCCIO = 3.3 V
IOL
IOH
Room Temperature
3.3
VO Output Voltage (V)
12345
30
60
90
150
120
VCCIO = 5.0 V
IOL
IOH
Room Temperature
IO
T
ypical
O
utput
C
urrent (mA)
IO
Typical
Output
Current (mA)
26 Altera Corporation
MAX 7000 Programmable Logic D evi ce F ami l y Da ta Sh eet
Figure 12. MAX 7000 Timing Model
Notes:
(1) Only avai lab le in MAX 7000E an d M AX 7000S dev ices.
(2) Not available in 44-pin devices.
The timing characteristics of any signal path can be derived from the
timing model and parameters of a particular device. External timing
parameters, which represent pin-to-pin timing delays, can be calculated
as the sum of internal parameters. Figure 13 shows the internal timing
relationship of internal and external delay parameters.
fFor more infomration, see Application Note 94 (Understanding MAX 7000
Timing).
Logic Array
Delay
t
LAD
Output
Delay
t
OD3
t
OD2
t
OD1
t
XZ
Z
t
X1
t
ZX2
t
ZX3
Input
Delay
t
IN
Register
Delay
t
SU
t
H
t
PRE
t
CLR
t
RD
t
COMB
t
FSU
t
FH
PIA
Delay
t
PIA
Shared
Expander Delay
t
SEXP
Register
Control Delay
t
LAC
t
IC
t
EN
I/O
Delay
t
IO
Global Control
Delay
t
GLOB
Internal Output
Enable Delay
t
IOE
Parallel
Expander Delay
t
PEXP
Fast
Input Delay
t
FIN
(1)
(2)
(1)
(1)
(2)
Altera Corporation 27
MAX 7000 Pr o grammable Log i c Dev ic e Fam ily D ata Sh eet
Figure 13. Switchi ng Waveform s
Combinatorial Mode
Input Pin
I/O Pin
PIA Delay
Shared Expander
Delay
Logic Array
Input
Parallel Expander
Delay
Logic Array
Output
Output Pin
t
IN
t
LAC
, t
LAD
t
PIA
t
OD
t
PEXP
t
IO
t
SEXP
t
COMB
Global Clock Mode
Global
Clock Pin
Global Clock
at Register
Data or Enable
(Logic Array Output)
t
F
t
CH
t
CL
t
R
t
IN
t
GLOB
t
SU
t
H
Array Clock Mode
Input or I/O Pin
Clock into PIA
Clock into
Logic Array
Clock at
Register
Data from
Logic Array
Register to PIA
to Logic Array
Register Output
to Pin
t
F
t
R
t
ACH
t
ACL
t
SU
t
IN
t
IO
t
RD
t
PIA
t
CLR
, t
PRE
t
H
t
PIA
t
IC
t
PIA
t
OD
t
OD
tR & tF < 3 ns.
Inputs are driven at 3 V
for a logic high and 0 V
f or a logic low. All ti ming
characterist ics are
measured at 1.5 V.
28 Altera Corporation
MAX 7000 Programmable Logic D evi ce F ami l y Da ta Sh eet
Tables 16 through 23 show th e MAX 7000 and MAX 7000E AC operating
conditions.
Table 16. MAX 70 00 & MA X 7000E Extern al Timing Parameters Note (1)
Symbol Par ameter Condit i ons -6 Speed Grade -7 Speed Grade U nit
Min Max Min Max
tPD1 Input to non-registered output C1 = 35 pF 6.0 7.5 ns
tPD2 I/O input to non-registered output C1 = 35 pF 6.0 7.5 ns
tSU Global clock setup time 5.0 6.0 ns
tHGlobal clock hold time 0.0 0.0 ns
tFSU Global clock setup time of fast input (2) 2.5 3.0 ns
tFH Global clock hold time of fast input (2) 0.5 0.5 ns
tCO1 Global clock to output delay C1 = 35 pF 4.0 4.5 ns
tCH Global clock high time 2.5 3.0 ns
tCL Global clock low time 2.5 3.0 ns
tASU Array clock setup time 2.5 3.0 ns
tAH Array clock hold time 2.0 2.0 ns
tACO1 Array clock to output delay C1 = 35 pF 6.5 7.5 ns
tACH Array clock high time 3.0 3.0 ns
tACL Array clock low time 3.0 3.0 ns
tCPPW Minimum pulse w idth for clear and
preset (3) 3.0 3.0 ns
tODH Output data hold time after clock C1 = 35 pF (4) 1.0 1.0 ns
tCNT Minimum global clock period 6.6 8.0 ns
fCNT Maximum internal global clock
frequency (5) 151.5 125.0 MHz
tACNT Minimum array clock period 6.6 8.0 ns
fACNT Maximum internal array clock
frequency (5) 151.5 125.0 MHz
fMAX Maximum clock frequency (6) 200 166.7 MHz
Altera Corporation 29
MAX 7000 Pr o grammable Log i c Dev ic e Fam ily D ata Sh eet
Table 17. MAX 7000 & MAX 7000E Internal Timing Parameters Note (1)
Symbol Parameter Conditions Speed Grade -6 Speed Grade -7 Unit
Min Max Min Max
tIN Input pad and buffer delay 0.4 0.5 ns
tIO I/O input p ad and buffer delay 0.4 0.5 ns
tFIN Fast inpu t delay (2) 0.8 1.0 ns
tSEXP Shared expander delay 3.5 4.0 ns
tPEXP Parallel expander delay 0.8 0.8 ns
tLAD Logic array delay 2.0 3.0 ns
tLAC Logic control array delay 2.0 3.0 ns
tIOE Inte rnal output enable delay (2) 2.0 ns
tOD1 Output buffer and pad delay
Slow slew rate = off, VCCIO = 5.0 V C1 = 35 pF 2.0 2.0 ns
tOD2 Output buffer and pad delay
Slow slew rate = off, VCCIO = 3.3 V C1 = 35 pF (7) 2.5 2.5 ns
tOD3 Output buffer and pad delay
Slow slew rate = on,
VCCIO = 5.0 V or 3.3 V
C1 = 35 pF (2) 7.0 7.0 ns
tZX1 Output buffer enable delay
Slow slew rate = off, VCCIO = 5.0 V C1 = 35 pF 4.0 4.0 ns
tZX2 Output buffer enable delay
Slow slew rate = off, VCCIO = 3.3 V C1 = 35 pF (7) 4.5 4.5 ns
tZX3 Output buffer enable delay
Slow slew rate = on
VCCIO = 5.0 V or 3.3 V
C1 = 35 pF (2) 9.0 9.0 ns
tXZ Output buffer disable delay C1 = 5 pF 4.0 4.0 ns
tSU Register setup time 3.0 3.0 ns
tHRegister hold time 1.5 2.0 ns
tFSU Register setup time of fast input (2) 2.5 3.0 ns
tFH Register hold time of fast input (2) 0.5 0.5 ns
tRD Register delay 0.8 1.0 ns
tCOMB Combinatorial delay 0.8 1.0 ns
tIC Array clock delay 2.5 3.0 ns
tEN Register enable time 2.0 3.0 ns
tGLOB Global control delay 0.8 1.0 ns
tPRE Register preset time 2.0 2.0 ns
tCLR Register clear time 2.0 2.0 ns
tPIA PIA delay 0.8 1.0 ns
tLPA Low-power adder (8) 10.0 10.0 ns
30 Altera Corporation
MAX 7000 Programmable Logic D evi ce F ami l y Da ta Sh eet
Table 18. MAX 7000 & MAX 7000E External Timing Para meters Note (1)
Symbol Para meter Conditio ns Speed Grade Unit
MAX 7000E (-10P) MAX 7000 (-10)
MAX 70 00E (-10 )
Min Max Min Max
tPD1 Input to non-registere d output C1 = 35 pF 10.0 10.0 ns
tPD2 I/O input to non-registered output C1 = 35 pF 10.0 10.0 ns
tSU Global clock setup time 7.0 8.0 ns
tHGlobal clock hold time 0.0 0.0 ns
tFSU Global clock setup time of fast input (2) 3.0 3.0 ns
tFH Global clock hold time of fast input (2) 0.5 0.5 ns
tCO1 Global clock to output delay C1 = 35 pF 5.0 5 ns
tCH Global clock high time 4.0 4.0 ns
tCL Global clock low time 4.0 4.0 ns
tASU Array clock setup time 2.0 3.0 ns
tAH Array clock hold time 3.0 3.0 ns
tACO1 Array clock to output delay C1 = 35 pF 10.0 10.0 ns
tACH Array clock high time 4.0 4.0 ns
tACL Array clock low time 4.0 4.0 ns
tCPPW Minimum pulse w idth for clear and
preset (3) 4.0 4.0 ns
tODH Output data hold time after clock C1 = 35 pF (4) 1.0 1.0 ns
tCNT Minimum global clock period 10.0 10.0 ns
fCNT Maximum internal global clock
frequency (5) 100.0 100.0 MHz
tACNT Minimum array clock period 10.0 10.0 ns
fACNT Maximum internal array clock
frequency (5) 100.0 100.0 MHz
fMAX Maximum clock frequency (6) 125.0 125.0 MHz
Altera Corporation 31
MAX 7000 Pr o grammable Log i c Dev ic e Fam ily D ata Sh eet
Table 19. MAX 7000 & MAX 7000E Internal Timing Parameters Note (1)
Symb ol Parameter Conditions Speed Grade Unit
MAX 7000E (-10P) MAX 7000 (-10)
MAX 7000E (-1 0)
Min Max Min Max
tIN Input pad and buffer delay 0.5 1.0 ns
tIO I/O input p ad and buffer delay 0.5 1.0 ns
tFIN Fast inpu t delay (2) 1.0 1.0 ns
tSEXP Shared expander delay 5.0 5.0 ns
tPEXP Parallel expander delay 0.8 0.8 ns
tLAD Logic array delay 5.0 5.0 ns
tLAC Logic control array delay 5.0 5.0 ns
tIOE Inte rnal output enable delay (2) 2.0 2.0 ns
tOD1 Output buffer and pad delay
Slow slew rate = off
VCCIO = 5.0 V
C1 = 35 pF 1.5 2.0 ns
tOD2 Output buffer and pad delay
Slow slew rate = off
VCCIO = 3.3 V
C1 = 35 pF (7) 2.0 2.5 ns
tOD3 Output buffer and pad delay
Slow slew rate = on
VCCIO = 5.0 V or 3.3 V
C1 = 35 pF (2) 5.5 6.0 ns
tZX1 Output buffer enable delay
Slow slew rate = off
VCCIO = 5.0 V
C1 = 35 pF 5.0 5.0 ns
tZX2 Output buffer enable delay
Slow slew rate = off
VCCIO = 3.3 V
C1 = 35 pF (7) 5.5 5.5 ns
tZX3 Output buffer enable delay
Slow slew rate = on
VCCIO = 5.0 V or 3.3 V
C1 = 35 pF (2) 9.0 9.0 ns
tXZ Output buffer disable delay C1 = 5 pF 5.0 5.0 ns
tSU Register setup time 2.0 3.0 ns
tHRegister hold time 3.0 3.0 ns
tFSU Register setup time of fast input (2) 3.0 3.0 ns
tFH Register hold time of fast input (2) 0.5 0.5 ns
tRD Register delay 2.0 1.0 ns
tCOMB Combinatorial delay 2.0 1.0 ns
tIC Array clock delay 5.0 5.0 ns
tEN Register enable time 5.0 5.0 ns
tGLOB Global control delay 1.0 1.0 ns
tPRE Register preset time 3.0 3.0 ns
tCLR Register clear time 3.0 3.0 ns
tPIA PIA de lay 1.0 1.0 ns
tLPA Low-power adder (8) 11.0 11.0 ns
32 Altera Corporation
MAX 7000 Programmable Logic D evi ce F ami l y Da ta Sh eet
Table 20. MAX 7000 & MAX 7000E External Timing Para meters Note (1)
Symbol Param et er Conditions Speed Grade Unit
MAX 70 00E ( -12P ) MAX 7000 (-12 )
MAX 7000E (-1 2)
Min Max Min Max
tPD1 Input to non-registere d output C1 = 35 pF 12.0 12.0 ns
tPD2 I/O input to non-registered output C1 = 35 pF 12.0 12.0 ns
tSU Global clock setup time 7.0 10.0 ns
tHGlobal clock hold time 0.0 0.0 ns
tFSU Global clock setup time of fast input (2) 3.0 3.0 ns
tFH Global clock hold time of fast input (2) 0.0 0.0 ns
tCO1 Global clock to output delay C1 = 35 pF 6.0 6.0 ns
tCH Global clock high time 4.0 4.0 ns
tCL Global clock low time 4.0 4.0 ns
tASU Array clock setup time 3.0 4.0 ns
tAH Array clock hold time 4.0 4.0 ns
tACO1 Array clock to output delay C1 = 35 pF 12.0 12.0 ns
tACH Array clock high time 5.0 5.0 ns
tACL Array clock low time 5.0 5.0 ns
tCPPW Minimum pulse w idth for clear and
preset (3) 5.0 5.0 ns
tODH Output data hold time after clock C1 = 35 pF (4) 1.0 1.0 ns
tCNT Minimum global clock period 11.0 11.0 ns
fCNT Maximum internal global clock
frequency (5) 90.9 90.9 MHz
tACNT Minimum array clock period 11.0 11.0 ns
fACNT Maximum internal array clock
frequency (5) 90.9 90.9 MHz
fMAX Maximum clock frequency (6) 125.0 125.0 MHz
Altera Corporation 33
MAX 7000 Pr o grammable Log i c Dev ic e Fam ily D ata Sh eet
Table 21. MAX 7000 & MAX 7000E Internal Timing Parameters Note (1)
Symbol Parameter Conditions Speed Grade Unit
MAX 7000E (-12P) MAX 7000 (-12)
MAX 7000E (-12)
Min Max Min Max
tIN Input pad and buffer delay 1.0 2.0 ns
tIO I/O input p ad and buffer delay 1.0 2.0 ns
tFIN Fast inpu t delay (2) 1.0 1.0 ns
tSEXP Shared expander delay 7.0 7.0 ns
tPEXP Parallel expander delay 1.0 1.0 ns
tLAD Logic array delay 7.0 5.0 ns
tLAC Logic control array delay 5.0 5.0 ns
tIOE Inte rnal output enable delay (2) 2.0 2.0 ns
tOD1 Output buffer and pad delay
Slow slew rate = off
VCCIO = 5.0 V
C1 = 35 pF 1.0 3.0 ns
tOD2 Output buffer and pad delay
Slow slew rate = off
VCCIO = 3.3 V
C1 = 35 pF (7) 2.0 4.0 ns
tOD3 Output buffer and pad delay
Slow slew rate = on
VCCIO = 5.0 V or 3.3 V
C1 = 35 pF (2) 5.0 7.0 ns
tZX1 Output buffer enable delay
Slow slew rate = off
VCCIO = 5.0 V
C1 = 35 pF 6.0 6.0 ns
tZX2 Output buffer enable delay
Slow slew rate = off
VCCIO = 3.3 V
C1 = 35 pF (7) 7.0 7.0 ns
tZX3 Output buffer enable delay
Slow slew rate = on
VCCIO = 5.0 V or 3.3 V
C1 = 35 pF (2) 10.0 10.0 ns
tXZ Output buffer disable delay C1 = 5 pF 6.0 6.0 ns
tSU Register setup time 1.0 4.0 ns
tHRegister hold time 6.0 4.0 ns
tFSU Register setup time of fast input (2) 4.0 2.0 ns
tFH Register hold time of fast input (2) 0.0 2.0 ns
tRD Register delay 2.0 1.0 ns
tCOMB Combinatorial delay 2.0 1.0 ns
tIC Array clock delay 5.0 5.0 ns
tEN Register enable time 7.0 5.0 ns
tGLOB Global control delay 2 .0 0.0 ns
tPRE Register preset time 4.0 3.0 ns
tCLR Register clear time 4.0 3.0 ns
tPIA PIA de lay 1.0 1.0 ns
tLPA Low-power adder (8) 12.0 12.0 ns
34 Altera Corporation
MAX 7000 Programmable Logic D evi ce F ami l y Da ta Sh eet
Table 22. MAX 7000 & MAX 7000E External Timing Para meters Note (1)
Symbo l Parameter Conditions Speed Gra de Unit
-15 -15T -20
Min Max Min Max Min Max
tPD1 Input to non-registered output C1 = 35 pF 15.0 15.0 20.0 ns
tPD2 I/O input to non-registered
output C1 = 35 pF 15.0 15.0 20.0 ns
tSU Global clock setup time 11.0 11.0 12.0 ns
tHGlobal clock hold time 0.0 0.0 0.0 ns
tFSU Global clock setup time of fast
input (2) 3.0 – 5.0 ns
tFH Global clock hold time of fast
input (2) 0.0 – 0.0 ns
tCO1 Global clock to output delay C1 = 35 pF 8.0 8.0 12.0 ns
tCH Global clock high time 5.0 6.0 6.0 ns
tCL Global clock low time 5.0 6.0 6.0 ns
tASU Array clock setup time 4.0 4.0 5.0 ns
tAH Array clock hold time 4.0 4.0 5.0 ns
tACO1 Array clock to output delay C1 = 35 pF 15.0 15.0 20.0 ns
tACH Array clock high time 6.0 6.5 8.0 ns
tACL Array clock low time 6.0 6.5 8.0 ns
tCPPW Minimum pulse width for clear
and preset (3) 6.0 6.5 8.0 ns
tODH Output data hold time after
clock C1 = 35 pF (4) 1.0 1.0 1.0 ns
tCNT Minimum global clock period 13.0 13.0 16.0 ns
fCNT Maximum internal global clock
frequency (5) 76.9 76.9 62.5 MHz
tACNT Minimum array clock period 13.0 13.0 16.0 ns
fACNT Maximum internal array clock
frequency (5) 76.9 76.9 62.5 MHz
fMAX Maximum clock frequency (6) 100 83.3 83.3 MHz
Altera Corporation 35
MAX 7000 Pr o grammable Log i c Dev ic e Fam ily D ata Sh eet
Table 23. MAX 7000 & MAX 7000E Internal Timing Parameters Note (1)
Symbol Parameter Conditions Speed Grade Unit
-15 -15T -20
Min Max Min Max Min Max
tIN Input pad and buffer delay 2.0 2.0 3.0 ns
tIO I/O input pad and buffer delay 2.0 2.0 3.0 ns
tFIN Fast input delay (2) 2.0 – 4.0 ns
tSEXP Shared e xpa nder delay 8.0 10.0 9.0 ns
tPEXP Parallel expander delay 1.0 1.0 2.0 ns
tLAD Logic array delay 6.0 6.0 8.0 ns
tLAC Logic control array delay 6.0 6.0 8.0 ns
tIOE In ternal output enable delay (2) 3.0 – 4.0 ns
tOD1 Output buffer and pad delay
Slow slew rate = off
VCCIO = 5.0 V
C1 = 35 pF 4.0 4.0 5.0 ns
tOD2 Output buffer and pad delay
Slow slew rate = off
VCCIO = 3.3 V
C1 = 35 pF (7) 5.0 – 6.0 ns
tOD3 Output buffer and pad delay
Slow slew rate = on
VCCIO = 5.0 V or 3.3 V
C1 = 35 pF (2) 8.0 – 9.0 ns
tZX1 Output buffer enable delay
Slow slew rate = off
VCCIO = 5.0 V
C1 = 35 pF 6.0 6.0 10.0 ns
tZX2 Output buffer enable delay
Slow slew rate = off
VCCIO = 3.3 V
C1 = 35 pF (7) 7.0 – 11.0 ns
tZX3 Output buffer enable delay
Slow slew rate = on
VCCIO = 5.0 V or 3.3 V
C1 = 35 pF (2) 10.0 – 14.0 ns
tXZ Outp ut buffer disable delay C1 = 5 pF 6.0 6.0 10.0 ns
tSU Register setup time 4.0 4.0 4.0 ns
tHRegister hold time 4.0 4.0 5.0 ns
tFSU Register setup time of fast input (2) 2.0 – 4.0 ns
tFH Register hold time of fast inpu t (2) 2.0 – 3.0 ns
tRD Register delay 1.0 1.0 1.0 ns
tCOMB Combinator ia l de lay 1.0 1.0 1.0 ns
tIC Array clock delay 6.0 6.0 8.0 ns
tEN Register enable time 6.0 6.0 8.0 ns
tGLOB Global control delay 1.0 1.0 3.0 ns
tPRE Register preset time 4.0 4.0 4.0 ns
tCLR Register clear time 4.0 4.0 4.0 ns
tPIA PIA delay 2.0 2.0 3.0 ns
tLPA Low-power adder (8) 13.0 15.0 15.0 ns
36 Altera Corporation
MAX 7000 Programmable Logic D evi ce F ami l y Da ta Sh eet
Notes to table s:
(1) These values are specified under the recommended operating conditions shown in Table 11. See Figure 13 for more
information on switching waveforms.
(2) This parameter applies to MA X 7000E devic es only .
(3) Thi s minimum puls e width for pre set and clear app lies for both g lobal clear a nd array controls. The tLPA pa ra met er
must be added to this minimum width if the clear or reset signal incorporates the tLAD parameter into the signal
path.
(4) This pa r ameter is a gu id eline that is s ample -t ested o nl y and is based o n extensive device c harac t er ization. This
parameter applies for both global and array clocking.
(5) These parameters are measured with a 16-bi t load ab le, enabled , up/ d own count er pr og r ammed into ea c h LA B.
(6) The fMAX values rep re s en t th e highest fr eq uency for pipeli ned dat a.
(7) Operating conditions: VCCIO = 3.3 V ± 10% for com me rci al an d in d u stri al u se.
(8) The tLPA parameter must be added to the tLAD, t LAC, tIC, tEN, tSEXP, tACL, and tCPPW parameters for macrocells
runn ing in the low-p ower mod e.
Tables 24 and 25 show the EPM703 2S AC operati ng condit ions .
Table 24. EPM7032S External Timing Parameters (Part 1 of 2) Note (1)
Symbol Parame t er Conditions Speed Grade U nit
-5 -6 -7 -10
Min Max Min Max Min Max Min Max
tPD1 Input to non-registered output C1 = 35 pF 5.0 6.0 7.5 10.0 ns
tPD2 I/O input to non-registered
output C1 = 35 pF 5.0 6.0 7.5 10.0 ns
tSU Global clock setup time 2.9 4.0 5.0 7.0 ns
tHGlobal clock hold time 0.0 0.0 0.0 0.0 ns
tFSU Global clock setup time of fast
input 2.5 2.5 2.5 3.0 ns
tFH Global clock hold time of fast
input 0.0 0.0 0.0 0.5 ns
tCO1 Global clock to output delay C1 = 35 pF 3.2 3.5 4.3 5.0 ns
tCH Global clock high time 2.0 2.5 3.0 4.0 ns
tCL Global clock low time 2.0 2.5 3.0 4.0 ns
tASU Array clock setup time 0.7 0.9 1.1 2.0 ns
tAH Array clock hold time 1.8 2.1 2.7 3. 0 ns
tACO1 Array clock to output delay C1 = 35 pF 5.4 6.6 8.2 10.0 ns
tACH Array clock high time 2.5 2.5 3.0 4. 0 ns
tACL Array clock low time 2.5 2.5 3.0 4.0 ns
tCPPW M inimum pulse width for clear
and preset (2) 2.5 2.5 3.0 4.0 ns
tODH Output data hold tim e after
clock C1 = 35 pF (3) 1.0 1.0 1.0 1.0 ns
tCNT Minimum global clock period 5.7 7.0 8.6 10.0 ns
fCNT Maximum inte rnal global clock
frequency (4) 175.4 142.9 116.3 100.0 MHz
tACNT Minimum array clock period 5.7 7.0 8.6 10.0 ns
Altera Corporation 37
MAX 7000 Pr o grammable Log i c Dev ic e Fam ily D ata Sh eet
fACNT Maximum internal array clock
frequency (4) 175.4 142.9 116.3 100.0 MHz
fMAX Maximum clock frequency (5) 250.0 200.0 166.7 125.0 MHz
Table 25. EPM7032S Inter n al Timing Parameters Note (1)
Symb ol Parameter Condit i o ns Spe ed G r ade Unit
-5 -6 -7 -10
MinMaxMinMaxMinMaxMinMax
tIN Input pad and buffer delay 0.2 0.2 0.3 0.5 ns
tIO I/O input pad and buffer delay 0.2 0.2 0.3 0.5 ns
tFIN Fast input delay 2.2 2.1 2.5 1.0 ns
tSEXP Shared expander delay 3.1 3.8 4.6 5.0 ns
tPEXP Parallel expander delay 0.9 1.1 1.4 0.8 ns
tLAD Logic array delay 2.6 3.3 4.0 5.0 ns
tLAC Logic control array delay 2.5 3.3 4.0 5.0 ns
tIOE Internal output enable delay 0.7 0.8 1.0 2.0 ns
tOD1 Output buffer and pad delay C1 = 35 pF 0.2 0.3 0.4 1. 5 ns
tOD2 Output buffer and pad delay C1 = 35 pF (6) 0.7 0.8 0.9 2.0 ns
tOD3 Output buffer and pad delay C1 = 35 pF 5.2 5.3 5.4 5.5 ns
tZX1 Output buffer e nable delay C1 = 35 pF 4.0 4.0 4.0 5.0 ns
tZX2 Output buffer e nable delay C1 = 35 pF (6) 4.5 4.5 4.5 5.5 ns
tZX3 Output buffer e nable delay C1 = 35 pF 9.0 9.0 9.0 9.0 ns
tXZ Output buffer disable delay C1 = 5 pF 4.0 4.0 4.0 5.0 ns
tSU Register setup time 0.8 1.0 1.3 2.0 ns
tHRegister hold time 1.7 2.0 2.5 3.0 ns
tFSU Register setup time of fast
input 1.9 1.8 1.7 3.0 ns
tFH Register hold time of fast
input 0.6 0.7 0.8 0.5 ns
tRD Register delay 1.2 1.6 1.9 2.0 ns
tCOMB Com bina torial delay 0.9 1.1 1.4 2.0 ns
tIC Array clock delay 2.7 3.4 4.2 5.0 ns
tEN Register enable time 2.6 3.3 4.0 5.0 ns
tGLOB Global control delay 1.6 1.4 1.7 1.0 ns
tPRE Register preset time 2.0 2.4 3.0 3.0 ns
Table 24. EPM7032S External Timing Parameters (Part 2 of 2) Note (1)
Symbol Parameter Conditions Speed Grade Unit
-5 -6 -7 -10
Min Max Min Max Min Max Min Max
38 Altera Corporation
MAX 7000 Programmable Logic D evi ce F ami l y Da ta Sh eet
Notes to table s:
(1) These values are specified under the recommended operating conditions shown in Table 11. See Figure 13 for more
information on switching waveforms.
(2) This minimum puls e width for pre set and clear app lies for both g lobal clear a nd array controls. The tLPA pa ra met er
must be added to this minimum width if the clear or reset signal incorporates the tLAD parameter into the signal
path.
(3) This pa r ameter is a gu id eline that is s ample -t ested o nl y and is based o n extensive device c harac t er ization. This
parameter applies for both global and array clocking.
(4) These parameters are measured with a 16-bi t load ab le, enabled , up/ d own count er pr og r ammed into ea c h LA B.
(5) The fMAX values rep re s en t th e highest fr eq uency for pipeli ned dat a.
(6) Operating conditions: VCCIO = 3.3 V ± 10% for com me rci al an d in d u stri al u se.
(7) For EPM7064S-5, E PM 7064S-6, EPM 7128S-6, EP M 7160S-6, EPM 7160S-7, EPM 7192S-7, an d EPM 7256S-7 devices,
these v alues are s pe c ified for a PIA fan-out of one LA B (16 macrocells). Fo r ea c h add itional LAB fan -out in these
devices, add an additional 0.1 ns to the PIA timing value.
(8) The tLPA parameter must be added to the tLAD, t LAC, tIC, tEN, tSEXP, tACL, and tCPPW parameters for macrocells
runn ing in the low-p ower mod e.
Tables 26 and 27 show the EPM706 4S AC operati ng condit ions .
tCLR Register clear time 2.0 2.4 3.0 3.0 ns
tPIA PIA delay (7) 1.1 1.1 1.4 1.0 ns
tLPA Low-power adder (8) 12.0 10.0 10.0 11.0 ns
Table 25. EPM7032S Internal Timing Par ameters Note (1)
Symb ol Param ete r Conditio ns Speed Grad e Un it
-5 -6 -7 -10
Min Max Min Max Min Max Min Max
Table 26. EPM7064S External Timing Parameters (Part 1 of 2) Note (1)
Symbol Parameter Conditions Speed Grade Unit
-5 -6 -7 -10
Min Max Min Max Min Max Min Max
tPD1 Input to non-registered output C1 = 35 pF 5.0 6.0 7.5 10.0 ns
tPD2 I/O input to non-registered
output C1 = 35 pF 5.0 6.0 7.5 10.0 ns
tSU Global clock setup time 2.9 3.6 6.0 7.0 ns
tHGlobal clock hold time 0.0 0.0 0.0 0.0 ns
tFSU Global clock setup time of fast
input 2.5 2.5 3.0 3.0 ns
tFH Global clock hold time of fast
input 0.0 0.0 0.5 0.5 ns
tCO1 Global clock to output delay C1 = 35 pF 3.2 4.0 4.5 5.0 ns
tCH Global clock high time 2.0 2.5 3.0 4.0 ns
tCL Global clock low time 2.0 2.5 3.0 4.0 ns
tASU Array clock setup time 0.7 0.9 3.0 2.0 ns
Altera Corporation 39
MAX 7000 Pr o grammable Log i c Dev ic e Fam ily D ata Sh eet
tAH Array clock hold time 1.8 2.1 2.0 3.0 ns
tACO1 Array clock to output delay C1 = 35 pF 5.4 6.7 7.5 10.0 ns
tACH Array clock high time 2.5 2.5 3.0 4.0 ns
tACL Array clock low time 2.5 2.5 3.0 4.0 ns
tCPPW Minimum pulse width for clear
and preset (2) 2.5 2.5 3.0 4.0 ns
tODH Output data hold time after
clock C1 = 35 pF (3) 1.0 1.0 1.0 1.0 ns
tCNT Minimum global clock period 5.7 7.1 8.0 10.0 ns
fCNT Maximum internal global clock
frequency (4) 175.4 140.8 125.0 100.0 MHz
tACNT Minimum array clock period 5.7 7 .1 8.0 10.0 ns
fACNT Maximum internal array clock
frequency (4) 175.4 140.8 125.0 100.0 MHz
fMAX Maximum clock frequency (5) 250.0 200.0 166.7 125.0 MHz
Table 27. EPM7064S Inter nal Timing Parameters (Part 1 of 2) Note (1)
Symbol Parameter Conditions Speed Grade Unit
-5 -6 -7 -10
Min Max Min Max Min Max Min Max
tIN Input pad and buffer delay 0.2 0.2 0.5 0.5 ns
tIO I/O input pad and buffer delay 0.2 0.2 0.5 0.5 ns
tFIN Fast input delay 2.2 2.6 1.0 1.0 ns
tSEXP Shared expander delay 3.1 3.8 4.0 5.0 ns
tPEXP Parallel expander delay 0.9 1.1 0.8 0.8 ns
tLAD Logic array delay 2.6 3.2 3.0 5.0 ns
tLAC Logic control array delay 2.5 3.2 3.0 5.0 ns
tIOE Internal output enable delay 0.7 0.8 2.0 2.0 ns
tOD1 Output buffer and pad delay C1 = 35 pF 0.2 0.3 2.0 1.5 ns
tOD2 Output buffer and pad delay C1 = 35 pF (6) 0.7 0.8 2.5 2.0 ns
tOD3 Output buffer and pad delay C1 = 35 pF 5.2 5.3 7.0 5.5 ns
tZX1 Output buffer e nable delay C1 = 35 pF 4.0 4.0 4.0 5.0 ns
tZX2 Output buffer e nable delay C1 = 35 pF (6) 4.5 4.5 4.5 5.5 ns
tZX3 Output buffer e nable delay C1 = 35 pF 9.0 9.0 9.0 9.0 ns
tXZ Output buffer disable delay C1 = 5 pF 4.0 4.0 4.0 5.0 ns
tSU Register setup time 0.8 1.0 3.0 2.0 ns
Table 26. EPM7064S External Timing Parameters (Part 2 of 2) Note (1)
Symbo l Parameter Conditions Speed Grade Unit
-5 -6 -7 -10
MinMaxMinMaxMinMaxMinMax
40 Altera Corporation
MAX 7000 Programmable Logic D evi ce F ami l y Da ta Sh eet
Notes to table s:
(1) These values are specified under the recommended operating conditions shown in Table 11. See Figure 13 for more
information on switching waveforms.
(2) This minimum puls e width for pre set and clear app lies for both g lobal clear a nd array controls. The tLPA pa ra met er
must be added to this minimum width if the clear or reset signal incorporates the tLAD parameter into the signal
path.
(3) This pa r ameter is a gu id eline that is s ample -t ested o nl y and is based o n extensive device c harac t er ization. This
parameter applies for both global and array clocking.
(4) These parameters are measured with a 16-bi t load ab le, enabled , up/ d own count er pr og r ammed into ea c h LA B.
(5) The fMAX values rep re s en t th e highest fr eq uency for pipeli ned dat a.
(6) Operating conditions: VCCIO = 3.3 V ± 10% for com me rci al an d in d u stri al u se.
(7) For EPM7064S-5, E PM 7064S-6, EPM 7128S-6, EP M 7160S-6, EPM 7160S-7, EPM 7192S-7, an d EPM 7256S-7 devices,
these v alues are s pe c ified for a PIA fan-out of one LA B (16 macrocells). Fo r ea c h add itional LAB fan -out in these
devices, add an additional 0.1 ns to the PIA timing value.
(8) The tLPA parameter must be added to the tLAD, t LAC, tIC, tEN, tSEXP, tACL, and tCPPW parameters for macrocells
runn ing in the low-p ower mod e.
tHRegister hold time 1.7 2.0 2.0 3.0 ns
tFSU Register setup time of fast
input 1.9 1.8 3.0 3.0 ns
tFH Register hold time of fast
input 0.6 0.7 0.5 0.5 ns
tRD Register delay 1.2 1.6 1.0 2.0 ns
tCOMB Combinatorial delay 0.9 1.0 1.0 2.0 ns
tIC Array clock delay 2.7 3.3 3.0 5.0 ns
tEN Register enable time 2.6 3.2 3.0 5.0 ns
tGLOB Global control delay 1.6 1.9 1.0 1.0 ns
tPRE Register preset time 2.0 2.4 2.0 3.0 ns
tCLR Register clear time 2.0 2.4 2.0 3.0 ns
tPIA PIA delay (7) 1.1 1.3 1.0 1.0 ns
tLPA Low-power adder (8) 12.0 11.0 10.0 11.0 ns
Table 27. EPM7064S Internal Timing Parameters (Part 2 of 2) Note (1)
Symbo l Pa rameter Condi t io ns Spe ed G rade Un it
-5 -6 -7 -10
Min Max Min Max Min Max Min Max
Altera Corporation 41
MAX 7000 Pr o grammable Log i c Dev ic e Fam ily D ata Sh eet
Tables 28 and 29 show the EPM7128S AC operating conditions.
Tab l e 28. EPM71 28 S Ext erna l Timi ng Par a met e r s Note (1)
Symbo l Parameter Conditions Speed Grade Unit
-6 -7 -10 -15
MinMaxMinMaxMinMaxMinMax
tPD1 Input to non-registered output C1 = 35 pF 6.0 7.5 10.0 15.0 ns
tPD2 I/O input to non-registered
output C1 = 35 pF 6.0 7.5 10.0 15.0 ns
tSU Global clock setup time 3.4 6.0 7.0 11.0 ns
tHGlobal clock hold time 0.0 0.0 0.0 0.0 ns
tFSU Global clock setup time of fast
input 2.5 3.0 3.0 3.0 ns
tFH Global clock hold time of fast
input 0.0 0.5 0.5 0.0 ns
tCO1 Global clock to output delay C1 = 35 pF 4.0 4.5 5.0 8.0 ns
tCH Global clock high time 3.0 3.0 4.0 5.0 ns
tCL Global clock low time 3.0 3.0 4.0 5.0 ns
tASU Array clock setup time 0.9 3.0 2.0 4.0 ns
tAH Array clock hold time 1.8 2.0 5.0 4.0 ns
tACO1 Array clock to output delay C1 = 35 pF 6.5 7.5 10.0 15.0 ns
tACH Array clock high time 3.0 3.0 4.0 6.0 ns
tACL Array clock low time 3.0 3.0 4.0 6.0 ns
tCPPW Minimum pulse width for clear
and preset (2) 3.0 3.0 4.0 6.0 ns
tODH Output data hold time after
clock C1 = 35 pF (3) 1.0 1.0 1.0 1.0 ns
tCNT Minimum global clock period 6.8 8.0 10.0 13.0 ns
fCNT Maximum internal global clock
frequency (4) 147.1 125.0 100.0 76.9 MHz
tACNT Minimum array clock period 6.8 8.0 10.0 13.0 ns
fACNT Maximum internal array clock
frequency (4) 147.1 125.0 100.0 76.9 MHz
fMAX Maximum clock frequency (5) 166.7 166.7 125.0 100.0 MHz
42 Altera Corporation
MAX 7000 Programmable Logic D evi ce F ami l y Da ta Sh eet
Table 29. EPM7128S Inter n al Timing Parameters Note (1)
Symbol Parameter Conditions Speed Grade Unit
-6 -7 -10 -15
Min Max Min Max Min Max Min Max
tIN Input pad and buffer delay 0.2 0.5 0.5 2.0 ns
tIO I/O input pad and buffer delay 0.2 0.5 0.5 2.0 ns
tFIN Fast input delay 2.6 1.0 1.0 2.0 ns
tSEXP Shared expander delay 3.7 4.0 5.0 8.0 ns
tPEXP Parallel expander delay 1.1 0.8 0.8 1.0 ns
tLAD Logic array delay 3.0 3.0 5.0 6.0 ns
tLAC Logic control array delay 3.0 3.0 5.0 6.0 ns
tIOE Internal output enable delay 0.7 2.0 2.0 3.0 ns
tOD1 Output buffer and pad delay C1 = 35 pF 0.4 2.0 1.5 4.0 ns
tOD2 Output buffer and pad delay C1 = 35 pF (6) 0.9 2.5 2.0 5.0 ns
tOD3 Output buffer and pad delay C1 = 35 pF 5.4 7.0 5.5 8.0 ns
tZX1 Output buffer e nable delay C1 = 35 pF 4.0 4.0 5.0 6.0 ns
tZX2 Output buffer e nable delay C1 = 35 pF (6) 4.5 4.5 5.5 7.0 ns
tZX3 Output buffer e nable delay C1 = 35 pF 9.0 9.0 9.0 10.0 ns
tXZ Output buffer disable delay C1 = 5 pF 4.0 4.0 5.0 6.0 ns
tSU Register setup time 1.0 3.0 2.0 4.0 ns
tHRegister hold time 1.7 2.0 5.0 4.0 ns
tFSU Register setup time of fast
input 1.9 3.0 3.0 2.0 ns
tFH Register hold time of fast
input 0.6 0.5 0.5 1.0 ns
tRD Register delay 1.4 1.0 2.0 1.0 ns
tCOMB Com b ina torial delay 1.0 1.0 2.0 1.0 ns
tIC Array clock delay 3.1 3.0 5.0 6.0 ns
tEN Register enable time 3.0 3.0 5.0 6.0 ns
tGLOB Global control delay 2.0 1.0 1.0 1.0 ns
tPRE Register preset time 2.4 2.0 3.0 4.0 ns
tCLR Register clear time 2.4 2.0 3.0 4.0 ns
tPIA PIA delay (7) 1.4 1.0 1.0 2.0 ns
tLPA Low-power adder (8) 11.0 10.0 11.0 13.0 ns
Altera Corporation 43
MAX 7000 Pr o grammable Log i c Dev ic e Fam ily D ata Sh eet
Notes to table s:
(1) These values are specified under the recommended operating conditions shown in Table 11. See Figure 13 for more
information on switching waveforms.
(2) This minimum puls e width for pre set and clear app lies for both g lobal clear a nd array controls. The tLPA pa ra met er
must be added to this minimum width if the clear or reset signal incorporates the tLAD parameter into the signal
path.
(3) This pa r ameter is a gu id eline that is s ample -t ested o nl y and is based o n extensive device c harac t er ization. This
parameter applies for both global and array clocking.
(4) These parameters are measured with a 16-bi t load ab le, enabled , up/ d own count er pr og r ammed into ea c h LA B.
(5) The fMAX values rep re s en t th e highest fr eq uency for pipeli ned dat a.
(6) Operating conditions: VCCIO = 3.3 V ± 10% for com me rci al an d in d u stri al u se.
(7) For EPM7064S-5, E PM 7064S-6, EPM 7128S-6, EP M 7160S-6, EPM 7160S-7, EPM 7192S-7, an d EPM 7256S-7 devices,
these v alues are s pe c ified for a PIA fan-out of one LA B (16 macrocells). Fo r ea c h add itional LAB fan -out in these
devices, add an additional 0.1 ns to the PIA timing value.
(8) The tLPA parameter must be added to the tLAD, t LAC, tIC, tEN, tSEXP, tACL, and tCPPW parameters for macrocells
runn ing in the low-p ower mod e.
Tables 30 and 31 show the EPM7160S AC operating conditions.
Table 30. EPM7160S External Timing Parameters (Part 1 of 2) Note (1)
Symbol Parameter Conditions Speed Grade Unit
-6 -7 -10 -15
Min Max Min Max Min Max Min Max
tPD1 Input to non-registered output C1 = 35 pF 6.0 7.5 10.0 15.0 ns
tPD2 I/O input to non-registered
output C1 = 35 pF 6.0 7.5 10.0 15 .0 ns
tSU Global clock setup time 3.4 4.2 7.0 11.0 ns
tHGlobal clock hold time 0.0 0.0 0.0 0.0 ns
tFSU Global clock setup time of fast
input 2.5 3.0 3.0 3.0 ns
tFH Global clock hold time of fast
input 0.0 0.0 0.5 0.0 ns
tCO1 Global clock to output delay C1 = 35 pF 3.9 4.8 5 8 ns
tCH Global clock high time 3.0 3.0 4.0 5.0 ns
tCL Global clock low time 3.0 3.0 4.0 5.0 ns
tASU Array clock setup time 0.9 1.1 2.0 4.0 ns
tAH Array clock hold time 1.7 2.1 3.0 4.0 ns
tACO1 Array clock to output delay C1 = 35 pF 6.4 7.9 10.0 15.0 ns
tACH Array clock high time 3.0 3.0 4.0 6.0 ns
tACL Array clock low time 3.0 3.0 4.0 6.0 ns
tCPPW M inimum pulse width for clear
and preset (2) 2.5 3.0 4.0 6.0 ns
tODH Output data hold tim e after
clock C1 = 35 pF (3) 1.0 1.0 1.0 1.0 ns
tCNT Minimum glob al clock period 6.7 8.2 10.0 13.0 ns
fCNT Maximum inte rnal global clock
frequency (4) 149.3 122.0 100.0 76.9 MHz
44 Altera Corporation
MAX 7000 Programmable Logic D evi ce F ami l y Da ta Sh eet
tACNT Minimum array clock period 6.7 8.2 10.0 13.0 ns
fACNT Maximum internal array clock
frequency (4) 149.3 122.0 100.0 76.9 MHz
fMAX Maximum clock frequency (5) 166.7 166.7 125.0 100.0 MHz
Table 31. EPM7160S Inter nal Timing Parameters (Part 1 of 2) Note (1)
Symbol Parameter Conditions Speed Grade Unit
-6 -7 -10 -15
Min Max Min Max Min Max Min Max
tIN Input pad and buffer delay 0.2 0.3 0.5 2.0 ns
tIO I/O input pad and buffer delay 0.2 0.3 0.5 2.0 ns
tFIN Fast input delay 2.6 3.2 1.0 2.0 ns
tSEXP Shared expander delay 3.6 4.3 5.0 8.0 ns
tPEXP Parallel expander delay 1.0 1.3 0.8 1.0 ns
tLAD Logic array delay 2.8 3.4 5.0 6.0 ns
tLAC Logic control array delay 2.8 3.4 5.0 6.0 ns
tIOE Internal output enable delay 0.7 0.9 2.0 3.0 ns
tOD1 Output buffer and pad delay C1 = 35 pF 0.4 0.5 1.5 4.0 ns
tOD2 Output buffer and pad delay C1 = 35 pF (6) 0.9 1.0 2.0 5.0 ns
tOD3 Output buffer and pad delay C1 = 35 pF 5.4 5.5 5.5 8.0 ns
tZX1 Output buffer e nable delay C1 = 35 pF 4.0 4.0 5.0 6.0 ns
tZX2 Output buffer e nable delay C1 = 35 pF (6) 4.5 4.5 5.5 7.0 ns
tZX3 Output buffer e nable delay C1 = 35 pF 9.0 9.0 9.0 10.0 ns
tXZ Output buffer disable delay C1 = 5 pF 4.0 4.0 5.0 6.0 ns
tSU Register setup time 1.0 1.2 2.0 4.0 ns
tHRegister hold time 1.6 2.0 3.0 4.0 ns
tFSU Register setup time of fast
input 1.9 2.2 3.0 2.0 ns
tFH Register hold time of fast
input 0.6 0.8 0.5 1.0 ns
tRD Register delay 1.3 1.6 2.0 1.0 ns
tCOMB Com b ina torial delay 1.0 1.3 2.0 1.0 ns
tIC Array clock delay 2.9 3.5 5.0 6.0 ns
tEN Register enable time 2.8 3.4 5.0 6.0 ns
tGLOB Global control delay 2.0 2.4 1.0 1.0 ns
Table 30. EPM7160S External Timing Parameters (Part 2 of 2) Note (1)
Symbo l Parameter Conditions Speed Grade Unit
-6 -7 -10 -15
MinMaxMinMaxMinMaxMinMax
Altera Corporation 45
MAX 7000 Pr o grammable Log i c Dev ic e Fam ily D ata Sh eet
Notes to table s:
(1) These values are specified under the recommended operating conditions shown in Table 11. See Figure 13 for more
information on switching waveforms.
(2) This minimum puls e width for pre set and clear app lies for both g lobal clear a nd array controls. The tLPA pa ra met er
must be added to this minimum width if the clear or reset signal incorporates the tLAD parameter into the signal
path.
(3) This pa r ameter is a gu id eline that is s ample -t ested o nl y and is based o n extensive device c harac t er ization. This
parameter applies for both global and array clocking.
(4) These parameters are measured with a 16-bi t load ab le, enabled , up/ d own count er pr og r ammed into ea c h LA B.
(5) The fMAX values rep re s en t th e highest fr eq uency for pipeli ned dat a.
(6) Operating conditions: VCCIO = 3.3 V ± 10% for commercial and industrial use.
(7) For EPM7064S-5, E PM 7064S-6, EPM 7128S-6, EP M 7160S-6, EPM 7160S-7, EPM 7192S-7, an d EPM 7256S-7 devices,
these v alues are s pe c ified for a PIA fan-out of one LA B (16 macrocells). Fo r ea c h add itional LAB fan -out in these
devices, add an additional 0.1 ns to the PIA timing value.
(8) The tLPA parameter must be added to the tLAD, t LAC, tIC, tEN, tSEXP, tACL, and tCPPW parameters for macrocells
runn ing in the low-p ower mod e.
Tables 32 and 33 show the EPM719 2S AC operati ng condit ions .
tPRE Register preset time 2.4 3.0 3.0 4.0 ns
tCLR Register clear time 2.4 3.0 3.0 4.0 ns
tPIA PIA delay (7) 1.6 2.0 1.0 2.0 ns
tLPA Low-power adder (8) 11.0 10.0 11.0 13.0 ns
Table 31. EPM7160S Internal Timing Parameters (Part 2 of 2) Note (1)
Symbo l Pa rameter Condi t io ns Spe ed G rade Un it
-6 -7 -10 -15
Min Max Min Max Min Max Min Max
Table 32. EPM7192S External Timing Parameters (Part 1 of 2) Note (1)
Symbol Parameter Conditions Speed Grade Unit
-7 -10 -15
MinMaxMinMaxMinMax
tPD1 Input to non-registered output C1 = 35 pF 7.5 10.0 15.0 ns
tPD2 I/O input to non-registered
output C1 = 35 pF 7.5 10.0 15.0 ns
tSU Global clock setup time 4.1 7.0 11.0 ns
tHGlobal clock hold time 0.0 0.0 0.0 ns
tFSU Global clock setup time of fast
input 3.0 3.0 3.0 ns
tFH Global clock hold time of fast
input 0.0 0.5 0.0 ns
tCO1 Global clock to output delay C1 = 35 pF 4.7 5 .0 8.0 ns
tCH Global clock high time 3.0 4.0 5.0 ns
46 Altera Corporation
MAX 7000 Programmable Logic D evi ce F ami l y Da ta Sh eet
tCL Global clock low time 3.0 4.0 5.0 ns
tASU Array clock setup time 1.0 2.0 4.0 ns
tAH Array clock hold time 1.8 3.0 4. 0 ns
tACO1 Array clock to output delay C1 = 35 pF 7.8 10.0 15.0 ns
tACH Array clock high time 3.0 4.0 6.0 ns
tACL Array clock low time 3.0 4.0 6.0 ns
tCPPW Minimum pulse width for clear
and preset (2) 3.0 4.0 6.0 ns
tODH Output data hold time after
clock C1 = 35 pF (3) 1.0 1.0 1.0 ns
tCNT Minimum global clock period 8.0 10.0 13.0 ns
fCNT Maximum internal global clock
frequency (4) 125.0 100.0 76.9 MHz
tACNT Minimum array clock period 8.0 10.0 13.0 ns
fACNT Maximum internal array clock
frequency (4) 125.0 100.0 76.9 MHz
fMAX Maximum clock frequency (5) 166.7 125.0 100.0 MHz
Table 33. EPM7192S Inter nal Timing Parameters (Part 1 of 2) Note (1)
Symbol Parameter Conditions Speed Grade Unit
-7 -10 -15
Min Max Min Max Min Max
tIN Input pad and buffer delay 0.3 0.5 2.0 n s
tIO I/O input pad and buffer delay 0.3 0.5 2.0 ns
tFIN Fast input delay 3.2 1.0 2.0 n s
tSEXP Shared expander delay 4.2 5.0 8.0 ns
tPEXP Parallel expander delay 1.2 0.8 1.0 ns
tLAD Logic array delay 3.1 5.0 6.0 ns
tLAC Logic control array delay 3.1 5.0 6.0 ns
tIOE Internal output enable delay 0.9 2.0 3.0 ns
tOD1 Output buffer and pad delay C1 = 35 pF 0.5 1.5 4.0 n s
tOD2 Output buffer and pad delay C1 = 35 pF (6) 1.0 2.0 5.0 ns
tOD3 Output buffer and pad delay C1 = 35 pF 5.5 5.5 7.0 ns
tZX1 Output buffer e nable delay C1 = 35 pF 4.0 5.0 6. 0 ns
tZX2 Output buffer e nable delay C1 = 35 pF (6) 4.5 5.5 7.0 ns
tZX3 Output buffer e nable delay C1 = 35 pF 9.0 9.0 10.0 ns
Table 32. EPM7192S External Timing Parameters (Part 2 of 2) Note (1)
Symbo l Parameter Conditions Speed Gra de Unit
-7 -10 -15
Min Max Min Max Min Max
Altera Corporation 47
MAX 7000 Pr o grammable Log i c Dev ic e Fam ily D ata Sh eet
Notes to table s:
(1) These values are specified under the recommended operating conditions shown in Table 11. See Figure 13 for more
information on switching waveforms.
(2) This minimum puls e width for pre set and clear app lies for both g lobal clear a nd array controls. The tLPA pa ra met er
must be added to this minimum width if the clear or reset signal incorporates the tLAD parameter into the signal
path.
(3) This pa r ameter is a gu id eline that is s ample -t ested o nl y and is based o n extensive device c harac t er ization. This
parameter applies for both global and array clocking.
(4) These parameters are measured with a 16-bi t load ab le, enabled , up/ d own count er pr og r ammed into ea c h LA B.
(5) The fMAX values rep re s en t th e highest fr eq uency for pipeli ned dat a.
(6) Operating conditions: VCCIO = 3.3 V ± 10% for com me rci al an d in d u stri al u se.
(7) For EPM7064S-5, E PM 7064S-6, EPM 7128S-6, EP M 7160S-6, EPM 7160S-7, EPM 7192S-7, an d EPM 7256S-7 devices,
these v alues are s pe c ified for a PIA fan-out of one LA B (16 macrocells). Fo r ea c h add itional LAB fan -out in these
devices, add an additional 0.1 ns to the PIA timing value.
(8) The tLPA parameter must be added to the tLAD, t LAC, tIC, tEN, tSEXP, tACL, and tCPPW parameters for macrocells
runn ing in the low-p ower mod e.
tXZ Output bu ffer disable delay C1 = 5 pF 4.0 5.0 6.0 ns
tSU Register setup time 1.1 2.0 4.0 ns
tHRegister hold time 1.7 3.0 4.0 ns
tFSU Register setup time of fast
input 2.3 3.0 2.0 ns
tFH Register hold time of fast
input 0.7 0.5 1.0 ns
tRD Register delay 1.4 2.0 1.0 ns
tCOMB Combinatorial delay 1.2 2.0 1.0 ns
tIC Array clock delay 3.2 5.0 6.0 ns
tEN Register enable time 3.1 5.0 6.0 ns
tGLOB Global control delay 2.5 1.0 1.0 ns
tPRE Register preset time 2.7 3.0 4.0 ns
tCLR Register clear time 2.7 3.0 4.0 ns
tPIA PIA delay (7) 2.4 1.0 2.0 ns
tLPA Low-power adder (8) 10.011.013.0ns
Table 33. EPM7192S Internal Timing Parameters (Part 2 of 2) Note (1)
Symbol Parameter Conditions Speed G rade Unit
-7 -10 -15
Min Max Min Max Min Max
48 Altera Corporation
MAX 7000 Programmable Logic D evi ce F ami l y Da ta Sh eet
Tables 34 and 35 show the EPM7256S AC operating conditions.
Tab l e 34. EPM72 56 S Ext erna l Timi ng Par a met e r s Note (1)
Symbo l Parameter Conditions Speed Gra de Unit
-7 -10 -15
Min Max Min Max Min Max
tPD1 Input to non-registered output C1 = 35 pF 7.5 10.0 15.0 ns
tPD2 I/O input to non-registered
output C1 = 35 pF 7.5 10.0 15.0 ns
tSU Global clock setup time 3.9 7.0 11.0 ns
tHGlobal clock hold time 0.0 0.0 0.0 ns
tFSU Global clock setup time of fast
input 3.0 3.0 3.0 ns
tFH Global clock hold time of fast
input 0.0 0.5 0.0 ns
tCO1 Global clock to output delay C1 = 35 pF 4.7 5.0 8.0 ns
tCH Global clock high time 3.0 4.0 5.0 ns
tCL Global clock low time 3.0 4.0 5.0 ns
tASU Array clock setup time 0.8 2.0 4.0 ns
tAH Array clock hold time 1.9 3.0 4. 0 ns
tACO1 Array clock to output delay C1 = 35 pF 7.8 10.0 15.0 ns
tACH Array clock high time 3.0 4.0 6.0 ns
tACL Array clock low time 3.0 4.0 6.0 ns
tCPPW Minimum pulse width for clear
and preset (2) 3.0 4.0 6.0 ns
tODH Output data hold time after
clock C1 = 35 pF (3) 1.0 1.0 1.0 ns
tCNT Minimum global clock period 7.8 10.0 13.0 ns
fCNT Maximum internal global clock
frequency (4) 128.2 100.0 76.9 MHz
tACNT Minimum array clock period 7.8 10.0 13.0 ns
fACNT Maximum internal array clock
frequency (4) 128.2 100.0 76.9 MHz
fMAX Maximum clock frequency (5) 166.7 125.0 100.0 MHz
Altera Corporation 49
MAX 7000 Pr o grammable Log i c Dev ic e Fam ily D ata Sh eet
Table 35. EPM7256S Internal Timing Par ameters Note (1)
Symbol Parameter Conditions Speed G rade Unit
-7 -10 -15
Min Max Min Max Min Max
tIN Input pad and buffer delay 0.3 0.5 2.0 ns
tIO I/O input pad and buffer delay 0.3 0.5 2.0 ns
tFIN Fast input de la y 3.4 1.0 2.0 ns
tSEXP Shared expander delay 3.9 5.0 8.0 ns
tPEXP Parallel expander delay 1.1 0.8 1.0 ns
tLAD Logic array delay 2.6 5.0 6.0 ns
tLAC Logic control array delay 2.6 5.0 6.0 ns
tIOE Internal output enable delay 0.8 2.0 3.0 ns
tOD1 Output buffer and pad delay C1 = 35 pF 0.5 1.5 4.0 ns
tOD2 Output buffer and pad delay C1 = 35 pF (6) 1.0 2.0 5.0 ns
tOD3 Output buffer and pad delay C 1 = 35 pF 5.5 5.5 8.0 ns
tZX1 Output buffer enable delay C1 = 35 pF 4.0 5.0 6.0 ns
tZX2 Output buffer enable delay C1 = 35 pF (6) 4.5 5.5 7.0 ns
tZX3 Output buffer enable delay C1 = 35 pF 9.0 9.0 10.0 ns
tXZ Output bu ffer disable delay C1 = 5 pF 4.0 5.0 6.0 ns
tSU Register setup time 1.1 2.0 4.0 ns
tHRegister hold time 1.6 3.0 4.0 ns
tFSU Register setup time of fast
input 2.4 3.0 2.0 ns
tFH Register hold time of fast
input 0.6 0.5 1.0 ns
tRD Register delay 1.1 2.0 1.0 ns
tCOMB Combinatorial delay 1.1 2.0 1.0 ns
tIC Array clock delay 2.9 5.0 6.0 ns
tEN Register enable time 2.6 5.0 6.0 ns
tGLOB Global control delay 2.8 1.0 1.0 ns
tPRE Register preset time 2.7 3.0 4.0 ns
tCLR Register clear time 2.7 3.0 4.0 ns
tPIA PIA delay (7) 3.0 1.0 2.0 ns
tLPA Low-power adder (8) 10.011.013.0ns
50 Altera Corporation
MAX 7000 Programmable Logic D evi ce F ami l y Da ta Sh eet
Notes to tables:
(1) These values are specified under the recommended operating conditions shown in Table 11. See Figure 13 for more
information on switching waveforms.
(2) This minimum pulse width for preset and clear applies for both global clear and array controls. The tLPA parameter
must be added to this minimum width if the clear or reset signal incorporates the tLAD parameter into the signal
path.
(3) This parameter is a guideline that is sample-tested only and is based on extensive device characterization. This
paramet er appli es for both global and array clocki ng.
(4) These p ar ameters are measured with a 16-bit loa d able, enab led, up / d own c ou nter programmed in to each LAB.
(5) The fMAX va lues repre s en t t h e high est frequ ency fo r pipelined da t a.
(6) Opera t i ng con ditions: VCCIO = 3.3 V ± 10% for commercial and industrial use.
(7) For EPM7064S-5, EPM 7064S-6, EPM 7128S-6, E PM7160S-6, EPM7160S-7, EPM719 2S-7, and EPM 7256S-7 dev ices,
these v alu es are specified fo r a PIA fan-out of on e L AB (16 macroc ells). For each additio na l L A B fan-out in these
device s, add an ad ditional 0.1 n s to the PI A timing value .
(8) The tLPA parameter must be added to the tLAD, tLAC, tIC, tEN, tSEXP, tACL, and tCPPW parameters for macrocell s
running in the low-power mode.
Power
Consumption
Supply power (P) v ersus frequency (fMAX in MHz) for MAX 7000 devices
is calculate d with the followin g equation:
P = PINT + PIO = ICCINT × VCC + PIO
The P IO value, which depends on the device output load characteristics
and switching frequency, can be calculated using the guidelines given in
Application Note 74 (Evaluating Power for Altera Devices).
The ICCINT value, which depends on the switching frequency and the
application logic, is calculated with the following equation:
ICCINT =
A × MCTON + B × (MCDEV – MCTON) + C × MCUSED × fMAX × togLC
The parameters in this equation are shown below:
MCTON = Numbe r o f macrocells wi th the Turbo Bit option turned on ,
as reported in the MAX+PLUS II Report File (.rpt)
MCDEV = Number of macrocells in the device
MCUSED = Total number of macrocells in the design, as reported
in the MAX+PLUS II Report File (.rpt)
fMAX = Highest clock frequency to the device
togLC = Average ratio of logic cells toggling at each clock
(typically 0.125)
A, B, C = Constants, shown in Table 36
Altera Corporation 51
MAX 7000 Pr o grammable Log i c Dev ic e Fam ily D ata Sh eet
This calculation provides an ICC estimate based on typical conditions
using a pattern of a 16-bit, loadable, enabled, up/down counter in each
LAB with no output load. Actual ICC valu es shou ld be verified during
operation because this measurement is sensitive to the actual pattern in
the device and the environmental operating conditions.
Tabl e 36 . MAX 70 00 I CC Equation Constants
Device A B C
EPM7032 1.87 0.52 0.144
EPM7064 1.63 0.74 0.144
EPM7096 1.63 0.74 0.144
EPM7128E 1.17 0.54 0.096
EPM7160E 1.17 0.54 0.096
EPM7192E 1.17 0.54 0.096
EPM7256E 1.17 0.54 0.096
EPM7032S 0.93 0.40 0.040
EPM7064S 0.93 0.40 0.040
EPM7128S 0.93 0.40 0.040
EPM7160S 0.93 0.40 0.040
EPM7192S 0.93 0.40 0.040
EPM7256S 0.93 0.40 0.040
52 Altera Corporation
MAX 7000 Programmable Logic D evi ce F ami l y Da ta Sh eet
Figure 14 shows typical supply current versus frequency for MAX 7000
devices.
Figu re 14. ICC vs. Frequency for MAX 7000 Devices (Part 1 of 2)
Frequency (MHz)
EPM7064
EPM7032
050
Frequency (MHz)
200100 150
High Speed
151.5 MHz
180
20
60
100
140
VCC = 5.0 V
Room Temperature
050 200100 150
Low Power
60.2 MHz
151.5 MHz
200
300
100
VCC = 5.0 V
Room Temperature
EPM7096
05
0
Frequency (MHz)
2
50
1
00
5
0
1
50
3
50
4
50
1
50
High Speed
V
CC
= 5.0 V
Room Temperature
Low Power
Typical I
Active (mA)
CC Typical I
Active (mA)
CC
Typical I
Active (mA)
CC
60.2 MHz
125 MHz
55.5 MHz
High Speed
Low Power
Altera Corporation 53
MAX 7000 Pr o grammable Log i c Dev ic e Fam ily D ata Sh eet
Figure 14. ICC vs. Frequency for MAX 7000 Devices (Part 2 of 2)
VCC = 5.0 V
Room Temperature
0
Frequency (MHz)
500
300
75
400
200
100
25 50 100 125
90.9 MHz
43.5 MHz
EPM7192E
VCC = 5.0 V
Room Temperature
0
Frequency (MHz)
750
450
75
600
300
150
25 50 100
90.9 MHz
43.4 MHz
EPM7256E
VCC = 5.0 V
Room Temperature
0
Frequency (MHz)
500
300
400
Low Power
200
100
50 100
100 MHz
47.6 MHz
EPM7160E
150 200
VCC = 5.0 V
Room Temperature
0
Frequency (MHz)
500
300
400
High Speed
200
100
50 100
125 MHz
55.5 MHz
EPM7128E
150 200
High Speed
High Speed
High Speed
Low Power
Low Power
Low Power
Typical I
Active (mA)
CC
Typical I
Active (mA)
CC
Typical I
Active (mA)
CC
Typical I
Active (mA)
CC
125
54 Altera Corporation
MAX 7000 Programmable Logic D evi ce F ami l y Da ta Sh eet
Figure 15 shows typical supply current versus frequency for MAX 7000S
devices.
Figu re 15. ICC vs. Freque ncy f or MAX 7000S Devices (Part 1 of 2)
VCC = 5.0 V
Room Temperature
0
Frequency (MHz)
High Speed
Low Power
50 100 150 200
142.9 MHz
58.8 MHz
EPM7032S
10
20
30
40
50
60
V
CC
= 5.0 V
Room Temperature
0
Frequency (MHz)
High Speed
Low Power
50 100 150200
175.4 MHz
56.5 MHz
EPM7064S
20
40
60
80
100
120
VCC = 5.0 V
Room Temperature
0
Frequency (MHz)
High Speed
Low Power
50 100 150 200
147.1 MHz
56.2 MHz
E
PM7128S
80
120
200
280
160
40
240
V
CC
= 5.0 V
Room Temperature
0
Frequency (MHz)
High Speed
Low Power
50 100 150200
149.3 MHz
56.5 MHz
EPM7160S
60
120
180
240
300
Typical I
Active (mA)
CC
T
ypical I
A
ctive (mA)
CC
Typical I
Active (mA)
CC
T
ypical I
A
ctive (mA)
CC
Altera Corporation 55
MAX 7000 Pr o grammable Log i c Dev ic e Fam ily D ata Sh eet
Figure 15. ICC vs. Frequency for MAX 7000S Devices (Part 2 of 2)
Device
Pin-Outs
See the A lte ra we b si te (http://www.altera.com) or the Altera Digital
Library for pin-out information.
EPM7192S
VCC = 5.0 V
Room Temperature
0
Frequency (MHz)
High Speed
Low Power
25 100 125
125.0 MHz
55.6 MHz
60
120
180
240
300
50 75
EPM7256S
VCC = 5.0 V
Room Temperature
0
Frequency (MHz)
High Speed
Low Power
25 100 125
128.2 MHz
56.2 MHz
100
200
300
400
50 75
Typical I
Active (mA)
CC Typical I
Active (mA)
CC
56 Altera Corporation
MAX 7000 Programmable Logic D evi ce F ami l y Da ta Sh eet
Figures 16 th r oug h 22 show th e pac ka ge pin-o u t d iag r ams for M AX 700 0
devices.
Figure 16. 44-Pin Package Pin-Out Diagram
Package outlines not drawn to scale.
Notes:
(1) The pin functi on s show n in par ent h esis are onl y ava ila bl e in MA X 7000E and MA X 7000S devices.
(2) JTAG ports are available in MAX 7000S devices only.
44-Pin PLCC
I/O
I/O
I/O
VCC
INPUT/OE2/(GCLK2) (1)
INPUT/GCLRn
INPUT/OE1
INPUT/GCLK1
GND
I/O
I/O
I/O
I/O/(TDO) (2
)
I/O
I/O
VCC
I/O
I/O
I/O/(TCK) (2)
I/O
GND
I/O
I/O
I/O
I/O
I/O
GND
VCC
I/O
I/O
I/O
I/O
I/O
6 5 4 3 2 1 44 43 42 41 40
18 19 20 21 22 23 24 25 26 27 28
7
8
9
10
11
12
13
14
15
16
17
39
38
37
36
35
34
33
32
31
30
29
EPM7032
EPM7032S
EPM7064
EPM7064S
(2) I/O/(TDI)
I/O
I/O
GND
I/O
I/O
(2) I/O/(TMS)
I/O
VCC
I/O
I/O
44-Pin PQFP
Pin 12 Pin 23
Pin 34
Pin 1
I/O
I/O
I/O
VCC
INPUT/OE2/(GCLK2) (1
)
INPUT/GCLRn
INPUT/OE1
INPUT//GCLK1
GND
I/O
I/O
I/O
I/O/(TDO) (2)
I/O
I/O
VCC
I/O
I/O
I/O/(TCK) (2)
I/O
GND
I/O
I/O
I/O
I/O
I/O
GND
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
(2) I/O/(TMS)
I/O
VCC
I/O
I/O
EPM7032
44-Pin TQFP
Pin 12 Pin 23
Pin 34
Pin 1
I/O
I/O
I/O
VCC
INPUT/OE2/(GCLK2) (1)
INPUT/GCLRn
INPUT/OE1
INPUT/GCLK1
GND
I/O
I/O
I/O
I/O/(TDO) (2)
I/O
I/O
VCC
I/O
I/O
I/O/(TCK) (2)
I/O
GND
I/O
I/O
I/O
I/O
I/O
GND
VCC
I/O
I/O
I/O
I/O
I/O
(2) I/O/(TDI)
I/O
I/O
GND
I/O
I/O
(2) I/O/(TMS)
I/O
VCC
I/O
I/O
EPM7032
EPM7032S
EPM7064
EPM7064S
(2) I/O/(TDI)
Altera Corporation 57
MAX 7000 Pr o grammable Log i c Dev ic e Fam ily D ata Sh eet
Figure 17. 68- P i n Package Pin-Out Diagram
Packag e outlin es not drawn to scale.
Notes:
(1) The p in functi ons s hown i n pa renthe sis are only a vail able in MAX 7000E and MAX
7000S devices.
(2) JTAG port s are av ai lab le in MAX 7000S dev ices only.
68-Pin PLCC
EPM7064
EPM7096
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
9
8
7
6
5
4
3
2
1
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
I/O
I/O
GND
I/O/(TDO) (2)
I/O
I/O
I/O
VCCIO
I/O
I/O
I/O/(TCK) (2)
I/O
GND
I/O
I/O
I/O
I/O
I/O
VCCIO
(2) I/O/(TDI)
I/O
I/O
I/O
GND
I/O
I/O
(2) I/O/(TMS)
I/O
VCCIO
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
GND
I/O
I/O
VCCINT
INPUT/OE2/(GCLK2) (1
)
INPUT/GCLRn
INPUT/OE1
INPUT/GCLK1
GND
I/O
I/O
VCCIO
I/O
I/O
I/O
I/O
I/O
I/O
VCCIO
I/O
I/O
GND
VCCINT
I/O
I/O
GND
I/O
I/O
I/O
I/O
VCCIO
58 Altera Corporation
MAX 7000 Programmable Logic D evi ce F ami l y Da ta Sh eet
Figure 18. 84-Pin Package Pin-Out Diagram
Package outline not drawn to scale.
Notes:
(1) Pins 6, 39, 46, and 79 are no- c on ne ct (N .C.) pins on EPM7096, EPM7 160E , an d EPM7160S d evices.
(2) The pin functi on s show n in par ent h esis are onl y ava ila bl e in MA X 7000E and MA X 7000S devices.
(3) JTAG por ts are available in M AX 7000S dev ices only .
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
I/O
VCCIO
I/O/(TDI)
(3)
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O/(TMS)
(3)
I/O
I/O
VCCIO
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
GND
I/O
(1)
I/O
I/O
VCCINT
INPUT/OE2/(GCLK2)
(2)
INPUT/GLCRn
INPUT/OE1
INPUT/GCLK1
GND
I/O
I/O
I/O
(1)
VCCIO
I/O
I/O
I/O
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
11
10
9
8
7
6
5
4
3
2
1
84
83
82
81
80
79
78
77
76
75
I/O
I/O
GND
I/O/(TDO)
(3)
I/O
I/O
I/O
I/O
VCCIO
I/O
I/O
I/O
I/O/(TCK)
(3)
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCIO
I/O
(1)
I/O
I/O
GND
VCCINT
I/O
I/O
I/O
(1)
GND
I/O
I/O
I/O
I/O
I/O
VCCIO
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
EPM7064
EPM7064S
EPM7096
EPM7128E
EPM7128S
EPM7160E
EPM7160S
84-Pin PLCC
Altera Corporation 59
MAX 7000 Pr o grammable Log i c Dev ic e Fam ily D ata Sh eet
Figure 19 . 100-Pin Package Pin -Out D i agram
Package outlin e not drawn to scale.
Figure 20 . 160-Pin Package Pin -Out D i agram
Package outlin e not drawn to scale.
100-Pin PQFP
Pin 31
EPM7064
EPM7096
EPM7128E
EPM7128S
EPM7160E
Pin 81
Pin 1
Pin 51
100-Pin TQFP
Pin 1
Pin 26
Pin 7
6
Pin 51
EPM7064S
EPM7128S
EPM7160S
Pin 1
EPM7128E
EPM7128S
EPM7160E
EPM7160S
EPM7192E
EPM7192S
EPM7256E
Pin 12
1
Pin 81
Pin 41
160-Pin PGA 160-Pin PQFP
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
EPM7192E
Bottom
View
60 Altera Corporation
MAX 7000 Programmable Logic D evi ce F ami l y Da ta Sh eet
Figure 21. 192-Pin Package Pin-Out Diagram
Package outline not drawn to scale.
Figure 22. 208-Pin Package Pin-Out Diagram
Package outline not drawn to scale.
192-Pin PGA
EPM7256E
Bottom
View
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
208-Pin PQFP/RQFP
Pin 1 Pin 15
7
Pin 10
5
Pin 53
EPM7256E
EPM7256S
Altera Corporation 61
MAX 7000 Pr o grammable Log i c Dev ic e Fam ily D ata Sh eet
Revision
History
The information contained in the MAX 7000 Programmable Logic Device
Fami ly Data Sh eet version 6.5 supersedes information published in
previous versions. The following changes were made in the M A X 700 0
Programmable Logic Device Family Data Sheet version 6.5:
Version 6.5
The following changes were made in the MAX 7000 Pr ogrammable Logic
Device Family Data Sheet version 6.5:
■Updated text on page 16.
Version 6.4
The following changes were made in the MAX 7000 Pr ogrammable Logic
Device Family Data Sheet version 6.4:
■Added Note (5) on page 25.
Version 6.3
The following changes were made in the MAX 7000 Pr ogrammable Logic
Device Family Data Sheet version 6.3:
■Updated the “Open-Drain Output Option (MAX 7000S Devi ces
Only)” sectio n on page 18.
Copyright © 2002 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, th
e
stylized Altera logo, specific device designations, and all other words and logos that are identified a
s
trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Alter
a
Corporation in the U.S. and other countries. All other product or service names are the property of the
ir
respective holders. Altera products are protected under numerous U.S. and foreign patents and pendin
g
applications, maskwork rights, and copyrights. Altera warrants performance of its semiconductor products t
o
current specifications in accordance with Alter a's sta ndard wa rran ty, but reserv es the r ight
to make changes to any products and services at any time without notice. Altera assumes no
responsibility or liabilit y arising out of the applicat ion or use of any information, product, or
service described herein except as expressly agreed to in writing by Altera Corporation.
Altera customers are advised to obtain the latest version of device specifications before
relying on any published information and before placing orders for products or services
1
01 Innovation Drive
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ttp://www.altera.com
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pplicat ions Hotlin e:
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usto mer Marketi ng:
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iterature Serv ices:
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MAX 7000 Pr o grammable Log ic Dev ice Fam ily D ata Sh eet
62 Altera Corporation
