MAX 7000 Programmable Logic Device Family (R) December 2002, ver. 6.5 Features... Data Sheet f High-performance, EEPROM-based programmable logic devices (PLDs) based on second-generation MAX(R) architecture 5.0-V in-system programmability (ISP) through the built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface available in MAX 7000S devices - ISP circuitry compatible with IEEE Std. 1532 Includes 5.0-V MAX 7000 devices and 5.0-V ISP-based MAX 7000S devices Built-in JTAG boundary-scan test (BST) circuitry in MAX 7000S devices with 128 or more macrocells Complete EPLD family with logic densities ranging from 600 to 5,000 usable gates (see Tables 1 and 2) 5-ns pin-to-pin logic delays with up to 175.4-MHz counter frequencies (including interconnect) PCI-compliant devices available For information on in-system programmable 3.3-V MAX 7000A or 2.5-V MAX 7000B devices, see the MAX 7000A Programmable Logic Device Family Data Sheet or the MAX 7000B Programmable Logic Device Family Data Sheet. Table 1. MAX 7000 Device Features Feature EPM7032 EPM7064 EPM7096 EPM7128E EPM7160E EPM7192E EPM7256E Usable gates 600 1,250 1,800 2,500 3,200 3,750 5,000 Macrocells 32 64 96 128 160 192 256 Logic array blocks 2 4 6 8 10 12 16 Maximum user I/O pins 36 68 76 100 104 124 164 tPD (ns) 6 6 7.5 7.5 10 12 12 tSU (ns) 5 5 6 6 7 7 7 tFSU (ns) 2.5 2.5 3 3 3 3 3 tCO1 (ns) fCNT (MHz) 4 4 4.5 4.5 5 6 6 151.5 151.5 125.0 125.0 100.0 90.9 90.9 Altera Corporation DS-MAX7000-6.5 1 MAX 7000 Programmable Logic Device Family Data Sheet Table 2. MAX 7000S Device Features Feature EPM7032S EPM7064S EPM7128S EPM7160S EPM7192S EPM7256S Usable gates 600 1,250 2,500 3,200 3,750 5,000 Macrocells 32 64 128 160 192 256 Logic array blocks 2 4 8 10 12 16 Maximum user I/O pins 36 68 100 104 124 164 tPD (ns) 5 5 6 6 7.5 7.5 tSU (ns) 2.9 2.9 3.4 3.4 4.1 3.9 tFSU (ns) 2.5 2.5 2.5 2.5 3 3 tCO1 (ns) 3.2 3.2 4 3.9 4.7 4.7 175.4 175.4 147.1 149.3 125.0 128.2 fCNT (MHz) ...and More Features 2 Open-drain output option in MAX 7000S devices Programmable macrocell flipflops with individual clear, preset, clock, and clock enable controls Programmable power-saving mode for a reduction of over 50% in each macrocell Configurable expander product-term distribution, allowing up to 32 product terms per macrocell 44 to 208 pins available in plastic J-lead chip carrier (PLCC), ceramic pin-grid array (PGA), plastic quad flat pack (PQFP), power quad flat pack (RQFP), and 1.0-mm thin quad flat pack (TQFP) packages Programmable security bit for protection of proprietary designs 3.3-V or 5.0-V operation - MultiVoltTM I/O interface operation, allowing devices to interface with 3.3-V or 5.0-V devices (MultiVolt I/O operation is not available in 44-pin packages) - Pin compatible with low-voltage MAX 7000A and MAX 7000B devices Enhanced features available in MAX 7000E and MAX 7000S devices - Six pin- or logic-driven output enable signals - Two global clock signals with optional inversion - Enhanced interconnect resources for improved routability - Fast input setup times provided by a dedicated path from I/O pin to macrocell registers - Programmable output slew-rate control Software design support and automatic place-and-route provided by Altera's development system for Windows-based PCs and Sun SPARCstation, and HP 9000 Series 700/800 workstations Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet General Description Additional design entry and simulation support provided by EDIF 2 0 0 and 3 0 0 netlist files, library of parameterized modules (LPM), Verilog HDL, VHDL, and other interfaces to popular EDA tools from manufacturers such as Cadence, Exemplar Logic, Mentor Graphics, OrCAD, Synopsys, and VeriBest Programming support - Altera's Master Programming Unit (MPU) and programming hardware from third-party manufacturers program all MAX 7000 devices - The BitBlasterTM serial download cable, ByteBlasterMVTM parallel port download cable, and MasterBlasterTM serial/universal serial bus (USB) download cable program MAX 7000S devices The MAX 7000 family of high-density, high-performance PLDs is based on Altera's second-generation MAX architecture. Fabricated with advanced CMOS technology, the EEPROM-based MAX 7000 family provides 600 to 5,000 usable gates, ISP, pin-to-pin delays as fast as 5 ns, and counter speeds of up to 175.4 MHz. MAX 7000S devices in the -5, -6, -7, and -10 speed grades as well as MAX 7000 and MAX 7000E devices in -5, -6, -7, -10P, and -12P speed grades comply with the PCI Special Interest Group (PCI SIG) PCI Local Bus Specification, Revision 2.2. See Table 3 for available speed grades. Table 3. MAX 7000 Speed Grades Device Speed Grade -5 EPM7032 EPM7032S v EPM7064 EPM7064S v -6 -7 v v v v v v v v v v v v v EPM7096 v EPM7128E EPM7128S v v v v v -10 -12 -15 -15T v v v v v v v v v v v EPM7256S Altera Corporation v v v v v v v v v v v v v v v EPM7256E v -20 v v EPM7192E EPM7192S -12P v v EPM7160E EPM7160S -10P v v v v 3 MAX 7000 Programmable Logic Device Family Data Sheet The MAX 7000E devices--including the EPM7128E, EPM7160E, EPM7192E, and EPM7256E devices--have several enhanced features: additional global clocking, additional output enable controls, enhanced interconnect resources, fast input registers, and a programmable slew rate. In-system programmable MAX 7000 devices--called MAX 7000S devices--include the EPM7032S, EPM7064S, EPM7128S, EPM7160S, EPM7192S, and EPM7256S devices. MAX 7000S devices have the enhanced features of MAX 7000E devices as well as JTAG BST circuitry in devices with 128 or more macrocells, ISP, and an open-drain output option. See Table 4. Table 4. MAX 7000 Device Features Feature EPM7032 EPM7064 EPM7096 All MAX 7000E Devices All MAX 7000S Devices ISP via JTAG interface v JTAG BST circuitry v(1) v Open-drain output option Fast input registers v v Six global output enables v v Two global clocks v v v v MultiVolt interface (2) v v v Programmable register v v v Parallel expanders v v v Shared expanders v v v Power-saving mode v v v Security bit v v v PCI-compliant devices available v v v Slew-rate control Notes: (1) (2) 4 Available only in EPM7128S, EPM7160S, EPM7192S, and EPM7256S devices only. The MultiVolt I/O interface is not available in 44-pin packages. Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet The MAX 7000 architecture supports 100% TTL emulation and high-density integration of SSI, MSI, and LSI logic functions. The MAX 7000 architecture easily integrates multiple devices ranging from PALs, GALs, and 22V10s to MACH and pLSI devices. MAX 7000 devices are available in a wide range of packages, including PLCC, PGA, PQFP, RQFP, and TQFP packages. See Table 5. Table 5. MAX 7000 Maximum User I/O Pins Device Note (1) 44446884- 100- 10044Pin Pin Pin Pin Pin Pin Pin PLCC PQFP TQFP PLCC PLCC PQFP TQFP EPM7032 36 EPM7032S 36 36 EPM7064 36 36 EPM7064S 36 36 EPM7096 36 160Pin PQFP 192Pin PGA 208Pin PQFP 208Pin RQFP 36 52 68 68 68 52 68 64 76 EPM7128E 68 84 EPM7128S 68 84 EPM7160E 64 84 EPM7160S 64 100 84 (2) 100 84 (2) 104 104 EPM7192E 124 EPM7192S 124 EPM7256E 132 (2) EPM7256S 160Pin PGA 124 164 164 164 (2) 164 Notes: (1) (2) When the JTAG interface in MAX 7000S devices is used for either boundary-scan testing or for ISP, four I/O pins become JTAG pins. Perform a complete thermal analysis before committing a design to this device package. For more information, see the Operating Requirements for Altera Devices Data Sheet. MAX 7000 devices use CMOS EEPROM cells to implement logic functions. The user-configurable MAX 7000 architecture accommodates a variety of independent combinatorial and sequential logic functions. The devices can be reprogrammed for quick and efficient iterations during design development and debug cycles, and can be programmed and erased up to 100 times. Altera Corporation 5 MAX 7000 Programmable Logic Device Family Data Sheet MAX 7000 devices contain from 32 to 256 macrocells that are combined into groups of 16 macrocells, called logic array blocks (LABs). Each macrocell has a programmable-AND/fixed-OR array and a configurable register with independently programmable clock, clock enable, clear, and preset functions. To build complex logic functions, each macrocell can be supplemented with both shareable expander product terms and highspeed parallel expander product terms to provide up to 32 product terms per macrocell. The MAX 7000 family provides programmable speed/power optimization. Speed-critical portions of a design can run at high speed/full power, while the remaining portions run at reduced speed/low power. This speed/power optimization feature enables the designer to configure one or more macrocells to operate at 50% or lower power while adding only a nominal timing delay. MAX 7000E and MAX 7000S devices also provide an option that reduces the slew rate of the output buffers, minimizing noise transients when non-speed-critical signals are switching. The output drivers of all MAX 7000 devices (except 44-pin devices) can be set for either 3.3-V or 5.0-V operation, allowing MAX 7000 devices to be used in mixed-voltage systems. The MAX 7000 family is supported byAltera development systems, which are integrated packages that offer schematic, text--including VHDL, Verilog HDL, and the Altera Hardware Description Language (AHDL)-- and waveform design entry, compilation and logic synthesis, simulation and timing analysis, and device programming. The software provides EDIF 2 0 0 and 3 0 0, LPM, VHDL, Verilog HDL, and other interfaces for additional design entry and simulation support from other industrystandard PC- and UNIX-workstation-based EDA tools. The software runs on Windows-based PCs, as well as Sun SPARCstation, and HP 9000 Series 700/800 workstations. f Functional Description 6 For more information on development tools, see the MAX+PLUS II Programmable Logic Development System & Software Data Sheet and the Quartus Programmable Logic Development System & Software Data Sheet. The MAX 7000 architecture includes the following elements: Logic array blocks Macrocells Expander product terms (shareable and parallel) Programmable interconnect array I/O control blocks Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet The MAX 7000 architecture includes four dedicated inputs that can be used as general-purpose inputs or as high-speed, global control signals (clock, clear, and two output enable signals) for each macrocell and I/O pin. Figure 1 shows the architecture of EPM7032, EPM7064, and EPM7096 devices. Figure 1. EPM7032, EPM7064 & EPM7096 Device Block Diagram INPUT/GLCK1 INPUT/GCLRn INPUT/OE1 INPUT/OE2 LAB A 8 to 16 8 to 16 I/O pins I/O Control Block LAB B 36 Macrocells 1 to 16 36 16 LAB C 8 to 16 I/O Control Block 36 16 8 to 16 Altera Corporation I/O Control Block 8 to 16 I/O pins I/O Control Block 8 to 16 I/O pins 8 to 16 LAB D PIA Macrocells 33 to 48 8 to 16 16 8 to 16 8 to 16 I/O pins Macrocells 17 to 32 36 Macrocells 49 to 64 8 to 16 16 8 to 16 7 MAX 7000 Programmable Logic Device Family Data Sheet Figure 2 shows the architecture of MAX 7000E and MAX 7000S devices. Figure 2. MAX 7000E & MAX 7000S Device Block Diagram INPUT/GCLK1 INPUT/OE2/GCLK2 INPUT/OE1 INPUT/GCLRn 6 Output Enables 6 Output Enables 6 to16 6 to 16 I/O Pins I/O Control Block LAB B LAB A 6 to16 36 Macrocells 1 to 16 36 16 6 to16 6 to 16 I/O Pins I/O Control Block 6 6 to16 6 to16 Macrocells 17 to 32 PIA 6 to16 6 to 16 I/O Pins 6 LAB D LAB C 36 Macrocells 33 to 48 I/O Control Block 16 6 to16 6 6 to16 36 16 16 6 to16 6 to16 Macrocells 49 to 64 6 to16 6 to16 I/O Control Block 6 to 16 I/O Pins 6 Logic Array Blocks The MAX 7000 device architecture is based on the linking of highperformance, flexible, logic array modules called logic array blocks (LABs). LABs consist of 16-macrocell arrays, as shown in Figures 1 and 2. Multiple LABs are linked together via the programmable interconnect array (PIA), a global bus that is fed by all dedicated inputs, I/O pins, and macrocells. 8 Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet Each LAB is fed by the following signals: 36 signals from the PIA that are used for general logic inputs Global controls that are used for secondary register functions Direct input paths from I/O pins to the registers that are used for fast setup times for MAX 7000E and MAX 7000S devices Macrocells The MAX 7000 macrocell can be individually configured for either sequential or combinatorial logic operation. The macrocell consists of three functional blocks: the logic array, the product-term select matrix, and the programmable register. The macrocell of EPM7032, EPM7064, and EPM7096 devices is shown in Figure 3. Figure 3. EPM7032, EPM7064 & EPM7096 Device Macrocell Global Clear Logic Array Parallel Logic Expanders (from other macrocells) Global Clocks From I/O pin 2 Fast Input Select Programmable Register Register Bypass PRN D/T Q Clock/ Enable Select ProductT m Ter Select Matrix To I/O Control Block ENA CLRN VCC Clear Select Shared Logic Expanders 36 Signals from PIA to PIA 16 Expander T ms Product Ter Altera Corporation 9 MAX 7000 Programmable Logic Device Family Data Sheet Figure 4 shows a MAX 7000E and MAX 7000S device macrocell. Figure 4. MAX 7000E & MAX 7000S Device Macrocell Global Clear Logic Array Parallel Logic Expanders (from other macrocells) Global Clocks from I/O pin 2 Fast Input Select Programmable Register Register Bypass PRN D/T Q Clock/ Enable Select ProductTerm Select Matrix to I/O Control Block ENA CLRN VCC Clear Select Shared Logic Expanders 36 Signals from PIA to PIA 16 Expander Product Terms Combinatorial logic is implemented in the logic array, which provides five product terms per macrocell. The product-term select matrix allocates these product terms for use as either primary logic inputs (to the OR and XOR gates) to implement combinatorial functions, or as secondary inputs to the macrocell's register clear, preset, clock, and clock enable control functions. Two kinds of expander product terms ("expanders") are available to supplement macrocell logic resources: Shareable expanders, which are inverted product terms that are fed back into the logic array Parallel expanders, which are product terms borrowed from adjacent macrocells The Altera development system automatically optimizes product-term allocation according to the logic requirements of the design. For registered functions, each macrocell flipflop can be individually programmed to implement D, T, JK, or SR operation with programmable clock control. The flipflop can be bypassed for combinatorial operation. During design entry, the designer specifies the desired flipflop type; the Altera development software then selects the most efficient flipflop operation for each registered function to optimize resource utilization. 10 Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet Each programmable register can be clocked in three different modes: By a global clock signal. This mode achieves the fastest clock-tooutput performance. By a global clock signal and enabled by an active-high clock enable. This mode provides an enable on each flipflop while still achieving the fast clock-to-output performance of the global clock. By an array clock implemented with a product term. In this mode, the flipflop can be clocked by signals from buried macrocells or I/O pins. In EPM7032, EPM7064, and EPM7096 devices, the global clock signal is available from a dedicated clock pin, GCLK1, as shown in Figure 1. In MAX 7000E and MAX 7000S devices, two global clock signals are available. As shown in Figure 2, these global clock signals can be the true or the complement of either of the global clock pins, GCLK1 or GCLK2. Each register also supports asynchronous preset and clear functions. As shown in Figures 3 and 4, the product-term select matrix allocates product terms to control these operations. Although the product-term-driven preset and clear of the register are active high, active-low control can be obtained by inverting the signal within the logic array. In addition, each register clear function can be individually driven by the active-low dedicated global clear pin (GCLRn). Upon power-up, each register in the device will be set to a low state. All MAX 7000E and MAX 7000S I/O pins have a fast input path to a macrocell register. This dedicated path allows a signal to bypass the PIA and combinatorial logic and be driven to an input D flipflop with an extremely fast (2.5 ns) input setup time. Expander Product Terms Although most logic functions can be implemented with the five product terms available in each macrocell, the more complex logic functions require additional product terms. Another macrocell can be used to supply the required logic resources; however, the MAX 7000 architecture also allows both shareable and parallel expander product terms ("expanders") that provide additional product terms directly to any macrocell in the same LAB. These expanders help ensure that logic is synthesized with the fewest possible logic resources to obtain the fastest possible speed. Altera Corporation 11 MAX 7000 Programmable Logic Device Family Data Sheet Shareable Expanders Each LAB has 16 shareable expanders that can be viewed as a pool of uncommitted single product terms (one from each macrocell) with inverted outputs that feed back into the logic array. Each shareable expander can be used and shared by any or all macrocells in the LAB to build complex logic functions. A small delay (tSEXP) is incurred when shareable expanders are used. Figure 5 shows how shareable expanders can feed multiple macrocells. Figure 5. Shareable Expanders Shareable expanders can be shared by any or all macrocells in an LAB. Macrocell Product-Term Logic Product-Term Select Matrix Macrocell Product-Term Logic 36 Signals from PIA 16 Shared Expanders Parallel Expanders Parallel expanders are unused product terms that can be allocated to a neighboring macrocell to implement fast, complex logic functions. Parallel expanders allow up to 20 product terms to directly feed the macrocell OR logic, with five product terms provided by the macrocell and 15 parallel expanders provided by neighboring macrocells in the LAB. 12 Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet The compiler can allocate up to three sets of up to five parallel expanders automatically to the macrocells that require additional product terms. Each set of five parallel expanders incurs a small, incremental timing delay (tPEXP). For example, if a macrocell requires 14 product terms, the Compiler uses the five dedicated product terms within the macrocell and allocates two sets of parallel expanders; the first set includes five product terms and the second set includes four product terms, increasing the total delay by 2 x tPEXP. Two groups of 8 macrocells within each LAB (e.g., macrocells 1 through 8 and 9 through 16) form two chains to lend or borrow parallel expanders. A macrocell borrows parallel expanders from lowernumbered macrocells. For example, macrocell 8 can borrow parallel expanders from macrocell 7, from macrocells 7 and 6, or from macrocells 7, 6, and 5. Within each group of 8, the lowest-numbered macrocell can only lend parallel expanders and the highest-numbered macrocell can only borrow them. Figure 6 shows how parallel expanders can be borrowed from a neighboring macrocell. Figure 6. Parallel Expanders Unused product terms in a macrocell can be allocated to a neighboring macrocell. From Previous Macrocell Preset ProductTerm Select Matrix Macrocell ProductTerm Logic Clock Clear Preset ProductTerm Select Matrix Macrocell ProductTerm Logic Clock Clear 36 Signals from PIA Altera Corporation 16 Shared Expanders To Next Macrocell 13 MAX 7000 Programmable Logic Device Family Data Sheet Programmable Interconnect Array Logic is routed between LABs via the programmable interconnect array (PIA). This global bus is a programmable path that connects any signal source to any destination on the device. All MAX 7000 dedicated inputs, I/O pins, and macrocell outputs feed the PIA, which makes the signals available throughout the entire device. Only the signals required by each LAB are actually routed from the PIA into the LAB. Figure 7 shows how the PIA signals are routed into the LAB. An EEPROM cell controls one input to a 2-input AND gate, which selects a PIA signal to drive into the LAB. Figure 7. PIA Routing To LAB PIA Signals While the routing delays of channel-based routing schemes in masked or FPGAs are cumulative, variable, and path-dependent, the MAX 7000 PIA has a fixed delay. The PIA thus eliminates skew between signals and makes timing performance easy to predict. I/O Control Blocks The I/O control block allows each I/O pin to be individually configured for input, output, or bidirectional operation. All I/O pins have a tri-state buffer that is individually controlled by one of the global output enable signals or directly connected to ground or VCC. Figure 8 shows the I/O control block for the MAX 7000 family. The I/O control block of EPM7032, EPM7064, and EPM7096 devices has two global output enable signals that are driven by two dedicated active-low output enable pins (OE1 and OE2). The I/O control block of MAX 7000E and MAX 7000S devices has six global output enable signals that are driven by the true or complement of two output enable signals, a subset of the I/O pins, or a subset of the I/O macrocells. 14 Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet Figure 8. I/O Control Block of MAX 7000 Devices EPM7032, EPM7064 & EPM7096 Devices VCC OE1 OE2 GND From Macrocell To PIA MAX 7000E & MAX 7000S Devices Six Global Output Enable Signals PIA VCC To Other I/O Pins From Macrocell Fast Input to Macrocell Register GND Open-Drain Output (1) Slew-Rate Control To PIA Note: (1) Altera Corporation The open-drain output option is available only in MAX 7000S devices. 15 MAX 7000 Programmable Logic Device Family Data Sheet When the tri-state buffer control is connected to ground, the output is tri-stated (high impedance) and the I/O pin can be used as a dedicated input. When the tri-state buffer control is connected to VCC, the output is enabled. The MAX 7000 architecture provides dual I/O feedback, in which macrocell and pin feedbacks are independent. When an I/O pin is configured as an input, the associated macrocell can be used for buried logic. In-System Programmability (ISP) MAX 7000S devices are in-system programmable via an industry-standard 4-pin Joint Test Action Group (JTAG) interface (IEEE Std. 1149.1-1990). ISP allows quick, efficient iterations during design development and debugging cycles. The MAX 7000S architecture internally generates the high programming voltage required to program EEPROM cells, allowing in-system programming with only a single 5.0 V power supply. During in-system programming, the I/O pins are tri-stated and pulled-up to eliminate board conflicts. The pull-up value is nominally 50 k3/4. ISP simplifies the manufacturing flow by allowing devices to be mounted on a printed circuit board with standard in-circuit test equipment before they are programmed. MAX 7000S devices can be programmed by downloading the information via in-circuit testers (ICT), embedded processors, or the Altera MasterBlaster, ByteBlasterMV, ByteBlaster, BitBlaster download cables. (The ByteBlaster cable is obsolete and is replaced by the ByteBlasterMV cable, which can program and configure 2.5-V, 3.3-V, and 5.0-V devices.) Programming the devices after they are placed on the board eliminates lead damage on high-pin-count packages (e.g., QFP packages) due to device handling and allows devices to be reprogrammed after a system has already shipped to the field. For example, product upgrades can be performed in the field via software or modem. In-system programming can be accomplished with either an adaptive or constant algorithm. An adaptive algorithm reads information from the unit and adapts subsequent programming steps to achieve the fastest possible programming time for that unit. Because some in-circuit testers cannot support an adaptive algorithm, Altera offers devices tested with a constant algorithm. Devices tested to the constant algorithm have an "F" suffix in the ordering code. The JamTM Standard Test and Programming Language (STAPL) can be used to program MAX 7000S devices with in-circuit testers, PCs, or embedded processor. 16 Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet f For more information on using the Jam language, see Application Note 88 (Using the Jam Language for ISP & ICR via an Embedded Processor). The ISP circuitry in MAX 7000S devices is compatible with IEEE Std. 1532 specification. The IEEE Std. 1532 is a standard developed to allow concurrent ISP between multiple PLD vendors. Programmable Speed/Power Control MAX 7000 devices offer a power-saving mode that supports low-power operation across user-defined signal paths or the entire device. This feature allows total power dissipation to be reduced by 50% or more, because most logic applications require only a small fraction of all gates to operate at maximum frequency. The designer can program each individual macrocell in a MAX 7000 device for either high-speed (i.e., with the Turbo BitTM option turned on) or low-power (i.e., with the Turbo Bit option turned off) operation. As a result, speed-critical paths in the design can run at high speed, while the remaining paths can operate at reduced power. Macrocells that run at low power incur a nominal timing delay adder (tLPA) for the tLAD, tLAC, tIC, tEN, and tSEXP, tACL, and tCPPW parameters. Output Configuration MAX 7000 device outputs can be programmed to meet a variety of system-level requirements. MultiVolt I/O Interface MAX 7000 devices--except 44-pin devices--support the MultiVolt I/O interface feature, which allows MAX 7000 devices to interface with systems that have differing supply voltages. The 5.0-V devices in all packages can be set for 3.3-V or 5.0-V I/O pin operation. These devices have one set of VCC pins for internal operation and input buffers (VCCINT), and another set for I/O output drivers (VCCIO). The VCCINT pins must always be connected to a 5.0-V power supply. With a 5.0-V VCCINT level, input voltage thresholds are at TTL levels, and are therefore compatible with both 3.3-V and 5.0-V inputs. The VCCIO pins can be connected to either a 3.3-V or a 5.0-V power supply, depending on the output requirements. When the VCCIO pins are connected to a 5.0-V supply, the output levels are compatible with 5.0-V systems. When VCCIO is connected to a 3.3-V supply, the output high is 3.3 V and is therefore compatible with 3.3-V or 5.0-V systems. Devices operating with VCCIO levels lower than 4.75 V incur a nominally greater timing delay of tOD2 instead of tOD1. Altera Corporation 17 MAX 7000 Programmable Logic Device Family Data Sheet Open-Drain Output Option (MAX 7000S Devices Only) MAX 7000S devices provide an optional open-drain (functionally equivalent to open-collector) output for each I/O pin. This open-drain output enables the device to provide system-level control signals (e.g., interrupt and write enable signals) that can be asserted by any of several devices. It can also provide an additional wired-OR plane. By using an external 5.0-V pull-up resistor, output pins on MAX 7000S devices can be set to meet 5.0-V CMOS input voltages. When VCCIO is 3.3 V, setting the open drain option will turn off the output pull-up transistor, allowing the external pull-up resistor to pull the output high enough to meet 5.0-V CMOS input voltages. When VCCIO is 5.0 V, setting the output drain option is not necessary because the pull-up transistor will already turn off when the pin exceeds approximately 3.8 V, allowing the external pull-up resistor to pull the output high enough to meet 5.0-V CMOS input voltages. Slew-Rate Control The output buffer for each MAX 7000E and MAX 7000S I/O pin has an adjustable output slew rate that can be configured for low-noise or highspeed performance. A faster slew rate provides high-speed transitions for high-performance systems. However, these fast transitions may introduce noise transients into the system. A slow slew rate reduces system noise, but adds a nominal delay of 4 to 5 ns. In MAX 7000E devices, when the Turbo Bit is turned off, the slew rate is set for low noise performance. For MAX 7000S devices, each I/O pin has an individual EEPROM bit that controls the slew rate, allowing designers to specify the slew rate on a pin-by-pin basis. Programming with External Hardware f MAX 7000 devices can be programmed on Windows-based PCs with the Altera Logic Programmer card, the Master Programming Unit (MPU), and the appropriate device adapter. The MPU performs a continuity check to ensure adequate electrical contact between the adapter and the device. For more information, see the Altera Programming Hardware Data Sheet. The Altera development system can use text- or waveform-format test vectors created with the Text Editor or Waveform Editor to test the programmed device. For added design verification, designers can perform functional testing to compare the functional behavior of a MAX 7000 device with the results of simulation. Moreover, Data I/O, BP Microsystems, and other programming hardware manufacturers also provide programming support for Altera devices. f 18 For more information, see the Programming Hardware Manufacturers. Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet IEEE Std. 1149.1 (JTAG) Boundary-Scan Support MAX 7000 devices support JTAG BST circuitry as specified by IEEE Std. 1149.1-1990. Table 6 describes the JTAG instructions supported by the MAX 7000 family. The pin-out tables (see the Altera web site (http://www.altera.com) or the Altera Digital Library for pin-out information) show the location of the JTAG control pins for each device. If the JTAG interface is not required, the JTAG pins are available as user I/O pins. Table 6. MAX 7000 JTAG Instructions JTAG Instruction Devices SAMPLE/PRELOAD EPM7128S EPM7160S EPM7192S EPM7256S Allows a snapshot of signals at the device pins to be captured and examined during normal device operation, and permits an initial data pattern output at the device pins. EXTEST EPM7128S EPM7160S EPM7192S EPM7256S Allows the external circuitry and board-level interconnections to be tested by forcing a test pattern at the output pins and capturing test results at the input pins. BYPASS EPM7032S EPM7064S EPM7128S EPM7160S EPM7192S EPM7256S Places the 1-bit bypass register between the TDI and TDO pins, which allows the BST data to pass synchronously through a selected device to adjacent devices during normal device operation. IDCODE EPM7032S EPM7064S EPM7128S EPM7160S EPM7192S EPM7256S Selects the IDCODE register and places it between TDI and TDO, allowing the IDCODE to be serially shifted out of TDO. ISP Instructions EPM7032S EPM7064S EPM7128S EPM7160S EPM7192S EPM7256S These instructions are used when programming MAX 7000S devices via the JTAG ports with the MasterBlaster, ByteBlasterMV, BitBlaster download cable, or using a Jam File (.jam), Jam Byte-Code file (.jbc), or Serial Vector Format file (.svf) via an embedded processor or test equipment. Altera Corporation Description 19 MAX 7000 Programmable Logic Device Family Data Sheet The instruction register length of MAX 7000S devices is 10 bits. Tables 7 and 8 show the boundary-scan register length and device IDCODE information for MAX 7000S devices. Table 7. MAX 7000S Boundary-Scan Register Length Device Boundary-Scan Register Length 1 (1) EPM7032S 1 (1) EPM7064S EPM7128S 288 EPM7160S 312 EPM7192S 360 EPM7256S 480 Note: (1) This device does not support JTAG boundary-scan testing. Selecting either the EXTEST or SAMPLE/PRELOAD instruction will select the one-bit bypass register. Table 8. 32-Bit MAX 7000 Device IDCODE Device Note (1) IDCODE (32 Bits) Version (4 Bits) Part Number (16 Bits) Manufacturer's 1 (1 Bit) Identity (11 Bits) (2) EPM7032S 0000 0111 0000 0011 0010 00001101110 1 EPM7064S 0000 0111 0000 0110 0100 00001101110 1 EPM7128S 0000 0111 0001 0010 1000 00001101110 1 EPM7160S 0000 0111 0001 0110 0000 00001101110 1 EPM7192S 0000 0111 0001 1001 0010 00001101110 1 EPM7256S 0000 0111 0010 0101 0110 00001101110 1 Notes: (1) (2) 20 The most significant bit (MSB) is on the left. The least significant bit (LSB) for all JTAG IDCODEs is 1. Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet Figure 9 shows the timing requirements for the JTAG signals. Figure 9. MAX 7000 JTAG Waveforms TMS TDI t JCP t JCH t JCL t JPSU t JPH TCK tJPZX t JPXZ t JPCO TDO tJSH tJSSU gnal o Be ured gnal o Be iven tJSCO tJSZX tJSXZ Table 9 shows the JTAG timing parameters and values for MAX 7000S devices. Table 9. JTAG Timing Parameters & Values for MAX 7000S Devices Symbol Altera Corporation Parameter Min Max 100 Unit tJCP TCK clock period tJCH TCK clock high time 50 ns ns tJCL TCK clock low time 50 ns tJPSU JTAG port setup time 20 ns tJPH JTAG port hold time 45 tJPCO JTAG port clock to output 25 tJPZX JTAG port high impedance to valid output 25 ns tJPXZ JTAG port valid output to high impedance 25 ns tJSSU Capture register setup time 20 ns tJSH Capture register hold time 45 ns tJSCO Update register clock to output 25 ns tJSZX Update register high impedance to valid output 25 ns tJSXZ Update register valid output to high impedance 25 ns ns ns 21 MAX 7000 Programmable Logic Device Family Data Sheet f For more information, see Application Note 39 (IEEE 1149.1 (JTAG) Boundary-Scan Testing in Altera Devices). Design Security All MAX 7000 devices contain a programmable security bit that controls access to the data programmed into the device. When this bit is programmed, a proprietary design implemented in the device cannot be copied or retrieved. This feature provides a high level of design security because programmed data within EEPROM cells is invisible. The security bit that controls this function, as well as all other programmed data, is reset only when the device is reprogrammed. Generic Testing Each MAX 7000 device is functionally tested. Complete testing of each programmable EEPROM bit and all internal logic elements ensures 100% programming yield. AC test measurements are taken under conditions equivalent to those shown in Figure 10. Test patterns can be used and then erased during early stages of the production flow. Figure 10. MAX 7000 AC Test Conditions Power supply transients can affect AC measurements. Simultaneous transitions of multiple outputs should be avoided for accurate measurement. Threshold tests must not be performed under AC conditions. Large-amplitude, fast ground-current transients normally occur as the device outputs discharge the load capacitances. When these transients flow through the parasitic inductance between the device ground pin and the test system ground, significant reductions in observable noise immunity can result. Numbers in brackets are for 2.5-V devices and outputs. Numbers without brackets are for 3.3-V devices and outputs. QFP Carrier & Development Socket f 464 [703 ] Device Output To Test System 250 [8.06 K ] C1 (includes JIG capacitance) Device input rise and fall times < 3 ns MAX 7000 and MAX 7000E devices in QFP packages with 100 or more pins are shipped in special plastic carriers to protect the QFP leads. The carrier is used with a prototype development socket and special programming hardware available from Altera. This carrier technology makes it possible to program, test, erase, and reprogram a device without exposing the leads to mechanical stress. For detailed information and carrier dimensions, refer to the QFP Carrier & Development Socket Data Sheet. 1 22 VCC MAX 7000S devices are not shipped in carriers. Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet Operating Conditions Tables 10 through 15 provide information about absolute maximum ratings, recommended operating conditions, operating conditions, and capacitance for 5.0-V MAX 7000 devices. Table 10. MAX 7000 5.0-V Device Absolute Maximum Ratings Symbol Parameter VCC Supply voltage Note (1) Conditions With respect to ground (2) Min Max Unit -2.0 7.0 V VI DC input voltage -2.0 7.0 V IOUT DC output current, per pin -25 25 mA TSTG Storage temperature No bias -65 150 C TAMB Ambient temperature Under bias -65 135 C TJ Junction temperature Ceramic packages, under bias 150 C PQFP and RQFP packages, under bias 135 C Table 11. MAX 7000 5.0-V Device Recommended Operating Conditions Symbol Parameter Conditions Min Max Unit VCCINT Supply voltage for internal logic and (3), (4), (5) input buffers 4.75 (4.50) 5.25 (5.50) V VCCIO Supply voltage for output drivers, 5.0-V operation (3), (4) 4.75 (4.50) 5.25 (5.50) V Supply voltage for output drivers, 3.3-V operation (3), (4), (6) 3.00 (3.00) 3.60 (3.60) V (7) VCCISP Supply voltage during ISP VI Input voltage VO Output voltage TA Ambient temperature TJ Junction temperature For commercial use For industrial use For commercial use For industrial use 4.75 5.25 V -0.5 (8) VCCINT + 0.5 V 0 VCCIO V 0 70 C -40 85 C 0 90 C -40 105 C tR Input rise time 40 ns tF Input fall time 40 ns Altera Corporation 23 MAX 7000 Programmable Logic Device Family Data Sheet Table 12. MAX 7000 5.0-V Device DC Operating Conditions Symbol Parameter Note (9) Conditions Min Max Unit VIH High-level input voltage 2.0 V CCINT + 0.5 V VIL Low-level input voltage -0.5 (8) 0.8 V VOH 5.0-V high-level TTL output voltage IOH = -4 mA DC, VCCIO = 4.75 V (10) 2.4 3.3-V high-level TTL output voltage IOH = -4 mA DC, VCCIO = 3.00 V (10) 2.4 V 3.3-V high-level CMOS output voltage IOH = -0.1 mA DC, VCCIO = 3.0 V (10) VCCIO - 0.2 V 5.0-V low-level TTL output voltage IOL = 12 mA DC, VCCIO = 4.75 V (11) 0.45 3.3-V low-level TTL output voltage IOL = 12 mA DC, VCCIO = 3.00 V (11) 0.45 V 3.3-V low-level CMOS output voltage IOL = 0.1 mA DC, VCCIO = 3.0 V(11) 0.2 V II Leakage current of dedicated input pins VI = -0.5 to 5.5 V (11) -10 10 A IOZ I/O pin tri-state output off-state current VI = -0.5 to 5.5 V (11), (12) -40 40 A VOL V V Table 13. MAX 7000 5.0-V Device Capacitance: EPM7032, EPM7064 & EPM7096 Devices Note (13) Symbol Max Parameter Conditions Min Unit CIN Input pin capacitance VIN = 0 V, f = 1.0 MHz 12 pF CI/O I/O pin capacitance VOUT = 0 V, f = 1.0 MHz 12 pF Max Unit Table 14. MAX 7000 5.0-V Device Capacitance: MAX 7000E Devices Symbol Parameter Conditions Note (13) Min CIN Input pin capacitance VIN = 0 V, f = 1.0 MHz 15 pF CI/O I/O pin capacitance VOUT = 0 V, f = 1.0 MHz 15 pF Max Unit Table 15. MAX 7000 5.0-V Device Capacitance: MAX 7000S Devices Symbol Parameter Conditions Note (13) Min CIN Dedicated input pin capacitance VIN = 0 V, f = 1.0 MHz 10 pF CI/O I/O pin capacitance VOUT = 0 V, f = 1.0 MHz 10 pF 24 Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet Notes to tables: (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) (12) (13) See the Operating Requirements for Altera Devices Data Sheet. Minimum DC input voltage on I/O pins is -0.5 V and on 4 dedicated input pins is -0.3 V. During transitions, the inputs may undershoot to -2.0 V or overshoot to 7.0 V for input currents less than 100 mA and periods shorter than 20 ns. Numbers in parentheses are for industrial-temperature-range devices. VCC must rise monotonically. The POR time for all 7000S devices does not exceed 300 s. The sufficient VCCINT voltage level for POR is 4.5 V. The device is fully initialized within the POR time after VCCINT reaches the sufficient POR voltage level. 3.3-V I/O operation is not available for 44-pin packages. The VCCISP parameter applies only to MAX 7000S devices. During in-system programming, the minimum DC input voltage is -0.3 V. These values are specified under the MAX 7000 recommended operating conditions in Table 11 on page 23. The parameter is measured with 50% of the outputs each sourcing the specified current. The IOH parameter refers to high-level TTL or CMOS output current. The parameter is measured with 50% of the outputs each sinking the specified current. The IOL parameter refers to low-level TTL, PCI, or CMOS output current. When the JTAG interface is enabled in MAX 7000S devices, the input leakage current on the JTAG pins is typically -60 A. Capacitance is measured at 25 C and is sample-tested only. The OE1 pin has a maximum capacitance of 20 pF. Figure 11 shows the typical output drive characteristics of MAX 7000 devices. Figure 11. Output Drive Characteristics of 5.0-V MAX 7000 Devices 150 150 IOL 120 Typical I O Output Current (mA) IOL 120 90 VCCIO = 5.0 V Room Temperature 60 Typical I O Output Current (mA) 90 VCCIO = 3.3 V Room Temperature 60 IOH IOH 30 30 1 2 3 4 VO Output Voltage (V) Timing Model Altera Corporation 5 1 2 3 3.3 4 5 VO Output Voltage (V) MAX 7000 device timing can be analyzed with the Altera software, with a variety of popular industry-standard EDA simulators and timing analyzers, or with the timing model shown in Figure 12. MAX 7000 devices have fixed internal delays that enable the designer to determine the worst-case timing of any design. The Altera software provides timing simulation, point-to-point delay prediction, and detailed timing analysis for a device-wide performance evaluation. 25 MAX 7000 Programmable Logic Device Family Data Sheet Figure 12. MAX 7000 Timing Model Internal Output Enable Delay t IOE (1) Global Control Delay t GLOB Input Delay t IN PIA Delay t PIA Logic Array Delay t LAD Parallel Expander Delay t PEXP Register Control Delay t LAC tIC t EN Shared Expander Delay t SEXP Fast Input Delay t F I N (1) Register Delay t SU tH t PRE t CLR t RD t COMB t FSU t FH Output Delay t OD1 t OD2 (2) t OD3 t XZ t Z X1 t Z X2 (2) t Z X3 (1) I/O Delay tIO Notes: (1) (2) Only available in MAX 7000E and MAX 7000S devices. Not available in 44-pin devices. The timing characteristics of any signal path can be derived from the timing model and parameters of a particular device. External timing parameters, which represent pin-to-pin timing delays, can be calculated as the sum of internal parameters. Figure 13 shows the internal timing relationship of internal and external delay parameters. f 26 For more infomration, see Application Note 94 (Understanding MAX 7000 Timing). Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet Figure 13. Switching Waveforms tR & tF < 3 ns. Inputs are driven at 3 V for a logic high and 0 V for a logic low. All timing characteristics are measured at 1.5 V. Combinatorial Mode tIN Input Pin tIO I/O Pin tPIA PIA Delay tSEXP Shared Expander Delay tLAC , tLAD Logic Array Input tPEXP Parallel Expander Delay tCOMB Logic Array Output tOD Output Pin Global Clock Mode Global Clock Pin tR tCH tIN Global Clock at Register tSU tCL tF tACL tF tGLOB tH Data or Enable (Logic Array Output) Array Clock Mode tR tACH Input or I/O Pin tIN tIO Clock into PIA Clock into Logic Array Clock at Register tPIA tIC tSU tH Data from Logic Array tRD tPIA tPIA tCLR , tPRE Register to PIA to Logic Array tOD tOD Register Output to Pin Altera Corporation 27 MAX 7000 Programmable Logic Device Family Data Sheet Tables 16 through 23 show the MAX 7000 and MAX 7000E AC operating conditions. Table 16. MAX 7000 & MAX 7000E External Timing Parameters Symbol Parameter Conditions Note (1) -6 Speed Grade Min Max -7 Speed Grade Min Unit Max tPD1 Input to non-registered output C1 = 35 pF 6.0 7.5 ns tPD2 I/O input to non-registered output C1 = 35 pF 6.0 7.5 ns tSU Global clock setup time 5.0 6.0 ns tH Global clock hold time 0.0 0.0 ns ns tFSU Global clock setup time of fast input (2) 2.5 3.0 tFH Global clock hold time of fast input (2) 0.5 0.5 tCO1 Global clock to output delay C1 = 35 pF tCH Global clock high time 2.5 3.0 ns tCL Global clock low time 2.5 3.0 ns tASU Array clock setup time 2.5 3.0 ns tAH Array clock hold time 2.0 2.0 ns tACO1 Array clock to output delay tACH Array clock high time 3.0 3.0 ns tACL Array clock low time 3.0 3.0 ns tCPPW Minimum pulse width for clear and preset (3) 3.0 3.0 ns C1 = 35 pF (4) 1.0 tODH Output data hold time after clock tCNT Minimum global clock period fCNT Maximum internal global clock frequency tACNT Minimum array clock period fACNT fMAX 28 4.0 C1 = 35 pF ns 4.5 6.5 7.5 1.0 6.6 ns ns ns 8.0 125.0 ns (5) 151.5 Maximum internal array clock frequency (5) 151.5 125.0 MHz Maximum clock frequency (6) 200 166.7 MHz 6.6 MHz 8.0 ns Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet Table 17. MAX 7000 & MAX 7000E Internal Timing Parameters Symbol Parameter Conditions Note (1) Speed Grade -6 Min Max Speed Grade -7 Min Unit Max tIN Input pad and buffer delay 0.4 0.5 ns tIO I/O input pad and buffer delay 0.4 0.5 ns tFIN Fast input delay 0.8 1.0 ns tSEXP Shared expander delay 3.5 4.0 ns tPEXP Parallel expander delay 0.8 0.8 ns tLAD Logic array delay 2.0 3.0 ns tLAC Logic control array delay 2.0 3.0 ns (2) tIOE Internal output enable delay (2) 2.0 ns tOD1 Output buffer and pad delay Slow slew rate = off, VCCIO = 5.0 V C1 = 35 pF 2.0 2.0 ns tOD2 Output buffer and pad delay Slow slew rate = off, VCCIO = 3.3 V C1 = 35 pF (7) 2.5 2.5 ns tOD3 Output buffer and pad delay Slow slew rate = on, VCCIO = 5.0 V or 3.3 V C1 = 35 pF (2) 7.0 7.0 ns tZX1 Output buffer enable delay Slow slew rate = off, VCCIO = 5.0 V C1 = 35 pF 4.0 4.0 ns tZX2 Output buffer enable delay Slow slew rate = off, VCCIO = 3.3 V C1 = 35 pF (7) 4.5 4.5 ns tZX3 Output buffer enable delay Slow slew rate = on VCCIO = 5.0 V or 3.3 V C1 = 35 pF (2) 9.0 9.0 ns C1 = 5 pF 4.0 ns tXZ Output buffer disable delay tSU Register setup time 3.0 3.0 ns tH Register hold time 1.5 2.0 ns tFSU Register setup time of fast input (2) 2.5 3.0 ns tFH Register hold time of fast input (2) 0.5 0.5 tRD Register delay tCOMB Combinatorial delay 0.8 1.0 ns tIC Array clock delay 2.5 3.0 ns tEN Register enable time 2.0 3.0 ns tGLOB Global control delay 0.8 1.0 ns tPRE Register preset time 2.0 2.0 ns tCLR Register clear time 2.0 2.0 ns tPIA PIA delay tLPA Low-power adder Altera Corporation 4.0 0.8 (8) ns 1.0 ns 0.8 1.0 ns 10.0 10.0 ns 29 MAX 7000 Programmable Logic Device Family Data Sheet Table 18. MAX 7000 & MAX 7000E External Timing Parameters Symbol Parameter Note (1) Conditions Speed Grade Unit MAX 7000E (-10P) MAX 7000 (-10) MAX 7000E (-10) Min Max Min Max tPD1 Input to non-registered output C1 = 35 pF 10.0 10.0 ns tPD2 I/O input to non-registered output C1 = 35 pF 10.0 10.0 ns tSU Global clock setup time 7.0 8.0 ns tH Global clock hold time 0.0 0.0 ns tFSU Global clock setup time of fast input (2) 3.0 3.0 ns tFH Global clock hold time of fast input (2) 0.5 0.5 tCO1 Global clock to output delay tCH Global clock high time 4.0 4.0 ns tCL Global clock low time 4.0 4.0 ns tASU Array clock setup time 2.0 3.0 ns tAH Array clock hold time 3.0 3.0 ns tACO1 Array clock to output delay tACH Array clock high time 4.0 4.0 ns tACL Array clock low time 4.0 4.0 ns tCPPW Minimum pulse width for clear and preset (3) 4.0 4.0 ns tODH Output data hold time after clock C1 = 35 pF (4) 1.0 tCNT Minimum global clock period fCNT Maximum internal global clock frequency C1 = 35 pF 5.0 C1 = 35 pF 10.0 10.0 1.0 10.0 (5) 100.0 ns 5 ns ns ns 10.0 100.0 ns MHz tACNT Minimum array clock period fACNT Maximum internal array clock frequency (5) 100.0 100.0 MHz fMAX Maximum clock frequency (6) 125.0 125.0 MHz 30 10.0 10.0 ns Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet Table 19. MAX 7000 & MAX 7000E Internal Timing Parameters Symbol Parameter Note (1) Conditions Speed Grade MAX 7000E (-10P) Min Max Unit MAX 7000 (-10) MAX 7000E (-10) Min Max tIN Input pad and buffer delay 0.5 1.0 ns tIO I/O input pad and buffer delay 0.5 1.0 ns tFIN Fast input delay 1.0 1.0 ns tSEXP Shared expander delay 5.0 5.0 ns tPEXP Parallel expander delay 0.8 0.8 ns tLAD Logic array delay 5.0 5.0 ns tLAC Logic control array delay 5.0 5.0 ns tIOE Internal output enable delay (2) 2.0 2.0 ns tOD1 Output buffer and pad delay Slow slew rate = off VCCIO = 5.0 V C1 = 35 pF 1.5 2.0 ns tOD2 Output buffer and pad delay Slow slew rate = off VCCIO = 3.3 V C1 = 35 pF (7) 2.0 2.5 ns tOD3 Output buffer and pad delay Slow slew rate = on VCCIO = 5.0 V or 3.3 V C1 = 35 pF (2) 5.5 6.0 ns tZX1 Output buffer enable delay Slow slew rate = off VCCIO = 5.0 V C1 = 35 pF 5.0 5.0 ns tZX2 Output buffer enable delay Slow slew rate = off VCCIO = 3.3 V C1 = 35 pF (7) 5.5 5.5 ns tZX3 Output buffer enable delay Slow slew rate = on VCCIO = 5.0 V or 3.3 V C1 = 35 pF (2) 9.0 9.0 ns tXZ Output buffer disable delay C1 = 5 pF 5.0 ns tSU Register setup time 2.0 3.0 ns tH Register hold time 3.0 3.0 ns tFSU Register setup time of fast input (2) 3.0 3.0 ns tFH Register hold time of fast input (2) 0.5 0.5 tRD Register delay tCOMB Combinatorial delay 2.0 1.0 ns tIC Array clock delay 5.0 5.0 ns tEN Register enable time 5.0 5.0 ns tGLOB Global control delay 1.0 1.0 ns tPRE Register preset time 3.0 3.0 ns tCLR Register clear time 3.0 3.0 ns tPIA PIA delay 1.0 1.0 ns tLPA Low-power adder 11.0 11.0 ns Altera Corporation (2) 5.0 2.0 (8) ns 1.0 ns 31 MAX 7000 Programmable Logic Device Family Data Sheet Table 20. MAX 7000 & MAX 7000E External Timing Parameters Symbol Parameter Note (1) Conditions Speed Grade MAX 7000E (-12P) Min Max Unit MAX 7000 (-12) MAX 7000E (-12) Min Max tPD1 Input to non-registered output C1 = 35 pF 12.0 12.0 ns tPD2 I/O input to non-registered output C1 = 35 pF 12.0 12.0 ns tSU Global clock setup time 7.0 10.0 ns tH Global clock hold time 0.0 0.0 ns ns tFSU Global clock setup time of fast input (2) 3.0 3.0 tFH Global clock hold time of fast input (2) 0.0 0.0 tCO1 Global clock to output delay tCH Global clock high time 4.0 4.0 ns tCL Global clock low time 4.0 4.0 ns tASU Array clock setup time 3.0 4.0 ns tAH Array clock hold time 4.0 4.0 ns tACO1 Array clock to output delay tACH Array clock high time 5.0 5.0 ns tACL Array clock low time 5.0 5.0 ns tCPPW Minimum pulse width for clear and preset (3) 5.0 5.0 ns tODH Output data hold time after clock C1 = 35 pF (4) 1.0 tCNT Minimum global clock period fCNT Maximum internal global clock frequency C1 = 35 pF ns 6.0 C1 = 35 pF 6.0 12.0 12.0 1.0 90.9 ns ns 11.0 (5) ns 11.0 90.9 ns MHz tACNT Minimum array clock period fACNT Maximum internal array clock frequency (5) 90.9 90.9 MHz fMAX Maximum clock frequency (6) 125.0 125.0 MHz 32 11.0 11.0 ns Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet Table 21. MAX 7000 & MAX 7000E Internal Timing Parameters Symbol Parameter Note (1) Conditions Speed Grade MAX 7000E (-12P) Min Max Unit MAX 7000 (-12) MAX 7000E (-12) Min Max tIN Input pad and buffer delay 1.0 2.0 ns tIO I/O input pad and buffer delay 1.0 2.0 ns tFIN Fast input delay 1.0 1.0 ns tSEXP Shared expander delay 7.0 7.0 ns tPEXP Parallel expander delay 1.0 1.0 ns tLAD Logic array delay 7.0 5.0 ns tLAC Logic control array delay 5.0 5.0 ns tIOE Internal output enable delay (2) 2.0 2.0 ns tOD1 Output buffer and pad delay Slow slew rate = off VCCIO = 5.0 V C1 = 35 pF 1.0 3.0 ns tOD2 Output buffer and pad delay Slow slew rate = off VCCIO = 3.3 V C1 = 35 pF (7) 2.0 4.0 ns tOD3 Output buffer and pad delay Slow slew rate = on VCCIO = 5.0 V or 3.3 V C1 = 35 pF (2) 5.0 7.0 ns tZX1 Output buffer enable delay Slow slew rate = off VCCIO = 5.0 V C1 = 35 pF 6.0 6.0 ns tZX2 Output buffer enable delay Slow slew rate = off VCCIO = 3.3 V C1 = 35 pF (7) 7.0 7.0 ns tZX3 Output buffer enable delay Slow slew rate = on VCCIO = 5.0 V or 3.3 V C1 = 35 pF (2) 10.0 10.0 ns tXZ Output buffer disable delay C1 = 5 pF 6.0 ns tSU Register setup time 1.0 4.0 ns tH Register hold time 6.0 4.0 ns tFSU Register setup time of fast input (2) 4.0 2.0 ns tFH Register hold time of fast input (2) 0.0 2.0 tRD Register delay tCOMB Combinatorial delay 2.0 1.0 ns tIC Array clock delay 5.0 5.0 ns tEN Register enable time 7.0 5.0 ns tGLOB Global control delay 2.0 0.0 ns tPRE Register preset time 4.0 3.0 ns tCLR Register clear time 4.0 3.0 ns tPIA PIA delay tLPA Low-power adder Altera Corporation (2) 6.0 2.0 (8) ns 1.0 ns 1.0 1.0 ns 12.0 12.0 ns 33 MAX 7000 Programmable Logic Device Family Data Sheet Table 22. MAX 7000 & MAX 7000E External Timing Parameters Symbol Parameter Note (1) Conditions Speed Grade -15 Min Unit -15T Max Min -20 Max Min Max tPD1 Input to non-registered output C1 = 35 pF 15.0 15.0 20.0 ns tPD2 I/O input to non-registered output C1 = 35 pF 15.0 15.0 20.0 ns tSU Global clock setup time 11.0 11.0 12.0 ns tH Global clock hold time 0.0 0.0 0.0 ns tFSU Global clock setup time of fast input (2) 3.0 - 5.0 ns tFH Global clock hold time of fast input (2) 0.0 - 0.0 ns tCO1 Global clock to output delay C1 = 35 pF tCH Global clock high time 5.0 6.0 6.0 ns tCL Global clock low time 5.0 6.0 6.0 ns tASU Array clock setup time 4.0 4.0 5.0 ns tAH Array clock hold time 4.0 4.0 5.0 ns tACO1 Array clock to output delay tACH Array clock high time 6.0 6.5 8.0 tACL Array clock low time 6.0 6.5 8.0 ns tCPPW Minimum pulse width for clear and preset (3) 6.0 6.5 8.0 ns tODH Output data hold time after clock C1 = 35 pF (4) 1.0 1.0 1.0 ns tCNT Minimum global clock period fCNT Maximum internal global clock frequency (5) 76.9 8.0 C1 = 35 pF 8.0 15.0 12.0 15.0 13.0 20.0 13.0 76.9 ns ns ns 16.0 62.5 ns MHz tACNT Minimum array clock period fACNT Maximum internal array clock frequency (5) 76.9 76.9 62.5 MHz fMAX Maximum clock frequency (6) 100 83.3 83.3 MHz 34 13.0 13.0 16.0 ns Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet Table 23. MAX 7000 & MAX 7000E Internal Timing Parameters Symbol Parameter Note (1) Conditions Speed Grade -15 Min Unit -15T Max Min -20 Max Min Max tIN Input pad and buffer delay 2.0 2.0 3.0 ns tIO I/O input pad and buffer delay 2.0 2.0 3.0 ns tFIN Fast input delay 2.0 - 4.0 ns tSEXP Shared expander delay 8.0 10.0 9.0 ns tPEXP Parallel expander delay 1.0 1.0 2.0 ns tLAD Logic array delay 6.0 6.0 8.0 ns tLAC Logic control array delay 6.0 6.0 8.0 ns tIOE Internal output enable delay (2) 3.0 - 4.0 ns tOD1 Output buffer and pad delay Slow slew rate = off VCCIO = 5.0 V C1 = 35 pF 4.0 4.0 5.0 ns tOD2 Output buffer and pad delay Slow slew rate = off VCCIO = 3.3 V C1 = 35 pF (7) 5.0 - 6.0 ns tOD3 Output buffer and pad delay Slow slew rate = on VCCIO = 5.0 V or 3.3 V C1 = 35 pF (2) 8.0 - 9.0 ns tZX1 Output buffer enable delay Slow slew rate = off VCCIO = 5.0 V C1 = 35 pF 6.0 6.0 10.0 ns tZX2 Output buffer enable delay Slow slew rate = off VCCIO = 3.3 V C1 = 35 pF (7) 7.0 - 11.0 ns tZX3 Output buffer enable delay Slow slew rate = on VCCIO = 5.0 V or 3.3 V C1 = 35 pF (2) 10.0 - 14.0 ns C1 = 5 pF 10.0 ns (2) tXZ Output buffer disable delay tSU Register setup time 4.0 4.0 4.0 ns tH Register hold time 4.0 4.0 5.0 ns tFSU Register setup time of fast input (2) 2.0 - 4.0 ns tFH Register hold time of fast input 2.0 - 3.0 tRD Register delay tCOMB Combinatorial delay 1.0 tIC Array clock delay 6.0 tEN Register enable time 6.0 6.0 tGLOB Global control delay 1.0 1.0 3.0 ns tPRE Register preset time 4.0 4.0 4.0 ns tCLR Register clear time 4.0 4.0 4.0 ns tPIA PIA delay 2.0 2.0 3.0 ns tLPA Low-power adder 13.0 15.0 15.0 ns Altera Corporation (2) 6.0 1.0 (8) 6.0 1.0 ns 1.0 ns 1.0 1.0 ns 6.0 8.0 ns 8.0 ns 35 MAX 7000 Programmable Logic Device Family Data Sheet Notes to tables: (1) (2) (3) (4) (5) (6) (7) (8) These values are specified under the recommended operating conditions shown in Table 11. See Figure 13 for more information on switching waveforms. This parameter applies to MAX 7000E devices only. This minimum pulse width for preset and clear applies for both global clear and array controls. The tLPA parameter must be added to this minimum width if the clear or reset signal incorporates the tLAD parameter into the signal path. This parameter is a guideline that is sample-tested only and is based on extensive device characterization. This parameter applies for both global and array clocking. These parameters are measured with a 16-bit loadable, enabled, up/down counter programmed into each LAB. The fMAX values represent the highest frequency for pipelined data. Operating conditions: VCCIO = 3.3 V 10% for commercial and industrial use. The tLPA parameter must be added to the tLAD, tLAC , tIC, tEN, tSEXP, tACL, and tCPPW parameters for macrocells running in the low-power mode. Tables 24 and 25 show the EPM7032S AC operating conditions. Table 24. EPM7032S External Timing Parameters (Part 1 of 2) Symbol Parameter Note (1) Conditions Speed Grade -5 -6 Unit -7 -10 Min Max Min Max Min Max Min Max tPD1 Input to non-registered output C1 = 35 pF 5.0 6.0 7.5 10.0 ns tPD2 I/O input to non-registered output C1 = 35 pF 5.0 6.0 7.5 10.0 ns tSU Global clock setup time 2.9 4.0 5.0 7.0 ns tH Global clock hold time 0.0 0.0 0.0 0.0 ns tFSU Global clock setup time of fast input 2.5 2.5 2.5 3.0 ns tFH Global clock hold time of fast input 0.0 0.0 0.0 0.5 ns tCO1 Global clock to output delay tCH Global clock high time 2.0 2.5 3.0 4.0 ns tCL Global clock low time 2.0 2.5 3.0 4.0 ns tASU Array clock setup time 0.7 0.9 1.1 2.0 ns tAH Array clock hold time 1.8 2.1 2.7 3.0 tACO1 Array clock to output delay tACH Array clock high time 2.5 2.5 3.0 4.0 ns tACL Array clock low time 2.5 2.5 3.0 4.0 ns tCPPW Minimum pulse width for clear and preset (2) 2.5 2.5 3.0 4.0 ns tODH Output data hold time after clock C1 = 35 pF (3) 1.0 1.0 1.0 1.0 ns tCNT Minimum global clock period fCNT Maximum internal global clock frequency tACNT Minimum array clock period 36 C1 = 35 pF 3.2 C1 = 35 pF 3.5 5.4 6.6 5.7 (4) 175.4 10.0 100.0 8.6 ns ns 10.0 8.6 116.3 7.0 5.0 8.2 7.0 142.9 5.7 4.3 ns ns MHz 10.0 ns Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet Table 24. EPM7032S External Timing Parameters (Part 2 of 2) Symbol Parameter Note (1) Conditions Speed Grade -5 -6 Unit -7 -10 Min Max Min Max Min Max Min Max fACNT Maximum internal array clock frequency (4) 175.4 142.9 116.3 100.0 MHz fMAX Maximum clock frequency (5) 250.0 200.0 166.7 125.0 MHz Table 25. EPM7032S Internal Timing Parameters Symbol Parameter Note (1) Conditions Speed Grade -5 Min -6 Max Min Unit -7 Max Min -10 Max Min Max tIN Input pad and buffer delay 0.2 0.2 0.3 0.5 tIO I/O input pad and buffer delay 0.2 0.2 0.3 0.5 ns tFIN Fast input delay 2.2 2.1 2.5 1.0 ns tSEXP Shared expander delay 3.1 3.8 4.6 5.0 ns tPEXP Parallel expander delay 0.9 1.1 1.4 0.8 ns tLAD Logic array delay 2.6 3.3 4.0 5.0 ns tLAC Logic control array delay 2.5 3.3 4.0 5.0 ns tIOE Internal output enable delay 0.7 0.8 1.0 2.0 ns tOD1 Output buffer and pad delay C1 = 35 pF 0.2 0.3 0.4 1.5 ns tOD2 Output buffer and pad delay C1 = 35 pF (6) 0.7 0.8 0.9 2.0 ns tOD3 Output buffer and pad delay C1 = 35 pF 5.2 5.3 5.4 5.5 ns tZX1 Output buffer enable delay C1 = 35 pF 4.0 4.0 4.0 5.0 ns tZX2 Output buffer enable delay C1 = 35 pF (6) 4.5 4.5 4.5 5.5 ns tZX3 Output buffer enable delay C1 = 35 pF 9.0 9.0 9.0 9.0 ns tXZ Output buffer disable delay C1 = 5 pF 5.0 ns tSU Register setup time 0.8 1.0 1.3 2.0 ns tH Register hold time 1.7 2.0 2.5 3.0 ns tFSU Register setup time of fast input 1.9 1.8 1.7 3.0 ns tFH Register hold time of fast input 0.6 0.7 0.8 0.5 ns 4.0 4.0 4.0 ns tRD Register delay 1.2 1.6 1.9 2.0 ns tCOMB Combinatorial delay 0.9 1.1 1.4 2.0 ns tIC Array clock delay 2.7 3.4 4.2 5.0 ns tEN Register enable time 2.6 3.3 4.0 5.0 ns tGLOB Global control delay 1.6 1.4 1.7 1.0 ns tPRE Register preset time 2.0 2.4 3.0 3.0 ns Altera Corporation 37 MAX 7000 Programmable Logic Device Family Data Sheet Table 25. EPM7032S Internal Timing Parameters Symbol Parameter Note (1) Conditions Speed Grade -5 Min tCLR Register clear time tPIA PIA delay tLPA Low-power adder -6 Max Min Unit -7 Max Min -10 Max Min Max 2.0 2.4 3.0 3.0 (7) 1.1 1.1 1.4 1.0 ns ns (8) 12.0 10.0 10.0 11.0 ns Notes to tables: (1) (2) (3) (4) (5) (6) (7) (8) These values are specified under the recommended operating conditions shown in Table 11. See Figure 13 for more information on switching waveforms. This minimum pulse width for preset and clear applies for both global clear and array controls. The tLPA parameter must be added to this minimum width if the clear or reset signal incorporates the tLAD parameter into the signal path. This parameter is a guideline that is sample-tested only and is based on extensive device characterization. This parameter applies for both global and array clocking. These parameters are measured with a 16-bit loadable, enabled, up/down counter programmed into each LAB. The fMAX values represent the highest frequency for pipelined data. Operating conditions: VCCIO = 3.3 V 10% for commercial and industrial use. For EPM7064S-5, EPM7064S-6, EPM7128S-6, EPM7160S-6, EPM7160S-7, EPM7192S-7, and EPM7256S-7 devices, these values are specified for a PIA fan-out of one LAB (16 macrocells). For each additional LAB fan-out in these devices, add an additional 0.1 ns to the PIA timing value. The tLPA parameter must be added to the tLAD, tLAC , tIC, tEN, tSEXP, tACL, and tCPPW parameters for macrocells running in the low-power mode. Tables 26 and 27 show the EPM7064S AC operating conditions. Table 26. EPM7064S External Timing Parameters (Part 1 of 2) Symbol Parameter Note (1) Conditions Speed Grade -5 -6 Unit -7 -10 Min Max Min Max Min Max Min Max tPD1 Input to non-registered output C1 = 35 pF 5.0 6.0 7.5 10.0 ns tPD2 I/O input to non-registered output C1 = 35 pF 5.0 6.0 7.5 10.0 ns tSU Global clock setup time 2.9 3.6 6.0 7.0 ns tH Global clock hold time 0.0 0.0 0.0 0.0 ns tFSU Global clock setup time of fast input 2.5 2.5 3.0 3.0 ns tFH Global clock hold time of fast input 0.0 0.0 0.5 0.5 ns tCO1 Global clock to output delay tCH Global clock high time 2.0 2.5 3.0 4.0 ns tCL Global clock low time 2.0 2.5 3.0 4.0 ns tASU Array clock setup time 0.7 0.9 3.0 2.0 ns 38 C1 = 35 pF 3.2 4.0 4.5 5.0 ns Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet Table 26. EPM7064S External Timing Parameters (Part 2 of 2) Symbol Parameter Note (1) Conditions Speed Grade -5 -6 Unit -7 -10 Min Max Min Max Min Max Min Max tAH Array clock hold time tACO1 Array clock to output delay 1.8 2.1 tACH Array clock high time 2.5 2.5 3.0 4.0 ns tACL Array clock low time 2.5 2.5 3.0 4.0 ns tCPPW Minimum pulse width for clear and preset (2) 2.5 2.5 3.0 4.0 ns tODH Output data hold time after clock C1 = 35 pF (3) 1.0 1.0 1.0 1.0 ns tCNT Minimum global clock period fCNT Maximum internal global clock frequency C1 = 35 pF 2.0 5.4 5.7 (4) 175.4 3.0 6.7 7.1 140.8 ns 7.5 10.0 8.0 125.0 10.0 100.0 ns ns MHz tACNT Minimum array clock period fACNT Maximum internal array clock frequency (4) 175.4 140.8 125.0 100.0 MHz fMAX Maximum clock frequency (5) 250.0 200.0 166.7 125.0 MHz 5.7 Table 27. EPM7064S Internal Timing Parameters (Part 1 of 2) Symbol Parameter 7.1 8.0 10.0 Note (1) Conditions Speed Grade -5 Min -6 Unit -7 Min Max Min -10 Max Min Max tIN Input pad and buffer delay 0.2 0.2 0.5 0.5 tIO I/O input pad and buffer delay 0.2 0.2 0.5 0.5 ns tFIN Fast input delay 2.2 2.6 1.0 1.0 ns tSEXP Shared expander delay 3.1 3.8 4.0 5.0 ns tPEXP Parallel expander delay 0.9 1.1 0.8 0.8 ns tLAD Logic array delay 2.6 3.2 3.0 5.0 ns tLAC Logic control array delay 2.5 3.2 3.0 5.0 ns tIOE Internal output enable delay 0.7 0.8 2.0 2.0 ns tOD1 Output buffer and pad delay C1 = 35 pF 0.2 0.3 2.0 1.5 ns tOD2 Output buffer and pad delay C1 = 35 pF (6) 0.7 0.8 2.5 2.0 ns tOD3 Output buffer and pad delay C1 = 35 pF 5.2 5.3 7.0 5.5 ns tZX1 Output buffer enable delay C1 = 35 pF 4.0 4.0 4.0 5.0 ns tZX2 Output buffer enable delay C1 = 35 pF (6) 4.5 4.5 4.5 5.5 ns tZX3 Output buffer enable delay C1 = 35 pF 9.0 9.0 9.0 9.0 ns tXZ Output buffer disable delay C1 = 5 pF 5.0 ns tSU Register setup time Altera Corporation Max ns 4.0 0.8 4.0 1.0 4.0 3.0 2.0 ns ns 39 MAX 7000 Programmable Logic Device Family Data Sheet Table 27. EPM7064S Internal Timing Parameters (Part 2 of 2) Symbol Parameter Note (1) Conditions Speed Grade -5 Min -6 Max Min Unit -7 Max -10 Min Max Min Max tH Register hold time 1.7 2.0 2.0 3.0 ns tFSU Register setup time of fast input 1.9 1.8 3.0 3.0 ns tFH Register hold time of fast input 0.6 0.7 0.5 0.5 ns tRD Register delay 1.2 1.6 1.0 2.0 tCOMB Combinatorial delay 0.9 1.0 1.0 2.0 ns tIC Array clock delay 2.7 3.3 3.0 5.0 ns tEN Register enable time 2.6 3.2 3.0 5.0 ns tGLOB Global control delay 1.6 1.9 1.0 1.0 ns tPRE Register preset time 2.0 2.4 2.0 3.0 ns tCLR Register clear time 2.0 2.4 2.0 3.0 ns tPIA PIA delay (7) 1.1 1.3 1.0 1.0 ns tLPA Low-power adder (8) 12.0 11.0 10.0 11.0 ns ns Notes to tables: (1) (2) (3) (4) (5) (6) (7) (8) 40 These values are specified under the recommended operating conditions shown in Table 11. See Figure 13 for more information on switching waveforms. This minimum pulse width for preset and clear applies for both global clear and array controls. The tLPA parameter must be added to this minimum width if the clear or reset signal incorporates the tLAD parameter into the signal path. This parameter is a guideline that is sample-tested only and is based on extensive device characterization. This parameter applies for both global and array clocking. These parameters are measured with a 16-bit loadable, enabled, up/down counter programmed into each LAB. The fMAX values represent the highest frequency for pipelined data. Operating conditions: VCCIO = 3.3 V 10% for commercial and industrial use. For EPM7064S-5, EPM7064S-6, EPM7128S-6, EPM7160S-6, EPM7160S-7, EPM7192S-7, and EPM7256S-7 devices, these values are specified for a PIA fan-out of one LAB (16 macrocells). For each additional LAB fan-out in these devices, add an additional 0.1 ns to the PIA timing value. The tLPA parameter must be added to the tLAD, tLAC , tIC, tEN, tSEXP, tACL, and tCPPW parameters for macrocells running in the low-power mode. Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet Tables 28 and 29 show the EPM7128S AC operating conditions. Table 28. EPM7128S External Timing Parameters Symbol Parameter Note (1) Conditions Speed Grade -6 -7 Unit -10 -15 Min Max Min Max Min Max Min Max tPD1 Input to non-registered output C1 = 35 pF 6.0 7.5 10.0 15.0 ns tPD2 I/O input to non-registered output C1 = 35 pF 6.0 7.5 10.0 15.0 ns tSU Global clock setup time 3.4 6.0 7.0 11.0 ns tH Global clock hold time 0.0 0.0 0.0 0.0 ns tFSU Global clock setup time of fast input 2.5 3.0 3.0 3.0 ns tFH Global clock hold time of fast input 0.0 0.5 0.5 0.0 ns tCO1 Global clock to output delay tCH Global clock high time 3.0 3.0 4.0 5.0 ns tCL Global clock low time 3.0 3.0 4.0 5.0 ns tASU Array clock setup time 0.9 3.0 2.0 4.0 ns tAH Array clock hold time 1.8 2.0 5.0 4.0 ns tACO1 Array clock to output delay tACH Array clock high time 3.0 3.0 4.0 6.0 ns tACL Array clock low time 3.0 3.0 4.0 6.0 ns tCPPW Minimum pulse width for clear and preset (2) 3.0 3.0 4.0 6.0 ns tODH Output data hold time after clock C1 = 35 pF (3) 1.0 1.0 1.0 1.0 ns tCNT Minimum global clock period fCNT Maximum internal global clock frequency C1 = 35 pF 4.0 C1 = 35 pF 4.5 6.5 7.5 6.8 (4) 147.1 5.0 10.0 8.0 125.0 8.0 15.0 10.0 100.0 13.0 76.9 ns ns ns MHz tACNT Minimum array clock period fACNT Maximum internal array clock frequency (4) 147.1 125.0 100.0 76.9 MHz fMAX Maximum clock frequency (5) 166.7 166.7 125.0 100.0 MHz Altera Corporation 6.8 8.0 10.0 13.0 ns 41 MAX 7000 Programmable Logic Device Family Data Sheet Table 29. EPM7128S Internal Timing Parameters Symbol Parameter Note (1) Conditions Speed Grade -6 Min -7 Max Unit -10 Min Max Min -15 Max Min Max tIN Input pad and buffer delay 0.2 0.5 0.5 2.0 tIO I/O input pad and buffer delay 0.2 0.5 0.5 2.0 ns tFIN Fast input delay 2.6 1.0 1.0 2.0 ns tSEXP Shared expander delay 3.7 4.0 5.0 8.0 ns tPEXP Parallel expander delay 1.1 0.8 0.8 1.0 ns tLAD Logic array delay 3.0 3.0 5.0 6.0 ns tLAC Logic control array delay 3.0 3.0 5.0 6.0 ns tIOE Internal output enable delay 0.7 2.0 2.0 3.0 ns tOD1 Output buffer and pad delay C1 = 35 pF 0.4 2.0 1.5 4.0 ns tOD2 Output buffer and pad delay C1 = 35 pF (6) 0.9 2.5 2.0 5.0 ns tOD3 Output buffer and pad delay C1 = 35 pF 5.4 7.0 5.5 8.0 ns tZX1 Output buffer enable delay C1 = 35 pF 4.0 4.0 5.0 6.0 ns tZX2 Output buffer enable delay C1 = 35 pF (6) 4.5 4.5 5.5 7.0 ns tZX3 Output buffer enable delay C1 = 35 pF 9.0 9.0 9.0 10.0 ns tXZ Output buffer disable delay C1 = 5 pF 6.0 ns tSU Register setup time 1.0 3.0 2.0 4.0 ns tH Register hold time 1.7 2.0 5.0 4.0 ns tFSU Register setup time of fast input 1.9 3.0 3.0 2.0 ns tFH Register hold time of fast input 0.6 0.5 0.5 1.0 ns 4.0 4.0 5.0 ns tRD Register delay 1.4 1.0 2.0 1.0 ns tCOMB Combinatorial delay 1.0 1.0 2.0 1.0 ns tIC Array clock delay 3.1 3.0 5.0 6.0 ns tEN Register enable time 3.0 3.0 5.0 6.0 ns tGLOB Global control delay 2.0 1.0 1.0 1.0 ns tPRE Register preset time 2.4 2.0 3.0 4.0 ns tCLR Register clear time 2.4 2.0 3.0 4.0 ns tPIA PIA delay (7) 1.4 1.0 1.0 2.0 ns tLPA Low-power adder (8) 11.0 10.0 11.0 13.0 ns 42 Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet Notes to tables: (1) (2) (3) (4) (5) (6) (7) (8) These values are specified under the recommended operating conditions shown in Table 11. See Figure 13 for more information on switching waveforms. This minimum pulse width for preset and clear applies for both global clear and array controls. The tLPA parameter must be added to this minimum width if the clear or reset signal incorporates the tLAD parameter into the signal path. This parameter is a guideline that is sample-tested only and is based on extensive device characterization. This parameter applies for both global and array clocking. These parameters are measured with a 16-bit loadable, enabled, up/down counter programmed into each LAB. The fMAX values represent the highest frequency for pipelined data. Operating conditions: VCCIO = 3.3 V 10% for commercial and industrial use. For EPM7064S-5, EPM7064S-6, EPM7128S-6, EPM7160S-6, EPM7160S-7, EPM7192S-7, and EPM7256S-7 devices, these values are specified for a PIA fan-out of one LAB (16 macrocells). For each additional LAB fan-out in these devices, add an additional 0.1 ns to the PIA timing value. The tLPA parameter must be added to the tLAD, tLAC , tIC, tEN, tSEXP, tACL, and tCPPW parameters for macrocells running in the low-power mode. Tables 30 and 31 show the EPM7160S AC operating conditions. Table 30. EPM7160S External Timing Parameters (Part 1 of 2) Symbol Parameter Note (1) Conditions Speed Grade -6 -7 Unit -10 -15 Min Max Min Max Min Max Min Max tPD1 Input to non-registered output C1 = 35 pF 6.0 7.5 10.0 15.0 ns tPD2 I/O input to non-registered output C1 = 35 pF 6.0 7.5 10.0 15.0 ns tSU Global clock setup time 3.4 4.2 7.0 11.0 ns tH Global clock hold time 0.0 0.0 0.0 0.0 ns tFSU Global clock setup time of fast input 2.5 3.0 3.0 3.0 ns tFH Global clock hold time of fast input 0.0 0.0 0.5 0.0 ns tCO1 Global clock to output delay tCH Global clock high time 3.0 3.0 4.0 5.0 ns tCL Global clock low time 3.0 3.0 4.0 5.0 ns tASU Array clock setup time 0.9 1.1 2.0 4.0 ns tAH Array clock hold time 1.7 2.1 3.0 4.0 ns tACO1 Array clock to output delay tACH Array clock high time 3.0 3.0 4.0 6.0 ns tACL Array clock low time 3.0 3.0 4.0 6.0 ns tCPPW Minimum pulse width for clear and preset (2) 2.5 3.0 4.0 6.0 ns tODH Output data hold time after clock C1 = 35 pF (3) 1.0 1.0 1.0 1.0 ns tCNT Minimum global clock period fCNT Maximum internal global clock frequency Altera Corporation C1 = 35 pF 3.9 C1 = 35 pF 4.8 6.4 7.9 6.7 (4) 149.3 5 10.0 8.2 122.0 8 15.0 10.0 100.0 13.0 76.9 ns ns ns MHz 43 MAX 7000 Programmable Logic Device Family Data Sheet Table 30. EPM7160S External Timing Parameters (Part 2 of 2) Symbol Parameter Note (1) Conditions Speed Grade -6 -7 Unit -10 -15 Min Max Min Max Min Max Min Max tACNT Minimum array clock period fACNT Maximum internal array clock frequency (4) 149.3 6.7 122.0 100.0 76.9 MHz fMAX Maximum clock frequency (5) 166.7 166.7 125.0 100.0 MHz Table 31. EPM7160S Internal Timing Parameters (Part 1 of 2) Symbol Parameter 8.2 10.0 13.0 Note (1) Conditions Speed Grade -6 Min -7 Max ns Unit -10 Min Max Min -15 Max Min Max tIN Input pad and buffer delay 0.2 0.3 0.5 2.0 tIO I/O input pad and buffer delay 0.2 0.3 0.5 2.0 ns tFIN Fast input delay 2.6 3.2 1.0 2.0 ns tSEXP Shared expander delay 3.6 4.3 5.0 8.0 ns tPEXP Parallel expander delay 1.0 1.3 0.8 1.0 ns tLAD Logic array delay 2.8 3.4 5.0 6.0 ns tLAC Logic control array delay 2.8 3.4 5.0 6.0 ns tIOE Internal output enable delay 0.7 0.9 2.0 3.0 ns tOD1 Output buffer and pad delay C1 = 35 pF 0.4 0.5 1.5 4.0 ns tOD2 Output buffer and pad delay C1 = 35 pF (6) 0.9 1.0 2.0 5.0 ns tOD3 Output buffer and pad delay C1 = 35 pF 5.4 5.5 5.5 8.0 ns tZX1 Output buffer enable delay C1 = 35 pF 4.0 4.0 5.0 6.0 ns tZX2 Output buffer enable delay C1 = 35 pF (6) 4.5 4.5 5.5 7.0 ns tZX3 Output buffer enable delay C1 = 35 pF 9.0 9.0 9.0 10.0 ns tXZ Output buffer disable delay C1 = 5 pF 6.0 ns tSU Register setup time 1.0 1.2 2.0 4.0 ns tH Register hold time 1.6 2.0 3.0 4.0 ns tFSU Register setup time of fast input 1.9 2.2 3.0 2.0 ns tFH Register hold time of fast input 0.6 0.8 0.5 1.0 ns 4.0 4.0 5.0 ns tRD Register delay 1.3 1.6 2.0 1.0 ns tCOMB Combinatorial delay 1.0 1.3 2.0 1.0 ns tIC Array clock delay 2.9 3.5 5.0 6.0 ns tEN Register enable time 2.8 3.4 5.0 6.0 ns tGLOB Global control delay 2.0 2.4 1.0 1.0 ns 44 Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet Table 31. EPM7160S Internal Timing Parameters (Part 2 of 2) Symbol Parameter Note (1) Conditions Speed Grade -6 Min -7 Max Min Unit -10 Max -15 Min Max Min Max tPRE Register preset time 2.4 3.0 3.0 4.0 ns tCLR Register clear time 2.4 3.0 3.0 4.0 ns tPIA PIA delay (7) 1.6 2.0 1.0 2.0 ns tLPA Low-power adder (8) 11.0 10.0 11.0 13.0 ns Notes to tables: (1) (2) (3) (4) (5) (6) (7) (8) These values are specified under the recommended operating conditions shown in Table 11. See Figure 13 for more information on switching waveforms. This minimum pulse width for preset and clear applies for both global clear and array controls. The tLPA parameter must be added to this minimum width if the clear or reset signal incorporates the tLAD parameter into the signal path. This parameter is a guideline that is sample-tested only and is based on extensive device characterization. This parameter applies for both global and array clocking. These parameters are measured with a 16-bit loadable, enabled, up/down counter programmed into each LAB. The fMAX values represent the highest frequency for pipelined data. Operating conditions: VCCIO = 3.3 V 10% for commercial and industrial use. For EPM7064S-5, EPM7064S-6, EPM7128S-6, EPM7160S-6, EPM7160S-7, EPM7192S-7, and EPM7256S-7 devices, these values are specified for a PIA fan-out of one LAB (16 macrocells). For each additional LAB fan-out in these devices, add an additional 0.1 ns to the PIA timing value. The tLPA parameter must be added to the tLAD, tLAC , tIC, tEN, tSEXP, tACL, and tCPPW parameters for macrocells running in the low-power mode. Tables 32 and 33 show the EPM7192S AC operating conditions. Table 32. EPM7192S External Timing Parameters (Part 1 of 2) Symbol Parameter Note (1) Conditions Speed Grade -7 Min Unit -10 Max Min -15 Max Min Max tPD1 Input to non-registered output C1 = 35 pF 7.5 10.0 15.0 ns tPD2 I/O input to non-registered output C1 = 35 pF 7.5 10.0 15.0 ns tSU Global clock setup time 4.1 7.0 11.0 ns tH Global clock hold time 0.0 0.0 0.0 ns tFSU Global clock setup time of fast input 3.0 3.0 3.0 ns tFH Global clock hold time of fast input 0.0 0.5 0.0 ns tCO1 Global clock to output delay tCH Global clock high time Altera Corporation C1 = 35 pF 4.7 3.0 5.0 4.0 8.0 5.0 ns ns 45 MAX 7000 Programmable Logic Device Family Data Sheet Table 32. EPM7192S External Timing Parameters (Part 2 of 2) Symbol Parameter Note (1) Conditions Speed Grade -7 Min Unit -10 Max Min -15 Max Min Max tCL Global clock low time 3.0 4.0 5.0 tASU Array clock setup time 1.0 2.0 4.0 ns tAH Array clock hold time 1.8 3.0 4.0 ns tACO1 Array clock to output delay tACH Array clock high time 3.0 4.0 6.0 tACL Array clock low time 3.0 4.0 6.0 ns tCPPW Minimum pulse width for clear and preset (2) 3.0 4.0 6.0 ns tODH Output data hold time after clock C1 = 35 pF (3) 1.0 1.0 1.0 ns tCNT Minimum global clock period fCNT Maximum internal global clock frequency tACNT Minimum array clock period fACNT fMAX C1 = 35 pF 7.8 8.0 15.0 10.0 100.0 ns ns 13.0 125.0 Maximum internal array clock frequency (4) 125.0 100.0 76.9 MHz Maximum clock frequency (5) 166.7 125.0 100.0 MHz 8.0 Parameter 76.9 ns (4) Table 33. EPM7192S Internal Timing Parameters (Part 1 of 2) Symbol 10.0 ns 10.0 MHz 13.0 Note (1) Conditions Speed Grade -7 Min ns Unit -10 Max Min -15 Max Min Max tIN Input pad and buffer delay 0.3 0.5 2.0 tIO I/O input pad and buffer delay 0.3 0.5 2.0 ns tFIN Fast input delay 3.2 1.0 2.0 ns tSEXP Shared expander delay 4.2 5.0 8.0 ns tPEXP Parallel expander delay 1.2 0.8 1.0 ns tLAD Logic array delay 3.1 5.0 6.0 ns tLAC Logic control array delay 3.1 5.0 6.0 ns tIOE Internal output enable delay 0.9 2.0 3.0 ns tOD1 Output buffer and pad delay C1 = 35 pF 0.5 1.5 4.0 ns tOD2 Output buffer and pad delay C1 = 35 pF (6) 1.0 2.0 5.0 ns tOD3 Output buffer and pad delay C1 = 35 pF 5.5 5.5 7.0 ns tZX1 Output buffer enable delay C1 = 35 pF 4.0 5.0 6.0 ns tZX2 Output buffer enable delay C1 = 35 pF (6) 4.5 5.5 7.0 ns tZX3 Output buffer enable delay C1 = 35 pF 9.0 9.0 10.0 ns 46 ns Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet Table 33. EPM7192S Internal Timing Parameters (Part 2 of 2) Symbol Parameter Note (1) Conditions Speed Grade -7 Min C1 = 5 pF Unit -10 Max Min 4.0 -15 Max Min 5.0 Max tXZ Output buffer disable delay tSU Register setup time 1.1 2.0 4.0 6.0 ns ns tH Register hold time 1.7 3.0 4.0 ns tFSU Register setup time of fast input 2.3 3.0 2.0 ns tFH Register hold time of fast input 0.7 0.5 1.0 ns tRD Register delay 1.4 2.0 1.0 tCOMB Combinatorial delay 1.2 2.0 1.0 ns tIC Array clock delay 3.2 5.0 6.0 ns tEN Register enable time 3.1 5.0 6.0 ns tGLOB Global control delay 2.5 1.0 1.0 ns tPRE Register preset time 2.7 3.0 4.0 ns tCLR Register clear time 2.7 3.0 4.0 ns tPIA PIA delay (7) 2.4 1.0 2.0 ns tLPA Low-power adder (8) 10.0 11.0 13.0 ns ns Notes to tables: (1) (2) (3) (4) (5) (6) (7) (8) These values are specified under the recommended operating conditions shown in Table 11. See Figure 13 for more information on switching waveforms. This minimum pulse width for preset and clear applies for both global clear and array controls. The tLPA parameter must be added to this minimum width if the clear or reset signal incorporates the tLAD parameter into the signal path. This parameter is a guideline that is sample-tested only and is based on extensive device characterization. This parameter applies for both global and array clocking. These parameters are measured with a 16-bit loadable, enabled, up/down counter programmed into each LAB. The fMAX values represent the highest frequency for pipelined data. Operating conditions: VCCIO = 3.3 V 10% for commercial and industrial use. For EPM7064S-5, EPM7064S-6, EPM7128S-6, EPM7160S-6, EPM7160S-7, EPM7192S-7, and EPM7256S-7 devices, these values are specified for a PIA fan-out of one LAB (16 macrocells). For each additional LAB fan-out in these devices, add an additional 0.1 ns to the PIA timing value. The tLPA parameter must be added to the tLAD, tLAC , tIC, tEN, tSEXP, tACL, and tCPPW parameters for macrocells running in the low-power mode. Altera Corporation 47 MAX 7000 Programmable Logic Device Family Data Sheet Tables 34 and 35 show the EPM7256S AC operating conditions. Table 34. EPM7256S External Timing Parameters Symbol Parameter Note (1) Conditions Speed Grade -7 Min Unit -10 Max Min -15 Max Min Max tPD1 Input to non-registered output C1 = 35 pF 7.5 10.0 15.0 ns tPD2 I/O input to non-registered output C1 = 35 pF 7.5 10.0 15.0 ns tSU Global clock setup time 3.9 7.0 11.0 ns tH Global clock hold time 0.0 0.0 0.0 ns tFSU Global clock setup time of fast input 3.0 3.0 3.0 ns tFH Global clock hold time of fast input 0.0 0.5 0.0 ns tCO1 Global clock to output delay tCH Global clock high time 3.0 4.0 5.0 ns tCL Global clock low time 3.0 4.0 5.0 ns tASU Array clock setup time 0.8 2.0 4.0 ns tAH Array clock hold time 1.9 3.0 4.0 ns tACO1 Array clock to output delay tACH Array clock high time 3.0 4.0 6.0 tACL Array clock low time 3.0 4.0 6.0 ns tCPPW Minimum pulse width for clear and preset (2) 3.0 4.0 6.0 ns tODH Output data hold time after clock C1 = 35 pF (3) 1.0 1.0 1.0 ns tCNT Minimum global clock period fCNT Maximum internal global clock frequency tACNT Minimum array clock period fACNT fMAX 48 C1 = 35 pF 4.7 C1 = 35 pF 5.0 7.8 8.0 10.0 7.8 15.0 10.0 100.0 ns ns ns 13.0 128.2 Maximum internal array clock frequency (4) 128.2 100.0 76.9 MHz Maximum clock frequency (5) 166.7 125.0 100.0 MHz 7.8 76.9 ns (4) 10.0 MHz 13.0 ns Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet Table 35. EPM7256S Internal Timing Parameters Symbol Parameter Note (1) Conditions Speed Grade -7 Min Unit -10 Max Min -15 Max Min Max tIN Input pad and buffer delay 0.3 0.5 2.0 ns tIO I/O input pad and buffer delay 0.3 0.5 2.0 ns tFIN Fast input delay 3.4 1.0 2.0 ns tSEXP Shared expander delay 3.9 5.0 8.0 ns tPEXP Parallel expander delay 1.1 0.8 1.0 ns tLAD Logic array delay 2.6 5.0 6.0 ns tLAC Logic control array delay 2.6 5.0 6.0 ns tIOE Internal output enable delay 0.8 2.0 3.0 ns tOD1 Output buffer and pad delay C1 = 35 pF 0.5 1.5 4.0 ns tOD2 Output buffer and pad delay C1 = 35 pF (6) 1.0 2.0 5.0 ns tOD3 Output buffer and pad delay C1 = 35 pF 5.5 5.5 8.0 ns tZX1 Output buffer enable delay C1 = 35 pF 4.0 5.0 6.0 ns tZX2 Output buffer enable delay C1 = 35 pF (6) 4.5 5.5 7.0 ns tZX3 Output buffer enable delay C1 = 35 pF 9.0 9.0 10.0 ns tXZ Output buffer disable delay C1 = 5 pF 6.0 ns tSU Register setup time 1.1 2.0 4.0 ns tH Register hold time 1.6 3.0 4.0 ns tFSU Register setup time of fast input 2.4 3.0 2.0 ns tFH Register hold time of fast input 0.6 0.5 1.0 ns tRD Register delay 1.1 2.0 1.0 tCOMB Combinatorial delay 1.1 2.0 1.0 ns tIC Array clock delay 2.9 5.0 6.0 ns tEN Register enable time 2.6 5.0 6.0 ns tGLOB Global control delay 2.8 1.0 1.0 ns tPRE Register preset time 2.7 3.0 4.0 ns tCLR Register clear time 2.7 3.0 4.0 ns tPIA PIA delay (7) 3.0 1.0 2.0 ns tLPA Low-power adder (8) 10.0 11.0 13.0 ns Altera Corporation 4.0 5.0 ns 49 MAX 7000 Programmable Logic Device Family Data Sheet Notes to tables: (1) (2) (3) (4) (5) (6) (7) (8) These values are specified under the recommended operating conditions shown in Table 11. See Figure 13 for more information on switching waveforms. This minimum pulse width for preset and clear applies for both global clear and array controls. The tLPA parameter must be added to this minimum width if the clear or reset signal incorporates the tLAD parameter into the signal path. This parameter is a guideline that is sample-tested only and is based on extensive device characterization. This parameter applies for both global and array clocking. These parameters are measured with a 16-bit loadable, enabled, up/down counter programmed into each LAB. The fMAX values represent the highest frequency for pipelined data. Operating conditions: V CCIO = 3.3 V 10% for commercial and industrial use. For EPM7064S-5, EPM7064S-6, EPM7128S-6, EPM7160S-6, EPM7160S-7, EPM7192S-7, and EPM7256S-7 devices, these values are specified for a PIA fan-out of one LAB (16 macrocells). For each additional LAB fan-out in these devices, add an additional 0.1 ns to the PIA timing value. The tLPA parameter must be added to the tLAD , tLAC, tIC, tEN, tSEXP, tACL, and tCPPW parameters for macrocells running in the low-power mode. Power Consumption Supply power (P) versus frequency (fMAX in MHz) for MAX 7000 devices is calculated with the following equation: P = PINT + PIO = ICCINT x VCC + PIO The PIO value, which depends on the device output load characteristics and switching frequency, can be calculated using the guidelines given in Application Note 74 (Evaluating Power for Altera Devices). The ICCINT value, which depends on the switching frequency and the application logic, is calculated with the following equation: ICCINT = A x MCTON + B x (MCDEV - MCTON) + C x MCUSED x fMAX x togLC The parameters in this equation are shown below: MCTON MCDEV MCUSED fMAX togLC A, B, C 50 = Number of macrocells with the Turbo Bit option turned on, as reported in the MAX+PLUS II Report File (.rpt) = Number of macrocells in the device = Total number of macrocells in the design, as reported in the MAX+PLUS II Report File (.rpt) = Highest clock frequency to the device = Average ratio of logic cells toggling at each clock (typically 0.125) = Constants, shown in Table 36 Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet Table 36. MAX 7000 ICC Equation Constants Device A B C EPM7032 1.87 0.52 0.144 EPM7064 1.63 0.74 0.144 EPM7096 1.63 0.74 0.144 EPM7128E 1.17 0.54 0.096 EPM7160E 1.17 0.54 0.096 EPM7192E 1.17 0.54 0.096 EPM7256E 1.17 0.54 0.096 EPM7032S 0.93 0.40 0.040 EPM7064S 0.93 0.40 0.040 EPM7128S 0.93 0.40 0.040 EPM7160S 0.93 0.40 0.040 EPM7192S 0.93 0.40 0.040 EPM7256S 0.93 0.40 0.040 This calculation provides an ICC estimate based on typical conditions using a pattern of a 16-bit, loadable, enabled, up/down counter in each LAB with no output load. Actual ICC values should be verified during operation because this measurement is sensitive to the actual pattern in the device and the environmental operating conditions. Altera Corporation 51 MAX 7000 Programmable Logic Device Family Data Sheet Figure 14 shows typical supply current versus frequency for MAX 7000 devices. Figure 14. ICC vs. Frequency for MAX 7000 Devices (Part 1 of 2) EPM7064 EPM7032 180 VCC = 5.0 V Room Temperature 300 VCC = 5.0 V Room Temperature 151.5 MHz 151.5 MHz 140 High Speed 200 Typical ICC Active (mA) High Speed 100 Typical ICC Active (mA) 60.2 MHz 100 60 60.2 MHz Low Power 20 0 Low Power 50 100 150 200 0 50 100 150 200 Frequency (MHz) Frequency (MHz) EPM7096 450 VCC = 5.0 V Room Temperature 125 MHz 350 High Speed Typical ICC Active (mA) 250 55.5 MHz 150 Low Power 50 0 50 100 150 Frequency (MHz) 52 Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet Figure 14. ICC vs. Frequency for MAX 7000 Devices (Part 2 of 2) EPM7128E EPM7160E 500 500 VCC = 5.0 V Room Temperature VCC = 5.0 V Room Temperature 400 400 100 MHz 125 MHz Typical ICC Active (mA) Typical ICC Active (mA) 300 300 High Speed High Speed 200 200 47.6 MHz 55.5 MHz 100 100 Low Power 50 0 Low Power 100 150 0 200 50 EPM7192E 150 200 EPM7256E 500 750 VCC = 5.0 V Room Temperature VCC = 5.0 V Room Temperature 90.9 MHz 400 Typical ICC Active (mA) 100 Frequency (MHz) Frequency (MHz) 600 300 High Speed 43.5 MHz 200 25 50 High Speed 43.4 MHz 150 75 100 Frequency (MHz) Altera Corporation 450 300 Low Power 100 0 Typical ICC Active (mA) 90.9 MHz 125 0 Low Power 25 50 75 100 125 Frequency (MHz) 53 MAX 7000 Programmable Logic Device Family Data Sheet Figure 15 shows typical supply current versus frequency for MAX 7000S devices. Figure 15. ICC vs. Frequency for MAX 7000S Devices (Part 1 of 2) EPM7032S EPM7064S VCC = 5.0 V Room Temperature 60 142.9 MHz 50 Typical ICC Active (mA) 40 VCC = 5.0 V Room Temperature 120 175.4 MHz 100 Typical ICC Active (mA) High Speed 30 80 High Speed 60 58.8 MHz 20 Low Power 10 0 50 56.5 MHz 40 100 Low Power 20 150 0 200 50 Frequency (MHz) 100 150 200 Frequency (MHz) EPM7160S EPM7128S VCC = 5.0 V Room Temperature 280 VCC = 5.0 V Room Temperature 300 149.3 MHz 240 240 147.1 MHz 200 Typical ICC Active (mA) 160 Typical ICC Active (mA) High Speed High Speed 180 120 120 Low Power 40 0 50 100 60 150 Frequency (MHz) 54 56.5 MHz 56.2 MHz 80 200 Low Power 0 50 100 150 200 Frequency (MHz) Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet Figure 15. ICC vs. Frequency for MAX 7000S Devices (Part 2 of 2) EPM7256S EPM7192S VCC = 5.0 V Room Temperature 300 VCC = 5.0 V Room Temperature 400 128.2 MHz 125.0 MHz 240 Typical ICC Active (mA) High Speed 180 High Speed 300 Typical ICC Active (mA) 200 56.2 MHz 55.6 MHz 120 Low Power Low Power 100 60 0 25 50 75 100 Frequency (MHz) Device Pin-Outs Altera Corporation 125 0 25 50 75 100 125 Frequency (MHz) See the Altera web site (http://www.altera.com) or the Altera Digital Library for pin-out information. 55 MAX 7000 Programmable Logic Device Family Data Sheet Figures 16 through 22 show the package pin-out diagrams for MAX 7000 devices. Figure 16. 44-Pin Package Pin-Out Diagram I/O I/O 1 44 43 42 41 40 GND 2 INPUT/GCLK1 3 INPUT/OE1 INPUT/OE2/(GCLK2) (1) 5 4 INPUT/GCLRn 6 VCC I/O I/O Pin 34 I/O I/O I/O GND INPUT//GCLK1 INPUT/OE1 INPUT/GCLRn INPUT/OE2/(GCLK2) (1) VCC I/O I/O Pin 1 I/O Package outlines not drawn to scale. (2) I/O /(TDI) 7 39 I/O I/O/(TDO) (2) I/O 8 38 I/O/(TDO) (2) I/O I/O I/O 9 37 I/O GND I/O GND 10 36 I/O I/O 11 35 VCC I/O 12 34 I/O (2) I/O/(TMS) 13 33 I/O I/O 14 32 I/O/(TCK) (2) 31 I/O (2) I/O/(TDI) I/O I/O I/O VCC I/O I/O EPM7032 (2) I/O/(TMS) I/O I/O/(TCK) (2) I/O EPM7032 EPM7032S EPM7064 EPM7064S VCC 15 I/O I/O 16 30 GND I/O GND I/O 17 29 I/O I/O I/O VCC I/O I/O I/O I/O I/O VCC GND I/O I/O Pin 23 I/O I/O I/O I/O I/O I/O I/O VCC GND I/O I/O I/O Pin 12 I/O 18 19 20 21 22 23 24 25 26 27 28 44-Pin PLCC I/O I/O GND INPUT/GCLK1 INPUT/OE1 INPUT/GCLRn INPUT/OE2/(GCLK2) (1) VCC I/O I/O Pin 1 I/O 44-Pin PQFP (2) I/O /(TDI) Pin 34 I/O I/O I/O/(TDO) (2) I/O I/O GND I/O EPM7032 EPM7032S EPM7064 EPM7064S I/O I/O (2) I/O /(TMS) I/O VCC I/O I/O I/O/(TCK) (2) I/O VCC I/O I/O I/O I/O I/O VCC GND I/O Pin 12 I/O I/O I/O GND I/O I/O I/O Pin 23 44-Pin TQFP Notes: (1) (2) 56 The pin functions shown in parenthesis are only available in MAX 7000E and MAX 7000S devices. JTAG ports are available in MAX 7000S devices only. Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet Figure 17. 68-Pin Package Pin-Out Diagram 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 I/O I/O I/O GND I/O I/O VCCINT INPUT/OE2/(GCLK2) (1) INPUT/GCLRn INPUT/OE1 INPUT/GCLK1 GND I/O I/O VCCIO I/O I/O Package outlines not drawn to scale. 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 EPM7064 EPM7096 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 I/O I/O GND I/O/(TDO) (2) I/O I/O I/O VCCIO I/O I/O I/O/(TCK) (2) I/O GND I/O I/O I/O I/O I/O I/O I/O I/O VCCIO I/O I/O GND VCCINT I/O I/O GND I/O I/O I/O I/O VCCIO 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 I/O VCCIO (2) I/O/(TDI) I/O I/O I/O GND I/O I/O (2) I/O/(TMS) I/O VCCIO I/O I/O I/O I/O GND 68-Pin PLCC Notes: (1) (2) Altera Corporation The pin functions shown in parenthesis are only available in MAX 7000E and MAX 7000S devices. JTAG ports are available in MAX 7000S devices only. 57 MAX 7000 Programmable Logic Device Family Data Sheet Figure 18. 84-Pin Package Pin-Out Diagram 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 I/O I/O I/O I/O GND I/O (1) I/O I/O VCCINT INPUT/OE2/(GCLK2) (2) INPUT/GLCRn INPUT/OE1 INPUT/GCLK1 GND I/O I/O I/O (1) VCCIO I/O I/O I/O Package outline not drawn to scale. I/O VCCIO (3) I/O/(TDI) EPM7064 EPM7064S EPM7096 EPM7128E EPM7128S EPM7160E EPM7160S 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 I/O I/O GND I/O/(TDO) (3) I/O I/O I/O I/O VCCIO I/O I/O I/O I/O/(TCK) (3) I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCIO I/O (1) I/O I/O GND VCCINT I/O I/O I/O (1) GND I/O I/O I/O I/O I/O VCCIO 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 I/O I/O I/O I/O GND I/O I/O I/O (3) I/O/(TMS) I/O I/O VCCIO I/O I/O I/O I/O I/O GND 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 84-Pin PLCC Notes: (1) (2) (3) 58 Pins 6, 39, 46, and 79 are no-connect (N.C.) pins on EPM7096, EPM7160E, and EPM7160S devices. The pin functions shown in parenthesis are only available in MAX 7000E and MAX 7000S devices. JTAG ports are available in MAX 7000S devices only. Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet Figure 19. 100-Pin Package Pin-Out Diagram Package outline not drawn to scale. Pin 1 Pin 81 Pin 1 Pin 76 EPM7064S EPM7128S EPM7160S EPM7064 EPM7096 EPM7128E EPM7128S EPM7160E Pin 31 Pin 51 Pin 26 100-Pin PQFP Pin 51 100-Pin TQFP Figure 20. 160-Pin Package Pin-Out Diagram Package outline not drawn to scale. Pin 121 Pin 1 R P N M L K J EPM7192E H Bottom View G EPM7128E EPM7128S EPM7160E EPM7160S EPM7192E EPM7192S EPM7256E F E D C B A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 160-Pin PGA Altera Corporation Pin 81 Pin 41 160-Pin PQFP 59 MAX 7000 Programmable Logic Device Family Data Sheet Figure 21. 192-Pin Package Pin-Out Diagram Package outline not drawn to scale. U T R P N M L K EPM7256E J Bottom View H G F E D C B A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 192-Pin PGA Figure 22. 208-Pin Package Pin-Out Diagram Package outline not drawn to scale. Pin 1 Pin 157 EPM7256E EPM7256S Pin 53 Pin 105 208-Pin PQFP/RQFP 60 Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet Revision History The information contained in the MAX 7000 Programmable Logic Device Family Data Sheet version 6.5 supersedes information published in previous versions. The following changes were made in the MAX 7000 Programmable Logic Device Family Data Sheet version 6.5: Version 6.5 The following changes were made in the MAX 7000 Programmable Logic Device Family Data Sheet version 6.5: Updated text on page 16. Version 6.4 The following changes were made in the MAX 7000 Programmable Logic Device Family Data Sheet version 6.4: Added Note (5) on page 25. Version 6.3 The following changes were made in the MAX 7000 Programmable Logic Device Family Data Sheet version 6.3: Altera Corporation Updated the "Open-Drain Output Option (MAX 7000S Devices Only)" section on page 18. 61 MAX 7000 Programmable Logic Device Family Data Sheet 101 Innovation Drive San Jose, CA 95134 (408) 544-7000 http://www.altera.com Applications Hotline: (800) 800-EPLD Customer Marketing: (408) 544-7104 Literature Services: lit_req@altera.com 62 Copyright (c) 2002 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Altera products are protected under numerous U.S. and foreign patents and pending applications, maskwork rights, and copyrights. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera Corporation. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services Altera Corporation