1
32 x 32 1.5 GBIT/S DIFFERENTIAL CROSSPOINT SWITCH S2025
June 24, 1999 / Revision B
®
Figure 1. Functional Block Diagram
FEATURES
• 32 x 32 differential crosspoint switch
• Full broadcast switching capability
• Differential 10K PECL data path
• Configurable differential output driver
enables
• Up to 1.5 Gbit/s NRZ data rate
• TTL configuration controls
• Reconfigurable without disturbing operation
• 196-pin LDCC package
APPLICATIONS
• Internet switches
• Digital video
• Digital demultiplexing
• Microwave or fiber-optic data distribution
• High-speed automatic test equipment
• Datacom or telecom switching
GENERAL DESCRIPTION
The S2025 is a very high-speed 32 x 32 differential
crosspoint switch with full broadcast capability. Any of its
32 differential PECL input signal pairs can be connected
to any or all of its 32 differential PECL output signal pairs.
In addition, the S2025 includes configurable differential
output driver enables that allow it to be expanded to
larger differential crosspoint switch structures.
The differential 10K PECL logic data path makes the
part ideal for high-speed applications. The differential
nature of the data path is retained throughout the
crosspoint structure, to minimize data distortion and to
handle NRZ data rates up to 1.5 gigabits per second.
TTL configuration controls simplify interfacing to slower
speed circuitry. Once a new configuration has been
entered into the configuration register file, the S2025
can be completely reconfigured in only 6 ns without
disturbing switch operations.
PECL
Diff.
Input
Buffers
PECL
Diff.
Output
Buffers
32 x 32
Differential
Crosspoint
64 64
DIN00P
DIN31P
DOUT00P
DOUT31P
Active Configuration Latch
160 32
32 x 6
Configuration
Register File
192 RESETN
IADDR
DATA
32
5:32
Decode
EN
CONFIGN
LOADN
OADDRØ-
4
IADDRØ-
5
5
Output
Enables
SELECT
DOUT00N
DOUT31N
DIN00N
DIN31N
IA Register IACLK
OA
Reg
OADDR
OACLK
6
32 x 32 1.5 GBIT/S DIFFERENTIAL CROSSPOINT SWITCH S2025
DEVICE SPECIFICATION
2
32 x 32 1.5 GBIT/S DIFFERENTIAL CROSSPOINT SWITCH
S2025
June 24, 1999 / Revision B
DATA TRANSFER
For each configured connection between a differential
input pair and an enabled output pair, any data appear-
ing at the input pair will be passed immediately through
to the output pair.
RECONFIGURATION
The S2025 can be selectively reconfigured one output
pair at a time, or any number of output pairs can be
reconfigured simultaneously. Configuration data is
stored in 32 registers, one register for each output pair.
As shown in Figure 1, the configuration data is passed
in parallel from all 32 registers to a latch which holds the
active switch configuration. This two-stage arrange-
ment allows one or more output pairs to be reconfigured
simultaneously.
Each configuration register in the configuration Regis-
ter File (CRF) holds 6 bits. Five bits are used to select
which input pair will be connected to the output pair and
one bit is used to enable or disable the output pair driver.
To connect an output pair to a given input pair, the
output pair to be reconfigured is selected using bits
OADDR0-4 of the OA register. These bits are set using the
OADDR and OACLK inputs. The OACLK input, with 100
MHz maximum frequency, can load the OA shift register
through the OADDR input, with the OADDR4 (MSB)
entering first, followed by the OADDR3, and so on. With
the configuration register selected, the desired input
selection is provided on the bits IADDR0-4 of the IA
register. Whether or not the output pair is to be enabled
is provided on the bit IADDR5 (1= enable, 0 = disable)
of the same register. The bits IADDR0-5 are set using
the IADDR and IACLK inputs. The IACLK input, with
100 MHz maximum frequency, can load the IA shift
register through the IADDR input, with the IADDR5
entering first, followed by the IADDR4 (MSB), and so
on. The IADDR0-5 information will be stored into the
selected configuration register by the LOADN strobe.
When the differential switch is to be reconfigured, the
S2025 minimizes the time required through the use of an
active configuration latch. While the switch is operational,
and prior to the time at which it must be reconfigured, a
new configuration can be loaded into the output pair
configuration registers. Once the 32 output pair configu-
ration registers contain the desired connection and
output pair driver enable information, the contents of the
registers are transferred in parallel to the active configu-
ration latch by the CONFIGN strobe. This allows multiple
connections to be simultaneously changed.
The configuration latch can be made transparent by
tying the CONFIGN input to a logic 0. When this is done,
changes strobed into the output pair configuration reg-
isters by the LOADN input pair will be passed immediately
to the switch.
Figure 2. Data Transfer Waveforms
tCFDO
tLDDO
tDIDO
DIMPW
DINO-31 P/N
DOUTO-31 P/N
CONFIGN
LOADN
A
AB CD E
BCDE
3
32 x 32 1.5 GBIT/S DIFFERENTIAL CROSSPOINT SWITCH S2025
June 24, 1999 / Revision B
tSUIAD tHIAD tSUOAD tHOAD
IACLK
IADDR
OACLK
OADDR
12 123456
tSUIAC
tSULC
tHIAC
LDMPW
CFMPW
IACLK
IADDR0-5
LOADN
CONFIGN
Figure 3. Reconfiguration Waveforms
c. Clock Timing
b. Output Address Register
a. Input Address Register
12 12345
tSUOAC
tSULC
tHOAC
LDMPW
CFMPW
OACLK
OADDR0-4
LOADN
CONFIGN
4
32 x 32 1.5 GBIT/S DIFFERENTIAL CROSSPOINT SWITCH
S2025
June 24, 1999 / Revision B
Reset Behavior
When the RESETN input pair is asserted, the S2025
assumes a configuration where all the differential out-
put drivers are disabled. Individual output drivers then
remain disabled until they are explicitly reconfigured to
be enabled.
Table 2. Reconfiguration Timing
2
Symbol Description Min. Max. Units
ns2
1
1
2
1
ns
ns
ns
ns
ns
tSUIAD
tHIAD
tSUIAC
tHIAC
tSULC
LDMPW
Setup time of IADDR before rising edge of IACLK
Hold time of IADDR after rising edge of IACLK
Setup time of IACLK before falling edge of LOADN
Setup time of LOADN to CONFIGN so that the falling
edge of CONFIGN will start reconfiguration
Hold time of IACLK after rising edge of LOADN
ns2
1
2
2
ns
ns
ns
tSUOAD
tHOAD
tSUOAC
tHOAC
Setup time of OADDR before rising edge of OACLK
Hold time of OADDR after rising edge of OACLK
Setup time of OACLK before falling edge of LOADN
Hold time of OACLK after rising edge of LOADN
Pulse width low of LOADN
ns
4.5
4.5
CFMPW Pulse width low of CONFIGN
MHz100
FMAX IACLK, OACLK maximum frequency
1. All timing measured from the VCC -1.3V point on the signals.
2. All timing measured from the 1.5V point on the signals.
Table 1. Data Transfer Timing
1
Symbol Description Min. Max. Units
ns
ns
ns
ns
Mbit/s
0.650
3
6
8
1500
tDIDO
tCFDO
tLDDO
DIMPW
FMAX
Propagation delay from DIN0–31 P/N to DOUT0–31 P/N
Propagation delay from falling edge of CONFIGN to
DOUT0–31 P/N valid
Propagation delay from falling edge of LOADN to
DOUT0–31 P/N valid (When CONFIGN is held low)
Pulse width of DIN0–31 P/N
Data rate
5
32 x 32 1.5 GBIT/S DIFFERENTIAL CROSSPOINT SWITCH S2025
June 24, 1999 / Revision B
Table 3. S2025 Pin Assignment and Descriptions
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P13NID N13NID P03NID N03NID P92NID N92NID P82NID N82NID P72NID N72NID P62NID N62NID P52NID N52NID P42NID N42NID P32NID N32NID P22NID N22NID P12NID N12NID P02NID N02NID P91NID N91NID P81NID N81NID P71NID N71NID P61NID N61NID P51NID N51NID
DNIP41 N41NID
DNIP31 N31NID
DNIP21 N21NID
DNIP11 N11NID
DNIP01 N01NID
DNIP9N9NID
DNIP8N8NID
DNIP7N7NID
DNIP6N6NID
.ffiD LCEP tupnI sriaP 99 001 5484 101 301 3444 401 701 2414 501 011 9373 601 111 8333 901 511 1363 611 211 9223 811 711 3203 121 911 7212 721 521 0291 921 821 8151 431 031 3141 731 131 2111
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6
32 x 32 1.5 GBIT/S DIFFERENTIAL CROSSPOINT SWITCH
S2025
June 24, 1999 / Revision B
Table 3. S2025 Pin Assignment and Descriptions (continued)
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P5NID N5NID P4NID N4NID P3NID N3NID P2NID N2NID P1NID N1NID P0NID N0NID
.ffiD LCEP I041 1419
8341 2416
7641 5413
5
sadesuebnacstupnilaitnereffiD.atadtupniLCEPlaitnereffiD hcaefoedisenootdeitBBVhtiwstupnidedne-elgnis .riaptupnilaitnereffid
RDDAOLTTI 061retsigeRtfihSsserddAtuptuOehtottupniatadlaireS
KLCAOLTTI 181foegdegnisirehtnodedaolsiretsigeRtfihSsserddAtuptuO .KLCAO
RDDAILTTI68.retsigeRtfihSsserddAtupnIehtottupniatadlaireS =0,elbane=1(tibelbanereffubtuptuoehtsi5RDDAI .)elbasid
KLCAILTTI56foegdegnisirehtnodedaolsiretsigeRtfihSsserddAtupnI .KLCAI
NDAOLLTTI 531noitarugifnocehtserots,wolnehW.woLevitca,ebortsdaoL .elifretsigernoitarugifnocehtotniretsigerAIniatad
NGIFNOCLTTI 931ehtsdaollellarap,wolnehW.woLevitca,ebortsnoitarugifnoC evitcaehtotnielifretsigernoitarugifnocehtfostnetnoc .hctalnoitarugifnoc
NTESERLTTI 631ehtnistibelbanetuptuoehtllasteseR.woLevitcA.teseR .hctalnoitarugifnocevitcaehtnidnaelifretsigernoitarugifnoc
P13TUOD N13TUOD P03TUOD N03TUOD P92TUOD N92TUOD P82TUOD N82TUOD P72TUOD N72TUOD P62TUOD N62TUOD
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7
32 x 32 1.5 GBIT/S DIFFERENTIAL CROSSPOINT SWITCH S2025
June 24, 1999 / Revision B
Table 3. S2025 Pin Assignment and Descriptions (continued)
emaNniPleveLO/I#niPnoitpircseD
P52TUOD N52TUOD P42TUOD N42TUOD P32TUOD N32TUOD P22TUOD N22TUOD P12TUOD N12TUOD P02TUOD N02TUOD P91TUOD N91TUOD P81TUOD N81TUOD P71TUOD N71TUOD P61TUOD N61TUOD P51TUOD N51TUOD P41TUOD N41TUOD P31TUOD N31TUOD P21TUOD N21TUOD P11TUOD N11TUOD P01TUOD N01TUOD P9TUOD N9TUOD P8TUOD N8TUOD P7TUOD N7TUOD P6TUOD N6TUOD P5TUOD N5TUOD P4TUOD N4TUOD P3TUOD N3TUOD P2TUOD N2TUOD P1TUOD N1TUOD P0TUOD N0TUOD
.ffiD LCEP O9787077786276696462695168575556525457494
1
2491 291 091 191 881 981 581 781 381 481 971 081 671 771 961 571 471 761 661 461 361 161 751 951 651 551 451 251 351 051
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8
32 x 32 1.5 GBIT/S DIFFERENTIAL CROSSPOINT SWITCH
S2025
June 24, 1999 / Revision B
Table 3. S2025 Pin Assignment and Descriptions (continued)
emaNniPleveLO/I#niPnoitpircseD
CCVV5+– ,61,01,4 ,82,22 ,04,43 ,15,64 ,06,35 ,17,76 ,18,47 ,59,88 ,201,79 ,411,801 ,621,021 ,831,231 ,941,441 ,851,151 ,861,561 ,871,271 ,391,681 591
seilppuSrewoPO/ILCEdnaeroC
DNGLTTDNG– ,89,05 691,841 dnuorGLTT
DNGLCEDNG– ,42,71 ,62,52 ,36,53 ,57,37 ,48,67 ,221,311 ,421,321 ,261,331 ,171,071 281,371
dnuorGeroC
9
32 x 32 1.5 GBIT/S DIFFERENTIAL CROSSPOINT SWITCH S2025
June 24, 1999 / Revision B
DIN1P
VCC
DIN7P
LOADN
ECLGND
DIN7N
VCC
ECLGND
ECLGND
DIN17P
DIN21N
DIN25P
VCC
DIN31P
THDIODE
DIN1N
VCC
DIN3P
DIN3N
DIN5N
DIN5P
CONFIGN
RESETN
DIN9P
VCC
DIN9N
DIN11P
DIN11N
DIN13P
DIN13N
ECLGND
DIN15P
VCC
DIN15N
DIN17N
DIN19P
DOUT15N
DIN0P
DIN0N
DIN2P
DIN4N
VCC
DIN6N
DIN6P
DIN8P
DIN8N
DIN10N
VCC
DIN12N
DIN14N
VCC
ECLGND
ECLGND
DIN14P
VCC
DIN16N
DIN20P
DIN22N
VCC
ECLGND
DIN20N
DIN22P
DIN24P
DOUT30P
DOUT30N
DOUT29N
DOUT28N
DOUT29P
DOUT28P
DOUT27P
ECLGND
DOUT27N
DOUT26P
DOUT26N
DOUT25P
DOUT25N
DOUT24N
ECLGND
ECLGND
ECLGND
DOUT23N
VCC
DOUT24P
DOUT23P
IACLK
DOUT21P
ECLGND
DOUT21N
DOUT20N
VCC
DOUT20P
DOUT19P
DOUT19N
DOUT18P
DOUT17N
DOUT17P
VCC
OADDR
DOUT4N
ECLGND
DOUT4P
DOUT5P
VCC
DOUT7P
ECLGND
ECLGND
ECLGND
DOUT6P
DOUT7N
DOUT8P
DOUT8N
VCC
DOUT9P
DOUT9N
OACLK
ECLGND
DOUT11P
DOUT10P
VCC
DOUT11N
DOUT12N
DOUT13P
DOUT13N
DOUT14N
VCC
DOUT14P
TTLGND
VCC
DOUT12P
DOUT10N
VCC
DOUT6N
VCC
DOUT5N
DOUT2P
DOUT1P
DOUT0N
VCC
TTLGND
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
VCC
ECLGND
DIN19N
DIN23N
DIN25N
DIN21P
VCC
DIN27N
DIN23P
DIN27P
DIN29N
DIN29P
DIN31N
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40 DIN26N
DIN26P
DIN28P
DIN28N
DIN30P
VCC
DOUT16P
DOUT16N
DIN30N
VCC
DIN24N
DIN18N
DIN18P
ECLGND
DIN16P
DIN12P
DIN10P
ECLGND
DIN4P
DIN2N
VCC
DOUT15P
41
42
43
44
45
46
47
48
49
93
92
91
90
89
88
87
86
85
84
83
82
VCC
IADDR
VCC
VCC
DOUT22N
VCC
DOUT22P
DOUT18N
VCC
TTLGND
TTLGND
DOUT31P
VCC
DOUT31N
98
97
96
95
94
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
160
161
162
163
164
165
166
167
168
169
170
171
VCC
DOUT1N
DOUT0P
DOUT2N
DOUT3P
VCC
DOUT3N
148
149
150
151
152
153
154
155
156
157
158
159
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
S2025 Pinout
Top View
196-pin LDCC
VCC
Figure 4. S2025 Pinout
10
32 x 32 1.5 GBIT/S DIFFERENTIAL CROSSPOINT SWITCH
S2025
June 24, 1999 / Revision B
Figure 5. 196-Pin LDCC Package
1
49
50
98
99
147
148 196
.290 min
.025 ± .002
.008 ± .002
Non-conductive Tie-bar*
1.350 ±.010
.105 ±.010
.045 ± .005
1.550
± .015
.055 ± .010
COPLANAR TO .004
TOP
TOP VIEW
All dimensions nominal in inches.
* Trim non-conductive tie-bar prior to board attachment
Thermal Management
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o
W/C
Θaj tneibmaotnoitcnujmorfecnatsiserlamrehTriallitS6.52
o
W/C
Θaj knistaehhtiwtneibmaotnoitcnujmorfecnatsiserlamrehT 008 MPFL 35.3
o
W/C
Note: S2025 requires an AMCC heatsink 45-17 with an airflow of 800 LFPM for operation over commercial temperatures.
11
32 x 32 1.5 GBIT/S DIFFERENTIAL CROSSPOINT SWITCH S2025
June 24, 1999 / Revision B
Figure 6. AMCC Heat Sink 45-17
12
32 x 32 1.5 GBIT/S DIFFERENTIAL CROSSPOINT SWITCH
S2025
June 24, 1999 / Revision B
THERMAL MANAGEMENT GUIDELINES
Because of the relatively high power dissipation of the
S2025 device, thermal management is a key design
consideration. The junction temperature (Tj) of the
device must not exceed 150°C for it to operate within its
specifications. There are a number of ways to imple-
ment thermal management, depending upon the system
requirements and applications. AMCC is offering the
following two methods as guidelines to ensure proper
operation of the S2025.
1. Convection—Heat Sink with Forced Air Flow
AMCC offers the standard heat sink 45–17 for
impingement cooling (air flow forced directly to the
face of the heat sink). This method is similar to the
fan/heat-sink devices used on new, high-perfor-
mance, and high-power microprocessors. The
dimensions of the heat sink are given in Figure 6.
Considering the junction-to-case, and case-to-
ambient thermal resistivities, one can estimate the
amount of required air flow and the maximum
ambient temperature (Ta) in order to keep the Tj
below the critical limit of 150°C. Table 4 lists these
values for 45-17 and 45-24 heat sinks when Tj =
150°C.
2. Conduction—Liquid Cooling Methods
Passive cooling schemes, such as Aavid
Engineering’s Oasis technology may also be used
to ensure low junction temperature. Oasis uses
Flourinert, a liquid that boils around 57°C, to transfer
heat from the hot device to a condenser, where the
vaporized Flourinert is cooled, becomes liquid again,
and returns to the hot device. The S2025 case
temperature would not exceed 57°C, as long as the
cooling system is functioning properly. In such
case, using the following equation, one could calcu-
late the maximum anticipated Tj to be around 85°C.
Tj = Tc + (Pd x 2)
(Tc is the case temperature in °C, and
Pd is the dissipated power in Watts.)
For more information on Oasis technology, please
contact: Aavid Engineering Incorporated
Oasis Products Group
One Kool Path/P.O. Box 400
Laconia, NH 03247-0400
Tel: 603/528-3400
FAX: 603/528-1478
Table 4. Maximum Ambient Temperatures
T
a
)xam(C˚ )71-54S/H( )MPFL(wolFriA
03002
05004
06006
07008
13
32 x 32 1.5 GBIT/S DIFFERENTIAL CROSSPOINT SWITCH S2025
June 24, 1999 / Revision B
Table 6. Recommended Operating Conditions
Parameter Min Nom Max Units
Supply Voltage VCC 4.75 5.0 5.25 V
Ambient Temperature 0 70 °C
Junction Temperature 150 °C
ICC 1950 2600 mA
Table 5. Absolute Maximum Ratings
Supply Voltage VCC 7.0V
PECL Input Voltage VCC – 2.5V to VCC
PECL Output Source Current (continuous) -50mA DC
TTL Input Voltage 5.5V
Operating Junction Temperature Tj+150°C
Storage Temperature -65°C to +150°C
1. Typical limits are at 25°C, VCC = 5.0V.
2. These input levels provide a zero noise immunity and should only be tested in a static, noise-free environment.
Symbol Parameter Conditions Min MaxTyp
2
Unit
Commercial 0° to 70°C
VIH
1
VIL
1
VIK
IIH
IIL
II
Input HIGH Voltage
Input LOW Voltage
Input HIGH Current
Input LOW Current
Guaranteed Input HIGH Voltage
for all input pairs
VCC = MIN, IIN = -18 mA
VCC = MAX, VIN = 2.7V
VCC = MAX,VIN = 0.5V
2.0
-0.8
50
V
V
V
µA
mA
Input HIGH Current at
Max.
Input Clamp Diode
Voltage
VCC = MAX, VIN =VCC + 0.3V mA
Guaranteed Input LOW Voltage
for all input pairs 0.8
1
-1.2
-0.4
Table 7. TTL Input DC Characteristics
14
32 x 32 1.5 GBIT/S DIFFERENTIAL CROSSPOINT SWITCH
S2025
June 24, 1999 / Revision B
Figure 7. Differential Input Voltage
Table 8. PECL DC Characteristics
3
Table 9. Differential PECL Characteristics
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V
HI 2
V
CC
5411–V
CC
006–Vm
V
LI 2
V
CC
0002–V
CC
0041–Vm
V
SAIB 2
V
CC
0031–Vm
I
HI 2
03Aµ
I
LI 2
5.–Aµ
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V
DI 1
0050082Vm
1. Differential input voltage – algebraic difference
VSWING
VID = 2 X VSWING
VIN (+)
VIN (–)
VIN (+) – VIN (–)
Note: VIN (+) – VIN (–)
is the algebraic difference
of the output signals
1. Internal bias point.
2. Single ended connection.
3. DC is considered to be an input signal between 0 Hz and 1 KHz.
15
32 x 32 1.5 GBIT/S DIFFERENTIAL CROSSPOINT SWITCH S2025
June 24, 1999 / Revision B
Figure 8. Differential Output Voltage
Table 10. PECL DC Characteristics
2
Table 11. Differential PECL Characteristics
VSWING
VOD = 2 X VSWING
VOUT (+)
VOUT (–)
VOUT (+) – VOUT (–)
Note: VOUT (+) – VOUT (–)
is the algebraic difference
of the output signals
lobmySniMpyTxaMstinU
V
DO 1
0070332Vm
lobmySniMpyTxaMstinU
V
HO 1
V
CC
5901–V
CC
596–Vm
V
LO 1
V
CC
0091–V
CC
5631–Vm
I
HO
02Am
I
LO
5Am
1. Differential input voltage – algebraic difference.
1. All outputs are loaded with 50Ω to VCC – 2V.
2. DC is considered to be an output signal between 0Hz and 1KHz.
16
32 x 32 1.5 GBIT/S DIFFERENTIAL CROSSPOINT SWITCH
S2025
June 24, 1999 / Revision B
EXPANDING TO A 64 X 64 SWITCH
The S2025 includes configurable differential output pair
driver enables that allow it to be expanded to form a 64
x 64 differential crosspoint switch.
As shown in Figure 9, four S2025 devices can be used
to form a 64 x 64 differential crosspoint switch. Each of
the 64 pairs of differential outputs are connected to
output pairs on two different S2025 devices.
Similarly, each of the 64 pairs of differential outputs are
connected to output pairs on two different S2025 de-
vices. The configuration register files of the two devices
are then programmed to enable only one of the two
connected output pairs at once.
With the interconnection scheme shown in Figure 9,
any of the 64 output pairs can be connected to any of the
64 input pairs.
To avoid power-up output pair contention, the Reset
condition for the S2025 assumes a configuration where
all the differential output pairs are disabled.
Normal high-speed PECL routing and termination prac-
tices are required for all PECL connections. For
maximum data throughput, reflected signals from im-
pedance mismatches at the package/pcb boundary, as
well as those due to poor placement of terminating
impedances must be minimized. Care also must be
taken during board layout to position the devices for the
shortest possible trace lengths when connecting differen-
tial outputs together.
Larger differential crosspoint switch structures can also
be built using the S2025’s ability to selectively enable
and disable its differential output pair drivers.
Figure 9. Expanding to a 64 x 64 Switch
DOUTOOP
DOUTOON
DOUT31P
DOUT31N
DOUT32P
DOUT32N
DOUT63P
DOUT63N
DINOOP
DINOON
DIN31P
DIN31N
DIN32P
DIN32N
DIN63P
DIN63N
32 X 32
Differential
Crosspoint
Switch
32 X 32
Differential
Crosspoint
Switch
32 X 32
Differential
Crosspoint
Switch
32 X 32
Differential
Crosspoint
Switch
17
32 x 32 1.5 GBIT/S DIFFERENTIAL CROSSPOINT SWITCH S2025
June 24, 1999 / Revision B
Ordering Information
Prefix Device Package
S – Integrated Circuit 2025 C – 8, 800MBPS, 196 LDCC
lead formed with Heatsink
unattached
C – 15, 1.5GBPS, 196 LDCC
lead formed with Heatsink
unattached
XXXX X
X
Prefix Device Package
AMCC is a registered trademark of Applied Micro Circuits Corporation.
Copyright ® 1999 Applied Micro Circuits Corporation
AMCC reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and
advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information being relied
on is current.
AMCC does not assume any liability arising out of the application or use of any product or circuit described herein, neither does it
convey any license under its patent rights nor the rights of others.
AMCC reserves the right to ship devices of higher grade in place of those of lower grade.
AMCC SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR
USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS.
Applied Micro Circuits Corporation • 6290 Sequence Dr., San Diego, CA 92121
Phone: (858) 450-9333 • (800)755-2622 • Fax: (858) 450-9885
http://www.amcc.com
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