CLA40MT1200NPB
1~ Triac
Three Quadrants operation: QI - QIII
High Efficiency Thyristor
4
1
3
Part number
CLA40MT1200NPB
Backside: anode/cathode
-
Negative Half Cycle
Positive Half Cycle
+
QII QI
QIII QIV
I
GT
-+ I
GT
Three
Q
u
a
dr
a
nt
s
O
p
e
r
a
tion
Note: All Polarities are referenced to T1
T2
T1
REF
(-) I
GT
T2
T1
REF
(-) I
GT
T2
T1
REF
(+) I
GT
TAV
T
V V1.37
RRM
20
1200
=
V=V
I=A
Features / Advantages: Applications: Package:
● Triac for line frequency
● Three Quadrants Operation
- QI - QIII
● Planar passivated chip
● Long-term stability
of blocking currents and voltages
● Line rectifying 50/60 Hz
● Softstart AC motor control
● DC Motor control
● Power converter
● AC power control
● Lighting and temperature control
TO-220
● Industry standard outline
● RoHS compliant
● Epoxy meets UL 94V-0
● High creepage distance
between terminals
The data contained in this product data sheet is exclusively intended for technically trained staff. The user will have to evaluate the suitability of the product for the intended application and
the completeness of the product data with respect to his application. The specifications of our components may not be considered as an assurance of component characteristics. The
information in the valid application- and assembly notes must be considered. Should you require product information in excess of the data given in this product data sheet or which concerns
the specific application of your product, please contact the sales office, which is responsible for you.
Due to technical requirements our product may contain dangerous substances. For information on the types in question please contact the sales office, which is responsible for you.
Should you intend to use the product in aviation, in health or live endangering or life support applications, please notify. For any such application we urgently recommend
- to perform joint risk and quality assessments;
- the conclusion of quality agreements;
- to establish joint measures of an ongoing product survey, and that we may make delivery dependent on the realization of any such measures.
Terms Conditions of usage:
IXYS reserves the right to change limits, conditions and dimensions. 20150827bData according to IEC 60747and per semiconductor unless otherwise specified
© 2015 IXYS all rights reserved
CLA40MT1200NPB
V = V
A²s
A²s
A²s
A²s
Symbol
Definition
Ratings
typ.
max.
I
V
IA
V
T
1.37
R0.8 K/W
min.
20
VV
10T = 25°C
VJ
T = °C
VJ
mA1.5V = V
T = 25°C
VJ
I = A
T
V
T = °C
C
115
P
tot
155 WT = 25°C
C
20
1200
forward voltage drop
total power dissipation
Conditions
Unit
1.71
T = 25°C
VJ
125
V
T0
V0.89T = °C
VJ
150
r
T
24 mΩ
V1.37T = °C
VJ
I = A
T
V
20
1.83
I = A40
I = A40
threshold voltage
slope resistance for power loss calculation only
µA
125
VV1200T = 25°C
VJ
IA44
P
GM
Wt = 30 µs 5
max. gate power dissipation
P
T = °C
C
150
Wt = 1
P
P
GAV
W0.2
average gate power dissipation
C
J
12
junction capacitance
V = V400 T = 25°Cf = 1 MHz
RVJ
pF
I
TSM
t = 10 ms; (50 Hz), sine T = 45°C
VJ
max. forward surge current
T = °C
VJ
150
I²t T = 45°C
value for fusing
T = °C150
V = 0 V
R
V = 0 V
R
V = 0 V
V = 0 V
t = 8,3 ms; (60 Hz), sine
t = 10 ms; (50 Hz), sine
t = 8,3 ms; (60 Hz), sine
t = 10 ms; (50 Hz), sine
t = 8,3 ms; (60 Hz), sine
t = 10 ms; (50 Hz), sine
t = 8,3 ms; (60 Hz), sine
VJ
R
VJ
R
thJC
thermal resistance junction to case
T = °C
VJ
150
200
215
145
140
A
A
A
A
170
185
200
190
1200
300 µs
RMS forward current per phase
RMS
TAV
180° sine
average forward current
(di/dt)
cr
A/µs
150repetitive, I =T
VJ
= 150 °C; f = 50 Hz
critical rate of rise of current
V
GT
gate trigger voltage
V = 6 V T = °C25
(dv/dt) T = 150°C
critical rate of rise of voltage
A/µs500
V/µs
t = µs;
I A; V = ⅔ V
R = ∞; method 1 (linear voltage rise)
VJ
DVJ
60 A
T
P
G
= 0.3
di /dt A/µs;
G
=0.3
DRM
cr
V = ⅔ V
DRM
GK
500
1.3 V
T = °C-40
VJ
I
GT
gate trigger current
V = 6 V T = °C25
DVJ
± 40 mA
T = °C-40
VJ
1.6 V
± 60 mA
V
GD
gate non-trigger voltage
T = °C
VJ
0.2 V
I
GD
gate non-trigger current
± 1 mA
V = ⅔ V
D DRM
150
latching current
T = °C
VJ
70 mA
I
L
25t µs
p
=10
I A;
G
= 0.3 di /dt A/µs
G
= 0.3
holding current
T = °C
VJ
50 mA
I
H
25V = 6 V
D
R = ∞
GK
gate controlled delay time
T = °C
VJ
2 µs
t
gd
25
I A;
G
= 0.3 di /dt A/µs
G
= 0.3
V = ½ V
D DRM
turn-off time
T = °C
VJ
150 µs
t
q
di/dt = A/µs10 dv/dt = V/µs20
V =
R
100 V; I A;
T
= 20 V = ⅔ V
DRM
tµs
p
= 200
non-repet., I = 20 A
T
125
R
thCH
thermal resistance case to heatsink
K/W
Rectifier
1300
RRM/DRM
RSM/DSM
max. non-repetitive reverse/forward blocking voltage
max. repetitive reverse/forward blocking voltage
R/D
reverse current, drain current
T
T
R/D
R/D
200
0.50
IXYS reserves the right to change limits, conditions and dimensions. 20150827bData according to IEC 60747and per semiconductor unless otherwise specified
© 2015 IXYS all rights reserved
CLA40MT1200NPB
Ratings
XXXXXX
Zyyww
Logo
Part Number
Date Code
Lot #
abcdef
Product Marking
Assembly Line
C
L
A
40
MT
1200
N
PB
Part description
Thyristor (SCR)
High Efficiency Thyristor
(up to 1200V)
1~ Triac
Three Quadrants operation: QI - QIII
TO-220AB (3)
=
=
=
=
Current Rating [A]
Reverse Voltage [V]
=
=
=
=
Package
T
op
°C
M
D
Nm0.6
mounting torque
0.4
T
VJ
°C150
virtual junction temperature
-40
Weight g2
Symbol
Definition
typ.
max.
min.
Conditions
operation temperature
Unit
F
C
N60
mounting force with clip
20
I
RMS
RMS current
35 A
per terminal
125-40
TO-220
Similar Part Package Voltage class
CLA40MT1200NPZ TO-263AB (D2Pak) (2HV) 1200
Delivery Mode Quantity Code No.Ordering Number Marking on ProductOrdering
CLA40MT1200NPB 517038Tube 50CLA40MT1200NPBStandard
T
stg
°C150
storage temperature
-40
threshold voltage
V0.89
mΩ
V
0 max
R
0 max
slope resistance *
21
Equivalent Circuits for Simulation
T =
VJ
I
V
0
R
0
Thyristor
150 °C
* on die level
IXYS reserves the right to change limits, conditions and dimensions. 20150827bData according to IEC 60747and per semiconductor unless otherwise specified
© 2015 IXYS all rights reserved
CLA40MT1200NPB
Dim. Millimeter Inches
Min. Max. Min. Max.
A 4.32 4.82 0.170 0.190
A1 1.14 1.39 0.045 0.055
A2 2.29 2.79 0.090 0.110
b 0.64 1.01 0.025 0.040
b2 1.15 1.65 0.045 0.065
C 0.35 0.56 0.014 0.022
D 14.73 16.00 0.580 0.630
E 9.91 10.66 0.390 0.420
e 2.54 BSC 0.100 BSC
H1 5.85 6.85 0.230 0.270
L 12.70 13.97 0.500 0.550
L1 2.79 5.84 0.110 0.230
ØP 3.54 4.08 0.139 0.161
Q 2.54 3.18 0.100 0.125
3x b2
E
ØP
Q
D
L1
L
3x b 2x e C
A2
H1
A1
A
= supplier option
1 2 3
4
4
1
3
Outlines TO-220
IXYS reserves the right to change limits, conditions and dimensions. 20150827bData according to IEC 60747and per semiconductor unless otherwise specified
© 2015 IXYS all rights reserved
CLA40MT1200NPB
0,01 0,1 1
60
80
100
120
140
1
6
0
0,5 1,0 1,5 2,0 2,5
0
10
20
30
40
10
0
10
1
10
2
10
3
10
4
0,0
0,2
0,4
0,6
0,8
1,0
I
TSM
[A]
I
T
[
A]
V
T
[V]
t [ms]
Z
thJC
[K/W]
2 3 4 5 6 7 8 9 011
10
100
1
0
00
I
2
t
[A
2
s]
t [ms]
I
T(AV)M
[A]
T
C
[°C]
0 25 50 75 100 125 150 175
0
10
20
30
40
Fig. 1 Forward characteristics Fig. 3 I
2
t versus time (1-10 ms)
t [s]
Fig. 6 Max. forward current
at case temperature
Fig. 2 Surge overload current
Fig. 8 Transient thermal impedance
T
VJ
= 25°C
T
VJ
= 125°C
T
VJ
= 45°C
50 Hz, 80% V
RRM
T
VJ
= 125°C
T
VJ
= 45°C
V
R
= 0 V
0 10 20
0
10
20
30
40
I
T(AV)
[A]
P
(AV)
[W]
Fig. 7a Power dissipation versus direct output current
Fig. 7b and ambient temperature
0 50 100 150
T
amb
[°C]
dc =
1
0.5
0.4
0.33
0.17
0.08
10 100 1000
1
10
100
1000
I
G
[mA]
V
G
[V]
t
gd
[µs]
I
G
[mA]
typ. Limit
T
VJ
= 125°C
Fig. 4 Gate trigger characteristics Fig. 5 Gate controlled delay time
dc =
1
0.5
0.4
0.33
0.17
0.08
T
VJ
= 125°C
T
VJ
= 150°C
R
thi
[K/W] t
i
[s]
0.10 0.0100
0.08 0.0011
0.20 0.0250
0.21 0.3200
0.21 0.0900
R
thHA
0.4
0.6
0.8
1.0
2.0
4.0
0 25 50 75
0
1
2
3
4I
GD
: T
VJ
= 125°C
I
GD
: T
VJ
= 25°C
I
GD
: T
VJ
= 25°C
I
GD
: T
VJ
= 0°C
I
GD
: T
VJ
= -40°C
A
B
B
B
C
Thyristor
IXYS reserves the right to change limits, conditions and dimensions. 20150827bData according to IEC 60747and per semiconductor unless otherwise specified
© 2015 IXYS all rights reserved
