CMOS Serial Input 12-Bit DAC General Description The MX7543 is a high precision 12-bit digital-to- analog converter (DAC) which uses a serial rather than parallel input scheme for loading data. Included are a serial-to-parallel shift register, a separate DAC register, and a multiplying DAC. Serial data is clocked in at the SRI pin on the rising or falling edge (user selected) of the strobe input. When the input register is full, the contents are transferred to the DAC register using the load input. A clear input is provided to initialize the part asynchronously. The MX7543 features excellent gain stability (sppm/C max.) and operates from a single +5V power supply while dissipating about 10mW. Applications Remote Analog Systems Robotics Programmable Attenuators Automatic Test Equipment Auto-Calibration Systems Functional Diagram 8 maxim fra MX7543 t n ver 12-817 D/A CONVERTER 2 qutz ZF fee an OAC REGISTER B or OAD y Zo REGISTER A 7 12-BIT SHIFT REGISTEA MAMAL/VI Features @ Serial Interface @ + and +1 LSB Linearity @ CLEAR input For Initialization @ Single +5V Supply Operation @ Sppm/C Gain Stability @ 1.LSB Max. Feedthrough At 10kHz @ Small Size: 16-Lead DIP Ordering Information PART TEMP. RANGE PACKAGE ERROR MX7543JN 0C to +70C Plastic DIP +1 LSB MX7543KN OC to +70C Plastic DIP +s LSB MX7543GKN 0C to +70C Plastic DIP +%LSB MX7543JCWE 0C to +70C Small Outline +1 LSB MX7543KCWE 0C to +70C Small Outline +': LSB MX7543GKCWE -0C to +70C_- Small Outline + LSB MX7543JC/D OC to +70C Dice +1 LSB MX7543AD -25C to +85C Ceramic +1 LSB MX7543BD0 -25C to +B5C Ceramic +, LSB MX7543GBD -25C to +85C Ceramic +'. LSB MX7543AQ -25C to +85C CERDIP** +1 LSB MX7543BQ -25C to +85C CERDIP" +", LSB MX7543GBQ -25C to +85C CERDIP** +2 LSB MX7543SD -55C to +125C Ceramic +1 LSB MX7543TD -65C to +125C Ceramic + LSB MX7543GTD --55C to +125C Ceramic + LSB MX7543SQ -55C to +125C CERDIP"* +1 LSB MX7543TQ -55C ta +125C CERDIP"* +'% LSB MX7543GTQ _-55C to +125C ~CERDIP"* +2 LSB * All devices16-pin packages " Maxim reserves the right to ship Ceramic packages in lieu of CERDIP packages Pin Configuration Top View OUTI a ouT2 2] AGND [2 stat | STB2 [2] in & ne [6] sal 7 MAXI VI MAXIM 1S 4 registered trademark of Maxim Integrated Products CrslXWCMOS Serial input 12-Bit DAC ABSOLUTE MAXIMUM RATINGS . Vop to AGND 0... eee -0.3V, +7V Power Dissipation ......... 0... sc eee eee e eee 450mW Vpp to DGND ......... eee eee -0.3V, +7V (derate 6mW/C above +70C) Wy) AGND to DGND ...... 0. cece cece teen nes Vpo Operating Temperature Range m& DGND to AGND ..... 0 ccc ee eee Vop Commercial MX7543J, K, GK ........... aC to +70C x Digital Input Voltage to OGND ........ -0.3V. Vop + 03V Industrial MX7543A, B, GB ........... -25C to +B5C (Pins 4-11, 13) Military MX7543S, T, GT ............. -55C to +125C = Veins: Vpin2 tO AGND .... 2... eee ee -0.3V. Vpp + 03V Storage Temperature ...............4. -65C to +150C Veer CO AGND 2.01. 425V Lead Temperature (Soldering 10 sec) ........... +300C Verg tO AGND 2.2... cece eens +25V Stresses above those tsted under Absolute Maximum Ratings may cause permanent damage to the device These are stress ratings only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications ts not implied. Exposure to absolute maximum ratings condifions for extended periods may affect device reliability ELECTRICAL CHARACTERISTICS (Ty = Twin tO Tax: Yop = t5V. Veer = +10V, Vouri = Vourz2 = GND, unless otherwise specified) PARAMETER [symBoL | CONDITIONS MIN TYP MAX | UNITS DC ACCURACY Resolution 12 Bits MX7543J/A/S +1 Non-Linearity MX7543K/B/T 40.5 LSB MX7543GK/GB/GT +0.5 MX7543J/A/S (Note 1) +2 Differential Non-Linearity MX7543K/B/T (Note 2) +1 LSB MX7543GK/GB/GT (Note 2) +1 MX75435/K/A/B/S/T T, = 25C +123 MX7543J/K/A/B Tun tO Trax +13.5 MX7543S/T T to T +145 Gain Error MIN MAX LSB MX7543GK/GB/GT Ty = 25C +1 MX7543GK/GB Tain tO Trax +1 MX7543GT Tan tO Trax +2 Gain Temperature Coefficient AGain/ATemperature (Note 4) 2 5 |ppmiC Power Supply Rejection PSRR | Voy = +4 75V to +5 25V Ta = 26C 0.005 lo /%V 56 Tran tO Tenax 0.01 Ty = 25C 1 Output Leakage Current MX7543J/K/GK Twin tO Tyax 10 nA lout lourz (Note 3) MX75434/B/GB Trin tO Trax 10 MX7543S/T/GT Twain tO Trax 200 DYNAMIC PERFORMANCE (Note 4) Output Current Settling Time To 1/2 LSB, Out! Load = 100Q 2 US Feedthrough Error Vper = 10V 10kHz sine wave 25 mVpp REFERENCE INPUT Input Resistance (pin 15) | Rrer | | 8 15 25 ka ANALOG OUTPUT (Note 4) Cour DAC Register 0000 0000 0000 75 DAC Register 1111 11111111 260 OuT1 Output Capacitance Coyra | DAC Register 1111 1111 1111 75 pF Cours | DAC Register 0000 0000 0000 260 Note 1: Monotonic to 11 bits from Tyin tO Tyax Note 2: Monotonic to 12 bits from Tyin tO Tuax Note 3: I5,,7, tested with DAC register loaded to all 0's lourt2 tested with DAC register loaded to all 1's Note 4: Guaranteed by design but not tested Note 5: Sample tested at +25C to ensure compliance. 2-90 MAXI /VICMOS Serial Input 12-Bit DAC ELECTRICAL CHARACTERISTICS (Continued) (T. = Twin tO Taax: Yoo = *5Y Veer = +10V, Vouri = Vout = GND, unless otherwise specified) PARAMETER |symsot| CONDITIONS MIN TYP MAX | UNITS LOGIC INPUTS Logic HIGH Voltage Vin +3.0 V Logic LOW Voltage Vine +08 Logic Input Current lin Vin = OV oF Von 1 uA Input Capacitance (Note 4) Ci 8 pF SWITCHING CHARACTERISTICS (see Figure 6) (Note 5) t Ty = 25C 50 DS! Trin tO Tyax 100 t Ta = 25C 20 Serial Input OS2 | Tain t0 Tax 40 ns to Strobe Setup Time t Ta = 25C 0 Oss Twin tO Twax 0 t T, = 25C 0 ps4 Tun tO Tax 0 t Ta = 25C 30 OF) Trin tO Tyax 60 t Ta = 25C 60 Serial Input He Tun tO Tmax 120 ns to Strobe Hold Time t T, = 25C 80 OHS Tran tO Tuax 160 t Ta = 25C 80 OHA Train tO Tyax 160 Ty = 25C 80 SRI data pulse width t A Pulse wi SPIT Thay tO Trax 160 . T, = 26C 80 STB1 pulse width t A pulse wi STB | Tay tO Tax 160 : Ty = 25C 80 STB2 pulse width t A pase STB? | Taw t2 Twax 160 <= , T, = 25C 100 STB3 pulse width tstea Thun tO Trax 200 T, = 25C 100 STB4 pulse width tstpa Tan to Tyax 200 ns . T, = 25C 150 Load 1 pulse width tips Than tO Trax 300 Ty = 25C 150 Load 2 pulse width tipo Tan to Tax 300 Time between strobing = 960 LSB into Register A and tase 1 - o loading Register B MIN MAX T, = 25C 200 Clear pulse width tour Twn tO Traax 400 POWER SUPPLY Supply Voltage Von | 5V + 5% 4.75 5.25 Vv Supply Current 'pp 2.5 mA MAAISVI 2-91 ErsZXwMX7543 CMOS Serial Input 12-Bit DAC Detailed Description The basic MX7543 DAC circuit consists of a laser- trimmed, thin-film R-2R resistor array with NMOS current switches as shown in Figure 1. Binarily weighted currents are switched to either OUT1 or OUT2 depending on the status of each input bit. Although the current at OUT1 or OUT2 will depend on the digital input code, the sum of the two output currents is always equal to the input current at Vref minus the termination resistor current (Ry). Either current output can be converted into a voltage externally by adding an output amplifier (Figure 4). The Vaer input accepts a wide range of signals in- cluding fixed and time varying voltage or current inputs. If a current source is used for the reference input, then a low temperature coefficient external resistor should be used for Reg to minimize gain variation with temperature. Equivalent Circuit Analysis Figures 2 and 3 show the equivalent circuits for the R-2R ladder when ali digital inputs are LOW and HIGH respectively. The input resistance at Vper is nominally 15kQ and does not change with digital input code. The Ige-/4096 current source, which is actually the ladder termination resistor (R;, Figure 1), results in an intentional 1-bit current loss to GND. The lleaxaGe Current sources represent junction and surface leakage currents. Capacitors Cour; and Court represent the switches ON and OFF capacitances respectively. When all inputs are switched from LOW to HIGH, the capaci- tance at OUT1 changes from approximately 75pF to 260pF. This capacitance is code-dependent and is a function of the number of ON switches that are con- nected to a specific output. 15K VREF Rr 30K 30K SN = | { ' { > OUT2 t = OUTI ~ $5" | Lae Ree BIT 1 (MSB) BIT N (LSB) Figure 1. MX7543 Functional Diagram Circuit Configurations Unipolar Operation The most common configuration for the MX7543 is shown in Figure 4. The circuit is used for unipolar binary operation and/or 2-quadrant multiplication. The code table is given in Table 1. Note that the polarity of the output is the inverse of the reference input. In many applications, gain adjustment of the MX7543 will not be necessary. In those cases, and also when gain is trimmed but only at the reference source, resistors R1 and R2 in Figure 4 can be omitted. However, if the trims are desired and the DAC is to operate over a wide temperature range, then low temipce {(<300ppm/ C) resistors should be used at R1 and Re. Are oumT1 R= 15K VaeF ouT2 _ I JRer ILeaKaGE 260pF REF 4096 L Fre OuT1 ILEAKAGE 7 260pF Greonce Ewe 7 ouT2 { LEAKAGE T 75pF Figure 2. MX7543 DAC Equivalent Circuit, Ail Digital inputs LOW 2-92 Figure 3. MX7543 DAC Equivalent Circuit, All Digital Inputs HIGH SVIAXI VICMOS Serial Input 12-Bit DAC Y 15 Vin VREF MAXI > VouT Rt MX7543 OUT2/2 MAXIM DGND_AGND MAX400 3 *TRIM J/K/A | GK/GB/ RESISTOR | 8/S/T GT Rt 1200 109 R2 600 50 Figure 4. Unipolar Binary Operation a4 . 20k asy R2 Ok 10pF-33pF URS ry 15 ~ R3 20k OWA TVREF MIKI Vin AM | 4x7543 OUT2/2 Z 10kQ DGND _AGNO Vout 12 3 R6 = = 5kQ) 10% "TRIM U/K/A | GK/GB/ RESISTOR | 8/S/T GT R1 1200 109 R2 600 52 Figure 5. Bipolar Operation (4-Quadrant Multiplication; Bipolar Operation With the circuit configuration in Figure 5, the MX7543 operates in the bipolar, or 4-quadrant multiplying mode. A second amplifier and three matched resistors are required. Matching to 0.01% is recommended for 12 bit performance. The code table for the output, which is offset binary, is listed in Table 2. In multi- plying applications, the MSB determines output po- larity while the other 11 bits control amplitude. MAAIWVI Table 1. Code TableUnipolar Binary DIGITAL INPUT MSB LSB ANALOG OUTPUT 1149 4771 71491 4095 4096 4 Vv, 1000 0000 0000 Veer ( Heap |= - 0000 0000 0001 Veer | 3355 | 0000 0000 0000 ov Table 2. Code Table Bipolar (Offset Binary) Operation DIGITAL INPUT MSB LSB ANALOG OUTPUT 2047 1441411 1 a 11111 *Vagr | saa | 1 1 1 Vaee | sap 000 0000 000 wae | sana 1000 0000 0000 ov 1 o11714111 1111 Veer | sau | 204 0000 0000 0000 Veer | 3eae | To adjust the circuit, load the DAC with a code of 1000 0000 0000 and trim R1 for a OV output. With R1 and R2 omitted, an alternative zero trim is to adjust the ratio of R3 and R4 for OV out. Full scale can be trimmed by loading the DAC with ail zeros or all ones and adjusting the amplitude of Veer or varying R5 until the desired positive or negative output is obtained. If gain and offset trims are not required, A1 and R2 in Figure 5 can be omitted. 2-93 ErsSlXWMX7543 CMOS Serial Input 12-Bit DAC Interface Logic Serial data is first loaded into the 12-bit Shift Register A, shown in the MX7543 functional diagram. Each bit of serial data appearing at pin SRI is clocked into Register A MSB first, by any one of the four strobe inputs. STB1, STB2, and STB4 all clock data into Shift Register A on the rising edge of the strobe pulse. STB3 clocks data into Register A on its falling edge. Table 3 illustrates the logic states for the control inputs. Figure 6 shows the timing diagram for the loading sequence. Data is then transferred from Shift Register_A into Register B by momentarily moving both LD1 and LD2, low. Bringing CLR input low asynchronously resets Regis- ter B to 0000 0000 0000. This initializes the DAC output voltage to a known condition. With the unipolar circuit of Figure 4, a CLR results in a DAC output voltage of 0 volts. Using the dipolar circuit of Figure 5, momentarily bringing CLR tow sets the DAC output voltage to its lowest value of -Vrer. 1 < tsni ; BIT 7 SRt MSB 'os1, tos2, tpsa STROBE INPUT =X | tsTe1 tsta2 ~4 CDT AND LD2 NOTE: STROBE WAVEFORM IS INVERTED IF STB3 IS USED TO STROBE SERIAL DATA BITS INTO REGISTER A. | toH1, tbH2. loa | | 2 1 12 Ty VEN OOF (NOTE) isTpa {Lor [emt LOADING REGISTER A __| \ X BIT 12 . BIT 11 x LSB x 7 ASB 7 pa 7 LOADING REGISTER B WITH CONTENTS OF REGISTER A Figure 6. Timing Diagram Table 3. MX7543 Truth Table MX7543 Logic Inputs Register A Register B : Control Inputs Control Inputs MX7543 Operation Notes STB4 STB3 STB2 STB1| CLR LD2 LD1 0 1 0 Ff X X X Data Appearing At SRI Strobed Into Register A 2,3 0 1 FF 0 x X x Data Appearing At SRI Strobed Into Register A 2,3 0 LV 0 0 x Xx X | Data Appearing At SRI Strobed Into Register A 2,3 f 1 0 0 x xX Xx Data Appearing At SRI Strobed Into Register A 2,3 1 x x xX X 0 X X ; No Operation (Register A) 3 xX xX 1 x x xX Xx 1 0 x Xx Clear Register B To Code 0000 0000 0000 1.3 (Asynchronous Operation) , 1 1 xX ; No Operation (Register B) 3 1 X 1 1 0 0 Load Register B With The Contents Of Register A 3 Notes: 1 CLR = 0 Asynchronously resets Register B to 0000 0000 0000. but has no effect on Register A 2 Serial data ts loaded into Register A MSB first, on edges shown f IS positive edge L Is negative edge 3 0 = Logic LOW, 1 = Logic HIGH, X = Dont Care 2-04 MIAXIE/VICMOS Serial input 12-Bit DAC Application information Output Amplifier Offset For best linearity, OUT1 and OUT2 should be termi- nated exactly at OV. In most applications OUT1 is connected to the summing junction of an inverting op-amp. The amplifier's input offset voltage can de- grade the linearity of the DAC by causing OUT1 to be terminated to a non-zero voltage. The resulting error 1S. Error Voltage = Vos5(1 + Reg/Ro), where Vog is the op-amps offset voltage and Ro is the output resistance of the DAC. Ro is a function of the digital input code, and varies from approximately 15kQ to 45kQ. The error voltage range is then typically 4/3V 95 to 2Vog, a change of 2/3Vogg. An amplifier with 3mvV OF offset will therefore degrade the linearity by 2mV, almost a full LSB with a 10V reference voltage. For best linearity, a low-offset amplifier such as the MAX400 should be used, or the amplifier offset must be trimmed to zero. A good rule of thumb is that Vos should be no more than 1/10 of an LSB's value. The output amplifier input bias current (Ig) can also limit performance since lp x Reg generates an offset error, lg should therefore be much less than the DAC output current for 1 LSB, typically 250nA with Vpaer = 10V. One tenth of this value, 25nA, is recommended. Offset and linearity can also be impaired if the output amplifiers noninverting input is grounded through a bias current compensation resistor. This resistor adds to offset at this pin and should not be used. Best performance is obtained when the noninverting input is directly connected to ground. Dynamic Considerations In static or DC applications, the AC characteristics of the output amplifier are not critical. In higher speed applications, where either the reference input is an AC signal or the DAC output must quickly settle to a new programmed value, the AC parameters of the output Op-amp must be considered. Another error source in dynamic applications is para- sitic coupling of signal from the Vagr terminal to OUT1 or OUT2. This is normally a function of board layout and package lead-to-lead capacitance. Signals can also be injected into the DAC outputs when the digital inputs are switched. This digital feedthrough is usually dependent on circuit board layout and on- chip capacitive coupling. Layout induced feedthrough can be minimized with guard traces between digital inputs, Vagre. and the DAC outputs. Compensation A compensation capacitor, C1, may be needed when the DAC is used with a high speed output amplifier. The purpose of the capacitor is to cancel the pole formed by the DACs output capacitance and internal feedback resistance. Its value depends on the type of Op-amp used but typical values range from 10 to 33pF. Too small a value causes output ringing while excess capacitance overdamps the output. The size of C1 can be minimized, and output settling perform- ance improved, by keeping the PC board trace and stray capacitance at OUT1 as small as possible. Grounding and Bypassing Since OUT1, OUT2 and the output amps noninverting inputs are sensitive to offset voltages, nodes that are to be grounded should be connected directly to single point ground through a separate, very low resistance (less than 0.2Q) path. The current at OUT1 and OUT2 varies with input code, creating a code dependent error if these terminals are connected to ground (or a virtual ground) through a resistive path. A uF bypass capacitor, in parallel with a 0.01pF ceramic capacitor, should be connected as close to the DAC's Vpp and GND pins as possible. The MX7543 has high-impedance digital inputs. To minimize noise pick-up, they should be tied to either Vpp or GND when not used. It is also good practice to connect active inputs to Vpp or GND through high valued resistors (1MQ) to prevent static charge accumulation if these pins are left floating, such as when a circuit card is left unconnected. Chip Topography 14 13 12 11 Voo CLA OGND STB4 , ae ee pa VREF ee 10 1 STB3 Rea 16 0.100" 9 2.54mm LD2 OUT a = 1 Pi Bea 8 OUT2 + STB2 2 7 AGND a SAI 4 S_ STB1 LDi 0.109" 2.77mm Max.m cannot assume responsibility for use Of any circuitry other than circuitry entirely embodied in a Maxim product No circurt patent licenses are imphed Maxam reserves the right to change the circuitry and specifications without notice al any time MIAXI/VI 2-95 ErSZLXN