M30240 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER REU03B0001-0100Z Rev. H Sep 18, 2003 1.1 Description The M30240 group is a 16-bit microcomputer based on the M16C family core technology. They are single-chip USB peripheral microcontrollers based on the Universal Serial Bus (USB) Version 1.1 specification. They are packaged in an 80-pin, molded plastic QFP. These single-chip microcontrollers operate using sophisticated instructions featuring a high level of instruction efficiency, making them capable of executing instructions at high speed. They also feature a built-in multiplier and DMAC, making them ideal for controlling office communications, industrial equipment, and other high-speed processing applications. 1.1.1 Features * * * * * * * * * * * * * * * * * * * * * CPU .................................................... 16-bit (including a hardware multiplier) Number of instructions ........................ 91 Shortest instruction execution time ..... 83ns (f(XIN)=12MHz) USB Features: .................................... 9 endpoints FIFO Sizes (endpoints 0-4):32,128, 32, 32, 32 Conforms to USB V1.1 Specification USB Transceiver ................................. Conforms to USB V1.1 Specification-Internal Vref Frequency Synthesizer ....................... PLL for 48MHz clock Memory capacity (mask device):......... ROM (40K, 48K) / RAM (3.0 K) Memory capacity (OTP device):.......... PROM (128K) / RAM (5K) Supply Voltage .................................... 4.1 to 5.25V (f(XIN)=12MHz) Interrupts ............................................. 21 internal and 4 external interrupt sources, 4 software interrupt sources; 7 levels (including key input interrupt x 16) Multifunction timer ............................... 5 X 16-bit, w/integrated 20mA (peak) PWM outputs General purpose timer ........................ 3 X 16-bit, internal interrupt only UART .................................................. 3 X 7/8/9 bits; Configurable for synchronous or asynchronous mode DMAC ................................................. 2 channels (trigger: 19 sources) A-D Converter ..................................... 10 bits X 8 channels CRC calculation circuit........................ 1 circuit (industry standard polynomial) Watchdog timer ................................... 1 line (15 bit) Programmable I/O............................... 63 lines High current and LED Drivers ............. 5 high current and 8 LED drivers Clock-generating circuit ...................... 1 built-in circuit including feedback resistor Package: ............................................. 80P6N-A (0.8 mm pitch) 1.1.2 Applications USB peripherals, such as telephones, audio systems, scanners, and digital cameras. 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H Sep 18, 2003 Page 1 of 139 M30240 Group Table of Contents 1.1.3 Table of Contents 1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Performance outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.2 Operation of Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Central Processing Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Processor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 SFR Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Clock-Generating Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Status Transition Of Internal Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Power Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 NMI Interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Key input interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Address Match Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Frequency Synthesizer Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Universal Serial Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 DMAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Timers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Timer A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Timer B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 UART0 to UART2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 A-D Converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 CRC Calculation Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Programmable I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 1.3 Usage Precautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Precautions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 1.4 Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 1.5 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 Frequency Synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 Attach/Detach Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 Low Pass Filter Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 USB Transceiver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 Programming Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 Rev. H Sep 18, 2003 Page 2 of 139 Pin Configuration M30240 Group 1.1.4 Pin Configuration P31 P30 P27/LED7 P26/LED6 P25/LED5 P24/LED4 P23/LED3 P22/LED2 P21/LED1 P20/LED0 Vcc P17/KI15 Vss P16/KI14 P15/KI13 P14/KI12 P13/KI11 P12/KI10 P11/KI9 P10/KI8 P07/KI7 P06/KI6 P05/KI5 P04/KI4 Figure 1.1 shows the pin configuration (top view). 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 P03/KI3 65 40 P32 P02/KI2 66 39 P33 P01/KI1 67 38 P34 P00/KI0 68 37 P35 P107/AN7 69 36 P36 P106/AN6 70 35 P37/CLKOUT P105/AN5 71 34 P60/CTS0/RTS0 33 P61/CLK0 32 P62/RxD0 P102/AN2 74 31 P63/TxD0 P101/AN1 75 30 P64/CTS1/RTS1/CLKS1 P100/AN0 76 29 P65/CLK1 AVss 77 28 P66/RxD1 LPF 78 27 P67/TxD1 VREF 79 26 P70/TxD2/TA0OUT AVcc 80 25 P71/RxD2/TA0IN M30240Mx/EC Figure 1.1: BYTE CNVss D+ P72/CLK2/TA1OUT EXTCAP P73/CTS2/RTS2/TA1IN P83/ATTACH P75/TA2IN P84/INT1 Rev. H Sep 18, 2003 Page 3 of 139 P74/TA2OUT P85/NMI Pin Configuration (top view) P76/TA3OUT P86/SOF 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 P77/TA3IN 9 P80/TA4OUT 8 P81/TA4IN 7 P82/INT0 6 Vcc 5 XIN 4 Vss 3 XOUT 2 D- 1 P87/ADTRG P103/AN3 73 RESET P104/AN4 72 Block Diagram M30240 Group 1.1.5 Block Diagram Figure 1.2 is a block diagram of the M30240 group. 8 8 I/O Ports Port P0 Port P1 8 Port P2 8 Port P3 8 Port P6 8 7 Port P80~P84, P86, P87 Port P7 Internal peripheral functions (16 (16 (16 (16 (16 (16 (16 (16 bits) bits) bits) bits) bits) bits) bits) bits) RAM M16C series 16-bit CPU core A-D converter 10 bits x 8 channels Registers R0H USB function control unit R1H R1L R2 DMAC (2 channels) UART/clock synchronous S I/O (8 bits x 3 channels) Note CRC arithemetic circuit (CCITT) (Polynomial: X16+X12+X5+1) Note: One serial I/O can be used for SIM interface Block diagram of M30240 group Rev. H Sep 18, 2003 Page 4 of 139 PC R0L R3 A0 Watchdog timer (1 line) Program counter R0L R0H Frequency Synthesizer Figure 1.2: Port P10 System clock generator XIN - XOUT Timer TA0 TA1 TA2 TA3 TA4 TB0 TB1 TB2 Port P85 Memory ROM Timer Timer Timer Timer Timer Timer Timer Timer 8 A1 Vector table INTB Stack Pointer ISP USP FB SB Multiplier FLG Performance outline M30240 Group 1.1.6 Performance outline Table 1.1 is a performance outline of the M30240 group. Table 1.1: Performance outline of M30240 group Item Performance Number of basic instructions 91 instructions Shortest instruction execution time 83ns (f(XIN) =12MHz) ROM Memory capacity (See Table 1.2: ROM capacity field) RAM I/O port P0 to P3, P6,P7, P8 (except P85), P10 8 bits x 7, 7 bits x 1 Input port P85 1 bit x 1 Multifunction Timer TA0, TA1, TA2, TA3, TA4 16 bits x 5 General purpose Timer TB0, TB1, TB2 16 bits x 3 Serial I/O UART0, UART1, UART2 (UART or clock synchronous) x 3 A-D converter 10 bits x 8 channels DMAC 2 channels (trigger:19 sources) CRC calculation circuit CRC-CCITT Watchdog timer 15 bits x 1 (with prescaler) Interrupt 21 internal and 4 external sources, 4 software sources, 7 levels Clock-generating circuit Built-in clock generation circuit (built-in feedback resistor, and external ceramic or quartz oscillator) Supply voltage (typical) 4.1 to 5.25V, (f(XIN)=12MHz, without software wait) Power consumption (typical) 250 mW, Vcc=5.0V, 12MHz I/O withstand voltage 5V Average output current 5 mA available on ports P0, P1, P3,P6, P71, P73, P75, P77, P81~P84, P86, P87, P10 10 mA available on ports P2, P70, P72, P74, P76, P80 I/O characteristics Operating temperature 0 to 70oC Device configuration CMOS high performance silicon gate Package 80-pin plastic molded QFP Rev. H Sep 18, 2003 Page 5 of 139 Performance outline M30240 Group Renesas plans to release the following products in the M30240 group: (1) Support for mask ROM version and one-time PROM version (2) ROM capacity (3) Package * 80P6N-A: Plastic molded QFP (mask ROM version and one-time PROM version) Figure 1.3 shows the type number, memory size and package for the M30240 group. Type No. M30 24 0 M 5 - XXX FP Package type: FP : Package 80P6N-A ROM No. Omitted for blank one-time PROM version and EPROM version ROM capacity: 1 : 8K bytes 2 : 16K bytes 3 : 24K bytes 4 : 32K bytes 5 : 40K bytes 6 : 48K bytes 7 : 56K bytes 8 : 64K bytes 9 : 80K bytes A : 96K bytes C : 128K bytes Memory type: M : Mask ROM version E : EPROM or one-time version Part type: Specifies part variations with M30240 group M30240 Group M16C Family Figure 1.3: Type number, memory size, and package Table 1.2 shows the Package Number, type, ROM and RAM Capacity for M30240 Group. Table 1.2: M30240 Group Type ROM Capacity RAM Capacity Package Type M30240M5-XXXXFP 40K bytes 3K bytes 80P6N-A Mask ROM Version M30240M6-XXXXFP 48K bytes 3K bytes 80P6N-A Mask ROM Version M30240ECFP 128K bytes 5K bytes 80P6N-A One-time PROM version Rev. H Sep 18, 2003 Page 6 of 139 Remarks Pin Description M30240 Group 1.1.7 Pin Description Table 1.3 shows the M30240 pin description. Table 1.3: Figure pin description Pin # Name I/O Description 1 P87 I/O CMOS I/O port. This pin also functions as an external trigger for A-D conversion. 2 P86 I/O CMOS I/O port. This pin also functions as the start of frame (SOF) pulse for the USB module. 3 P85/(NMI) I CMOS input port. This pin also functions as a non-maskable external interrupt. 4,5 P84 ~ P83 I/O CMOS I/O port. P84 also functions as external interrupt 1 and P83 is used to enable the stealth detach function for the USB transceiver. 6 EXTCAP _ An external capacitor (Ext. Cap) pin. When the USB transceiver voltage converter is used, a 2.2 F and a 0.1 F capacitor should connect between this pin and Vss to ensure proper operation of the USB line driver. This option is enabled by setting bit 4 of the USB control register (000C16) to a "1". 7 BYTE I Connect this pin to Vss 8 CNVss I Connect this pin to Vss 9 USB D+ I/O USB D+ voltage line interface, a series resistor of 27 to 33 is connected to this pin. 10 USB D- I/O USB D- voltage line interface, a series resistor of 27 to 33 is connected to this pin. 11 RESET I A "L" on this input resets the microcomputer. 12 XOUT O See Xin 13 Vss - Ground: Vss = 0V 14 Xin I Input and output signals to and from the internal clock generation circuit. Connect a ceramic resonator or quartz crystal between Xin and Xout pins to set the oscillation frequency. If an external clock is used, connect the clock source to the Xin pin and leave the Xout pin open. 15 Vcc - Power: Vcc = 4.1~ 5.25V 16 P82 I/O CMOS I/O port. This pin also functions as external interrupt 0. P81 ~ P80 I/O CMOS I/O port. Pins in this port also function as TimerA4 input and output as selected by software. I/O CMOS I/O port. Pins in this port also function as timer pins. P77 and P76 can function as TimerA3 input and output as selected by software. P75 and P74 can function as TimerA2 input and output as selected by software. 17-18 19-22 P77 ~ P74 23-26 P73 ~ P70 I/O CMOS I/O port. Pins in this port also function as UART2 CTS, RTS, CLK, RXD, and TXD as selected by software. P73 and P72 can function as TimerA1 input and output as selected by software. P71 and P70 can function as TimerA0 input and output as selected by software. 27-30 P67 ~ P64 I/O CMOS I/O port. Pins in this port also function as UART1 CTS, RTS, CLK, Serial Clock, RXD, and TXD as selected by software. TXD(OE~) and RTS(SUSPEND) in addition to D+ and D- can be used to run the device in USB bypass mode. 31-34 P63 ~ P60 I/O CMOS I/O port. Pins in this port also function as UART0 CTS, RTS, CLK, RXD, and TXD as selected by software. 35-42 P37 ~ P30 I/O CMOS I/O port. Rev. H Sep 18, 2003 Page 7 of 139 Pin Description M30240 Group Pin # Name I/O Description 43-50 P27/LED7 ~ P20/LED0 I/O CMOS I/O port. These pins are capable of driving up to 20mA (peak) for LEDs. 51 Vcc 52 P17/KI15 53 Vss I I/O I Power: Vcc = 4.1~ 5.25V CMOS I/O port. This port can also function as the key-on wakeup interrupt KI15. Ground: Vss = 0V 54-60 P16/KI14~ P10/KI8 I/O CMOS I/O port. This port can also function as the key-on wakeup interrupts (KI8 ~ KI14). 61-68 P07/KI7~ P00/KI0 I/O CMOS I/O port. This port can also function as the key-on wakeup interrupts (KI0 ~ KI7). 69-76 P107 ~ P100 I/O CMOS I/O port. These pins also function as Analog inputs 7-0 for A-D conversion 77 AVss I This pin is a power supply input for the AD converter. (Connect to Vss) 78 LPF O Loop filter for the frequency synthesizer. 79 VREF I This pin is the reference voltage input for the A-D converter. 80 AVcc I This pin is a power supply input for the AD converter. (Connect to Vcc) Rev. H Sep 18, 2003 Page 8 of 139 Overview M30240 Group 1.1.8 Overview The M30240 group is a single chip PC peripheral microcontroller based on the Universal Serial Bus (USB) Version 1.1 specification. This device provides interface between a USB-equipped host computer and PC peripherals such as telephones, audio systems, and digital cameras. The M30240 block diagram is shown in Figure 1.4. The USB function control unit of the M30240 group can support all four data transfer types listed in the USB specification: Isochronous, Interrupt, Bulk, and Control. Each transfer type is used for controlling a different set of PC peripherals. Isochronous transfers provide guaranteed bus access, a constant data rate, and error tolerance for devices such as computer-telephone integration (CTI) and audio systems. Interrupt transfers are designed to support human input devices (HID) that communicate small amounts of data infrequently. Bulk transfers are necessary for devices such as digital cameras and scanners that communicate large amounts of data to the PC as bus bandwidth becomes free. Finally, control transfers are supported and are useful for bursty, host-initiated type communication where bus management is the primary concern. 1 - 12MHz LED Drivers (X 8) Timers x 8 ROM M16C CPU Watchdog Timer A-D Converter DMAC x 2 CRC Circuit FIFOs (Normal MCU or DMA Transfer) I/O Ports (P0~P3, P6 ~ P8, P10) Figure 1.4: M30240 block diagram Rev. H Sep 18, 2003 Page 9 of 139 Transceiver RAM UART x 3 USB Function Control Unit frequency 48 MHz synthesizer D+ D- Central Processing Unit M30240 Group 1.2 Operation of Functional Blocks The M30240 group accommodates certain units in a single chip. These units include ROM and RAM to store instructions and data, and the central processing unit (CPU) to execute arithmetic/logic operations. Also included are peripheral units such as USB, timers, serial I/O, DMAC, CRC calculation circuit, A-D converter, and I/O ports. The following explains each unit. 1.2.1 Central Processing Unit The CPU has a total of 13 registers shown in Figure 1.5. Seven of these registers (R0, R1, R2, R3, A0, A1, and FB) come in two sets; therefore, these have two register banks. b15 R0(Note) b8 b7 b15 R1(Note) b0 L H b8 b7 H b19 b0 L b0 Program counter PC Data registers b15 b0 b19 R2(Note) INTB b15 b0 H b15 b0 Interrupt table register L b0 User stack pointer USP R3(Note) b15 b15 b0 b0 Interrupt stack pointer ISP A0(Note) b15 b0 Address registers b15 b0 Static base register SB A1(Note) b15 b15 b0 Frame base registers FB(Note) IPL b0 FLG Flag register U I O B S Z D C Note: These registers consist of two register banks. Figure 1.5: Central processing unit register 1.2.1.1 Data registers Data registers (R0, R1, R2, and R3) are configured with 16 bits, and are used primarily for transfer and arithmetic/logic operations. Registers R0 and R1 each can be used as separate 8-bit data registers, high-order bits as (R0H/R1H), and low-order bits as (R0L/R1L). In some instructions, registers R2 and R0, as well as R3 and R1, can be used as 32-bit data registers (R2R0/R3R1). 1.2.1.2 Address registers (A0 and A1) Address registers (A0 and A1) are configured with 16 bits, and have functions equivalent to those of data registers. These registers can also be used for address register indirect addressing and address register relative addressing. In some instructions, registers A1 and A0 can be combined for use as a 32-bit address register (A1A0). Rev. H Sep 18, 2003 Page 10 of 139 M30240 Group Central Processing Unit 1.2.1.3 Frame base register (FB) Frame base register (FB) is configured with 16 bits, and is used for FB relative addressing. 1.2.1.4 Program counter (PC) Program counter (PC) is configured with 20 bits, indicating the address of an instruction to be executed. 1.2.1.5 Interrupt table register (INTB) Interrupt table register (INTB) is configured with 20 bits, indicating the start address of an interrupt vector table. INTB can be used as separate registers of four high-order bits and 16 low-order bits. 1.2.1.6 Stack pointer (USP/ISP) Stack pointer comes in two types: user stack pointer (USP) and interrupt stack pointer (ISP), each configured with 16 bits. Your desired type of stack pointer (USP or ISP) can be selected by a stack pointer select flag (U flag). This flag is located at the position of bit 7 in the flag register (FLG). 1.2.1.7 Static base register (SB) Static base register (SB) is configured with 16 bits, and is used for SB relative addressing. 1.2.1.8 Flag register (FLG) Flag register (FLG) is configured with 11 bits, each bit is used as a flag. Figure 1.6 shows the flag register (FLG). The following explains the function of each flag: 1.2.1.8.1 Bit 0: Carry flag (C flag) This flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit. 1.2.1.8.2 Bit 1: Debug flag (D flag) This flag enables a single-step interrupt. When this flag is "1", a single-step interrupt is generated after instruction execution. This flag is cleared to "0" when the interrupt is acknowledged. 1.2.1.8.3 Bit 2: Zero flag (Z flag) This flag is set to "1" when an arithmetic operation resulted in 0; otherwise, cleared to "0". 1.2.1.8.4 Bit 3: Sign flag (S flag) This flag is set to "1" when an arithmetic operation resulted in a negative value; otherwise, cleared to "0". 1.2.1.8.5 Bit 4: Register bank select flag (B flag) This flag chooses a register bank. Register bank 0 is selected when this flag is "0"; register bank 1 is selected when this flag is "1". 1.2.1.8.6 Bit 5: Overflow flag (O flag) This flag is set to "1" when an arithmetic operation resulted in overflow; otherwise, cleared to "0". 1.2.1.8.7 Bit 6: Interrupt enable flag (I flag) This flag enables a maskable interrupt. An interrupt is disabled when this flag is "0", and is enabled when this flag is "1". This flag is cleared to "0" when the interrupt is acknowledged. 1.2.1.8.8 Bit 7: Stack pointer select flag (U flag) Interrupt stack pointer (ISP) is selected when this flag is "0"; user stack pointer (USP) is selected when this flag is "1". This flag is cleared to "0" when a hardware interrupt is acknowledged or an INT instruction of software interrupts 0 to 31 is executed. Rev. H Sep 18, 2003 Page 11 of 139 Central Processing Unit M30240 Group 1.2.1.8.9 Bits 8 to 11: Reserved area 1.2.1.8.10 Bits 12 to 14: Processor interrupt priority level (IPL) Processor interrupt priority level (IPL) is configured with three bits, for specification of up to eight processor interrupt priority levels from level 0 to level 7. If a requested interrupt has priority greater than the processor interrupt priority level (IPL), the interrupt is enabled. 1.2.1.8.11 Bit 15: Reserved area The C, Z, S, and O flags are changed when instructions are executed. See the M16C software manual for details. b15 b0 IPL U I O B S Z D C Flag register (FLG) Carry flag Debug flag Zero flag Sign flag Register bank select flag Overflow flag Interrupt enable flag Stack pointer select flag Reserved area Processor interrupt priorit Reserved area Figure 1.6: Flag register (FLG) Rev. H Sep 18, 2003 Page 12 of 139 Processor Mode M30240 Group 1.2.2 Processor Mode Figure 1.7 shows the processor mode registers 0 and 1. Processor mode register 0 (Note ) b7 b6 b5 b4 0 b3 b2 b1 b0 0 0 0 0 Symbol PM0 Address 000416 Bit symbol Bit name Reserved bit PM03 When reset 0016 (Note) Function R W Must always be set to "0" Software reset bit The device is reset when this bit is set to "1". The value of this bit is "0" when read. Nothing is assigned. These bits can neither be set nor reset. When read, their contents are indeterminate. Note : Set bit 1 of the protect register (address 000A values to this register. 16) to "1" when writing new Processor mode register 1 (Note) b7 b6 b5 b4 b3 b2 b1 b0 0 0 Symbol PM1 Address 000516 Bit symbol When reset 00XXXXX0 2 Bit name Function R W Must always be set to "0" Reserved bit Nothing is assigned. These bits can neither be set nor reset. When read, their contents are indeterminate. PM17 Wait bit 0 : No wait state 1 : Wait state inserted Note : Set bit 1 of the protect register (address 000A to this register. Figure 1.7: Processor mode registers 0 and 1 Rev. H Sep 18, 2003 Page 13 of 139 16) to "1" when writing new values Memory M30240 Group 1.2.3 Memory 0000016 SFR 00400 16 RAM XXXXX16 unused yyyyy 16 ROM FFE0016 Special page vector table FFFDC 16 Undefined instruction Overflow Type Figure 1.8: Address xxxxx 16 Address yyyyy 16 M30240M5 00FFF16 F6000 16 M30240M6 00FFF 16 F4000 16 M30240ECFP 017FF16 E0000 16 FFFFF 16 BRK instruction Address match Single step Watchdog timer DBC NMI Reset Memory Map Figure 1.8 is a memory map of the M30240 group. The address space extends the 1M bytes from address 0000016 to FFFFF16. Addresses above yyyyy16 are ROM. For example, in the M30240ECFP, there is 128K bytes of internal ROM from E000016 to FFFFF16. The special page vector table is mapped from FFE0016 to FFFDB16. If the starting addresses of subroutines or the destination addresses of jumps are stored here, subroutine call instructions and jump instructions can be used as two-byte instructions, reducing the number of program steps. The vector table for fixed interrupts such as the reset and NMI are mapped from FFFDC16 to FFFFF16. The starting addresses of the interrupt routines are stored here. The address of the vector table for software interrupts can be set as desired using the internal register (INTB). See Section 2.12 on interrupts for further details. Addresses below xxxxx16 are RAM. For example, in M30240ECFP, 5K bytes of internal RAM are mapped to the space from 0040016 to 017FF16. In addition to storing data, the RAM also stores the stack used when calling subroutines and when interrupts are generated.The SFR area is mapped to 0000016 to 003FF16. This area accommodates control registers for peripheral devices such as I/O ports, A-D converter, serial I/O, and timers. Section 2.4 describes the SFR area for peripheral unit control registers. Any part of the SFR area that is unoccupied is reserved and cannot be used for other purposes. Rev. H Sep 18, 2003 Page 14 of 139 SFR Map M30240 Group 1.2.4 SFR Map The SFR tables show the peripheral control registers, their addresses, acronyms, and values after reset. Address 000016 000116 000216 000316 000416 000516 000616 000716 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16 001016 001116 001216 001316 001416 001516 001616 001716 001816 001916 001A16 001B16 001C16 001D16 001E16 001F16 002016 002116 002216 002316 002416 002516 002616 002716 002816 002916 002A16 002B16 002C16 002D16 002E16 002F16 003016 003116 003216 003316 003416 003516 003616 003716 Register name Acronym Processor mode register 0 Processor mode register 1 System clock control register 0 System clock control register 1 PM0 PM1 CM0 CM1 Address match interrupt enable register Protect register AIER PRCR USB control register USBC Watchdog timer start register Watchdog timer control register WDTS WDC Address match interrupt register 0 RMAD0 Value after reset Figure number 0016 0 0 0 4816 2016 0 0 0 0 0 0016 0 0 0 ? ? ? ? ? 0016 0016 Figure 1.7 Figure 1.7 Figure 1.13 Figure 1.13 Figure 1.16 Figure 1.14 Figure 1.31 Figure 1.22 Figure 1.22 Figure 1.16 0 0 0 0 Address match interrupt register 1 RMAD1 0016 0016 Figure 1.16 0 0 0 0 Reserved USB attach / detach register USBAD DMA0 source pointer SAR0 Figure 1.56 DMA0 destination pointer DAR0 Figure 1.56 DMA0 transfer counter TCR0 Figure 1.56 DMA0 control register DM0CON DMA1 source pointer SAR1 Figure 1.56 DMA1 destination pointer DAR1 Figure 1.56 Rev. H Sep 18, 2003 Page 15 of 139 0016 0 0 0 0 0 ? 0 0 Figure 1.30 Figure 1.55 SFR Map M30240 Group Address 003816 003916 003A16 003B16 003C16 003D16 003E16 003F16 004016 004116 004216 004316 004416 004516 004616 004716 004816 004916 004A16 004B16 004C16 004D16 004E16 004F16 005016 005116 005216 005316 005416 005516 005616 005716 005816 005916 005A16 005B16 005C16 005D16 005E16 005F16 030016 030116 030216 030316 030416 030516 030616 030716 030816 030916 030A16 030B16 030C16 030D16 030E16 030F16 031016 031116 031216 031316 Register name DMA1 transfer counter Acronym DMA1 control register DM1CON USB Suspend interrupt control register SUSPIC USB Resume interrupt control register USB SOF interrupt control register Value after reset Figure number TCR1 Figure 1.56 0 0 0 0 0 ? 0 0 Figure 1.55 ? 0 0 0 Figure 1.16 RSMIC SOFIC ? 0 0 0 0 0 ? 0 0 0 Figure 1.16 Figure 1.16 Bus collision detection interrupt control register DMA0 interrupt control register DMA1 interrupt control register Key input interrupt control register A-D conversion interrupt control register UART2 transmit interrupt control register UART2 receive interrupt control register UART0 transmit interrupt control register UART0 receive interrupt control register UART1 transmit interrupt control register UART1 receive interrupt control register Timer A0 interrupt control register Timer A1 interrupt control register Timer A2 interrupt control register Timer A3 interrupt control register Timer A4 interrupt control register Timer B0 interrupt control register Timer B1 interrupt control register USB Reset interrupt control register INT0 interrupt control register INT1 interrupt control register USB function interrupt control register BCNIC DM0IC DM1IC KUPIC ADIC S2TIC S2RIC S0TIC S0RIC S1TIC S1RIC TA0IC TA1IC TA2IC TA3IC TA4IC TB0IC TB1IC RSTIC INT0IC INT1IC USBFIC ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 0 ? 0 0 ? ? Figure 1.16 Figure 1.16 Figure 1.16 Figure 1.16 Figure 1.16 Figure 1.16 Figure 1.16 Figure 1.16 Figure 1.16 Figure 1.16 Figure 1.16 Figure 1.16 Figure 1.16 Figure 1.16 Figure 1.16 Figure 1.16 Figure 1.16 Figure 1.16 Figure 1.16 Figure 1.16 Figure 1.16 Figure 1.16 USB function address register USB power management register USB interrupt status register 1 USB interrupt status register 2 USB interrupt enable register 1 USB interrupt enable register 2 USB frame number low register USB frame number high register USB ISO control register USB DMA0 Request register USB DMA1 Request register USB Endpoint enable USBA USBPM USBIS1 USBIS2 USBIE1 USBIE2 USBSOFL USBSOFH USBISOC USBSAR0 USBSAR1 USBEPEN 0016 0016 0016 0016 FF16 3316 0016 0016 0016 0016 0016 FF16 Figure 1.32 Figure 1.33 Figure 1.34 Figure 1.35 Figure 1.36 Figure 1.37 Figure 1.38 Figure 1.39 Figure 1.40 Figure 1.41 Figure 1.42 Figure 1.43 EP0CS 0016 Figure 1.44 EP0MP 0816 Figure 1.45 USB reserved USB Endpoint 0 control/status register USB reserved USB Endpoint 0 max packet size register Rev. H Sep 18, 2003 Page 16 of 139 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SFR Map M30240 Group Address 031416 031516 031616 031716 031816 031916 031A16 031B16 031C16 031D16 031E16 031F16 032016 032116 032216 032316 032416 032516 032616 032716 032816 032916 032A16 032B16 032C16 032D16 032E16 032F16 033016 033116 033216 033316 033416 033516 033616 033716 033816 033916 033A16 033B16 033C16 033D16 033E16 033F16 034016 034116 034216 034316 034416 034516 034616 034716 034816 034916 034A16 034B16 034C16 034D16 034E16 034F16 035016 Register name USB reserved USB Endpoint 0 OUT write count USB reserved USB reserved USB reserved USB Endpoint 1 IN control/status register USB Endpoint 1 OUT control/status register USB Endpoint 1 IN max packet size register USB Endpoint 1 OUT max packet size register USB Endpoint 1 OUT write count USB reserved USB reserved USB reserved USB Endpoint 2 IN control/status register USB Endpoint 2 OUT control/status register USB Endpoint 2 IN max packet size register USB Endpoint 2 OUT max packet size register USB Endpoint 2 OUT write count USB reserved USB reserved USB reserved USB Endpoint 3 IN control/status register USB Endpoint 3 OUT control/status register USB Endpoint 3 IN max packet size register USB Endpoint 3 OUT max packet size register USB Endpoint 3 OUT write count USB reserved USB reserved USB reserved USB Endpoint 4 IN control/status register USB Endpoint 4 OUT control/status register USB Endpoint 4 IN max packet size register USB Endpoint 4 OUT max packet size register USB Endpoint 4 OUT write count USB reserved USB reserved USB Endpoint 0 FIFO USB Endpoint 1 FIFO USB Endpoint 2 FIFO USB Endpoint 3 FIFO USB Endpoint 4 FIFO Reserved Reserved Reserved Rev. H Sep 18, 2003 Page 17 of 139 Acronym Value after reset Figure number EP0WC 0016 Figure 1.46 EP1ICS EP1OCS EP1IMP EP1OMP EP1WC 0016 0016 0016 0016 0016 Figure 1.47 Figure 1.48 Figure 1.49 Figure 1.50 Figure 1.51 EP2ICS EP2OCS EP2IMP EP2OMP EP2WC 0016 0016 0016 0016 0016 Figure 1.47 Figure 1.48 Figure 1.49 Figure 1.50 Figure 1.51 EP3ICS EP3OCS EP3IMP EP3OMP EP3WC 0016 0016 0016 0016 0016 0016 Figure 1.47 Figure 1.48 Figure 1.49 Figure 1.50 Figure 1.51 EP4ICS EP4OCS EP4IMP EP4OMP EP4WC 0016 0016 0016 0016 0016 Figure 1.47 Figure 1.48 Figure 1.49 Figure 1.50 Figure 1.51 EP0 EP1 EP2 EP3 EP4 Figure 1.52 Figure 1.52 Figure 1.52 Figure 1.52 Figure 1.52 SFR Map M30240 Group Address 035116 035216 035316 035416 035516 035616 035716 035816 035916 035A16 035B16 035C16 035D16 035E16 035F16 037016 037116 037216 037316 037416 037516 037616 037716 037816 037916 037A16 037B16 037C16 037D16 037E16 037F16 038016 038116 038216 038316 038416 038516 038616 038716 038816 038916 038A16 038B16 038C16 038D16 038E16 038F16 039016 039116 039216 039316 039416 039516 Register name Acronym Reserved UART2 transmit / receive mode register UART2 bit rate generator UART2 transmit buffer register U2MR U2BRG UART2 transmit / receive control register 0 UART2 transmit / receive control register 1 UART2 receive buffer register Value after reset Figure number 0016 Figure 1.77 Figure 1.76 U2TB Figure 1.76 0816 0216 U2C0 U2C1 U2RB Figure 1.76 TABSR Count start flag Reserved One-shot start flag Trigger select register Up/down flag Timer A0 Timer A1 Timer A2 Timer A3 Timer A4 Timer B0 Timer B1 Timer B2 ONSF TRGSR UDF 0 0 0016 Figure 1.61 0 0 0 0 0 0016 0016 Figure 1.62 Figure 1.62 Figure 1.61 TA0 Figure 1.61 TA1 Figure 1.61 TA2 Figure 1.61 TA3 Figure 1.61 TA4 Figure 1.61 TB0 Figure 1.72 TB1 Figure 1.72 TB2 Figure 1.72 039616 Timer A0 mode register TA0MR 0016 039716 Timer A1 mode register TA1MR 0016 Rev. H Sep 18, 2003 Page 18 of 139 Figure 1.78 Figure 1.79 Figure 1.63 Figure 1.64 Figure 1.66 Figure 1.68 Figure 1.63 Figure 1.64 Figure 1.66 Figure 1.68 SFR Map M30240 Group Address Register name Acronym Timer A2 mode register 039816 TA2MR 039916 Timer A3 mode register TA3MR 039A16 Timer A4 mode register TA4MR 039B16 039C16 039D16 039E16 039F16 03A016 03A116 03A216 03A316 03A416 03A516 03A616 03A716 03A816 03A916 03AA16 03AB16 03AC16 03AD16 03AE16 03AF16 03B016 03B116 03B216 03B316 03B416 03B516 03B616 03B716 03B816 03B916 03BA16 03BB16 03BC16 03BD16 03BE16 03BF16 03C016 03C116 03C216 03C316 03C416 03C516 03C616 03C716 03C816 03C916 03CA16 03CB16 Timer B0 mode register Timer B1 mode register Value after reset Figure number Figure 1.63 Figure 1.64 0016 Figure 1.65 Figure 1.66 Figure 1.68 Figure 1.63 Figure 1.66 0016 Figure 1.65 Figure 1.68 Figure 1.63 Figure 1.65 0016 Figure 1.66 Figure 1.68 0 0 ? 0 0 0 0 Figure 1.71 0 0 ? 0 0 0 0 Figure 1.71 0 0 ? 0 0 0 0 Figure 1.71 Timer B2 mode register TB0MR TB1MR TB2MR UART0 transmit / receive mode register UART0 bit rate generator U0MR U0BRG UART0 transmit buffer register U0TB UART0 transmit / receive control register 0 UART0 transmit / receive control register 1 U0C0 U0C1 UART0 receive buffer register U0RB UART1 transmit / receive mode register UART1 bit rate generator U1MR U1BRG UART1 transmit buffer register U1TB UART1 transmit / receive control register 0 UART1 transmit / receive control register 1 U1C0 U1C1 UART1 receive buffer register U1RB UART transmit / receive control register 2 UCON DMA0 Request cause select register DM0SL 0016 Figure 1.54 DMA1 Request cause select register DM1SL 0016 Figure 1.54 CRC data register CRCD Figure 1.105 CRC input register CRCIN Figure 1.105 A-D register 0 AD0 Figure 1.98 A-D register 1 AD1 Figure 1.98 A-D register 2 AD2 Figure 1.98 A-D register 3 AD3 Figure 1.98 A-D register 4 AD4 Figure 1.98 A-D register 5 AD5 Figure 1.98 Rev. H Sep 18, 2003 Page 19 of 139 0016 Figure 1.77 Figure 1.76 Figure 1.76 0816 0216 Figure 1.78 Figure 1.79 Figure 1.76 0016 Figure 1.77 Figure 1.76 Figure 1.76 0816 0216 Figure 1.77 Figure 1.79 Figure 1.76 0 0 0 0 0 0 0 Figure 1.80 SFR Map M30240 Group Address 03CC16 03CD16 03CE16 03CF16 03D016 03D116 03D216 03D316 03D416 03D516 03D616 03D716 03D816 03D916 03DA16 03DB16 03DC16 03DD16 03DE16 03DF16 03E016 03E116 03E216 03E316 03E416 03E516 03E616 03E716 03E816 03E916 03EA16 03EB16 03EC16 03ED16 03EE16 03EF16 03F016 03F116 03F216 03F316 03F416 03F516 03F616 03F716 03F816 03F916 03FA16 03FB16 03FC16 03FD16 03FE16 03FF16 Register name Acronym A-D register 6 AD6 Figure 1.98 A-D register 7 AD7 Figure 1.98 A-D control register 2 ADCON2 0 Figure 1.98 A-D control register 0 A-D control register 1 ADCON0 ADCON1 0 0 0 0 0 ? ? ? 0016 Figure 1.97 Figure 1.97 Frequency synthesizer clock control Frequency synthesizer control Frequency synthesizer multiplier control Frequency synthesizer prescaler control Frequency synthesizer divider Port P0 Port P1 Port P0 direction register Port P1 direction register Port P2 Port P3 Port P2 direction register Port P3 direction register FSCCR FSC FSM FSP FSD P0 P1 PD0 PD1 P2 P3 PD2 PD3 0016 6016 FF16 FF16 FF16 Figure 1.28 Figure 1.27 Figure 1.25 Figure 1.24 Figure 1.26 Figure 1.110 Figure 1.110 Figure 1.109 Figure 1.109 Figure 1.110 Figure 1.110 Figure 1.109 Figure 1.109 Port P6 Port P7 Port P6 direction register Port P7 direction register Port P8 P6 P7 PD6 PD7 P8 Port P8 direction register PD8 Port P10 P10 Port P10 direction register PD10 0016 Figure 1.109 P2 drive capacity Timer A Output Drive Capacity Pull-up control register 0 Pull-up control register 1 P2DR TADR PUR0 PUR1 0016 0016 0016 0016 Figure 1.112 Figure 1.112 Figure 1.111 Figure 1.111 Rev. H Sep 18, 2003 Page 20 of 139 Value after reset Figure number 0016 0016 0016 0016 0016 0016 0 0 0 0 0 0 0 Figure 1.110 Figure 1.110 Figure 1.109 Figure 1.109 Figure 1.110 Figure 1.109 Figure 1.110 Reset M30240 Group 1.2.5 Reset There are two types of resets: hardware and software. In both cases, operation is the same after the reset. 1.2.5.1 Hardware reset When the supply voltage is within the range where operation is guaranteed, a reset is effected by holding the reset pin level "L" (0.2Vcc max.) for at least 20 f(XIN) cycles. When the reset pin level is then returned to the "H" level while main clock is stable, the reset status is cancelled and program execution resumes from the address in the reset vector table. Figure 1.9 shows an example of a reset circuit. Figure 1.10 shows the reset sequence. . 5V 4.0V VCC RESET 0V 5V VCC RESET 0.8V 0V Example when VCC = 5V Figure 1.9: Reset circuit XIN At least 20 cycles are needed Internal clock 24 cycles RESET Internal clock FFFFC 16 Address Content of reset vector FFFFE16 Figure 1.10: Reset sequence When the RESET pin level = "L", all ports change to input mode (floating.) Table 1.4 shows the status of the other pins while the RESET pin level is "L". Table 1.4: Pin status when RESET pin level is "L" Pin name Status P0 Input port (floating) P1 Input port (floating) P2, P3 Input port (floating) P6, P7, P80 to P84, P86, P87, P10 Input port (floating) Rev. H Sep 18, 2003 Page 21 of 139 Clock-Generating Circuit M30240 Group 1.2.5.2 Software Reset Writing a "1" to bit 3 of the processor mode register 0 (address 000416) applies a (software) reset to the microcomputer. A software reset has almost the same effect as a hardware reset with the following exceptions: The contents of internal RAM are preserved USB registers (030016 to 033C16), USB attach/detach register (001F16), USB control register (000C16), and Frequency synthesizer related registers (03DB16-03DF16) values are preserved. 1.2.6 Clock-Generating Circuit The clock-generating circuit contains one oscillator circuit that supplies the operating clock sources to the CPU and internal peripheral units. Table 1.5 shows the main clock generating circuits. Table 1.5: Main clock-generating circuits Functions Main clock-generating circuit Use of clock * CPU's operating clock source * Internal peripheral units' operating clock source Usable oscillator Ceramic or crystal oscillator Pins to connect oscillator Xin, Xout Oscillation stop/restart function Available Oscillator status immediately after reset Oscillating Figure 1.11 shows some examples of the main clock circuit, one using an oscillator connected to the circuit, and the other one using an externally derived clock for input. Circuit constants in Figure 1.11 vary with each oscillator used. Use circuit constant values recommended by the oscillator manufacturer. Microcomputer Microcomputer (Built-in feedback resistor) (Built-in feedback resistor) X in Xin Xout Xout Open (Note) Rd Externally derived clock Cin Cout Vcc Vss Note: Insert a damping resistor if required. The resistance will vary depending on the oscillator and the oscillation drive capacity setting. Use the value recommended by the maker of the oscillator. When the oscillation drive capacity is set to low, check that oscillation is stable. Figure 1.11: Examples of clock source 1.2.6.1 Clock Control Figure 1.12 shows the block diagram of the clock-generating circuit. Rev. H Sep 18, 2003 Page 22 of 139 Clock-Generating Circuit M30240 Group XIN XOUT fusb (48MHz) Main clock Frequency Synthesizer Circuit fAD fsyn f1SIO2 f1 CM10 "1" Write signal FSCCR0=1 f8 FSCCR0=0 f32 f8SIO2 f32 SIO2 S Q b R a c d Divider RESET BCLK Software reset CM02 NMI Interrupt request level judgment output S Q WAIT instruction R c b a 1/2 1/2 1/2 1/2 1/2 CM06=0 CM17,CM16=11 CM06=1 CM06=0 CM17,CM16=10 d CM06=0 CM17,CM16=01 CM06=0 CM17,CM16=00 CM0i : Bit i at address 000616 CM1i : Bit i at address 000716 FSCCRi: Bit i at address 03DB16 Details of divider Figure 1.12: Clock-generating circuit 1.2.6.2 Clocks generated by the clock-generating circuit. Main clock The main clock is generated by the main clock oscillation circuit. After a reset, the clock is divided by 8 to the internal clock . After the oscillation of the main clock oscillation circuit has stabilized, the drive capacity of the XOUT pin can be reduced using the XIN - XOUT) drive capacity select bit (bit 5 at address 000716). Reducing the drive capacity of the XOUT pin reduces the power dissipation. This bit defaults to "1" when shifting to stop mode and after a reset. Internal clock The internal clock is the clock that drives the CPU, and is either the main clock or is derived by dividing the main clock by 2, 4, 8, or 16. The internal clock is derived by dividing the main clock by 8 after a reset. When shifting to stop mode, the main clock division select bit (bit 6 at 000616) is set to "1". Peripheral Function clock * f1, f8, f32 The clock for the peripheral devices is derived from the main clock or by dividing it by 8 or 32. The peripheral function clock is stopped by stopping the main clock or by setting the WAIT peripheral function clock stop bit (bit 2 at 000616) to "1" and then executing a WAIT instruction. Rev. H Sep 18, 2003 Page 23 of 139 Clock-Generating Circuit M30240 Group * fAD This clock has the same frequency as the main clock and is used for A-D conversion. * fUSB This is the 48mHz clock that is used for USB operation. This clock is generated from the main clock by the frequency synthesizer circuit. 1.2.6.3 Clock Output In single-chip mode, the clock output function select bits (bits 0 and 1 at address 000616) enable f8 or f32 to be output from the P37/CLKOUT pin. When the WAIT peripheral function clock stop bit (bit 2 at address 000616) is set to "1", the output of f8 and f32 stops when a WAIT instruction is executed. Figure 1.13 shows the system clock control registers 0 and 1. System clock control register 0 (Note 1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol CM0 Address 0006 16 Bit symbol When reset 48 16 Bit name Clock output function select bit CM00 CM01 WAIT peripheral function clock stop bit CM02 Function Reserved bit Always set to "1" Reserved bit Always set to "0" Reserved bit Always set to "0" Main clock division select bit 0 (Note 2) CM06 RW b1 b0 0 0 : I/O port P3 7 0 1 : Invalid 1 0 : f 8 output 1 1 : f 32 output 0 : Do not stop f 1, f 8, f32 in wait mode 1 : Stop f 1, f8, f 32 in wait mode 0 : CM16 and CM17 valid 1 : Division by 8 mode Always set to "0" Reserved bit Note 1: Set bit 0 of the Protect register (address 000A16) to "1" before writing to this register. Note 2: Changes to "1" when shifting to stop mode. System clock control register 1 (Note 1) b7 b6 b5 b4 b3 b2 b1 0 0 0 0 b0 Symbol CM1 Address 0007 16 Bit symbol CM10 Bit name All clock stop control bit Reserved bit CM15 CM16 When reset 2016 XIN-XOUT drive capacity select bit (Note 2) Main clock division select bit 1 (Note 3) CM17 Function RW 0 : Clock on 1 : All clocks off (stop mode) oo Always set to "0" oo 0 : LOW 1 : HIGH oo b7 b6 0 0 : No division mode 0 1 : Division by 2 mode 1 0 : Division by 4 mode 1 1 : Division by 16 mode oo Note 1: Set bit 0 of the Protect register (address 000A16) to "1" before writing to this register. Note 2: Changes to "1" when shifting to stop mode. Note 3: Can be selected when bit 6 of the System clock control register 0 (address 000616) is "0". If "1", division mode is fiixed at "8". Figure 1.13: System clock control registers 0 and 1 Rev. H Sep 18, 2003 Page 24 of 139 Stop Mode M30240 Group 1.2.7 Stop Mode Writing "1" to the all-clock stop control bit (bit 0 at address 000716 ) stops all oscillation and the microcomputer enters stop mode. In stop mode, the content of the internal RAM is retained provided that VCC remains above 2V. Because the oscillation of internal clock , f1 to f32, and fAD stops in stop mode, peripheral functions such as the A-D converter and watchdog timer do not function. However, timer A operates, provided that the event counter mode is set to an external pulse, and UARTi (i = 0 to 2) functions provided an external clock is selected. Table 1.6 shows the status of the ports in stop mode. Stop mode is cancelled by a hardware reset or interrupt. If an interrupt is to be used to cancel stop mode, that interrupt must first have been enabled. The I flag must also be set prior to stopping for an interrupt to cancel it. After coming out of stop mode, it is recommended that four "NOP" instructions be executed to clear the instruction queue. When shifting to stop mode, the main clock division select bit 0 (bit 6 at 000616) is set to "1". Table 1.6: Port status during stop mode Pin Single-chip mode Port Retains status before stop mode CLKOUT Retains status before stop mode 1.2.8 Wait Mode When a WAIT instruction is executed, the internal clock stops and the microcomputer enters the wait mode. In this mode, oscillation continues but the internal clock and watchdog timer stop. Writing "1" to the WAIT peripheral function clock stop bit and executing a WAIT instruction stops the clock being supplied to the internal peripheral functions, allowing power dissipation to be reduced. Table 1.7 shows the status of the ports in wait mode. Wait mode is cancelled by a hardware reset or interrupt. If an interrupt is used to cancel wait mode, the microcomputer restarts using as internal clock the clock that had been selected when the WAIT instruction was executed. Table 1.7: Port status during wait mode Pin Single-chip mode Port Retains status before stop mode CLKOUT Does not stop when the WAIT peripheral function clock stop bit is "0". When the WAIT peripheral function clock stop bit is "1", the status immediately prior to entering WAIT mode is maintained. 1.2.9 Status Transition Of Internal Clock Power dissipation can be reduced and low-voltage operation achieved by changing the count source for internal clock . Table 1.8 shows the operating modes corresponding to the settings of system clock control registers 0 and 1. After a reset, operation defaults to division by 8 mode. When shifting to stop mode, the main clock division select bit 0 (bit 6 at address 000616) is set to "1". The following shows the operational modes of internal clock * Division by 2 mode The main clock is divided by 2 to obtain the internal clock . Rev. H Sep 18, 2003 Page 25 of 139 Power Control M30240 Group * Division by 4 mode The main clock is divided by 4 to obtain the internal clock . * Division by 8 mode The main clock is divided by 8 to obtain the internal clock . Note that oscillation of the main clock must have stabilized before transferring from this mode to another mode. * Division by 16 mode The main clock is divided by 16 to obtain the internal clock . * No-division mode The main clock is used as internal clock. Table 1.8: Operating modes dictated by settings of system clock control registers 0 and 1 CM17 CM16 CM06 Operating mode of internal clock 0 1 0 Division by 2 mode 1 0 0 Division by 4 mode Invalid Invalid 1 Division by 8 mode 1 1 0 Division by 16 mode 0 0 0 No-division mode 1.2.10 Power Control The following is a description of the three available power control modes: 1.2.10.1 Normal Operation Mode * High-speed mode Divide-by-1 frequency of the main clock become the internal clock . The CPU operates with the internal clock selected. Each peripheral function operates according to its assigned clock. * Medium-speed mode Divide-by-2, divide-by-4, divide-by-8, or divide-by-16 frequency of the main clock becomes the internal clock . The CPU operates according to the internal clock selected. Each peripheral function operates according to its assigned clock. 1.2.10.2 Wait mode The CPU operation is stopped. The oscillators do not stop. 1.2.10.3 Stop Mode All oscillators stop. The CPU and all built-in peripheral functions stop. Of the three modes listed, this mode is the most effective in decreasing power consumption. Rev. H Sep 18, 2003 Page 26 of 139 Protection M30240 Group 1.2.11 Protection The protection function is provided so that the values in important registers cannot be changed in the event that the program runs out of control. Figure 1.14 shows the protect register. The values in the processor mode register 0 (address 000416), processor mode register 1 (address 000516), system clock control register 0 (address 000616), system clock control register 1 (address 000716) and frequency synthesizer registers can only be changed when the respective bit in the protect register is set to "1". The system clock control registers 0 and 1 write-enable bit (bit 0 at 000A16) and processor mode register 0 and 1 write-enable bit (bit 1 at 000A16) do not automatically return to "0" after a value has been written to an address. The program must therefore be written to return these bits to "0". Protect register b7 b6 b5 b4 b3 b2 b1 b0 O Symbol PRCR Address 000A 16 When reset XXXXX000 2 Bit symbol Bit name PRC0 Enables writing to system clock control registers 0 and 1 (addresses 0006 16 and 0007 16) and frequency Function 0 : Write-inhibited 1 : Write-enabled synthesizer registers (addresses 03DB 16 to 03DF 16) PRC1 Reserved bit Enables writing to processor mode 0 : Write-inhibited registers 0 and 1 (addresses 0004 16 1 : Write-enabled and 0005 16) Must always be set to "0" Nothing is assigned. These bits can neither be set nor reset. When read, their contents are indeterminate. Figure 1.14: Protect register Rev. H Sep 18, 2003 Page 27 of 139 R W Interrupts M30240 Group 1.2.12 Interrupts Table 1.9 and Table 1.10 show the interrupt sources and vector table addresses. When an interrupt is received, the program is executed from the address shown by the respective interrupt vector. The vector table addresses for the interrupts in Table 1.9 are fixed (interrupt vector addresses). These interrupts are not affected by the interrupt enable flag (I flag) (non-maskable interrupts). The vector table addresses for the interrupts in Table 1.10 are variable, being determined as relative to the fixed address in the interrupt table register (INTB). These interrupts can be enabled or disabled using the interrupt enable flag (I flag) (maskable interrupts). Sixty four vectors can be set in the interrupt table register (INTB). Any of software interrupts 0 to 63 can be assigned to each vector. By using the INT instruction to specify a software interrupt number, the program can be executed starting at the address indicated by the respective vector. The BRK instruction interrupt has interrupt vectors in both the fixed vector address and variable vector address. When the contents of FFFE416 through FFFE716 are all "FF16", the program is executed from the address shown in the BRK instruction interrupt vector in the variable vector address. Specify the starting address of the interrupt program in the interrupt vector. Figure 1.15 shows the format for specifying the address. Table 1.9: Interrupt vectors with fixed addresses Interrupt source Vector table addresses Address(L) to Address(H) Remarks Undefined instruction FFFDC16 to FFFDF16 Interrupt on UND instruction Overflow FFFE016 to FFFE316 Interrupt on INTO instruction BRK instruction FFFE416 to FFFE716 If the vector is filled with FF16, program execution starts from the address shown by the vector in the variable vector table Address Match FFFE816 to FFFEB16 There is an address-matching interrupt enable bit Single Step (Note) FFFEC16 to FFFEF16 Do not use Watchdog timer FFFF016 to FFF316 DBC (Note) FFFF416 to FFFF716 Do not use NMI FFFF816 to FFFFB16 External interrupt by NMI pin Reset FFFFC16 to FFFFF16 Note: Interrupts used for debugging purposes only MSB Vector address + 0 Vector address + 1 LSB Low address Mid address Vector address + 2 0000 High address Vector address + 3 0000 0000 Figure 1.15: Format for specifying interrupt vector addresses Rev. H Sep 18, 2003 Page 28 of 139 Interrupts M30240 Group Table 1.10: Interrupt vectors with variable addresses) Software interrupt number Vector table addresses Address(L) to Address(H) (Note 1) Interrupt source Software interrupt number 0 +0 to +3 BRK instruction Software interrupt number 4 +16 to +19 USB Suspend Software interrupt number 6 +24 to +27 USB Resume Software interrupt number 7 +28 to +31 USB Start of Frame Software interrupt number 10 +40 to +43 Bus collision detection Software interrupt number 11 +44 to +47 DMA0 Software interrupt number 12 +48 to +51 DMA1 Software interrupt number 13 +52 to +55 Key input interrupt Software interrupt number 14 +56 to +59 A-D Software interrupt number 15 +60 to +63 UART2 transmit Software interrupt number 16 +64 to +67 UART2 receive Software interrupt number 17 +68 to +71 UART0 transmit Software interrupt number 18 +72 to +75 UART0 receive Software interrupt number 19 +76 to +79 UART1 transmit Software interrupt number 20 +80 to +83 UART1 receive Software interrupt number 21 +84 to +87 Timer A0 Software interrupt number 22 +88 to +91 Timer A1 Software interrupt number 23 +92 to +95 Timer A2 Software interrupt number 24 +96 to +99 Timer A3 Software interrupt number 25 +100 to +103 Timer A4 Software interrupt number 26 +104 to +107 Timer B0 Software interrupt number 27 +108 to +111 Timer B1 Software interrupt number 28 +112 to +115 USB Reset Software interrupt number 29 +116 to +119 INT0 Software interrupt number 30 +120 to +123 INT1 Software interrupt number 31 +124 to +127 USB Function Software interrupt number 32 to Software interrupt number 63 +128 to +131 Software interrupt +252 to +255 Note:Address relative to address in interrupt table base address register (INTB) Rev. H Sep 18, 2003 Page 29 of 139 Remarks Cannot be masked by I flag Cannot be masked by I flag Interrupts M30240 Group 1.2.12.1 Interrupt control registers Peripheral I/O interrupts have their own interrupt control registers. Table 1.11 shows the addresses of the interrupt control registers. Figure 1.16 shows the interrupt control registers. The interrupt request bit is set by hardware to "0" when an interrupt request is received. The interrupt request bit can also be set by software to "0". (Do not set to "1".) INT0 and INT1 are triggered by the edges of external inputs. The edge polarity is selected using the polarity select bit. (Other interrupts are described elsewhere.) An interrupt must first be enabled before it can be used to cancel stop mode. Table 1.11: Addresses in interrupt control register Symbol name Address USB Suspend Interrupt SUSPIC 004416 UART1 receive S1RIC 005416 USB Resume interrupt RSMIC 004616 Timer A0 TA0IC 005516 USB Start Of Frame SOFIC 004716 Timer A1 TA1IC 005616 Bus collision detection BCNIC 004A16 Timer A2 TA2IC 005716 DMA0 DM0IC 004B16 Timer A3 TA3IC 005816 DMA1 DM1IC 004C16 Timer A4 TA4IC 005916 Key input interrupt KUPIC 004D16 Timer B0 TB0IC 005A16 A-D ADIC 004E16 Timer B1 TB1IC 005B16 UART2 transmit S2TIC 004F16 USB Reset RSTIC 005C16 UART2 receive S2RIC 005016 INT0 INT0IC 005D16 UART0 transmit S0TIC 005116 INT1 INT1IC 005E16 UART0 receive S0RIC 005216 USB Function USBFIC 005F16 UART1 transmit S1TIC 005316 Interrupt control register Rev. H Sep 18, 2003 Page 30 of 139 Interrupt control register Symbol name Address Interrupts M30240 Group Interrupt control register b7 b6 b5 b4 b3 b2 b1 Symbol SUSPIC RSMIC BCNIC DMiIC(i=0, 1) KUPIC ADIC SiTIC(i=0 to 2) SiRIC(i=0 to 2) TAiIC(i=0 to 4) TBiIC(i=0 to 1) RSTIC USBFIC b0 Bit symbol ILVL0 Address When reset 004416 004616 004A16 004B16, 004C16 004D16 004E16 005116, 0053 16, 004F 16 005216, 0054 16, 0050 16 005516 to 0059 16 005A16 to 005B 16 005C16 005F16 XXXXX000 2 XXXXX000 2 XXXXX000 2 XXXXX000 2 XXXXX000 2 XXXXX000 2 XXXXX000 2 XXXXX000 2 XXXXX000 2 XXXXX000 2 XXXXX000 2 XXXXX000 2 Bit name Interrupt priority level select bit ILVL1 ILVL2 IR Interrupt request bit Function R W b2 b1 b0 000: 001: 010: 011: 100: 101: 110: 111: Level Level Level Level Level Level Level Level 0 (interrupt disabled) 1 2 3 4 5 6 7 0 : Interrupt not requested 1 : Interrupt requested (Note) Nothing is assigned. These bits can neither be set nor reset. When read, their contents are indeterminate. Note 1: This bit can only be reset (= 0), but cannot be set ( = 1). Note 2: When rewriting the interrupt control register, do so at a point that does not generate an interrupt requst for that register. For details, see the interrupt precaution section. b7 b6 b5 b4 b3 b2 b1 Symbol INTiIC ( i= 0, 1) SOFIC b0 0 Bit symbol ILVL0 Address 005D16, 005E16 004716 Bit name Interrupt priority level select bit ILVL1 ILVL2 IR POL When reset XX00X000 2 XX00X000 2 Interrupt request bit Polarity select bit Reserved bit Function R 0 0 0 : Level 0 0 1 : Level 0 1 0 : Level 0 1 1 : Level 1 0 0 : Level 1 0 1 : Level 1 1 0 : Level 1 1 1 : Level 0 (interrupt disabled) 1 2 3 4 5 6 7 0: Interrupt not requested 1: Interrupt requested 0 : Selects falling edge 1 : Selects rising edge Must always be set to "0" Nothing is assigned. These bits can neither be set nor reset. When read, their contents are indeterminate. Note 1: This bit can only be reset (=0), but cannot be set (=1). Note 2: For SOFIC (address 0047 1 6 ), a "0" should always be written. Note 3: When rewriting the interrupt control register, do so at a point that does not generate an interrupt requst for that register. For details, see the interrupt precaution section. Figure 1.16: Interrupt control registers Rev. H Sep 18, 2003 Page 31 of 139 W b2 b1 b0 (Note 1) (Note 2) M30240 Group Interrupts 1.2.12.2 Interrupt priority The order of priority when two or more interrupts are generated simultaneously is determined by both hardware and software. The interrupt priority levels determined by hardware are Reset > NMI > DBC > Watchdog timer > peripheral I/O interrupts > single-step > Address matching interrupt. The interrupt priority levels determined by software are set in the interrupt control registers. Figure 1.17 shows the circuit that judges the interrupt hardware priority level. When two or more interrupts are generated simultaneously, the interrupt with the higher software priority is selected. However, if the interrupts have the same software priority level, the interrupt is selected according to the hardware priority set in the circuit. The selected interrupt is accepted only when the priority level is higher than the processor interrupt priority level (IPL) in the flag register (FLG) and the interrupt enable flag (I flag) is "1". Note that the reset, NMI, DBC, watchdog timer, single-step, address-match, BRK instruction, overflow, and undefined instruction interrupts are accepted regardless of the interrupt enable flag (I flag). Rev. H Sep 18, 2003 Page 32 of 139 Interrupts M30240 Group Priority level of each interrupt INT1 Level 0 (initial value) High USB Reset Timer B0 Timer A3 Timer A1 USB Resume USB Suspend USB Function INT0 Timer B1 Timer A4 Timer A2 USB SOF UART1 reception UART0 reception UART2 reception A-D conversion Priority of peripheral I/O interrupts (if priority levels are same) DMA1 Bus collision detection Timer A0 UART1 transmission UART0 transmission UART2 transmission Key input interrupt DMA0 Processor interrupt priority level (IPL) Low Interrupt enable flag (I flag) Address match Watchdog timer DBC NMI Reset Figure 1.17: Interrupt resolution circuit Rev. H Sep 18, 2003 Page 33 of 139 Interrupt request accepted NMI Interrupt M30240 Group 1.2.12.3 Flag changes When an interrupt request is received, the stack pointer select flag (U flag) changes to "0" and the flag register (FLG) and program counter (PC) are saved to the stack area indicated by the interrupt stack pointer (ISP). Thereafter, the interrupt enable flag (I flag) and debug flag (D flag) change to "0" and the processor interrupt priority level (IPL) at the flag register (FLG) is replaced by the priority level of the received interrupt. However, when interrupt requests are received for software interrupts 32 to 63, the flag register (FLG) and program counter (PC) are saved to the stack shown by the stack pointer select flag (U flag) at the time the interrupt was received. The stack pointer select flag (U flag) does not change. The value of the processor interrupt priority level (IPL) in the flag register (FLG) differs in the case of reset, NMI, DBC, watchdog timer, single-step, address-match, BRK instruction, overflow, and undefined instruction interrupts. Table 1.12 shows how the IPL changes when interrupt requests are received. Table 1.12: Change of IPL state when interrupt request are accepted Interrupt Change of IPL Reset Level 0 (0002), is set NMI Level 7 (1112), is set DBC Does not change Watchdog timer Level 7 (1112), is set Single step Does not change Address match Does not change Software interrupt Does not change 1.2.13 NMI Interrupt An NMI interrupt is generated when the input to the P85/NMI pin changes from "H" to "L". The NMI interrupt is a non-maskable external interrupt. The pin level can be checked in the Port P85 register (bit 5 at address 03F016). This pin cannot be used as a normal port input. Notes: 1. When not intending to use the NMI function, be sure to connect the NMI pin to VCC. Because the NMI interrupt is non-maskable, it cannot be disabled. 2. When the NMI pin input is "L", do not set the microcomputer in stop mode or wait mode. The NMI interrupt is triggered by the falling edge, so the "L" level does not need to be maintained longer than necessary. Rev. H Sep 18, 2003 Page 34 of 139 Key input interrupt M30240 Group 1.2.14 Key input interrupt If the direction register of any of pin of Port0 or Port1 is set for input and a falling edge is input to that port, a key-input interrupt is generated. A key-input interrupt can also be used as a key-on wakeup function for cancelling the wait mode or stop mode. Figure 1.18 shows the block diagram of the key-input interrupt. Port P0i pull-up select bit (Pull-up transistor) Port P0i direction register Key input interrupt control circuit (address 004D16) i=0; j=0~7 Port P0i/KIj KI0 Port PXi pull-up select bit (Pull-up transistor) Interrupt control circuit Port P1i direction register Key input interrupt request i=0~7; j=8~15 Port P1i/KIj KI15 Figure 1.18: Block diagram of key input interrupt 1.2.14.1 Enable/Disable The key-input interrupt can be enabled and disabled using the key-input interrupt register (004D16). The key-input interrupt is affected by the interrupt priority level (IPL) and the interrupt enable flag (I flag). 1.2.14.2 Occurrence timing of the key-input interrupt With key-input interrupt acceptance enabled, ports P0 and P1, which are set to input, become keyinput interrupt pins (KI0 through KI15). A key-input interrupt occurs when a falling edge is input to a key-input interrupt pin. At this moment, the level of other key-input interrupt pins must be "H". No interrupt occurs when the level of any other key-input interrupt pins is "L". 1.2.14.3 How to determine a key-input interrupt A key-input interrupt occurs when a falling edge is input to one of 16 pins, but each pin has the same vector address.Therefore, read the input level of ports P0 and P1 in the key-input interrupt routine to determine the interrupted pin. 1.2.14.4 Related registers Figure 1.19 shows the memory map of key-input interrupt-related registers Register name Address 004E16 004D16 Key input interrupt register ~ ~ 03E016 Port 0 03E116 Port 1 03E216 Port 0 direction register 03E316 Port 1 direction register 03E416 ~ ~ 03FA16 03FB16 03FC16 Pull-up control register 0 03FD16 Pull-up control register 1 03FE16 03FF16 Acronym KUPIC ~ ~ P0 P1 PD0 PD1 ~ ~ PUR0 PUR1 Figure 1.19: Memory Map of key input interrupt related registers Rev. H Sep 18, 2003 Page 35 of 139 Address Match Interrupt M30240 Group 1.2.15 Address Match Interrupt An address match interrupt is generated when the address match interrupt address register contents match the program counter value. Two address match interrupts can be set, each of which can be enabled and disabled by an address match interrupt enable bit. Address match interrupts are not affected by the interrupt enable flag (I flag) and processor interrupt priority level (IPL). Figure 1.20 shows the address match interrupt-related registers. Address match interrupt enable register b7 b6 b5 b4 b3 b2 b1 b0 Symbol AIER Address 0009 16 Bit symbol When reset XXXXXX00 2 Bit name Function AIER0 Address match interrupt 0 enable bit 0 : Interrupt disabled 1 : Interrupt enabled AIER1 Address match interrupt 1 enable bit 0 : Interrupt disabled 1 : Interrupt enabled RW Nothing is assigned. Write 0 when writing to these bits. If read, the value is indeterminate. Address match interrupt register i (i = 0, 1) (b23) b7 (b19) b3 (b16)(b15) b0 b7 (b8) b0 b7 b0 Symbol RMAD0 RMAD1 Address 001216 to 0010 16 001616 to 0014 16 Function Address setting register for address match interrupt When reset X00000 16 X00000 16 Values that can be set R W 00000 16 to FFFFF 16 Nothing is assigned. Write 0 when writing to these bits. If read, the value is indeterminate. Figure 1.20: Address match interrupt-related registers 1.2.16 Watchdog Timer The watchdog timer has the function of detecting when the program is out of control. The watchdog timer is a 15-bit counter that decrements using the clock derived by dividing the internal clock using the prescaler. A watchdog timer interrupt is generated when an underflow occurs in the watchdog timer. Bit 7 of the watchdog timer control register (address 000F16) selects the prescaler division ratio (by 16 or 128). Table 1.13 shows the periodic table for the watchdog timer. Table 1.13: Watchdog timer periodic table (f(XIN)=12MHz) CM06 CM17 CM16 Internal clock 0 0 0 12MHz 0 0 0 1 0 1 1 Invalid 1 0 1 Invalid WDC7 Period (Note) 0 Approx. 43.7ms 1 Approx. 349.5ms 0 Approx. 87.4ms 1 Approx. 699.1ms 0 Approx. 174.8ms 1 Approx. 1.40s 0 Approx. 699.1ms 1 Approx. 5.59s 0 Approx. 349.5ms 1 Approx. 2.80s 6MHz 3MHz 0.75MHz 1.5MHz Note: The watchdog timer's period is subject to some error due to the prescaler. Rev. H Sep 18, 2003 Page 36 of 139 Watchdog Timer M30240 Group The watchdog timer is initialized by writing to the watchdog timer start register (address 000E16) and when a watchdog timer interrupt request is generated. The prescaler is initialized only when the microcomputer is reset. After a reset, the watchdog timer and prescaler are both stopped. The count is started by writing to the watchdog timer start register (address 000E16). Figure 1.21 shows the block diagram of the watchdog timer. Figure 1.22 shows the watchdog timerrelated registers. 1/16 WDC7 = 0 Internal clock Watchdog timer 1/128 Watchdog timer interrupt request WDC7 = 1 Prescaler Write to the watchdog timer start register (address 000E16) Set to 7FFF16 RESET Figure 1.21: Block diagram of watchdog timer Watchdog timer control register (Note) b7 b6 b5 b4 b3 b2 b1 b0 Symbol WDC 0 0 Bit symbol Address 000F 16 When reset 000XXXXX 2 Bit name Function R W High-order bit of Watchdog timer Reserved bit WDC7 Must always be set to "0" 0 : Divided by 16 1 : Divided by 128 Prescaler select bit Note: Set the desired prescale value before initializing the Watchdog timer. Watchdog timer start register b7 b0 Symbol WDTS Address 000E 16 When reset Indeterminate Function The Watchdog timer is initialized and starts counting after the first write instruction to this register after reset. Writing any value to this register resets the counter to 7FFF16. Figure 1.22: Watchdog timer control and start registers Rev. H Sep 18, 2003 Page 37 of 139 RW Frequency Synthesizer Circuit M30240 Group 1.2.17 Frequency Synthesizer Circuit The Frequency Synthesizer Circuit generates a 48MHz clock needed by the USB block and a clock fSYN that are both a multiple of the external input reference clock f(XIN). A block diagram of the circuit is shown in Figure 1.23. fUSB EN USBC5 f(XIN) Prescaler Frequency Multiplier fPIN fVCO Frequency Divider fSYN 8 Bit 8 Bit FSCCR0 FSP FSM LS 8 Bit 03DE FSC FSD 03DC 03DD FSCCR 03DB 03DF Data Bus Figure 1.23: Frequency Synthesizer Circuit The frequency synthesizer consists of a prescaler, frequency multiplier macro, a frequency divider macro, and five registers, namely FSP, FSM, FSC, FSD, and FSCCR. Clock f(XIN) is prescaled down using FSP to generate fPIN. fPIN is multiplied using FSM to generate an fVCO clock which is then divided using FSD to produce the clock fSYN. The fVCO clock is optimized for 48 MHz operation and is buffered and sent out of the frequency synthesizer block as signal fUSB. This signal is used by the USB block. 1.2.17.1 Prescaler Clock fPIN is a divided down version of clock f(XIN) (see Figure 1.24). The relationship between fPIN and the clock input to the prescaler f(XIN) is as follows: * fPIN = f(XIN) / 2(n+1) where n is a decimal number between 0 and 254. Setting FSP to 255 disables the prescaler and fPIN = f(XIN). * Note: f(XIN) frequency below 1 MHz is not recommended. MSB 7 Bit 7 Bit 6 fPIN 12 MHz 1 MHz 2 MHz 3 MHz 6 MHz Bit 5 2 Bit 4 Bit 3 FSP Dec(n) Hex(n) 255 FF 5 05 2 02 1 01 0 00 Bit 2 Bit 0 LSB 0 Address: 03DE16 Access: R/W Reset: f(Xin) 12.00 MHz 12.00 MHz 12.00 MHz 12.00 MHz 12.00 MHz f(XIN)/2(n+1) = fPIN Figure 1.24: Frequency Synthesizer Prescaler Register (FSP) Rev. H Sep 18, 2003 Page 38 of 139 Bit 1 FF16 Frequency Synthesizer Circuit M30240 Group 1.2.17.2 Multiplier Clock fVCO is a multiplied up version of clock fPIN (See Figure 1.25). The relationship between fVCO and the clock input to the multiplier (fPIN) from the prescaler is as follows: * fVCO = fPIN x 2(n+1) where n is the decimal equivalent of the value loaded in FSM. Setting FSM to 255 disables the multiplier and fVCO = fPIN. Note 1: n must be chosen such that fVCO equals 48 MHz. Note 2: Minimum fPIN is 1 MHz. MSB 7 Bit 7 Bit 5 Bit 6 fPIN 1 MHz 2 MHz 4 MHz 6 MHz 12 MHz Bit 4 FSM Dec(n) 23 11 5 3 1 Bit 3 Hex(n) 17 0B 05 03 01 Bit 2 Bit 1 Bit 0 Address: 03DD16 LSB Access: R/W 0 Reset: FF16 fVCO 48.00 MHz 48.00 MHz 48.00 MHz 48.00 MHz 48.00 MHz fPIN x 2(n+1) = fVCO Figure 1.25: Frequency Synthesizer Multiply Register (FSM) 1.2.17.3 Divider Clock fSYN is a divided down version of clock fVCO (See Figure 1.26). The relationship between fSYN and the clock input to the divider (fVCO) from the multiplier is as follows: * fSYN = fVCO / 2(m+1) where m is the decimal equivalent of the value loaded in FSD. Setting FSD to 255 disables the divider and fSYN = fVCO. MSB 7 Bit 7 Bit 6 Bit 5 Bit 4 FSD Dec(m) 48.00 MHz 1 48.00 MHz 127 fVCO Bit 3 Hex(m) 01 7F Bit 2 fSYN 12.00 MHz 187.50 KHz fVCO/2(m+1) = fSYN Figure 1.26: Frequency Synthesizer Divide Register (FSD) Rev. H Sep 18, 2003 Page 39 of 139 Bit 1 Bit 0 LSB Address: 03DF16 0 Access: R/W Reset: FF16 Frequency Synthesizer Circuit M30240 Group The FSC0 bit in the FSC Control Register enables the frequency synthesizer block. When disabled (FSC0 = "0"), fVCO is held at either a high or low state. When the frequency synthesizer control bit is active (FSC0 = "1"), a lock status (LS = "1") indicates that fSYN and fVCO are the correct frequency. The LS and FSCO control bits in the FSC Control register are shown in Figure 1.27. When using the frequency synthesizer, a low-pass filter must be connected to the LPF pin. Once the frequency synthesizer is enabled, a delay of 2-5ms is recommended before the output of the frequency synthesizer is used. This is done to allow the output to stabilize. It is also recommended that none of the registers be modified once the frequency synthesizer is enabled as it will cause the output to be temporarily (2-5ms) unstable. The MCU clock source is selected via the Frequency Synthesizer Clock Control register (FSCCR). See Figure 1.28. Note: None of the registers must be written to once the frequency synthesizer is enabled and used as the system clock source (FSCCR register, address 03DB16, bit "0" set to "1") because it will cause the output of the PLL to freeze. Switch system back to f(XIN) and disable before modifying PLL registers. Frequency Synthesizer Control Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol FSC 0 0 Bit symbol Address 03DC 16 Bit name Bit 2 0 0 1 1 VCO0 VCO Gain Control VCO1 Reserved bit Lowest Gain (Note) Low Gain High Gain Highest Gain LPF Current Control Bit 6 0 0 1 1 Bit 5 0: 1: 0: 1: Frequency Synthesizer Lock Status 0: 1: Unlocked Locked CHG1 Note : Bit 1 0: 1: 0: 1: Must always be set to "0" CHG0 LS R W Function 0 : Disable 1 : Enabled Frequency Synthesizer Enable FSE When reset 6016 Disabled Low Current Intermediate Current (Note) High Current Recommended Figure 1.27: Frequency Synthesizer Control Register (FSC) Frequency Synthesizer Clock Control Register b7 b6 b5 0 0 0 b4 b3 b2 b1 0 0 0 0 b0 Symbol FSCCR Bit symbol FSCCR0 Reserved Address 03DB 16 Bit name Clock source selection Function 0 : XIN 1 : fsyn Must always be set to "0" Figure 1.28: Frequency Synthesizer Clock Control Register (FSCCR) Rev. H Sep 18, 2003 Page 40 of 139 When reset 0016 R W M30240 Group Universal Serial Bus 1.2.18 Universal Serial Bus The Universal Serial Bus (USB) has the following features: * Complete USB Specification (version 1.1) Compatibility * Error-handling capabilities * FIFOs: * Endpoint 0:IN/OUT 32-byte * Endpoint 1:IN 128-byteOUT 128-byte * Endpoint 2:IN 32-byteOUT 32-byte * Endpoint 3:IN 32-byteOUT 32-byte * Endpoint 4:IN 32-byteOUT 32-byte * Nine endpoints - control endpoint (Endpoint 0 - bi-directional) plus four IN and four OUT endpoints * Complete device configuration * Support of all device commands * Supports of full-speed functions * Support of all USB transfer types: * Isochronous * Bulk * Control * Interrupt * Suspend/Resume operation * On-chip USB transceiver with voltage converter * Start-of-frame interrupt and output pin 1.2.18.1 USB Function Control Unit (USB FCU) The implementation of the USB by this device is accomplished chiefly through the device's USB Function Control Unit (See Figure 1.29). The Function Control Unit's overall purpose is to handle the USB packet protocol layer. The Function Control Unit notifies the MCU that a valid token has been received. When this occurs, the data portion of the token is routed to the appropriate FIFO. The MCU transfers the data to, or from, the host by interacting with that endpoint's FIFO and CSR register. The USB Function Control Unit is composed of five sections: * Serial Interface Engine (SIE) * Generic Function Interface (GFI) * Serial Engine Interface Unit (SIU) * Microcontroller Interface (MCI) * USB Transceiver 1.2.18.1.1 Serial Interface Engine The SIE interfaces to the USB serial data and handles deserialization/serialization of data, NRZI encoding decoding, clock extraction, CRC generation and checking, bit stuffing, and other items pertaining to the USB protocol such as handling inter-packet time-outs and packet ID (PID) decoding. Rev. H Sep 18, 2003 Page 41 of 139 Universal Serial Bus M30240 Group 1.2.18.1.2 Generic Function Interface The GFI handles all USB standard requests from the host through the control endpoint (endpoint zero), handles Bulk, Isochronous and Interrupt transfers through Endpoints 1-4. The GFI handles read pointer reversal for re-transmission the current data set; write pointer reversal for reception of the last data set again and data toggle synchronization. 1.2.18.1.3 Serial Engine Interface Unit The SIU block decodes the Address and Endpoint fields from the USB host. 1.2.18.1.4 Microcontroller Interface The MCI block handles the Microcontroller interface and performs address decoding and synchronization of control signals. 1.2.18.1.5 USB Transceiver The USB transceiver, designed to interface with the physical layer of the USB, is compliant with the USB Specification (version 1.1) for full-speed devices. It consists of two 6-ohm drivers, a receiver, and Schmitt triggers for single-ended receive signals. The transceiver also includes a voltage converter. The voltage converter can supply 3.0 - 3.6V to the transmitter when the rest of the chip (CPU, USB FCU) operates at 4.15 - 5.25V. To enable the voltage converter, set bit 4 of the USB Control Register (USBC) to a "1". To disable the voltage converter, set bit 4 of the USBC to a "0". Refer to Section 1.5.4 "USB Transceiver" for more detailed information. SIU CPU MCI SIE Transceiver D+ D- GFI FIFOs Figure 1.29: USB Function Control Unit Block Diagram 1.2.18.2 USB Interrupts There are five USB interrupts in this device: * USB Function interrupt * USB Reset interrupt * USB Suspend interrupt * USB Resume interrupt * USB Start-of-Frame (SOF) interrupt. The first four interrupts are used to control the data flow and USB power. The SOF interrupt is used to monitor the transfer of isochronous (ISO) data. Each of the five USB interrupts is enabled by setting the corresponding bit in the Interrupt Control Register of the Interrupt Control Unit. Because the USB Function Interrupt has multiple interrupt sources, another level of enabling is within the USB Interrupt Registers 1 & 2. Rev. H Sep 18, 2003 Page 42 of 139 M30240 Group Universal Serial Bus 1.2.18.2.1 USB Function Interrupt The USB Function Interrupt can be triggered by 10 sources; many of these may be cause by several different events. Interrupt status flags associated with each source are contained in USBIS1 and USBIS2. Endpoints 1-4 have two interrupt status flags associated with it to control data transfer or to report a STALL/ UNDER_RUN/OVER RUN condition. The USB Endpoint x Out Interrupt Status Flag is set when * USB FCU successfully receives a packet of data OR * USB FCU sets the FORCE_STALL flag or OVER_RUN flag of the Endpoint x OUT CSR. The USB Endpoint x In Interrupt Status Flag is set when * USB FCU successfully sends a packet of data OR * USB FCU sets the UNDER_RUN flag of the Endpoint x IN CSR. The USB Endpoint 0 (control endpoint) has one interrupt status bit associated with it to control data transfer or report a STALL condition. The USB Endpoint 0 Interrupt Status Flag is set when * USB FCU successfully receives/sends a packet of data * Sets the SETUP_END flag or the FORCE_STALL flag, OR clears the DATA_END bit in the Endpoint 0 IN CSR. The Overrun/Underrun Interrupt Status Flag is set when (applicable to endpoints used for isochronous data transfer) * Overrun condition occurs in a endpoint (CPU is too slow to unload the data from the FIFO), OR * Underrun condition occurs in an endpoint (CPU is too slow to load the data to the FIFO). Each endpoint interrupt and overrun/underrun interrupt is enabled by setting the corresponding bit in the USB Interrupt Enable Register 1 and 2. 1.2.18.2.2 USB Reset Interrupt The USB Reset Interrupt Status Flag is set when the USB FCU sees a SE0 present on D+/D- for at least 2.5s. When this bit is set, all USB internal registers except INTST13 (bit5 of USBIS2) are reset to their default values. INTST13, the USB reset Interrupt Status Flag, is set to a "1" when the USB Reset is detected. When the CPU recognizes a USB Reset Interrupt, it needs to re initialize the USB FCU so that the USB operation can behave properly. It must also clear INTST13 by writing a "1" to this bit to allow a USB Reset Interrupt request to occur the next time a USB Reset is detected. Register RSTIC contains the USB Reset Interrupt's request bit and its interrupt priority select bits which are used to enable the interrupt and set its software priority level. 1.2.18.2.3 USB Suspend and Resume Interrupts The USB Suspend Interrupt is set when the USB FCU does not detect any bus activity on D+/D- (in J-state) for at least 3ms. The USB Suspend Signaling Interrupt Status Flag (INTST15, bit 7 of USBIS2) is set to a "1" when the USB Suspend is detected. The CPU must clear INTST15 by writing a "1" to this bit to allow a USB Suspend Interrupt request to occur the next time a USB Suspend is detected. The USB Resume Signaling Interrupt Status Flag is set when a USB FCU is in the suspend state and detects non-idle signaling on the D+/D-. Register SUSPIC contains the USB Suspend Interrupt's request bit and its interrupt priority select bits which are used to enable the interrupt and set its software priority level. The USB Resume Interrupt request is set when the USB FCU is in the suspend state and detects non-idle signaling on D+/D-. The USB Signaling Interrupt Status Flag (INTST14, bit 6 of USBIS2) is set to a "1" when the USB Resume is detected. The CPU must clear INTST14 by writing a "1" to this bit to allow a USB Resume Interrupt request to occur the next time a USB Resume is detected. Register RSMIC contains the USB Resume Interrupt's request bit and its interrupt priority select bits, which are used to enable the interrupt an set its software priority level. Rev. H Sep 18, 2003 Page 43 of 139 M30240 Group Universal Serial Bus 1.2.18.2.4 USB SOF Interrupt The USB SOF (Start-Of-Frame) Interrupt is used to control the transfer of isochronous data. The USB FCU generates a USB SOF Interrupt request when a start-of-frame packet is received. Register SOFIC contains the USB SOF Interrupt's request bit and its interrupt priority select bits, which are used to enable the interrupt and set its software priority level. 1.2.18.3 USB Endpoint FIFOs The USB FCU has an IN (transmit) FIFO and an OUT (receive) FIFO for each endpoint. Each endpoint (except endpoint 0) can be configured to support either single packet mode (in which only a single data packet is allowed to reside in the endpoint's FIFO) or dual packet mode (in which up to two data packets are allowed to reside in the endpoint's FIFO). Dual packet mode provides support for back-to-back transmission or back-toback reception. The mode is automatically determined by the MAXP value. When MAXP > 1/2 of the endpoint's FIFO size, single packet mode is set. When MAXP <= 1/2 of the endpoint's FIFO size, dual packet mode is set. In the event of a bad transmission/reception, the USB FCU handles all the FIFO read/write pointer reversal and data set management tasks required. Throughout this specification, the terms "IN FIFO" and "OUT FIFO" usually refer to the FIFOs associated with a specific endpoint. 1.2.18.3.1 IN (Transmit) FIFOs The CPU/DMA writes data to the endpoint's IN FIFO location specified by the FIFO write pointer, which automatically increments by "1" after a write. The CPU/DMA should only write data to the IN FIFO when the IN_PKT_RDY bit of the associated IN CSR is a "0". * Endpoint 0 IN FIFO Operation: The CPU writes a "1" to the IN_PKT_RDY bit of Endpoint 0 CSR after it finishes writing a packet of data to the IN FIFO. The USB FCU clears the IN_PKT_RDY bit after the packet has been successfully transmitted to the host (i.e., ACK is received from the host) or the SETUP_END flag of the Endpoint O CSR is set to a "1". * Endpoint 1-4 IN FIFO Operation when AUTO_SET (bit 7 of Endpoint x IN CSR) = "0" (disabled): MAXP > 1/2 of the IN FIFO size: The CPU writes a "1" to the IN_PKT_RDY bit of the associated IN CSR after the CPU/DMAC finishes writing a packet of data to the IN FIFO. The USB FCU clears the IN_PKT_RDY bit after the packet has been successfully transmitted to the host (which is assumed for isochronous transfers and is concluded when an ACK is received from the host for non-isochronous transfers). MAXP <= 1/2 of the IN FIFO size: The CPU writes a "1" to the IN_PKT_RDY bit of the associated IN CSR after the CPU/DMAC finishes writing a packet of data to the IN FIFO. The USB FCU clears the IN_PKT_RDY bit as soon as the IN FIFO is ready to accept another data packet. (The FIFO can hold up to two data packets at the same time in this configuration for back-to-back transmission.) * Endpoint 1-4 IN FIFO Operation when AUTO_SET (bit 7 of Endpoint x IN CSR) = "1" (enabled): MAXP > 1/2 of the IN FIFO size: When the number of bytes of data equal to the MAXP (maximum packet size) has been written to the IN FIFO by the CPU/DMAC, the USB FCU sets the IN_PKT_RDY bit of the associated IN CSR to a "1" automatically. The USB FCU clears the IN_PKT_RDY bit after the packet has been successfully transmitted to the host (which is assumed for isochronous transfers and is concluded when an ACK is received from the host for non-isochronous transfers). MAXP <= 1/2 of the IN FIFO size: When the number of bytes of data equal to the MAXP (maximum packet size) has been written to the IN FIFO by the CPU/DMAC, the USB FCU sets the IN_PKT_RDY bit to a "1" automatically. The USB FCU clears the IN_PKT_RDY bit as soon as the IN FIFO is ready to accept another data packet. (The FIFO can hold up to two data packets at the same time in this configuration for back-to-back transmission.) A software or a hardware flush causes the USB FCU to act as if a packet has been successfully transmitted out to the host. When there is one packet in the IN FIFO, a flush causes the IN FIFO to be empty. When there are two packets in the IN FIFO, a flush causes the older packet to be flushed out from the IN FIFO. A flush also updates the IN FIFO status bits IN_PKT_RDY and TX_NOT_EPT of the associated IN CSR. Rev. H Sep 18, 2003 Page 44 of 139 Universal Serial Bus M30240 Group The status of endpoint 1-4 IN FIFOs for both of the above cases can be obtained from the IN CSR of the corresponding IN FIFO as shown in Table 1.14 . Table 1.14: TA FIFO Status IN_PKT_RDY TX_NOT_EPT IN FIFO Status 0 0 No data packet in IN FIFO 0 1 One data packet in IN FIFO if MAXP <= 1/2 of the FIFO size./ Invalid when MAXP>1/2 of the FIFO size 1 0 Invalid 1 1 Two data packets in IN FIFO when MAXP <=1/2 of the FIFO size One data packet in IN FIFO when MAXP > 1/2 of the FIFO size 1.2.18.3.2 Out (Receive) FIFOs The USB FCU writes data to the endpoint's OUT FIFO location specified by the FIFO write pointer, which automatically increments by one after a write. When the USB FCU has successfully received a data packet, it sets the OUT_PKT_RDY bit of the corresponding OUT CSR to a "1". The CPU/DMAC should only read data from the OUT FIFO when the OUT_PKT_RDY bit of the OUT CSR is a "1". * Endpoint 0 OUT FIFO Operation: The USB FCU sets the OUT_PKT_RDY bit to a "1" after it has successfully received a packet of data from the host. The CPU sets bit SERVICED_OUT_PKT_RDY to a "1" to clear the OUT_PKT_RDY bit after the packet of data has been unloaded from the OUT FIFO by the CPU. * Endpoint 1-4 OUT FIFO Operation when AUTO_CLR (bit 7 of Endpoint x OUT CSR) = "0" (disabled): MAXP > 1/2 of the OUT FIFO size: The USB FCU sets the OUT_PKT_RDY bit of the associated IN CSR to a "1" after it has successfully received a packet of data from the host. The CPU writes a "0" to the OUT_PKT_RDY bit after the packet of data has been unloaded from the OUT FIFO by the CPU/DMAC. MAXP <= 1/2 of the OUT FIFO size: The USB FCU sets the OUT_PKT_RDY bit of the associated IN CSR to a "1" after it has successfully received a packet of data from the host. The CPU writes a "0" to the OUT_PKT_RDY bit after the packet of data has been unloaded from the OUT FIFO by the CPU/DMAC. If another packet is in the OUT FIFO, the OUT_PKT_RDY bit will be set to a "1" again almost immediately (such that it may appear that the OUT_PKT_RDY bit remains a "1"). In this configuration, the FIFO can store up to two data packets at the same time for back-to-back reception. * Endpoint 1-4 OUT FIFO Operation when AUTO_CLR (bit 7 of Endpoint x OUT CSR) = "1" (enabled): MAXP > 1/2 of the OUT FIFO size: The USB FCU sets the OUT_PKT_RDY bit of the associated IN CSR to a "1" after it has successfully received a packet of data from the host. The USB FCU clears the OUT_PKT_RDY bit to a "0" automatically when the number of bytes of data equal to the MAXP (maximum packet size) has been unloaded from the OUT FIFO by the CPU/DMAC. MAXP <= 1/2 of the OUT FIFO size: The USB FCU sets the OUT_PKT_RDY bit of the associated IN CSR to a "1" after it has successfully received a packet of data from the host. The USB FCU clears the OUT_PKT_RDY bit to a "0" automatically when the number of bytes of data equal to the MAXP (maximum packet size) has been unloaded from the OUT FIFO by the CPU/DMAC. If another packet is in the OUT FIFO, the OUT_PKT_RDY bit will be set to a "1" again almost immediately (such that it may appear that the OUT_PKT_RDY bit remains a "1"). In this configuration, the FIFO can store up to two data packets at the same time for back-to-back reception. A software flush causes the USB FCU to act as if a packet has been unloaded from the OUT FIFO. If there is one packet in the OUT FIFO, a flush will cause the OUT FIFO to be empty. If there are two packets in the OUT FIFO, a flush will cause the older packet to be flushed out from the OUT FIFO. Rev. H Sep 18, 2003 Page 45 of 139 Universal Serial Bus M30240 Group 1.2.18.3.3 Interrupt Endpoints Any endpoint can be used for interrupt transfers. For normal interrupt transfers, the interrupt transactions behave the same as bulk transactions, i.e., no special setting is required. The IN endpoints may also be used to communicate rate feedback information for certain types of isochronous functions. This is done by setting the INTPT bit in the IN CSR register of the corresponding endpoint. The following outlines the operation sequence for an IN endpoint used to communicate rate feedback information: 1. Set MAXP > 1/2 of the endpoint's FIFO size; 2. Set INTPT bit of the IN CSR; 3. Flush the old data in the FIFO; 4. Load interrupt status information and set IN_PKT_RDY bit in the IN CSR; 5. Repeat steps 3 & 4 for all subsequent interrupt status updates. 1.2.18.4 USB Special Function Registers The MCU controls USB operation through the use of special function registers (SFR). This section describes each USB related SFR. Some USB special function registers have a mix of read/write, read only, and write only register bits. Additionally, the bits may be configured to allow the user to write only a "0" or a "1" to individual bits. * When accessing these registers, writing a "0" to a register that can only be set to a "1" by the CPU has no effect on that register bit. * Writing a "1" to a register that can only be set to a "0" by the CPU has not effect on that register bit. Each figure and description of the special function registers details this operation. All USB Special Function Registers, with the exception of USB Attach/Detach (001F16) and USB control (000C16) must use byte access. Work access is prohibited for USB internal registers (030016 033C16). The contents of all USB Special Functions Registers, including USB Attach/Detach and USB Control, are preserved on a software reset. 1.2.18.4.1 USB Attach/Detach Register The USB Attach / Detach Register is shown in Figure 1.30. The register is used to attach and detach the USB function from a USB host without physically disconnecting the USB cable. This functionality is enabled by setting P83_Second to a "1". Doing this forces P83 to operate as a pull-up for D+ (through an external 1.5k ohm resistor). The port driver is tri-stated and a "1" is always read from the port bit in this mode. When the ATTACH/ DETACH bit is a "1" (and P83_Second is a "1"), P83 is driven with the voltage on EXTCAP, causing D+ to be pulled up and the host to detect an attach. When the ATTACH/DETACH bit is a "0" (and P83_Second is a "1"), P83 is tri-stated, causing D+ to be pulled down (through the cable and 15k ohm resistor on the host/hub side) and a detach to be registered by the host. A 1.5k ohm pull-up resistor must be connected externally from P83 to D+ when this functionality is used. When it is not used, the 1.5k ohm resistor should be placed between EXTCAP and D+. USB Attach/Detach Register b7 b6 b5 b4 b3 b2 b1 b0 0 0 0 0 0 0 Symbol USBAD Address 001F16 Bit symbol P83_2nd Attach/ Detach Bit name Function Port 83-Second 0 : Normal mode for Port P83 1 : Forces Port P83 to operate as pull up for D+. Attach/Detach 0 : Tri-states, P83 causing the host to detect a detach 1 : Drives P83 with voltage on EXTCAP, causing the host to detect an attach Reserved Figure 1.30: USB Attach/Detach Register Rev. H Sep 18, 2003 Page 46 of 139 When reset 0016 Must always be set to "0" R W Universal Serial Bus M30240 Group 1.2.18.4.2 USB Control Register The USB Control Register, shown in Figure 1.31, is used to control the USB FCU. This register is not reset by a USB reset signaling. After the USB is enabled (USBC7 set to "1"), a minimum delay of 250ns (three 12 MHz clock periods) is needed before performing any other USB register read/write operations. USB Control Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol USBC 0 00 Address 000C16 Bit name Bit symbol Function USBC3 Tranceiver voltage converter High/Low current mode selection USBC4 USB tranceiver voltage converter enable bit USBC5 USB clock enable bit USBC6 USB SOF port select bit USBC7 USB enable bit 1: 2: 3: 4: R W Must always be set to "0" Reserved Note Note Note Note When reset 0016 0: 1: 0: 1: 0: 1: 0: 1: 0: 1: High current mode (Note 1) Low current mode (Note 2) Disabled Enabled Disabled Enabled Disabled (Note 3) Enabled Disabled (Note 4) Enabled For USB normal operation For USB suspend operation P8 6 is used as GPIO pin All USB internal registers are held at their default values. Figure 1.31: USB Control Register 1.2.18.4.3 USB Function Address Register The USB Function Address Register, shown in Figure 1.32, maintains the 7-bit USB address assigned by the host. The USB FCU uses this register value to decode USB token packet addresses. At reset, when the device is not yet configured, the value is 0016. For the procedures on how to update this register, refer to Application Notes USB Consecutive Set Address. USB Function Address Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol USBA 0 Address 030016 Bit symbol FUNAD0-6 Bit name Function Address Reserved Figure 1.32: USB Function Address Register Rev. H Sep 18, 2003 Page 47 of 139 When reset 00 16 Function 7-bit programmable Function Address Must always be set to "0" R W Universal Serial Bus M30240 Group 1.2.18.4.4 USB Power Management Register The USB Power Management Register, shown in Figure 1.33, is used for power management in the USB FCU. * SUSPEND Detection Flag: When the USB FCU does not detect any bus activity on D+/D- for at least 3ms (and D+/D- are in the J-state), it sets the Suspend Detection Flag and generates an interrupt. This bit is cleared when signaling from the host is detected on D+/D- (which sets the Resume Detection Flag and generates an interrupt), or the Remote Wake-up Bit is set and then cleared by the CPU. If the USB clock was disabled during the suspend state, the SUSPEND Detection Flag is not cleared until after the USB clock is re-enabled. * RESUME Detection Flag: When the USB FCU is in the suspend state and detects activity on D+/D- from the host, it sets the Resume Detection Flag and generates an interrupt. The CPU writes a "1" to INTST14 (bit 6 of USB Interrupt Status Register 2) to clear this flag. * WAKEUP Control Bit: The CPU writes a "1" to the WAKEUP Control Bit for remote wake-up. While this bit is set and the USB FCU is in suspend mode, resume signaling is sent to the host. The CPU must keep this bit set for a minimum of 10ms and a maximum of 15ms before writing a "0" to this bit. USB Power Management Register b7 b6 b5 b4 b3 00000 b2 b1 b0 Symbol USBPM Bit symbol SUSPEND RESUME WAKEUP Address 0301 16 Bit name Function R W USB Suspend Detection Flag 0 : No USB suspend signal detected 1 : USB suspend signal detected Note 1 USB Resume Detection Flag 0 : No USB resume signal detected 1 : USB resume signal detected Note 1 USB Remote Wakeup Bit 0 : End remote resume signaling 1 : Remote resume signaling (Note 2) Reserved Note 1: Write "0" only or Read Note 2: If SUSPEND = "1" Figure 1.33: USB Power Management Register Rev. H Sep 18, 2003 Page 48 of 139 When reset 00 16 Must always be set to "0" Universal Serial Bus M30240 Group 1.2.18.4.5 USB Interrupt Status Registers 1 and 2 USB Interrupt Status Registers 1 and 2, shown in Figure 1.34 and Figure 1.35, are used to indicate the condition that caused a USB function interrupt and USB Reset, Suspend and Resume Interrupts to the CPU. A "1" indicates the corresponding condition caused an interrupt. The USB Interrupt Status Register bits can be cleared by writing a "1" to the corresponding bit. INTST0 is set to a "1" by the USB FCU when (in Endpoint 0 CSR): * A packet of data is successfully received (EP0CSR0 - OUT_PKT_RDY is set by the USB FCU) * A packet of data is successfully sent (EP0CSR - IN_PKT_RDY is cleared by the USB FCU) * EP0CSR3 (DATA_END) bit is cleared by the USB FCU * EP0CSR4 (FORCE_STALL) bit is set by the USB FCU * EP0CSR5 (SETUP_END) bit is set by the USB FCU INTST2, INTST4, INTST6 or INTST8 is set to a "1" by the USB FCU when (in Endpoint x IN CSR): * A packet of data is successfully sent (INXCSR0 - IN_PKT_RDY is cleared by the USB FCU) * INXCSR1 (UNDER_RUN) bit is set by the USB FCU INTST3, INTST5, INTST7 or INTST9 is set to a "1" by the USB FCU when (in Endpoint xOUT CSR): * A packet of data is successfully received (OUTXCSR0 - OUT_PKT_RDY is set by the USB FCU) * OUTXCSR1 (OVER_RUN) bit is set by the USB FCU * OUTXCSR4 (FORCE_STALL) bit is set by the USB FCU INTST12 is set to a "1" by the USB FCU when an overrun or underrun condition occurs in any of the endpoints. INTST13 is set to a "1" by the USB FCU when a USB reset signaling from the host is received. All internal register bits except this bit are reset to their default values when the USB reset is received. INTST14 is set to a "1" by the USB FCU when the USB FCU is in the suspend state and non-idle signaling is received from D+/D-. INTST15 is set to a "1" by the USB FCU when D+/D- are in the idle state for more than 3ms. USB Interrupt Status Register 1 b7 b6 b5 b4 b3 b2 b1 b0 Symbol USBIS1 0 Bit symbol INTST0 Address 030216 Bit name USB Endpoint 0 Interrupt Status Flag When reset 0016 Function 0 : No interrupt request issued 1 : Interrupt request issued Must always be set to "0" Reserved INTST2 USB Endpoint 1 IN Interrupt Status Flag 0 : No interrupt request issued 1 : Interrupt request issued INTST3 USB Endpoint 1 OUT Interrupt Status Flag 0 1 0 1 0 1 : : : : : : No interrupt request issued Interrupt request issued No interrupt request issued Interrupt request issued No interrupt request issued Interrupt request issued 0 1 0 1 : : : : No interrupt request issued Interrupt request issued No interrupt request issued Interrupt request issued INTST4 INTST5 INTST6 INTST7 USB Endpoint 2 IN Interrupt Status Flag USB Endpoint 2 OUT Interrupt Status Flag USB Endpoint 3 IN Interrupt Status Flag USB Endpoint 3 OUT Interrupt Status Flag Figure 1.34: USB Interrupt Status Register 1 Rev. H Sep 18, 2003 Page 49 of 139 R W Universal Serial Bus M30240 Group USB Interrupt Status Register 2 b7 b6 b5 b4 b3 b2 b1 b0 Symbol USBIS2 0 0 Bit symbol Address 030316 Bit name When reset 0016 Function INTST8 USB Endpoint 4 IN Interrupt Status Flag 0 : No interrupt request issued 1 : Interrupt request issued INTST9 USB Endpoint 4 OUT Interrupt Status Flag 0 : No interrupt request issued 1 : Interrupt request issued Reserved INTST12 INTST13 INTST14 INTST15 R W Must always be set to "0" USB Overrun/Underrun Interrupt Status Flag USB Reset Interrupt Status Flag USB Resume Signaling Interrupt Status Flag 0 1 0 1 0 1 : : : : : : No interrupt request issued Interrupt request issued No interrupt request issued Interrupt request issued No interrupt request issued Interrupt request issued USB Suspend Signaling Interrupt Status Flag 0 : No interrupt request issued 1 : Interrupt request issued Figure 1.35: USB Interrupt Status Register 2 1.5.0.0.1 Clearing USB Interrupt Status Registers The USB Interrupt Status Register 1 and 2 are used to indicate pending interrupts for a given source. The USB FCU sets the interrupt status bits. The CPU writes a "1" to each status bit to clear it. Because the USB Function Interrupt has multiple sources that can generate an interrupt, it is recommended that the user first read the two status registers and store them in variables then write back the same value for clearing all the existing interrupts that were pending when the status registers were read. This procedure prevents any interrupt that occurs after the status registers are read from being cleared by the `write-back' operation. The CPU must read, then write both status registers, writing to status register 1 first and status register 2 second to guarantee proper operation. The upper three bits of the value written back to USBIS2 should always be "000" to prevent any of the USB Reset, Suspend and Resume Status Flags from being cleared. The USB Reset, Suspend and Resume Status Flags are contained in USBIS2 along with the USB Endpoint 4 In/Out Interrupt Status Flags and the USB Overrun/Underrun Interrupts Status Flag. Because the flags are not all sources for the same interrupt, use caution when clearing one or more of the flags to avoid inadvertently clearing other flags. The Reset, Suspend and Resume Status Flags should be cleared individually by writing a byte value with at "1" only at the position corresponding to the flag to be cleared. The USB Endpoint 4 In/Out Interrupt status Flags and the USB Overrun/Underrun Interrupt Status Flag should be cleared as described in the preceding paragraph because they are sourced for the USB Function Interrupt. "Read-modify-write" instructions, such as "BCLR" and "BSET", should not be used to clear any of the interrupt status bits in USBIS1 or USBIS2. Using these instructions could cause pending interrupts to be cleared without the firmware's knowledge. Rev. H Sep 18, 2003 Page 50 of 139 Universal Serial Bus M30240 Group 1.2.18.4.6 USB Interrupt Enable Registers 1 and 2 The USB Interrupt Enable Registers 1 and 2, shown in Figure 1.36 and Figure 1.37, are used to enable the corresponding interrupt status conditions that can generate a USB Function Interrupt. When the bit to a corresponding interrupt condition is "0", that condition does not generate a USB function interrupt. When the bit is a "1", that condition can generate a USB function interrupt. At reset, all USB function interrupt status conditions are enabled. USB Interrupt Enable Register 1 b7 b6 b5 b4 b3 b2 b1 b0 Symbol USBIE1 1 Address 030416 Bit symbol Bit name USB Endpoint 0 Interrupt Enable Bit INTEN0 When reset FF16 R W Function 0 : Interrupt disabled 1 : Interrupt enabled Must always be set to "1" Reserved INTEN2 USB Endpoint 1 IN Interrupt Enable Bit 0 : Interrupt disabled 1 : Interrupt enabled INTEN3 USB Endpoint 1 OUT Interrupt Enable Bit 0 1 0 1 : : : : Interrupt Interrupt Interrupt Interrupt disabled enabled disabled enabled 0 1 0 1 : : : : Interrupt Interrupt Interrupt Interrupt disabled enabled disabled enabled USB Endpoint 2 IN Interrupt Enable Bit USB Endpoint 2 OUT Interrupt Enable Bit USB Endpoint 3 IN Interrupt Enable Bit INTEN4 INTEN5 INTEN6 USB Endpoint 3 OUT Interrupt Enable Bit INTEN7 0 : Interrupt disabled 1 : Interrupt enabled Figure 1.36: USB Interrupt Enable Register 1 USB Interrupt Enable Register 2 b7 b6 b5 0 01 b4 b3 b2 b1 b0 Symbol USBIE2 0 0 Bit symbol Address 030516 Bit name When reset 3316 Function INTEN8 USB Endpoint 4 IN Interrupt Enable Bit 0 : Interrupt disabled 1 : Interrupt enabled INTEN9 USB Endpoint 4 OUT Interrupt Enable Bit 0 : Interrupt disabled 1 : Interrupt enabled Reserved INTEN12 Must always be set to "0" USB Overrun/Underrun Interrupt Enable Bit 0 : Interrupt disabled 1 : Interrupt enabled Reserved Must always be set to "1" Reserved Must always be set to "0" Figure 1.37: USB Interrupt Enable Register 2 Rev. H Sep 18, 2003 Page 51 of 139 R W Universal Serial Bus M30240 Group 1.2.18.4.7 USB Frame Number Registers The USB Frame Number Low Register, shown in Figure 1.38, contains the lower 8 bits of the 11-bit frame number received from the host. The USB Frame Number High Register, shown in Figure 1.39 contains the upper 3 bits of the 11-bit frame number received from the host. USB Frame Number Low Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol USBSOFL Bit symbol FN0 to FN7 Address 0306 16 When reset 0016 Bit name Function R W Lower 8 bits of the 11-bit frame number issued with a SOF token X Figure 1.38: USB Frame Number Low Register USB Frame Number High Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol USBSOFH 00 00 0 Bit symbol FN8 Address 0307 16 When reset 0016 Bit name Function R W Upper 3 bits of the 11-bit frame number issued with a SOF token FN9 X FN10 Must always be set to "0" Reserved X Figure 1.39: USB Frame Number High Register 1.2.18.4.8 USB ISO Control Register The USB ISO Control Register, shown in Figure 1.40, contains two global bits, ISO_UPD and AUTO_FL for controlling endpoints 1-4 isochronous data transfer. When ISO_UPD = "0", a data packet in an endpoint's IN FIFO is always `ready to transmit' upon receiving the next IN_TOKEN from the host (with matched address and endpoint number) if the endpoint's IN_PKT_RDY is set. When ISO_UPD = "1" and the ISO/TOGGLE_INIT bit of the corresponding endpoint's IN CSR is set, the internal `ready to transmit' signal to the transmit control logic is not activated when the endpoint's IN_PKT_RDY is set. Instead, it is activated when the next SOF is received, this way, the data loaded in frame n is transmitted out in frame n+1. The ISO_UPD bit is a global bit for endpoints 1-4 and works with isochronous pipes only. When AUTO_FL = "1", ISO_UPD = "1", a particular IN endpoint's ISO/TOGGLE_INIT bit is set, and the IN endpoint's IN_PKT_RDY = "1", the USB FCU detects a SOF packet and the USB FCU automatically flushes the oldest packet from the IN FIFO. In this case, IN_PKT_RDY = "1", indicates that two data packets are in the IN FIFO. Because double buffering is a requirement for ISO transfer, MAXP must be set to less than or equal to 1/2 of the FIFO size. USB ISO Control Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol USBISOC 0 00 0 0 0 Bit symbol Address 0308 16 Bit name AUTO_FL AUTO_FLUSH Bit ISO_UPD ISO_UPDATE Bit USB ISO Control Register Rev. H Sep 18, 2003 Page 52 of 139 Function Must always be set to "0" Reserved Figure 1.40: When reset 0016 0: 1: 0: 1: Hardware auto FIFO flush diabled Hardware auto FIFO flush enabled ISO_UPDATE disabled ISO_UPDATE enabled R W Universal Serial Bus M30240 Group 1.2.18.4.9 USB DMAx Request Registers The USB DMAx Request Registers, shown in Figure 1.41 and Figure 1.42, are used to select which USB Endpoint x FIFO read/write requests are selected as the DMAC channel 0 or channel 1 request source. The USB DMA0 (DMA1) Request Register should have only one bit set at any given time. When multiple bits are set, no request is selected. USB DMA0 Request Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol USBSAR0 Address 0309 16 Bit symbol DMA0R0 DMA0R1 DMA0R2 DMA0R3 DMA0R4 DMA0R5 DMA0R6 DMA0R7 Figure 1.41: Bit name Endpoint Endpoint Endpoint Endpoint Endpoint Endpoint Endpoint Endpoint When reset 0016 Function 1 IN FIFO write request selection bit 2 IN FIFO write request selection bit 3 IN FIFO write request selection bit 4 IN FIFO write request selection bit 1 OUT FIFO read request selection bit 2 OUT FIFO read request selection bit 3 OUT FIFO read request selection bit 4 OUT FIFO read request selection bit R W 0 0 0 0 0 0 0 0 0 : Not selected 1 : Selected 0 0 0 0 0 0 0 0 USB DMA0 Request Register USB DMA1 Request Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol USBSAR1 Address 030A 16 Bit symbol DMA1R0 DMA1R1 DMA1R2 DMA1R3 DMA1R4 DMA1R5 DMA1R6 DMA1R7 Figure 1.42: Bit name Endpoint Endpoint Endpoint Endpoint Endpoint Endpoint Endpoint Endpoint 1 2 3 4 1 2 3 4 When reset 0016 Function IN FIFO write request selection bit IN FIFO write request selection bit IN FIFO write request selection bit IN FIFO write request selection bit OUT FIFO read request selection bit OUT FIFO read request selection bit OUT FIFO read request selection bit OUT FIFO read request selection bit 0 : Not selected 1 : Selected R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USB DMA1 Request Register 1.2.18.4.10 USB Endpoint Enable Register The USB Endpoint Enable Register, shown in Figure 1.43, is used to enable/disable an individual endpoint. Endpoint 0 is always enabled and cannot be disabled by firmware. All endpoints are enabled after reset. USB Endpoint Enable Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol USBEPEN Address 030B 16 Bit symbol EP1_OUT EP1_IN EP2_OUT EP2_IN EP3_OUT EP3_IN EP4_OUT EP4_IN Figure 1.43: Bit name Endpoint 1OUT FIFO Enable bit Endpoint 1 IN FIFO Enable bit Endpoint 2OUT FIFO Enable bit Endpoint 2 IN FIFO Enable bit Endpoint 3 OUT FIFO Enable bit Endpoint 3 IN FIFO Enable bit Endpoint 4 OUT FIFO Enable bit Endpoint 4 IN FIFO Enable bit USB Endpoint Enable Register Rev. H Sep 18, 2003 Page 53 of 139 When reset FF16 Function 0 : Disabled 1 : Enabled R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 M30240 Group Universal Serial Bus 1.2.18.4.11 USB Endpoint 0 Control and Status Register The Endpoint 0 CSR (Control and Status Register), shown in Figure 1.44 contains the control and status information of Endpoint 0. * EP0CSR0 (OUT_PKT_RDY): The USB FCU sets this bit to a "1" after it receives a valid SETUP/OUT token from the host. The CPU clears this bit after unloading the packet from the FIFO by writing a "1" to EP0CSR6. The CPU should not clear the OUT_PKT_RDY bit before it finishes decoding the host request. When EP0CSR2 (SEND_STALL) needs to be set (because the CPU decodes an invalid or unsupported request) a "1" should be written to EP0CSR6 and EP0CSR2 at the same time using the same instruction. * EP0CSR1 (IN_PKT_RDY): The CPU writes a "1" to this bit after it finishes writing a packet of data to the endpoint 0 FIFO. The USB FCU clears this bit after the packet is successfully transmitted to the host, or the EP0CSR5 (SETUP_END) bit is set. * EP0CSR2 (SEND_STALL): The CPU writes a "1" to this bit when it decodes an invalid or unsupported standard device request from the host. When the OUT-PKT_RDY bit is a "1" at the time the CPU wants to set the SEND_STALL bit to a "1", the CPU must also set SERVICED_OUT_PKT_RDY to a "1" to clear the OUT-PKT_RDY at the same time as setting the SEND_STALL bit. The USB FCU returns a STALL handshake for all subsequent IN/OUT transactions (during control transfer data or status stages) while this bit is set. The CPU writes a "0" to clear it after it receives a new SETUP packet. It is up to the firmware to decide what SETUP packet should lead the clearing of the SEND_STALL bit. * EP0CSR3 (DATA_END): The CPU writes a "1" to this bit when it writes (IN data phase) or reads (OUT data phase) the last packet of data to or from the FIFO. The CPU sets this bit at the same time as it sets the last IN_PKT_RDY bit or sets the last SERVICED_OUT_PKT_RDY bit.This bit indicates to the USB FCU that the specific amount of data in the setup phase is transferred. The USB FCU advances to the status phase once this bit is set. When the status phase completes, the USB FCU clears this bit. When this bit is set to a "1", and the host requests or sends more data, the USB FCU returns a STALL handshake and terminates the current control transfer. * EP0CSR4 (FORCE_STALL): The USB FCU sets this bit to a "1" to report an error status when one of the following occur: * Host sends an IN token in the absence of a SETUP stage * Host sends a bad data toggle in the STATUS stage, (i.e. DATA0 is used) * Host sends a bad data toggle in the SETUP stage, (i.e. DATA1 is used) * Host request more data than specified in the SETUP state, * (i.e. IN token comes after DATA_END bit is set) * Host sends more data than specified in the SETUP state, * (i.e. OUT token comes after DATA_END bit is set) * Host sends larger data packet than MAXP size All of the conditions stated (except bad data toggle in the SETUP stage) cause the device to send a STALL handshake for the current IN/OUT transaction. For the bad data toggle in the SETUP state, the device sends ACK for the SETUP stage and then sends STALL for the next IN/OUT transaction. A STALL handshake caused by the above listed conditions lasts for one transaction and terminates the ongoing control transfer. Any packet after the STALL handshake will be seen as the beginning of a new control transfer. The CPU writes a "0" to clear the FORCE_STALL status bit. * EP0CSR5 (SETUP_END): The USB FCU sets this bit to a "1" if a control transfer has ended before the specific length of data is transferred during the data phase (status phase starts before DATA_END bit is set) or a control transfer has ended before a new SETUP has arrived and before successfully completing the status phase. The CPU clears this bit by writing a "1" to IN0CSR7. Once the CPU detects the SETUP_END flag as set, it should stop accessing the FIFO to service the previous setup transaction. If the SETUP_END is caused by the reception of the SETUP packet prior to the end of the current control transfer, the OUT_PKT_RDY bit is set once the reception of the SETUP packet has completed (without errors). After the OUT_PKT_RDY bit is set, the new SETUP packet Rev. H Sep 18, 2003 Page 54 of 139 Universal Serial Bus M30240 Group data will be in the FIFO. For this case, because the SETUP_END bit is set near the beginning of the packet when the SETUP PID is encountered and the OUT_PKT_RDY bit is set at the end of the packet, the value read from EP0IN_CSR in the USB functional interrupt routine may only show that the SETUP_END flag as "1" instead of both the SETUP_END and OUT_PKT_RDY bits. * EP0CSR6 and EP0CSR7: These bits are used to clear EP0CSR0 and EP0CSR5 respectively. Writing a "1" to these bits clears the corresponding register bit. USB Endpoint 0 Control and Status Register (Note 5) b7 b6 b5 b4 b3 b2 b1 b0 Symbol EP0CS Address 0311 16 Bit symbol EP0CSR0 EP0CSR1 Bit name IN_PKT_RDY Bit SEND_STALL Bit EPOCSR3 DATA_END Bit EP0CSR4 FORCE_STALL Flag SETUP_END Flag EP0CSR6 SERVICED_OUT_PKY_RDY Bit EPOCSR7 SERVICED_SETUP_END Bit Note Note Note Note Note R W Function 0 1 0 1 0 1 0 1 0 1 0 1 OUT_PKT_RDY Flag EPOCSR2 EPOCSR5 When reset 0016 : : : : : : : : : : : : 0: 1: 0: 1: Not ready Ready Not ready Ready No action Stall Endpoint 0 by CPU No action Last packet transferred from/to FIFO No action Stall Endpoint 0 by USB FCU No action Control transfer ended before specific length of data transferred during data phase No change Clear the OUT_PKT_RDY bit (EPOCSR0) No change Clear the STUP-END bit (EP0CSR5) 0 0 Note 1 0 0 Note 2 0 0 0 0 Note 2 0 0 Note 3 0 0 Note 1 0 0 Note 4 0 0 Note 4 1: Read only 2: Write "1" only or Read 3: Write "0" only or Read 4: Write only - Read "0" 5: Refer to Section 1.5.5 "Programming Notes" for this register Figure 1.44: USB Endpoint 0 CSR 1.2.18.4.12 USB Endpoint 0 MAXP Register The USB Endpoint 0 MAXP Register, shown in Figure 1.45, indicates the maximum packet size (MAXP) of Endpoint 0 IN/OUT packet. The default value for Endpoint 0 MAXP is 8 bytes. USB Endpoint 0 MAXP Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol EP0MP 0 0 Bit symbol EP0MXP0 to EP0MXP5 Reserved Figure 1.45: USB Endpoint 0 MAXP Rev. H Sep 18, 2003 Page 55 of 139 Address 0313 16 Bit name When reset 0816 Function Maximum packet size (MAXP) of Endpoint 0 IN/OUT packet Must always be set to "0" R W Universal Serial Bus M30240 Group 1.2.18.4.13 USB Endpoint 0 OUT Write Count Register The USB Endpoint 0 OUT Write Count (WRT CNT) Register, shown in Figure 1.46, contains the number of bytes of the current data set in the OUT FIFO. The USB FCU sets the value in the Write Count Register after having successfully received a packet of data from the host. The CPU reads the register to determine the number of bytes to be read from the FIFO. USB Endpoint 0 OUT Write Count Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol EP0WC 0 0 0 Address 031516 Bit symbol W_CNT0 to W_CNT4 Bit name When reset 00 16 Function Receive byte count Reserved R W X Must always be set to "0" X Figure 1.46: USB Endpoint 0 OUT WRT CNT 1.2.18.4.14 USB Endpoint x IN Control and Status Register The USB Endpoint x IN CSR (Control and Status Register), shown in Figure 1.47, contains control and status information of the respective IN endpoint 1-4. * INxCSR0 (IN_PKT_RDY) and INxCSR5 (TX_FIFO_NOT_EMPTY): These two bits are for IN FIFO status when in read operation (see "IN (Transmit) FIFO" operation for details). The CPU writes a "1" to the INxCSR0 bit to inform the USB FCU that a packet of data is written to the FIFO. The USB FCU updates the pointers up on this bit set. The USB FCU also updates the pointers upon a packet of data successfully sent to the host. When the pointer updates are completed, the IN FIFO status is shown on INxCSR0 and INxCSR5 bits for the CPU to read. The CPU must allow at least one wait state between writing and reading these bits for proper FIFO status. * INxCSR1 (UNDER_RUN): This bit is used in ISO mode only to indicate to the CPU that a FIFO underrun has occurred. The USB FCU sets this bit to a "1" at the beginning of an IN token if no data packet is in the FIFO. Setting this bit causes the INST12 bit of the Interrupt Status Register 2 to set. The CPU writes a "0" to clear this bit. * INxCSR2 (SEND_STALL): The CPU writes a "1" to this bit when the endpoint is stalled (transmitter halt). The USB FCU returns a STALL handshake while this bit is set. The CPU writes a "0" to clear this bit. * INxCSR3 (ISO/TOGGLE_INIT): When the endpoint is used for isochronous data transfer, the CPU sets this bit to a "1" for the entire duration of the isochronous transfer. With the ISO bit set to a "1", the device uses DATA0 as the pid for all packets sent back to the host. When the endpoint is required to initialize the data toggle, this set/reset of the TOGGLE_INIT bit method assumes that there is no activity IN transaction to the respective endpoint on the bus at the time the initialization process is ongoing. Set/reset of the TOGGLE_INIT bit is performed only when an endpoint experiences a configuration event. * INxCSR4 (INTPT): The CPU writes a "1" to this bit to initialize this endpoint as a status change endpoint for IN transactions. This bit is set only when the corresponding endpoint is to be used to communicate rate feedback information (see Chapter. IN (Transmit) FIFOs for details). * INxCSR5 (TX_FIFO_NOT_EPT): The USB FCU sets this bit to a "1" when there is at least one data packet in the IN FIFO. This bit, in conjunction with IN_PKT_RDY bit, provides the transmit IN FIFO status information (see "IN (Transmit) FIFO" for details). * INxCSR6 (FLUSH): Rev. H Sep 18, 2003 Page 56 of 139 Universal Serial Bus M30240 Group The CPU writes a "1" to this bit to flush the IN FIFO. When there is one packet in the IN FIFO, a flush causes the IN FIFO to be empty. When there are two packets in the IN FIFO, a flush causes the older packet to be flushed out from the IN FIFO. Setting the INXCSR6 (FLUSH) bit during transmission could produce unpredictable results. * INxCSR7 (AUTO_SET): When the CPU sets this bit to a "1", the IN_PKT_RDY bit is set automatically by the USB FCU after the number of bytes of data equal to the maximum packet size (MAXP) is written into the IN FIFO (see "IN (Transmit) FIFO" operation for details). USB Endpoint x IN Control and Status Register (Note 5) b7 b6 b5 b4 b3 b2 b1 b0 Symbol EPiICS (i= 1-4) Bit symbol INxCSR0 INxCSR1 Address 031916, 0321 16, 0329 16, 0331 16 Bit name IN_PKT_RDY Bit UNDER_RUN Flag INxCSR2 SEND_STALL Bit INxCSR3 ISO Bit INxCSR4 INTPT INxCSR5 TX_NOT_EPT Flag INxCSR6 FLUSH Bit INxCSR7 AUTO_SET Bit Note Note Note Note Note When reset 0016 Function 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 : : : : : : : : : : : : : : : : Not ready Ready No FIFO underrun FIFO underrun has occured No action Stall IN Endpoint x by CPU Select non-isochronous transfer Select isochronous transfer Select non-rate feedback interrupt transfer Select rate feedback interrupt transfer Transmit FIFO is empty Transmit FIFO is not empty No action Flush the FIFO AUTO-SET disabled AUTO-SET enabled R W 0 0 Note 1 0 0 Note 2 0 0 0 0 0 0 0 0 Note 3 0 0 Note 4 0 0 1: Write "1" only or read 2: Write "0" only or read 3: Read only 4: Write only - Read "0" 5: Refer to section 1.5.5 "Programming Notes" for this register Figure 1.47: USB Endpoint x IN CSR 1.2.18.4.15 USB Endpoint x OUT Control and Status Register The USB Endpoint x OUT CSR (Control and Status Register), shown in Figure 1.48 contains control and status information of the respective OUT Endpoint 1-4. * OUTxCSR0 (OUT_PKT_RDY): The OUTxCSR0 bit for the OUT FIFO status (see "OUT (Receive) FIFOs" for details). The USB FCU sets this bit to a "1" and updates the FIFO pointers after a data packet has been successfully received from the host. The CPU writes a "0" to this bit to inform the USB FCU that a data packet has been unloaded. The USB FCU updates the FIFO pointers when this occurs. The CPU must allow at least one clock cycle between writing and reading bit OUTxCSR0. * OUTXxCSR1 (OVER_RUN): This bit is used in ISO mode only to indicate to the CPU that a FIFO overrun has occurred. The USB FCU sets this bit to a "1" at the beginning of an OUT token when two data packets are already present in the FIFO. Setting this bit causes the INST12 bit of the Interrupt Status Register 2 to set. The CPU writes a "0" to clear OUTXCSR1. * OUTxCSR2 (SEND_STALL): The CPU writes a "1" to this bit when the endpoint is stalled. The USB FCU returns a STALL handshake while this bit is set. The CPU writes a "0" to clear this bit. * OUTxCSR3 (ISO/TOGGLE_INIT): When the endpoint is used for isochronous data transfer, the CPU sets this bit to a "1" for the entire duration of the isochronous transfer. With the ISO/TOGGLE_INIT bit set to a "1", the device accepts either DATA0 or DATA1 for the PID sent by the host. Rev. H Sep 18, 2003 Page 57 of 139 Universal Serial Bus M30240 Group When endpoint is required to initialize the data toggle sequence bit (i.e. reset to DATA0 for the next data packet), the CPU sets this bit to a "1" and then resets it to a "0" to initialize the respective endpoint's data toggle. Successful initialization of the data toggle sequence bit can only be guaranteed if no active OUT transaction to the respective endpoint is ongoing when the initialization process is taking place. Set/reset of the ISO/ TOGGLE_INIT bit should only be performed when an endpoint experiences a configuration event. * OUTxCSR4 (FORCE_STALL): The USB FCU sets this bit to a "1" when the host sends out a larger data packet than the MAXP size. The USB FCU returns a STALL handshake while this bit is set. The CPU writes a "0" to clear this bit. * OUTxCSR5 (DATA_ERR): The USB FCU sets this bit to a "1" to indicate that a CRC error or a bit stuffing error was received in an ISO packet. The CPU writes a "0" to clear this bit. * OUTxCSR6 (FLUSH): The CPU writes a "1" to this to flush the OUT FIFO. When there is one packet in the OUT FIFO, a flush causes the OUT FIFO to be empty. When there are two packets in the OUT FIFO, a flush causes the older packet to be flushed out from the OUT FIFO. Setting the OUTXCSR6 (FLUSH) bit during reception could produce unpredictable results. * OUTxCSR7 (AUTO_CLR): When the CPU sets this bit to a "1", the OUT_PKT_RDY bit is cleared automatically by the USB FCU after the number of bytes of data equal to the maximum packet size (MAXP) is unloaded from the OUT FIFO (see "OUT (Receive) FIFO" for details). USB Endpoint x OUT Control and Status Register (Note 3) b7 b6 b5 b4 b3 b2 b1 b0 Symbol EPiOCS (i = 1-4) Bit symbol Address 031A 16, 0322 16, 032A 16, 033216 When reset 0016 Bit name OUTxCSR0 OUT_PKT_RDY Flag OUTxCSR1 OVER_RUN Flag OUTxCSR2 SEND_STALL Bit OUTxCSR3 ISO Bit OUTxCSR4 FORCE-STALL Flag OUTxCSR5 DATA-ERR Flag OUTxCSR6 FLUSH Bit OUTxCSR7 AUTO_CLR Bit R W Function 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 : : : : : : : : : : : : : : : : Not ready Ready No FIFO overrun FIFO overrun occured No action Stall OUT Endpoint x by CPU Select non-isochronous transfer Select isochronous transfer No action Stall Endpoint X by the USB FCU No error CRC or bit stuffing error received in ISO packet No action Flush the FIFO AUTO-CLR disabled AUTO-CLR enabled 0 0 Note 1 0 0 Note 1 0 0 0 0 0 0 Note 1 0 0 Note 1 0 0 Note 2 0 0 Note 1: Write "0" only or read Note 2: Write only - Read "0" Note 3: Refer to section 1.5.5 "Programming Notes" for this register Figure 1.48: USB Endpoint x OUT CSR 1.2.18.4.16 USB Endpoint x IN MAXP Register The USB Endpoint x IN MAXP Register, shown in Figure 1.49, indicates the maximum packet size (MAXP) of an Endpoint x IN packet. The default values for Endpoints 1-4 are 0 bytes. The setting of this register also affects the configuration of single/dual packet operation. When MAXP > 1/2 of the FIFO size, single packet mode is set. When MAXP <= 1/2 of the FIFO size, dual packet mode is set. USB Endpoint x IN MAXP Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol EPiIMP (i = 1-4) Bit symbol IMAXP0 to IMAXP7 Figure 1.49: USB Endpoint x IN MAXP Rev. H Sep 18, 2003 Page 58 of 139 Address When reset 031B16, 032316, 032B 16, 0333 16 0016 Bit name Maximum packet size (MAXP) of Endpoint x IN packet. Function For endpoints that support smaller FIFO size, unused bits are not implemented, (always write "0" to these bits). R W Universal Serial Bus M30240 Group 1.2.18.4.17 USB Endpoint x OUT MAXP Register The USB Endpoint x OUT MAXP Register, shown in Figure 1.50, indicates the maximum packet size (MAXP) of an Endpoint x OUT packet. The default values for endpoints 1-4 are 0 bytes. The setting of this register also affects the configuration of single/dual packet operation. When MAXP > 1/2 of the FIFO size, single packet is set. When MAXP <= 1/2 of the FIFO size, dual packet mode is set. USB Endpoint x OUT MAXP Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol EPiOMP (i = 1-4) Address 031C16, 032416, 032C 16, 0334 16 Bit symbol OMAXP0 to OMAXP7 Function Bit name Maximum packet size (MAXP) of Endpoint x OUT packet. When reset 0016 R W For endpoints that support smaller FIFO size, unused bits are not implemented, (always write "0" to these bits). Figure 1.50: USB Endpoint x OUT MAXP 1.2.18.4.18 USB Endpoint x OUT Write Count Register The USB Endpoint x OUT Write Count (WRT CNT) Register, shown in Figure 1.51, contains the number of bytes of the current data set in the OUT FIFO. The USB FCU sets the value in the Write Count Register after having successfully received a packet of data from the host. The CPU reads the register to determine the number of bytes to be read from the FIFO. USB Endpoint x OUT Write Count Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol EPiWC (i = 1-4) Bit symbol W_CNT0 to W_CNT7 Address 031D 16, 0325 16, 032D16, 033516 Bit name Function When reset 0016 R W X Receive Byte Count Figure 1.51: USB Endpoint x OUT WRT CNT 1.2.18.4.19 USB Endpoint x FIFO Register The USB Endpoint x FIFO Register, shown in Figure 1.52 is the USB IN (transmit) and OUT (receive) FIFO data register. The CPU writes data to this register for the corresponding Endpoint IN FIFO and reads data from this register for the corresponding Endpoint OUT FIFO. USB Endpoint x FIFO Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol EPi (i = 0-4) Address 033816, 033916, 033A 16, 033B 16, 033C 16 Bit name Bit symbol DATA_0 to DATA_7 Endpoint x IN/OUT FIFO Figure 1.52: USB Endpoint x FIFO Register Rev. H Sep 18, 2003 Page 59 of 139 Function When reset Indeterminate R W O DMAC M30240 Group 1.2.19 DMAC This microcomputer has two DMAC (direct memory access controller) channels that allow data to be sent to memory without using the CPU.Table 1.15 shows the DMAC specifications. Figure 1.53 shows the block diagram of the DMAC. Figure 1.54, Figure 1.55 and Figure 1.56 show the registers used by the DMAC. Table 1.15: DMAC Specifications Item Specification Number of channels 2 (cycle steal method) Transfer memory space *From any SFR, RAM, or ROM address to a fixed address *From a fixed address to any SFR or RAM address *From a fixed address to a fixed address (Note that DMA-related registers [002016 to 003F16] cannot be accessed) Maximum number of bytes transferred 128K bytes (with 16-bit transfers) or 64K bytes (with 8-bit transfers) DMA request sources Falling edge of INT0 or INT1 (INT0 can be selected by DMA0, INT1 by DMA1) Timer A0 to timer A4 Timer B0 to timer B1 UART0 transmission and reception UART1 transmission and reception UART2 transmission and reception A-D conversion complete USB function Software triggers Channel priority DMA0 takes precedence if DMA0 and DMA1 requests are generated simultaneously Transfer unit 8 bits or 16 bits Transfer address direction forward/fixed (forward direction cannot be specified for both source and destination simultaneously) Transfer modes *Single transfer mode The DMA enable bit is cleared and transfer ends when an underflow occurs in the transfer counter. *Repeat transfer mode When an underflow occurs in the transfer counter, the value in the transfer counter reload register is loaded into the transfer counter and the DMA transfer is repeated DMA interrupt request generation timing When an underflow occurs in the transfer counter DMA startup *Single transfer mode Transfer starts when the DMA is requested after "1" is written to the DMA enable bit *Repeat transfer mode Transfer starts when the DMA is requested after "1" is written to the DMA enable bit or after an underflow occurs in the transfer counter DMA shutdown *When "0" is written to the DMA enable bit *When, in single transfer mode, an underflow occurs in the transfer counter Forward address pointer and reload timing for transfer counter When DMA transfer starts, the value of whichever of the source or destination pointer that is set up as the forward pointer is loaded into the forward address pointer. The value in the transfer counter reload register is loaded into the transfer counter. Writing to register Registers specified for forward direction transfer are always write-enabled. Registers specified for fixed address transfer are write-enabled when the DMA enable bit is "0". Reading the register Can be read at any time. However, when the DMA enable bit is "1", reading the register sets up as the forward register is the same as reading the value of the forward address pointer. Note: DMA transfers are not affected by the interrupt enable flag (I-FLAG) of any interrupt or by the interrupt priority level. Rev. H Sep 18, 2003 Page 60 of 139 DMAC M30240 Group Address bus DMA0 source pointer SAR0(20) (addresses 0022 16 to 0020 16) DMA0 destination pointer DAR0 (20) (addresses 0026 16 to 0024 16) DMA0 forward address pointer (20) (Note) DMA0 transfer counter reload register TCR0 (16) DMA1 source pointer SAR1 (20) (addresses 0029 16, 0028 16) DMA0 transfer counter TCR0 (16) (addresses 0032 16 to 0030 16) a DMA1 destination pointer DAR1 (20) (addresses 0036 16 to 0034 16) DMA1 forward address pointer (20) (Note) DMA1 transfer counter reload register TCR1 (16) (addresses 0039 16, 0038 16) DMA latch high-order bits DMA1 transfer counter TCR1 (16) DMA latch low-order bits Data bus low-order bits Data bus high-order bits Note: Pointer is incremented by a DMA request. Figure 1.53: Block diagram of DMAC DMAi request cause select register b7 b6 b5 b4 b3 b2 b1 b0 Address 03B816, 03BA16 Symbol DMiSL (i=0,1) Bit symbol Bit name When reset 0016 Function (Note) b3 b2 b1 b0 DSEL0 DSEL1 DMA request cause select bits DSEL2 DSEL3 0 0 0 0 : Falling edge of INT0/INT1pin (Note 1) 0 0 0 1 : Software trigger 0 0 1 0 : Timer A0 0 0 1 1 : Timer A1 0 1 0 0 : Timer A2 0 1 0 1 : Timer A3 0 1 1 0 : Timer A4 0 1 1 1 : Timer B0 1 0 0 0 : Timer B1 1 0 0 1 : USB0/USB1 (Note 3) 1 0 1 0 : UART0 transmit 1 0 1 1 : UART0 receive 1 1 0 0 : UART2 transmit 1 1 0 1 : UART2 receive 1 1 1 0 : A-D conversion 1 1 1 1 : UART1 transmit/UART receive (Note 2) Nothing is assigned. Write "0" when writing to these bits. If read, the value is "0". DSR Software DMA request bit If software trigger is selected, a DMA request is generated by setting this bit to "1" (When read, the value of this bit is always "0") Note 1: Address 03B816 is for INT0, 3BA16 is for INT1. Note 2: Address 03B816 is for UART1 transmit, 03BA16 is for UART1 receive. Note 3: Address 03B816 is for USB0, 03BA16 is for USB1. Figure 1.54: DMAC register (1) Rev. H Sep 18, 2003 Page 61 of 139 R W DMAC M30240 Group DMAi control register b7 b6 b5 b4 b3 b2 b1 Address 002C 16, 003C 16 Symbol DMiCON(i=0,1) b0 Bit symbol Bit name When reset 00000X00 2 Function DMBIT Transfer unit bit select bit 0 : 16 bits 1 : 8 bits DMASL Repeat transfer mode select bit 0 : Single transfer 1 : Repeat transfer DMAS DMA request bit (Note 1) 0 : DMA not requested 1 : DMA requested DMA enable bit 0 : Disabled 1 : Enabled DSD Source address direction select bit (Note 3) 0 : Fixed 1 : Forward DAD Destination address 0 : Fixed direction select bit (Note 3) 1 : Forward DMAE R Nothing is assigned. Write "0" when writing to these bits. If read, the value is "0". Note 1: DMA request can be cleared by resetting the bit. Note 2: This bit can only be set to "0". Note 3: Source address direction select bit and destination address direction select bit cannot be set to "1" simultaneously. Figure 1.55: DMAC register (2) Rev. H Sep 18, 2003 Page 62 of 139 W (Note 2) DMAC M30240 Group DMAi source pointer (i = 0, 1) (b23) b7 (b19) b3 (b16)(b15) b0 b7 (b8) b0 b7 b0 Symbol SAR0 SAR1 Address 002216 to 0020 16 003216 to 0030 16 When reset Indeterminate Indeterminate Transfer count specification Function * Source pointer Stores the source address R W 00000 16 to FFFFF 16 Nothing is assigned. Write "0" when writing to these bits. If read, the value is "0". DMAi destination pointer (i = 0, 1) (b23) b7 (b19) b3 (b16) (b15) b0 b7 (b8) b0 b7 b0 Symbol DAR0 DAR1 Address 002616 to 0024 16 003616 to 0034 16 When reset Indeterminate Indeterminate Transfer count specification Function * Destination pointer Stores the destination address R W 00000 16 to FFFFF 16 Nothing is assigned. Write "0" when writing to these bits. If read, the value is "0". DMAi transfer counter (i = 0, 1) (b15) b7 (b8) b0 b7 b0 Symbol TCR0 TCR1 Address 002916, 0028 16 003916, 0038 16 Function * Transfer counter Set a value one less than the transfer count When reset Indeterminate Indeterminate Transfer count specification R W 0000 16 to FFFF 16 Figure 1.56: DMAC register (3) * Transfer cycle The transfer cycle consists of the bus cycle in which data is read from memory or from the SFR area (source read) and the bus cycle in which the data is written to memory or to the SFR area (destination write). The number of read and write bus cycles depends on the source and destination addresses and the software waits are inserted. * Effect of source and destination addresses When 16-bit data is transferred on a 16-bit data bus, and the source and destination both start at odd addresses, there is one more source read cycle and destination write cycle than when the source and destination both start at even addresses. * Calculations Any combination of even or odd transfer read and write addresses is possible. Table 1.16 show the number of DMAC transfer cycles. Table 1.17 shows the corresponding coefficient values. Figure 1.57 shows an example of the transfer cycle for a source read. The number of DMAC transfer cycles can be calculated as follows: Rev. H Sep 18, 2003 Page 63 of 139 DMAC M30240 Group Number of transfer cycles per transfer unit = Number of read cycles x j + Number of write cycles x k Table 1.16: Number of DMAC transfer cycles Single-chip mode Transfer unit Access address Number of read cycles Number of write cycles Even 1 1 Odd 1 1 Even 1 1 Odd 2 2 8-bit transfers (DMBIT="1") 16-bit transfers (DMBIT="0") Table 1.17: Coefficients j,k Internal memory Internal ROM/RAM No wait Internal ROM/RAM with wait SFR area 1 2 2 (1) 8-bit transfers 16-bit transfers from even address and the source address is even. Internal clock Address bus CPU use Data bus CPU use Source Destination Source CPU use Destination CPU use (2) 16-bit transfers and the source address is odd Internal clock Address bus Data bus CPU use CPU use Source Source + 1 Destination Source CPU use Source + 1 Destination CPU use (3) One wait is inserted into the source read under the conditions in (1) Internal clock Address bus Data bus CPU use CPU use Source Destination Source CPU use Destination CPU use (4) One wait is inserted into the source read under the conditions in (2) (When 16-bit data is transfferred on an 8-bit data but, there are two destination write cycles.) Internal clock Address bus Data bus CPU use CPU use Source Source Source + 1 Destination Source + 1 Destination CPU use CPU use Note : The same timing changes occur with the respective conditions at the destination as at the source. Figure 1.57: Example of the transfer cycle for a source read Rev. H Sep 18, 2003 Page 64 of 139 Timers M30240 Group 1.2.20 Timers There are eight 16-bit timers. These timers can be classified by function into timers A (five) and timers B (three). All these timers function independently. Figure 1.58 shows the block diagram of Timers A and B. f1 f8 XIN 1/8 1/4 f1 f 8 f32 f32 * Timer mode * One-shot mode * PWM mode TA0 IN Noise filter Timer A0 * Event counter mode Timer A0 interrupt * Timer mode * One-shot mode * PWM mode TA1 IN Noise filter Timer A1 * Event counter mode Timer A1 interrupt * Timer mode * One-shot mode * PWM mode TA2 IN Noise filter Timer A2 * Event counter mode Timer A2 interrupt * Timer mode * One-shot mode * PWM mode TA3 IN Noise filter Timer A3 * Event counter mode Timer A3 interrupt * Timer mode * One-shot mode * PWM mode TA4 IN Noise filter Timer A4 * Event counter mode Timer A4 interrupt * Timer mode Timer B0 Timer B0 interrupt * Timer mode Timer B1 Timer B1 interrupt * Timer mode Timer B2 Timer B2 overflow Figure 1.58: Timer A and Timer B block diagram Rev. H Sep 18, 2003 Page 65 of 139 Timer A M30240 Group 1.2.21 Timer A Figure 1.59, Figure 1.60,Figure 1.61, and Figure 1.62 show the timer A-related registers. Except in event counter mode, timers A0 through A4 all have the same function. Use the timer Ai mode register (i = 0 to 4) bits 0 and 1 to choose the desired mode. Timer A has the four operation modes listed as follows: * Timer mode: The timer counts an internal count source. * Event counter mode: The timer counts pulses from an external source or a timer over flow. * One-shot timer mode: The timer stops counting when the count reaches "000016". * Pulse width modulation (PWM) mode: The timer outputs pulses of a given width. Data bus high-order bits Clock source selection Data bus low-order bits * Timer * One shot * PWM f1 f8 f32 Low-order 8 bits * Timer (gate function) High-order 8 bits Reload register (16) * Event counter Counter (16) Polarity selection Up count/down count Clock selection TAi IN (i = 0 to 4) Always count down except in event counter mode Count start flag (Address 0380 16) TAi Timer A0 Timer A1 Timer A2 Timer A3 Timer A4 Down count TB2 overflow External trigger TAj overflow (j = i - 1. Note that j = 4 when i = 0) Up/down flag (Address 0384 16) Addresses 038716 038616 038916 038816 038B16 038A16 038D16 038C16 038F16 038E16 TAj Timer A4 Timer A0 Timer A1 Timer A2 Timer A3 TAk Timer A1 Timer A2 Timer A3 Timer A4 Timer A0 TAk overflow (k = i + 1. Note that k = 0 when i = 4) Pulse output TAi OUT (i = 0 to 4) Toggle flip-flop Figure 1.59: Block diagram of Timer A Timer Ai mode register b7 b6 b5 b4 b3 b2 b1 b0 Symbol TAiMR(i=0 to 4) Bit symbol TMOD0 TMOD1 Address 039616 to 039A 16 Bit name Function b1 b0 Operation mode select bit 0 0 : Timer mode 0 1 : Event counter mode 1 0 : One-shot timer mode 1 1 : Pulse width modulation (PWM) mode MR0 MR1 Function varies with each operation mode MR2 MR3 TCK0 TCK1 Figure 1.60: Timer A related Registers (1) Rev. H Sep 18, 2003 Page 66 of 139 When reset 0016 Count source select bit Function varies with each operation mode R W Timer A M30240 Group Timer Ai register (Note) (b15) b7 (b8) b0 b7 b0 Symbol TA0 TA1 TA2 TA3 TA4 Address 038716,0386 16 038916,0388 16 038B16,038A 16 038D16,038C 16 038F16,038E 16 When reset Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Function Values that can be set * Timer mode Counts an internal count source 000016 to FFFF 16 * Event counter mode Counts pulses from an external source or timer overflow 000016 to FFFF 16 * One-shot timer mode Counts a one shot width 0000 16 to FFFF 16 * Pulse width modulation mode (16-bit PWM) Functions as a 16-bit pulse width modulator 000016 to FFFE 16 R W 0016 to FE 16 (Both high-order and low-order addresses) * Pulse width modulation mode (8-bit PWM) Timer low-order address functions as an 8-bit prescaler and high-order address functions as an 8-bit pulse width modulator Note: Read and write data in 16-bit units. Count start flag b7 b6 b5 b4 b3 b2 b1 b0 Symbol TABSR Bit symbol Address 0380 16 When reset 0016 Bit name TA0S Timer A0 count start flag TA1S Timer A1 count start flag TA2S Timer A2 count start flag TA3S Timer A3 count start flag TA4S Timer A4 count start flag TB0S Timer B0 count start flag TB1S Timer B1 count start flag TB2S Timer B2 count start flag Function R W 0 : Stops counting 1 : Starts counting Up/down flag b7 b6 b5 b4 b3 b2 b1 b0 Symbol UDF Bit symbol Bit name TA0UD Timer A0 up/down flag TA1UD Timer A1 up/down flag TA2UD Timer A2 up/down flag TA3UD Timer A3 up/down flag TA4UD Timer A4 up/down flag TA2P Timer A2 two-phase pulse signal processing select bit TA3P Timer A3 two-phase pulse signal processing select bit TA4P Timer A4 two-phase pulse signal processing select bit Figure 1.61: Timer A-related registers (2) Rev. H Sep 18, 2003 Page 67 of 139 Address 038416 When reset 0016 Function 0 : Down count 1 : Up count This specification becomes valid when the up/down flag content is selected for up/down switching cause 0 : two-phase pulse signal processing disabled 1 : two-phase pulse signal processing enabled When not using the two-phase pulse signal processing function, set the select bit to "0" R W Timer A M30240 Group One-shot start flag b7 b6 b5 b4 b3 b2 b1 Symbol ONSF b0 Address 038216 Bit symbol When reset 00X00000 2 Bit name TA0OS Timer A0 one-shot start flag TA1OS Timer A1 one-shot start flag TA2OS Timer A2 one-shot start flag TA3OS Timer A3 one-shot start flag TA4OS Timer A4 one-shot start flag Function R W 1 : Timer start When read, the value is "0" Nothing is assigned. Write "0" when writing to this bit. When read, the value is indeterminate. b7 b6 TA0TGL TA0TGH Timer A0 event/trigger select bit 0 0 : Input on TA0 IN is selected (Note) 0 1 : TB2 overflow is selected 1 0 : TA4 overflow is selected 1 1 : TA1 overflow is selected Note: Set the corresponding port direction register to "0". Trigger select register b7 b6 b5 b4 b3 b2 b1 b0 Symbol TRGSR Address 0383 16 Bit symbol When reset 0016 Bit name Function b1 b0 TA1TGL Timer A1 event/trigger select bit TA1TGH 0 0 : Input on TA1 IN is selected (Note) 0 1 : TB2 overflow is selected 1 0 : TA0 overflow is selected 1 1 : TA2 overflow is selected b3 b2 TA2TGL Timer A2 event/trigger select bit TA2TGH 0 0 : Input on TA2 IN is selected (Note) 0 1 : TB2 overflow is selected 1 0 : TA1 overflow is selected 1 1 : TA3 overflow is selected b5 b4 TA3TGL TA3TGH Timer A3 event/trigger select bit 0 0 : Input on TA3 IN is selected (Note) 0 1 : TB2 overflow is selected 1 0 : TA2 overflow is selected 1 1 : TA4 overflow is selected b7 b6 TA4TGL TA4TGH Timer A4 event/trigger select bit 0 0 : Input on TA4 IN is selected (Note) 0 1 : TB2 overflow is selected 1 0 : TA3 overflow is selected 1 1 : TA0 overflow is selected Note: Set the corresponding port direction register to "0". Figure 1.62: Timer A-related registers (3) Rev. H Sep 18, 2003 Page 68 of 139 R W Timer A M30240 Group 1.2.21.1 Timer mode In this mode, the timer counts an internally generated count source. See Table 1.18 below. Figure 1.63 shows the timer Ai mode register in timer mode. Table 1.18: Specifications of timer mode Item Specification Count source f1, f8, f32 Count operation * Down count * When the timer underflows, it loads the reload register contents before continuing counting Divide ratio 1/(n+1) n: Set value Count start condition Count start flag is set (= 1) Count stop condition Count start flag is reset (= 0) Interrupt request generation timing When the timer underflows TAiIN pin function Programmable I/O port or gate input TAiOUT pin function Programmable I/O port or pulse output Read from timer Count value can be read out by reading timer Ai register Write to timer * When counting is stopped and a value is written to timer Ai register, it is written to both reload register and counter * When counting is in progress and a value is written to timer Ai register, it is written only to reload register (to be transferred to counter at the next reload time) Select function * Gate function Counting can be started and stopped by TAiIN pin's input signal * Pulse output function Each time the timer underflows, the TAiOUT pin's polarity is reversed Timer Ai mode register b7 b6 b5 0 b4 b3 b2 b1 b0 Address 039616 to 039A16 Symbol TAiMR(i=0 to 4) 0 0 Bit symbol TMOD0 Bit name 0 0 : Timer mode Pulse output function select bit 0 : Pulse is not output (TAiOUT pin is a normal port pin) 1 : Pulse is output (Note 1) (TAiOUT pin is a pulse output pin) Gate function select bit MR1 R W b4 b3 0 X : Gate function not available (Note 2)(TAi IN pin is a normal port pin) 1 0 : Timer counts only when TAiIN pin is held "L" (Note 3) 1 1 : Timer counts only when TAiIN pin is held "H" (Note 3) MR2 MR3 Function b1 b0 Operation mode select bit TMOD1 MR0 When reset 0016 0 (Must always be fixed to "0" in timer mode) b7 b6 TCK0 Count source select bit TCK1 0 0 1 1 0 : f1 1 : f8 0 : f 32 1 : Reserved Note 1: The settings of the corresponding port register and port direction register are invalid. Note 2: The bit can be "0" or "1". Note 3: Set the corresponding port direction register to "0". Figure 1.63: Timer Ai mode register in timer mode Rev. H Sep 18, 2003 Page 69 of 139 Timer A M30240 Group 1.2.21.2 Event counter mode In this mode, the timer counts an external signal or an internal timer's overflow. Timers A0 and A1 can count a single-phase external signal. Timers A2, A3, and A4 can count a single-phase and a twophase external signal. Table 1.19 lists the timer specifications when counting a single-phase external signal. Figure 1.64 shows Timer Ai mode register in event counter mode, Note: Timer Ai register's value can be indeterminate when the count starts. Table 1.19: Timer specification in event counter mode (when not processing two-phase pulse signal) Item Specification Count source * External signals input to TAiIN pin (effective edge can be selected by software) * TB2 overflow, TAj overflow Count operation * Up count or down count can be selected by external signal of software * When the timer overflows or underflows, it loads the reload register contents before continuing counting (However, this does not apply when the free-run function is selected) Divide ratio 1/(FFFF16-n+1) for up count 1/(n+1) for down count Count start condition Count start flag is set (= 1) Count stop condition Count start flag is reset (= 0) Interrupt request generation timing When the timer underflows or underflows TAiIN pin function Programmable I/O port or count source input TAiOUT pin function Programmable I/O port, pulse output, or up/down count select input Read from timer Count value can be read out by reading Timer Ai register Write to timer * When counting is stopped and a value is written to Timer Ai register, it is written to both reload register and counter * When counting is in progress and a value is written to Timer Ai register, it is written only to reload register (to be transferred to counter at the next reload time) Select function * Free-run count function (Note) When the timer overflows or underflows, the reload register's content is not reloaded. * Pulse output function Each time the timer underflows, the TAiOUT pin's polarity is reversed n: Set value Note: Timer Ai register's value can be indeterminate when the count starts. Timer Ai mode register b7 b6 b5 0 b4 b3 b2 b1 b0 Symbol TAiMR(i = 0, 1) 0 1 Address 0396 16, 0397 16 Bit symbol Bit name TMOD0 Operation mode select bit When reset 0016 Function R W R W b1 b0 0 1 : Event counter mode (Note 1) TMOD1 MR0 Pulse output function select bit 0 : Pulse is not output (TA iOUT pin is a normal port pin) 1 : Pulse is output (Note 2) (TA iOUT pin is a pulse output pin) MR1 Count polarity select bit (Note 3) 0 : Counts external signal's falling edge 1 : Counts external signal's rising edge MR2 Up/down switching cause select bit 0 : Up/down flag's content 1 : TA iOUT pin's input signal (Note 4) MR3 0 (Must always be fixed to "0" in event counter mode) TCK0 Count operation type select bit TCK1 Invalid in event counter mode Can be "0" or "1" 0 : Reload type 1 : Free-run type (Note 5) Note 1: In event counter mode, the count source is selected by the event / trigger select bit (addresses 038216 and 038316). Note 2: The settings of the corresponding port register and port direction register are invalid. Note 3: Valid only when counting an external signal. Note 4: When an "L" signal is input to the TAi OUT pin, the downcount is activated. When "H", the upcount is activated. Set the corresponding port direction register to "0". Note 5: This value can be indeterminate when the count starts. Figure 1.64: Timer Ai mode register in event counter mode, single signal Rev. H Sep 18, 2003 Page 70 of 139 Timer A M30240 Group Table 1.20: Timer specification in event counter mode (when processing two-phase pulse signal with Timers A2, A3, A4.) Item Count Source Count operation Divide ratio Specification *Two-phase pulse signals input to TAiIN or TAiOUT pin *Up count or down count can be selected by two-phase pulse signal *When the timer overflows or underflows, the reload register content is loaded and the timer starts over again (Note 1) 1/ (FFFF16 - n + 1) for up count 1/ (n+1) for down count Count start condition Count start flag is set (=1) Count stop condition Count start flag is reset (=0) Interrupt request generation timing Timer overflow or underflows TAiIN pin function Two-phase pulse input TAiOUT pin function Read from timer Writer to timer n: Set value Two-phase pulse input Count value can be read out by reading timer A2, A3, or A4 register *When counting is stopped and a value is written to timer A2, A3, or A4 register, it is written to both the reload register and counter *When counting is in progress and a value is written to timer A2, A3, or A4 register, it is written to only reload register to be transferred to counter at the next reload time. *Normal processing operation The timer counts up rising edges or counts down falling edges on the TAiIN pin when input signal on the TAiOUT pin is "H" TAiOUT TAiIN (i=2,3) Up count Up count Up count Down count Down count Down count *Multiply-by-4 processing operation If the phase relationship is such that the TAiIN pin goes "H" when the input signal on the TAiOUT pin Select function is "H", the timer counts up rising and falling edges on the TAiOUT and TAiIN pins. If the phase relationship is such that the TAiIN pin goes "L" when the input signal on the TAiOUT pin is "H", the timer counts down rising and falling edges on the TAiOUT and TAiIN pins. TAiOUT Count up all edges Count down all edges TAiIN (i=3,4) Count up all edges Count down all edges Figure 1.65 shows Timer Ai mode register in event counter mode when processing two-phase signal. Rev. H Sep 18, 2003 Page 71 of 139 Timer A M30240 Group Timer Ai mode register (When not using two-phase pulse signal processing) b7 b6 b5 b4 b3 b2 0 b1 Address 039816 to 039A 16 Symbol TAiMR(i = 2 to 4) b0 0 1 Bit symbol TMOD0 Bit name When reset 0016 Function Operation mode select bit TMOD1 R W b1 b0 0 1 : Event counter mode MR0 Pulse output function select bit 0 : Pulse is (TAi OUT 1 : Pulse is (TAi OUT not output pin is a normal port pin) output (Note 1) pin is a pulse output pin) MR1 Count polarity select bit (Note 2) 0 : Counts external signal's falling edges 1 : Counts external signal's rising edges MR2 Up/down switching cause select bit 0 : Up/down flag's content 1 : TA iOUT pin's input signal (Note 3) MR3 0 : (Must always be "0" in event counter mode) TCK0 Count operation type select bit 0 : Reload type 1 : Free-run type (Note 6) TCK1 Two-phase pulse signal processing operation select bit (Note 4)(Note 5) 0 : Normal processing operation 1 : Multiply-by-4 processing operation Note Note Note Note 1: 2: 3: 4: The settings of the corresponding port register and port direction register are invalid. This bit is valid when only counting an external signal. Set the corresponding port direction register to "0". This bit is valid for the Timer A3 mode register. For Timer A2 and A4 mode registers, this bit can be "0 "or "1". Note 5: When performing two-phase pulse signal processing, make sure the two-phase pulse signal processing operation select bit (address 038416) is set to "1". Also, always be sure to set the event/trigger select bit (addresses 038216 and 0383 16) to "00". Note 6: This value can be indeterminate when the count starts. Timer Ai mode register (When using two-phase pulse signal processing) b7 b6 b5 b4 b3 b2 b1 b0 0 1 0 0 0 1 Symbol TAiMR(i = 2 to 4) Bit symbol TMOD0 Address 039816 to 039A 16 Bit name Operation mode select bit TMOD1 When reset 0016 Function R W b1 b0 0 1 : Event counter mode MR0 0 (Must always be "0" when using two-phase pulse signal processing) MR1 0 (Must always be "0" when using two-phase pulse signal processing) MR2 1 (Must always be "1" when using two-phase pulse signal processing) MR3 0 (Must always be "0" when using two-phase pulse signal processing) TCK0 Count operation type select bit 0 : Reload type 1 : Free-run type (Note 3) TCK1 Two-phase pulse processing operation select bit (Note 1)(Note 2) 0 : Normal processing operation 1 : Multiply-by-4 processing operation Note 1: This bit is valid for Timer A3 mode register. For Timer A2 and A4 mode registers, this bit can be "0" or "1". Note 2: When performing two-phase pulse signal processing, make sure the two-phase pulse signal processing operation select bit (address 038416) is set to "1". Also, always be sure to set the event/trigger select bit (addresses 038216 and 0383 16) to "00". Note 3: This value can be indeterminate when the count starts. Figure 1.65: Timer Ai mode register in event counter mode, two-phase signal Rev. H Sep 18, 2003 Page 72 of 139 Timer A M30240 Group 1.2.21.3 One-shot timer mode In this mode, the timer operates only once (See Table 1.21 ). When a trigger occurs, the timer starts up and continues operating for a given period. Figure 1.66 shows the Timer Ai mode register in oneshot mode. Table 1.21: Timer specifications in one-shot timer mode Item Specification Count source f1, f8, f32 Count operation *The timer counts down *When the count reaches 000016, the timer stops counting after reloading a new count * If a trigger occurs when counting, the timer reloads a new count and restarts counting Divide ratio 1/n Count start condition * An external trigger is input * The selected timer overflows * The one-shot start flag is set (= 1) Count stop condition * A new count is reloaded after the count has reached 000016 * The count start flag is reset (= 0) Interrupt request generation timing The count reaches 000016 TAiIN pin function Programmable I/O port or trigger input TAiOUT pin function Programmable I/O port or pulse output Read from timer When timer Ai register is read, it indicates an indeterminate value Write to timer *When counting is stopped and a value is written to timer Ai register, it is written to both reload register and counter *When counting is in progress and a value is written to timer Ai register, it is written to the reload register to be transferred to counter at next load time n: Set value Timer Ai mode register b7 b6 b5 0 b4 b3 b2 b1 b0 1 0 Address 039616 to 039A 16 Symbol TAiMR(i=0 to 4) Bit symbol TMOD0 TMOD1 MR0 Bit name When reset 0016 Function R W b1 b0 Operation mode select bit 1 0 : One-shot timer mode Pulse output function select bit 0 : Pulse is not output (TA iOUT pin is a normal port pin) 1 : Pulse is output (Note 1) (TAiOUT pin is a pulse output pin) 0 : Falling edge of TAi IN pin's input signal MR1 External trigger select bit (Note 2) (Note3) 1 : Rising edge of TAi IN pin's input signal (Note3) 0 : One-shot start flag is valid 1 : Selected by event/trigger select register MR2 Trigger select bit MR3 0 (Must always be fixed to "0" in timer mode) b7 b6 TCK0 Count source select bit TCK1 0 0 : f1 0 1 : f8 1 0 : f 32 1 1 : Reserved Note 1: The settings of the corresponding port register and port direction register are invalid. Note 2: Valid only when the TAiIN pin is selected by the event/trigger select bit. (addresses 038216 and 038316). If timer overflow is selected, this bit can be "1", or "0". Note 3: Set the corresponding port direction register to "0". Figure 1.66: Timer Ai mode register in one-shot mode Rev. H Sep 18, 2003 Page 73 of 139 Timer A M30240 Group 1.2.21.4 Pulse-width modulation (PWM) mode In this mode, the timer outputs pulses of a given width in succession (See Table 1.22 ). In this mode, the counter functions as either a 16-bit pulse-width modulator or an 8-bit pulse-width modulator. Figure 1.67 shows an example of how a 16-bit pulse-width modulator operates. Figure 1.68 shows the Timer Ai mode register in pulse-width modulation mode. Figure 1.69 shows the example of how an 8-bit pulse width modulator operates. Table 1.22: Timer specifications in pulse-width modulation mode Item Specification Count source f1, f8, f32 Count operation *The timer counts down (operating as an 8-bit or a 16-bit pulse-width modulator) *The timer reloads a new count at a rising edge of PWM pulse and continues counting * The timer is not affected by a trigger that occurs when counting 16-bit PWM *High level width n / fi 8-bit PWM Count start condition n: Set value 16-1) / fi fixed n (m+1) /fi n: values set to timer Ai register's high-order address *Cycle time (28-1) (m+1) /fi m: values set to timer Ai register's low-order address *External trigger is input *The timer overflows *The count start flag is set (= 1) *Cycle time (2 *High level width Count stop condition *The count start flag is reset (= 0) Interrupt request generation timing PWM pulse goes "L" TAiIN pin function Programmable I/O port or trigger input TAiOUT pin function Pulse output Read from timer When Timer Ai register is read, it indicates an indeterminate value Write to timer *When counting is stopped and a value is written to Timer Ai register, it is written to both reload register and the counter *When counting in progress and a value is written to Timer A register, it is written to only reload register to be transferred to the counter at next reload timer. Condition : Reload register = 0003 16 , when external trigger (rising edge of TA iIN pin input signal) is selected 1 / f i X (2 16 - 1) Count source TA iIN pin input signal "H" "L" Trigger is not generated by this signal 1 / fi X n PWM pulse output from TA iOUT pin "H" Timer Ai interrupt request bit "1" "L" "0" fi : Frequency of count source (f1, f8, f32 ) Cleared to "0" when interrupt request is accepted, or cleared by software Note: n = 0000 16 to FFFE 16 Figure 1.67: Example of how a 16-bit pulse-width modulator operates Rev. H Sep 18, 2003 Page 74 of 139 Timer A M30240 Group Timer Ai mode register b7 b6 b5 b4 b3 b2 b1 b0 Address 039616 to 039A 16 Symbol TAiMR(i=0 to 4) 1 1 1 Bit symbol TMOD0 TMOD1 Bit name When reset 0016 Function R W b1 b0 Operation mode select bit 1 1 : PWM mode MR0 Must always be "1" in PWM mode) MR1 External trigger select bit (Note 1) 0 : Falling edge of TAi IN pin's input signal (Note 2) 1 : Rising edge of TAi IN pin's input signal (Note 2) MR2 Trigger select bit 0 : Count start flag is valid 1 : Selected by event /trigger select register MR3 16/8 PWM mode select bit 0 : Functions as a 16-bit pulse width modulator 1 : Functions as an 8-bit pulse width modulator b7 b6 TCK0 Count source select bit TCK1 0 0 1 1 0 1 0 1 : f1 : f8 : f 32 : Reserved Note 1: Valid only when the TAi IN pin is selected by the event/trigger select bit. (addresses 0382 16 and 0383 16). If timer overflow is selected, this bit can be "1", or "0". Note 2: Set the corresponding port direction register to "0". Figure 1.68: Timer Ai mode register in pulse-width modulation mode Condition : Reload register high-order 8 bits = 02 16 Reload register low-order 8 bits = 02 16 External trigger (falling edge of TAiIN pin input signal) is selected 8 1 / fi X (m + 1) X (2 - 1) Count source (Note1) TA iIN pin input signal "H" "L" 1 / f i X (m + 1) "H" Underflow signal of 8-bit prescaler (Note 2) "L" 1 / f i X (m + 1) X n PWM pulse output from TA iOUT pin "H" Timer Ai interrupt request bit "1" "L" "0" fi : Frequency of count source (f1, f8, f32 ) Cleared to "0" when interrupt request is accepted, or cleared by software Note 1: The 8-bit prescaler counts the count source. Note 2: The 8-bit pulse width modulator counts the 8-bit prescaler's underflow signal. Note 3: m = 0016 to FE16; n = 0016 to FE16 Figure 1.69: Example of how an 8-bit pulse-width modulator operates Rev. H Sep 18, 2003 Page 75 of 139 Timer B M30240 Group 1.2.22 Timer B Figure 1.70 shows the block diagram of timer B. Figure 1.71 and Figure 1.72 show the Timer B-related registers. Use the Timer Bi mode register (i = 0 to 2) bits 0 and 1 to choose the desired mode. Timer B works in Timer mode only (i.e., the timer counts an in internal count source). Data bus high-order bits Data bus low-order bits Clock source selection Low-order 8 bits f1 High-order 8-bits Reload register (16) f8 f32 Counter (16) Count start flag (address 0380 16) Counter reset circuit TBi Timer B0 Timer B1 Timer B2 TBj overflow j = i - 1. Note, however, j = 2 when i = 0 Address TBj 0391 16 039016 Timer B2 0393 16 0392 16 Timer B0 039516 039416 Timer B1 Figure 1.70: Block diagram of Timer B Timer Bi mode register b7 b6 b5 b4 b3 b2 b1 Symbol TBiMR(i=0 to 2) b0 00 Bit symbol TMOD0 TMOD1 MR0 MR1 MR2 Address 039B 16 to 039D 16 Bit name When reset 00XX0000 2 Function R b1 b0 Operation mode select bit 0 0 : Timer mode Invalid in timer mode Can be "0" or "1" 0 (Fixed to "0" in timer mode ; i = 0) (Note 1) Nothing is assigned (i=1,2). In an attempt to write to this bit, write "0". The value, if read, turns out to be indeterminate. (Note 2) MR3 Invalid in timer mode. In an attempt to write to this bit, write "0". The value, if read, turns out to be indeterminate. b7 b6 TCK0 TCK1 Count source select bit Note 1: Timer B0. Note 2: Timer B1, Timer B2. Figure 1.71: Timer B-related registers (1) Rev. H Sep 18, 2003 Page 76 of 139 0 0 : f1 0 1 : f8 1 0 : f 32 1 1 : Reserved W Timer B M30240 Group Timer Bi register (Note) (b15) b7 (b8) b0 b7 Symbol TB0 TB1 TB2 b0 Address 039116, 0390 16 039316, 0392 16 039516, 0394 16 Function When reset Indeterminate Indeterminate Indeterminate Values that can be set * Timer mode Counts the timer's period R W 000016 to FFFF 16 Note: Read and write data in 16-bit units. Count start flag b7 b6 b5 b4 b3 b2 b1 b0 Symbol TABSR Address 0380 16 Bit symbol When reset 0016 Bit name Function TA0S Timer A0 count start flag TA1S Timer A1 count start flag TA2S Timer A2 count start flag TA3S Timer A3 count start flag TA4S Timer A4 count start flag TB0S Timer B0 count start flag TB1S Timer B1 count start flag TB2S Timer B2 count start flag R W 0 : Stops counting 1 : Starts counting Figure 1.72: Timer B-related registers (2) 1.2.22.1 Timer mode In this mode, the timer counts an internally generated count source as shown in Table 1.23 . Table 1.23: Timer B timer specifications in timer mode Item Specification Count source f1, f8, f32 Count operation * Counts down * When the timer underflows, it reloads the reload register contents before continuing counting Divide ratio 1/(n+1) Count start condition Count start flag is set (= 1) Count stop condition Count start flag is reset (= 0) Interrupt request generation timing The timer underflows (see Note) Read from timer Count value is read out by reading timer Bi register Write to timer * When counting stopped When a value is written to Timer Bi register, it is written to both reload register and counter * When counting is in progress When a value is written to Timer Bi register, it is written to only reload register (Transferred to counter at the next reload time) n: Set value Note: Timer B2 does not generate an interrupt; it is used as a prescaler only. Rev. H Sep 18, 2003 Page 77 of 139 UART0 to UART2 M30240 Group 1.2.23 UART0 to UART2 Serial I/O is configured as three channels: UART0, UART1, and UART2. UART0, UART1, and UART2 each have an exclusive timer to generate a transfer clock, so they operate independently of each other. Figure 1.73 shows the block diagram of UART0, UART1, and UART2. Figure 1.74 and Figure 1.75 show the block diagram of the transmit/receive unit. (UART0) RxD0 TxD0 UART reception 1/16 Clock source selection Bit rate generator Internal (address 03A1 16) f1 f8 f32 1 / (n0+1) Reception control circuit Clock synchronous type UART transmission 1/16 Transmission control circuit Clock synchronous type External Receive clock Transmit/ receive unit Transmit clock Clock synchronous type (when internal clock is selected) 1/2 Clock synchronous type (when internal clock is selected) Clock synchronous type (when external clock is selected) CLK polarity reversing circuit CLK0 CTS/RTS disabled CTS/RTS selected RTS 0 CTS0 / RTS 0 VCC CTS/RTS disabled CTS0 (UART1) RxD1 TxD1 Clock source selection Bit rate generator Internal (address 03A9 16) f1 f8 f32 1 / (n1+1) Clock synchronous type UART transmission 1/16 1/2 CLK1 CTS1 / RTS1 CLKS1 Reception control circuit Transmission control circuit Clock synchronous type Clock synchronous type External CLK polarity reversing circuit UART reception 1/16 Receive clock Transmit/ receive unit Transmit clock (when internal clock is selected) Clock synchronous type (when internal clock is selected) Clock synchronous type (when external clock is selected) CTS/RTS disabled RTS 1 VCC Clock output pin select switch CTS/RTS disabled CTS1 (UART2) TxD polarity reversing circuit RxD polarity reversing circuit RxD2 Clock source selection Bit rate generator Internal (address 0379 16) f1 f8 f32 UART reception 1/16 1 / (n2+1) Clock synchronous type UART transmission 1/16 Clock synchronous type External Reception control circuit Transmission control circuit Receive clock TxD2 Transmit/ receive unit Transmit clock Clock synchronous type 1/2 CLK2 CLK polarity reversing circuit (when internal clock is selected) Clock synchronous type (when internal clock is selected) CTS/RTS selected Clock synchronous type (when external clock is selected) CTS/RTS disabled RTS 2 CTS2 / RTS 2 Vcc CTS/RTS disabled CTS2 Figure 1.73: Block diagram of UARTi (i=0 to 2) Rev. H Sep 18, 2003 Page 78 of 139 n0 : Values set to UART0 bit rate generator (BRG0) n1 : Values set to UART1 bit rate generator (BRG1) n2 : Values set to UART2 bit rate generator (BRG2) UART0 to UART2 M30240 Group Clock synchronous type SP RxDi SP UART (7 bits) UART (8 bits) Clock synchronous type PAR disabled 1SP UARTi receive register UART (7 bits) PAR PAR enabled 2SP UART UART (9 bits) Clock synchronous type UART (8 bits) UART (9 bits) 0 0 0 0 0 0 0 D8 D7 D6 D5 D4 D3 D2 D1 D0 UARTi receive buffer register Address 03A616 Address 03A716 Address 03AE16 Address 03AF16 MSB/LSB conversion circuit Data bus low-order bits MSB/LSB conversion circuit D7 D8 D6 D5 D4 D3 D2 D1 D0 Address 03A216 Address 03A316 Address 03AA16 Address 03AB16 UART (8 bits) UART (9 bits) Clock synchronous type UART (9 bits) PAR enabled 2SP SP SP UARTi transmit buffer register UART TxDi PAR 1SP PAR disabled Clock synchronous type UART (7 bits) UARTi transmit register UART (7 bits) UART (8 bits) "0" SP: Stop bit PAR: Parity bit Clock synchronous type Figure 1.74: Block diagram of UARTi (i=0,1) transmit/receive circuit No reverse RxD data reverse circuit RxD2 Reverse Clock synchronous type PAR disabled 1SP SP UART (7 bits) UART (8 bits) Clock synchronous type 2SP PAR enabled UART Clock synchronous type UART (9 bits) PAR: Parity bit 0 UART2 receive register UART(7 bits) PAR SP 0 0 0 0 0 0 UART (8 bits) UART (9 bits) D8 D0 UART2 receive buffer register Logic reverse circuit + MSB/LSB conversion circuit Address 037E16 Address 037F16 D7 D6 D5 D4 D3 D2 D1 Data bus high-order bits Data bus low-order bits Logic reverse circuit + MSB/LSB conversion circuit D7 D8 D6 D5 D4 D3 D2 D1 D0 UART2 transmit buffer register Address 037A16 Address 037B16 UART (8 bits) UART (9 bits) PAR enabled 2SP SP SP UART (9 bits) Clock synchronous type UART PAR 1SP PAR disabled "0" Clock synchronous type UART (7 bits) UART (8 bits) UART(7 bits) UART2 transmit register Clock synchronous type Error signal output disable No reverse TxD data reverse circuit Error signal output circuit Error signal output enable Reverse SP: Stop bit PAR: Parity bit Figure 1.75: Block diagram of UART2 transmit/receive circuit Rev. H Sep 18, 2003 Page 79 of 139 TxD2 UART0 to UART2 M30240 Group UARTi (i = 0 to 2) has two operation modes: a clock synchronous serial I/O mode and a clock asynchronous serial I/O mode (UART mode). The contents of the serial I/O mode select bits (bits 0 to 2 at addresses 03A016, 03A816 and 037816) determine whether UARTi is used as a clock synchronous serial I/O or as a UART. Although a few functions are different, UART0 and UART1 have almost the same functions. UART0 through UART2 are almost equal in their functions with minor exceptions.Table 1.24 shows the comparison of functions of UART0 through UART2, and Figure 1.76, Figure 1.77, Figure 1.78, Figure 1.79, and Figure 1.80 show the registers related to UARTi. Table 1.24: Comparison of functions of UART0 through UART2 Function UART0 UART1 UART2 CLK polarity selection Possible (Note 1) Possible (Note 1) Possible (Note 1) LSB first / MSB first selection Possible (Note 1) Possible (Note 1) Possible (Note 2) Continuous receive mode selection Possible (Note 1) Possible (Note 1) Possible (Note 1) Transfer clock output from multiple pins selection Impossible Possible (Note 1) Impossible Serial data logic switch Impossible Impossible Possible (Note 4) Sleep mode selection Possible (Note 3) Possible (Note 3) Impossible TxD, RxD I/O polarity switch Impossible Impossible Possible TxD, RxD port output format CMOS output CMOS output CMOS output Parity error signal output Impossible Impossible Possible (Note 4) Bus collision detection Impossible Impossible Possible Note 1: Note 2: Note 3: Note 4: Only during clock synchronous serial I/O mode. Only during clock synchronous serial I/O mode and 8-bit UART mode. Only during UART mode. Used for SIM interface. Rev. H Sep 18, 2003 Page 80 of 139 UART0 to UART2 M30240 Group UARTi transmit buffer register (b15) b7 (b8) b0 b7 b0 Symbol U0TB U1TB U2TB Address 03A3 16, 03A216 03AB 16, 03AA16 037B 16, 037A16 When reset Indeterminate Indeterminate Indeterminate Function R W Transmit data Nothing is assigned. These bits can neither be set nor reset. When read, their contents are indeterminate. UARTi receive buffer register (b15) b7 (b8) b0 b7 Symbol U0RB U1RB U2RB b0 Bit symbol Address 03A716, 03A6 16 03AF16, 03AE 16 037F16, 037E 16 When reset Indeterminate Indeterminate Indeterminate Function (During clock synchronous serial I/O mode) Bit name Receive data Function (During UART mode) R W Receive data Nothing is assigned. These bits can neither be set nor reset. When read, the value of these bits is "0". OER Overrun error flag (Note) 0 : No overrun error 1 : Overrun error found 0 : No overrun error 1 : Overrun error found FER Framing error flag (Note) Invalid 0 : No framing error 1 : Framing error found PER Parity error flag (Note) Invalid 0 : No parity error 1 : Parity error found SUM Error sum flag (Note) Invalid 0 : No error 1 : Error found Note : Bits 15 through 12 are set to "0" when the serial I/O mode select bit (bits 2 to 0 at addresses 03A0 16, 03A816 and 0378 16) are set to "000 2" or the receive enable bit is set to "0". (Bit 15 is set to "0" when bits 14 to 12 all are set to "0".) Bits 14 and 13 are also set to "0" when the lower byte of the UARTi receive buffer register (addresses 03A616 , 03AE16 and 037E 16) is read out. UARTi bit rate generator b7 Symbol U0BRG U1BRG U2BRG b0 Address 03A116 03A916 037916 When reset Indeterminate Indeterminate Indeterminate Function Assuming that set value = n, BRGi divides the count source by n+1 Figure 1.76: Serial I/O-related registers (1) Rev. H Sep 18, 2003 Page 81 of 139 Values that can be set 0016 to FF 16 R W UART0 to UART2 M30240 Group UARTi transmit/receive mode register b7 b6 b5 b4 b3 b2 b1 b0 Symbol UiMR(i=0,1) Address 03A016, 03A816 When reset 0016 Function (During clock synchronous serial I/O mode) Bit symbol Bit name SMD0 Serial I/O mode select bit Must be fixed to 001 b2 b1 b0 0 0 0 : Serial I/O invalid 0 1 0 : Inhibited 0 1 1 : Inhibited 1 1 1 : Inhibited SMD1 SMD2 Function (During UART mode) R W b2 b1 b0 1 0 0 : Transfer data 7 bits long 1 0 1 : Transfer data 8 bits long 1 1 0 : Transfer data 9 bits long 0 0 0 : Serial I/O invalid 0 1 0 : Inhibited 0 1 1 : Inhibited 1 1 1 : Inhibited CKDIR Internal/external clock select bit 0 : Internal clock 1 : External clock 0 : Internal clock 1 : External clock STPS Stop bit length select bit Invalid 0 : One stop bit 1 : Two stop bits PRY Odd/even parity select bit Invalid Valid when bit 6 = "1" 0 : Odd parity 1 : Even parity PRYE Parity enable bit Invalid 0 : Parity disabled 1 : Parity enabled SLEP Sleep select bit Must always be "0" 0 : Sleep mode deselected 1 : Sleep mode selected UART2 transmit/receive mode register b7 b6 b5 b4 b3 b2 b1 Symbol U2MR b0 Address 0378 16 Bit symbol Bit name SMD0 Serial I/O mode select bit When reset 0016 Function (During clock synchronous serial I/O mode) Must be fixed to 001 b2 b1 b0 0 0 0 : Serial I/O invalid 0 1 1 : Inhibited 1 1 1 : Inhibited SMD1 SMD2 Function (During UART mode) b2 b1 b0 1 0 0 : Transfer data 7 bits long 1 0 1 : Transfer data 8 bits long 1 1 0 : Transfer data 9 bits long 0 0 0 : Serial I/O invalid 0 1 1 : Inhibited 1 1 1 : Inhibited CKDIR Internal/external clock select bit 0 : Internal clock 1 : External clock Must always be "0" STPS Stop bit length select bit Invalid 0 : One stop bit 1 : Two stop bits PRY Odd/even parity select bit Invalid Valid when bit 6 = "1" 0 : Odd parity 1 : Even parity PRYE Parity enable bit Invalid 0 : Parity disabled 1 : Parity enabled IOPOL TxD, RxD I/O polarity reverse bit 0 : No reverse 1 : Reverse Usually set to "0" 0 : No reverse 1 : Reverse Usually set to "0" Figure 1.77: Serial I/O-related registers (2) Rev. H Sep 18, 2003 Page 82 of 139 R W UART0 to UART2 M30240 Group UARTi transmit/receive control register 0 b7 b6 b5 b4 b3 b2 b1 b0 Symbol UiC0(i=0,1) Bit symbol CLK0 Address When reset 0816 03A4 16, 03AC 16 Function (During clock synchronous serial I/O mode) Bit name b1 b0 TXEPT 0 0 : f 1 is selected 0 1 : f 8 is selected 1 0 : f 32 is selected 1 1 : Reserved 0 0 : f 1 is selected 0 1 : f 8 is selected 1 0 : f 32 is selected 1 1 : Reserved CTS/RTS function select bit Valid when bit 4 = "0" 0 : CTS function is selected (Note 1) 1 : RTS function is selected (Note 2) Valid when bit 4 = "0" 0 : CTS function is selected (Note 1) 1 : RTS function is selected (Note 2) 0 : Data present in transmit register (during transmission) 1 : No data present in transmit register (transmission completed) 0 : Data present in transmit register (during transmission) 1 : No data present in transmit register (transmission completed) CRD 0 : CTS/RTS function enabled 1 : CTS/RTS function disabled (P60 and P6 4 function as programmable I/O port) 0 : CTS/RTS function enabled 1 : CTS/RTS function disabled (P60 and P6 4 function as programmable I/O port) Transmit register empty flag CTS/RTS disable bit R W b1 b0 BRG count source select bit CLK1 CRS Function (During UART mode) Nothing is assigned. This bit can neither be set nor reset. When read, the value of this bit is "0". CKPOL CLK polarity select bit 0 : Transmit data is output at falling edge of transfer clock and receive data is input at rising edge 1 : Transmit data is output at rising edge of transfer clock and receive data is input at falling edge UFORM Transfer format select bit 0 : LSB first 1 : MSB first Must always be "0" Must always be "0" Note 1: Set the corresponding port direction register to "0". Note 2: The settings of the corresponding port register and port direction register are invalid. UART2 transmit/receive control register 0 b7 b6 b5 b4 b3 b2 b1 b0 Symbol U2C0 Bit symbol CLK0 Address 037C16 Bit name TXEPT CRD Function (During clock synchronous serial I/O mode) Function (During UART mode) BRG count source select bit b1 b0 b1 b0 0 0 : f 1 is selected 0 1 : f 8 is selected 1 0 : f 32 is selected 1 1 : Reserved 0 0 : f 1 is selected 0 1 : f 8 is selected 1 0 : f 32 is selected 1 1 : Reserved CTS/RTS function select bit Valid when bit 4 = "0" 0 : CTS function is selected (Note 1) 1 : RTS function is selected (Note 2) Valid when bit 4 = "0" 0 : CTS function is selected (Note 1) 1 : RTS function is selected (Note 2) 0 : Data present in transmit register (during transmission) 1 : No data present in transmit register (transmission completed) 0 : Data present in transmit register (during transmission) 1 : No data present in transmit register (transmission completed) 0 : CTS/RTS function enabled 1 : CTS/RTS function disabled (P73 functions programmable I/O port) 0 : CTS/RTS function enabled 1 : CTS/RTS function disabled (P73 functions programmable I/O port) CLK1 CRS When reset 0816 Transmit register empty flag CTS/RTS disable bit Nothing is assigned. This bit can neither be set nor reset. When read, the value of this bit is "0". CKPOL CLK polarity select bit 0 : Transmit data is output at falling edge of transfer clock and receive data is input at rising edge 1 : Transmit data is output at rising edge of transfer clock and receive data is input at falling edge UFORM Transfer format select bit 0 : LSB first (Note 3) 1 : MSB first Must always be "0" 0 : LSB first 1 : MSB first Note 1: Set the corresponding port direction register to "0". Note 2: The settings of the corresponding port register and port direction register are invalid. Note 3: Only clock synchronous serial I/O mode and 8-bit UART mode are valid. Figure 1.78: Serial I/O-related registers (3) Rev. H Sep 18, 2003 Page 83 of 139 R W UART0 to UART2 M30240 Group UARTi transmit/receive control register 1 b7 b6 b5 b4 b3 b2 b1 b0 Address 03A5 16 , 03AD 16 Symbol UiC1(i=0,1) Bit symbol Bit name Function (During clock synchronous serial I/O mode) When reset 0216 Function (During UART mode) TE Transmit enable bit 0 : Transmission disabled 1 : Transmission enabled 0 : Transmission disabled 1 : Transmission enabled TI Transmit buffer empty flag 0 : Data present in transmit buffer register 1 : No data present in transmit buffer register 0 : Data present in transmit buffer register 1 : No data present in transmit buffer register RE Receive enable bit 0 : Reception disabled 1 : Reception enabled 0 : Reception disabled 1 : Reception enabled RI Receive complete flag 0 : No data present in receive buffer register 1 : Data present in receive buffer register 0 : No data present in receive buffer register 1 : Data present in receive buffer register RW Nothing is assigned. Write "0" when writing to these bits. If read, the value is "0". UART2 transmit/receive control register 1 b7 b6 b5 b4 b3 b2 b1 b0 Address 037D16 Symbol U2C1 Bit symbol Bit name Function (During clock synchronous serial I/O mode) When reset 0216 Function (During UART mode) 0 : Transmission disabled 1 : Transmission enabled 0 : Transmission disabled 1 : Transmission enabled Transmit buffer empty flag 0 : Data present in transmit buffer register 1 : No data present in transmit buffer register 0 : Data present in transmit buffer register 1 : No data present in transmit buffer register RE Receive enable bit 0 : Reception disabled 1 : Reception enabled 0 : Reception disabled 1 : Reception enabled RI Receive complete flag 0 : No data present in receive buffer register 1 : Data present in receive buffer register 0 : No data present in receive buffer register 1 : Data present in receive buffer register UART2 transmit interrupt cause select bit 0 : Transmit buffer empty (TI = 1) 1 : Transmit is completed (TXEPT = 1) 0 : Transmit buffer empty (TI = 1) 1 : Transmit is completed (TXEPT = 1) U2RRM UART2 continuous receive mode enable bit 0 : Continuous receive mode disabled 1 : Continuous receive mode enabled Invalid U2LCH Data logic select bit 0 : No reverse 1 : Reverse 0 : No reverse 1 : Reverse U2ERE Error signal output enable bit Must be fixed to "0" 0 : Output disabled TE Transmit enable bit TI U2IRS Figure 1.79: Serial I/O-related registers (4) Rev. H Sep 18, 2003 Page 84 of 139 1 : Output enabled RW UART0 to UART2 M30240 Group UART transmit/receive control register 2 b7 b6 b5 b4 b3 b2 b1 b0 Symbol UCON 0 Bit symbol Address 03B0 16 When reset X0000000 2 Function (During clock synchronous serial I/O mode) Bit name Function (During UART mode) UART0 transmit interrupt cause select bit 0 : Transmit buffer empty (Tl = 1) 1 : Transmission completed UART1 transmit interrupt cause select bit 0 : Transmit buffer empty (Tl = 1) 1 : Transmission completed U0RRM UART0 continuous receive mode enable bit 0 : Continuous receive mode disabled 1 : Continuous receive mode enable Invalid U1RRM UART1 continuous receive mode enable bit 0 : Continuous receive mode disabled 1 : Continuous receive mode enabled Invalid CLKMD0 CLK/CLKS select bit 0 Valid when bit 5 = "1" 0 : Clock output to CLK1 1 : Clock output to CLKS1 Invalid CLKMD1 CLK/CLKS select bit 1 (Note) 0 : Normal mode Must always be "0" U0IRS U1IRS (TXEPT = 1) (TXEPT = 1) (CLK output is CLK1 only) R W 0 : Transmit buffer empty (Tl = 1) 1 : Transmission completed (TXEPT = 1) 0 : Transmit buffer empty (Tl = 1) 1 : Transmission completed (TXEPT = 1) 1 : Transfer clock output from multiple pins function selected Reserved Must always be "0" Must always be "0" Nothing is assigned. This bit can neither be set nor reset. When read, its content is indeterminate. Note: When using multiple pins to output the transfer clock, the following requirements must be met: * UART1 internal/external clock select bit (bit 3 at address 03A8 16) = "0". Figure 1.80: Serial I/O-related registers (5) 1.2.23.1 Clock synchronous serial I/O mode The clock synchronous serial I/O mode uses a transfer clock to transmit and receive data. Figure 1.81 shows the UARTi transmit/receive mode register. Table 1.25 lists the specifications of the clock synchronous serial I/O mode. UARTi transmit/receive mode registers b7 b6 b5 b4 b3 0 b2 b1 b0 001 Symbol UiMR(i=0,1) Bit symbol Bit name Function SMD0 SMD1 When reset 0016 Address 03A0 16, 03A816 R W b2 b1 b0 Serial I/O mode select bit 0 0 1 : Clock synchronous serial I/O mode Internal/external clock select bit 0 : Internal clock 1 : External clock SMD2 CKDIR STPS PRY Invalid in clock synchronous serial I/O mode PRYE SLEP 0 (Must always be "0" in clock synchronous serial I/O mode) UART2 transmit/receive mode register b7 b6 b5 b4 b3 0 b2 b1 b0 001 Symbol U2MR Bit symbol Address 037816 Bit name When reset 0016 Function SMD0 b2 b1 b0 SMD1 Serial I/O mode select bit 0 0 1 : Clock synchronous serial I/O mode Internal/external clock select bit 0 : Internal clock 1 : External clock SMD2 CKDIR R W STPS PRY Invalid in clock synchronous serial I/O mode PRYE IOPOL TxD, RxD I/O polarity reverse bit (Note) 0 : No reverse 1 : Reverse Note 1: Usually set to "0". Figure 1.81: UARTi transmit/receive mode register in clock synchronous serial I/O mode Rev. H Sep 18, 2003 Page 85 of 139 UART0 to UART2 M30240 Group Table 1.25: Specifications of Clock synchronous serial I/O mode Item Specification Transfer data format *Transfer data length: 8 bits Transfer clock *When internal clock is selected (bit 3 at addresses 03A016, 03A816, 037816 = "0"): fi/2(n+1) (Note 1) fi = f1, f8, f32 *When external clock is selected (bit 3 at addresses 03A016, 03A816, 037816 = "1"): Input from CLKi pin (Maximum 5 Mbps.) Transmission/reception control CTS function/RTS function/CTS, RTS function chosen to be invalid Transmission start condition *To start transmission, the following requirements must be met: Transmit enable bit (bit 0 at addresses 03A516, 03AD16, 037D16) = "1" Transmit buffer empty flag (bit 1 at addresses 03A516, 03AD16, 037D16) = "0" When CTS function selected, CTS input level = "L" *Furthermore, if external clock is selected, the following requirements must also be met: CLKi polarity select bit (bit 6 at addresses 03A416, 03AC16, 037C16) = "0": CLKi input level = "H" CLKi polarity select bit (bit 6 at addresses 03A416, 03AC16, 037C16) = "1": CLKi input level = "L" *To start reception, the following requirements must be met: Reception start condition Receive enable bit (bit 2 at addresses 03A516, 03AD16, 037D16) = "1" Transmit enable bit (bit 0 at addresses 03A516, 03AD16, 037D16) = "1" Transmit buffer empty flag (bit 1 at addresses 03A516, 03AD16, 037D16) = "0" *Furthermore, if external clock is selected, the following requirements must also be met: CLKi polarity select bit (bit 6 at addresses 03A416, 03AC16, 037C16) = "0": CLKi input level = "H" CLKi polarity select bit (bit 6 at addresses 03A416, 03AC16, 037C16) = "1": CLKi input level = "L" *When transmitting Interrupt request generation timing Error detection Transmit interrupt cause select bit (bits 0, 1 at address 03B016, bit 4 at address 037D16) = "0": Interrupts requested when data transfer from UARTi Transmit interrupt cause select bit (bits 0, 1 at address 03B016, bit 4 at address 037D16) = "1": Interrupts requested when data transmission from *When receiving Interrupt requested when the data transfer from the UARTi receive register to the UARTi receive buffer register is complete. *Overrun error (Note 2) This error occurs when the next data is ready before contents of UARTi receive buffer is read. *CLK polarity selection Select function Whether transmit data is output/input at the rising edge or falling edge of the transfer clock can be selected *LSB first/MSB first selection Whether transmission/reception begins with bit 0 or bit 7 can be selected *Continuous receive mode selection Reception is enabled simultaneously by a read from the receive buffer register *Transfer clock output from multiple pins selection (UART1) UART1 transfer clock can be chosen by software to be output from one of the two pins set *Switching serial data logic (UART2) Whether to reverse data in writing to the transmission buffer register or reading the reception buffer register can be selected. *Switching serial data logic (UART2) This function is reversing TxD port output and RxD port input. All I/O data level is reversed. Note 1: "n" denotes the value 0016 to FF16 that is set to the UART bit rate generator. Note 2: The UARTi receive buffer has the next data written when an overrun error occurs. Note: the UARTi receive interrupt request bit is set to "0". Rev. H Sep 18, 2003 Page 86 of 139 UART0 to UART2 M30240 Group Table 1.26 lists the functions of the input/output pins during clock synchronous serial I/O mode. This table shows the pin functions when the transfer clock output from multiple pins function is not selected. Note that for a period from when the UARTi operation mode is selected to when transfer starts, the TxD pin outputs a "H". The typical clock synchronous timing diagrams are shown in Figure 1.82. Table 1.26: Pin name IART mode input/output pin functions Function Method of selection TxDi (P63, P67, P70) Serial data output (Outputs dummy data when performing reception only) RxDi (P62, P66, P71) Serial data input Port P62, P66, and P71 direction register (bits 2 and 6 at address 03EE16 bit 1 at address 03EF16)= "0" (Can be used as an input port when performing transmission only.) Transfer clock output Internal/external clock select bit (bit 3 at address 03A016, 03A816, 037816) = "0" Transfer clock input Internal/external clock select bit (bit 3 at address 03A016, 03A816, 037816) = "1" Port P61, P65, and P72 direction register (bits 1 and 5 at address 03EE16, bit 2 at address 03EF16) = "0" CTS input CTS/RTS disable bit (bit 4 at address 03A416, 03AC16, 037C16) = "0" CTS/RTS function select bit (bit 2 at address 03A416, 03AC16, 037C16) = "0" Port P60, P64 and P73 direction register (bits 0 and 4 at address 03EE16, bit 3 at address 03EF16) = "0" RTS output CTS/RTS disable bit (bit 4 at address 03A416, 03AC16, 037C16) = "0" CTS/RTS function select bit (bit 2 at address 03A416, 03AC16, 037C16) = "1" Programmable I/ O port CTS/RTS disable bit (bit 4 at address 03A416, 03AC16, 037C16) = "1" CLKi (P61, P65, P72) CTSi/RTSi (P60,P64,P73) Rev. H Sep 18, 2003 Page 87 of 139 UART0 to UART2 M30240 Group Example of transit timing (when internal clock is selected) Tc Transfer clock Transmit enable bit (TE) Transmit buffer empty flag (Tl) "1" "0" Data is set in UARTi transmit buffer register "1" "0" Transferred from UARTi transmit buffer register to UARTi transmit register "H" CTSi TCLK "L" Stopped pulsing because CTS = "H" Stopped pulsing because transfer enable bit = "0" CLKi TxDi D0 D1 D2 D3 D4 D5 D6 D7 Transmit register empty flag (TXEPT) "1" Transmit interrupt request bit (IR) "1" D0 D1 D2 D3 D4 D5 D6 D7 D 0 D1 D2 D3 D4 D5 D6 D7 "0" "0" Cleared to "0" when interrupt request is accepted, or cleared by software Shown in ( ) are bit symbols. The above timing applies to the following settings: * Internal clock is selected. * CTS function is selected. * CLK polarity select bit = "0". * Transmit interrupt cause select bit = "0". Tc = TCLK = 2(n + 1) / fi fi: frequency of BRGi count source (f 1, f8, f32) n: value set to BRGi Example of receive timing (when external clock is selected) "1" Receive enable bit (RE) "0" Transmit enable bit (TE) "0" Transmit buffer empty flag (Tl) "1" "0" "H" RTSi Dummy data is set in UARTi transmit buffer register "1" Transferred from UARTi transmit buffer register to UARTi transmit register "L" 1 / fEXT CLKi Receive data is taken in D0 D1 D2 D 3 D4 D5 D6 D7 RxDi "1" Receive complete "0" flag (Rl) Receive interrupt request bit (IR) Transferred from UARTi receive register to UARTi receive buffer register D0 D1 D 2 D 3 D4 D5 Read out from UARTi receive buffer register "1" "0" Cleared to "0" when interrupt request is accepted, or cleared by software Shown in ( ) are bit symbols. The above timing applies to the following settings: * External clock is selected. * RTS function is selected. * CLK polarity select bit = "0". Meet the following conditions are met when the CLK input before data reception = "H" * Transmit enable bit "1" * Receive enable bit "1" * Dummy data write to UARTi transmit buffer register fEXT: frequency of external clock Figure 1.82: Typical transmit/receive timings in clock synchronous serial I/O mode Polarity select function Rev. H Sep 18, 2003 Page 88 of 139 UART0 to UART2 M30240 Group 1.2.23.1.1 Polarity select function As shown in Figure 1.83, the CLK polarity select bit (bit 6 at addresses 03A416, 03AC16, 037C16) allows selection of the polarity of the transfer clock. * When CLK polarity select bit = "0" CLKi TXDi D0 D1 D2 D3 D4 D5 D6 D7 RXDi D0 D1 D2 D3 D4 D5 D6 D7 Note 1: The CLK pin level when not transferring data is "H". * When CLK polarity select bit = "1" CLKi TXDi D0 D1 D2 D3 D4 D5 D6 D7 RXDi D0 D1 D2 D3 D4 D5 D6 D7 Note 2: The CLK pin level when not transferring data is "L". Figure 1.83: Polarity of transfer clock 1.2.23.1.2 LSB first/MSB first select function As shown in Figure 1.84, when the transfer format select bit (bit 7 at addresses 03A416, 03AC16, 037C16) = "0", the transfer format is "LSB first"; when the bit = "1", the transfer format is "MSB first". Note: This applies CLK polarity select bit = "0". * When transfer format select bit = "0" CLKi TXDi D0 D1 D2 D3 D4 D5 D6 D7 RXDi D0 D1 D2 D3 D4 D5 D6 D7 LSB first * When transfer format select bit = "1" CLKi TXDi D7 D6 D5 D4 D3 D2 D1 D0 RXDi D7 D6 D5 D4 D3 D2 D1 D0 MSB first Figure 1.84: Transfer format 1.2.23.1.3 Transfer clock output from multiple pins function (UART1) This function allows using two transfer clock output pins and choosing one of the two to output a clock by using the CLK and CLKS select bit (bits 4 and 5 at address 03B016). See Figure 1.85. The multiple pins function is valid only when the internal clock is selected for UART1. Note that when this function is selected, the UART1 CTS/RTS function cannot be used. Microcomputer TXD 1 (P6 7) CLKS 1 (P6 4) CLK1 (P6 5) IN IN CLK CLK Note: This applies when the internal clock is selected and transmission is performed only in clock synchronous serial I/O mode. Figure 1.85: The transfer clock output from the multiple pins function usage Rev. H Sep 18, 2003 Page 89 of 139 UART0 to UART2 M30240 Group 1.2.23.1.4 Continuous receive mode If the continuous receive mode enable bit (bits 2 and 3 at address 03B016, bit 5 at address 037D16) is set to "1", the unit is placed in continuous receive mode. In this mode, when the receive buffer register is read out, the unit simultaneously goes to a receive enable state without having to set dummy data to the transmit buffer register back again. 1.2.23.1.5 Serial data logic switch function (UART2) When the data logic select bit (bit6 at address 037D16) = "1", and writing to transmit buffer register or reading from receive buffer register, data is reversed. Figure 1.86 shows the example of serial data logic switch timing. *When LSB first Transfer clock "H" "L" TxD2 "H" (no reverse) "L" TxD2 "H" (reverse) "L" D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 Figure 1.86: Serial data logic switch timing Rev. H Sep 18, 2003 Page 90 of 139 UART0 to UART2 M30240 Group 1.2.23.2 Clock asynchronous serial I/O (UART) mode The UART mode allows transmitting and receiving data after setting the desired transfer rate and transfer data format. Table 1.27 lists the specifications of the UART mode. Table 1.27: Specifications of UART mode Item Specification Transfer data format * Character bit (transfer data): 7 bits, 8 bits, or 9 bits as selected * Start bit: 1 bit * Parity bit: Odd, even, or nothing as selected * Stop bit: 1 bit or 2 bits as selected Transfer clock * When internal clock is selected (bit 3 at addresses 03A016, 03A816, 037816 = "0"): fi/16(n+1) (Note 1) fi = f1, f8, f32 * When external clock is selected (bit 3 at addresses 03A016, 03A816="1"): fEXT/16(n+1)(Note 1) (Note 2) Transmission/reception control * CTS function/RTS function/ CTS, RTS function disabled Transmission start condition * To start transmission, the following requirements must be met: Transmit enable bit (bit 0 at addresses 03A516, 03AD16, 037D16) = "1" Transmit buffer empty flag (bit 1 at addresses 03A516, 03AD16, 037D16) = "0" When CTS function selected, CTS input level = "L" Reception start condition * To start reception, the following requirements must be met: Receive enable bit (bit 2 at addresses 03A516, 03AD16, 037D16) = "1" Start bit detection Interrupt request generation timing * When transmitting Transmit interrupt cause select bits (bits 0,1 at address 03B016, bit4 at address 037D16) = "0": Interrupts requested when data transfer from UARTi transfer buffer register to UARTi transmit register is completed Transmit interrupt cause select bits (bits 0, 1 at address 03B016, bit4 at address 037D16) = "1": Interrupts requested when data transmission from UARTi transfer register is completed * When receiving Interrupts requested when data transfer from UARTi receive register to UARTi receive buffer register is completed Error detection * Overrun error (Note 3) This error occurs when the next data is ready before contents of UARTi receive buffer register are read out * Framing error This error occurs when the number of stop bits set is not detected * Parity error This error occurs when if parity is enabled, the number of 1's in parity and character bits does not match the number of 1's set * Error sum flag This flag is set (= 1) when any of the overrun, framing, and parity errors is encountered Select function * Sleep mode selection (UART0, UART1) This mode is used to transfer data to and from one of multiple slave micro-computers *Serial data logic switch (UART2) This function is reversing logic value of transferring data. Start bit, parity bit and stop bit are not reversed. *TxD, RxD I/O polarity switch (UART2) This function is reversing TxD port output and RxD port input. All I/O data level is reversed. Note 1: `n' denotes the value 0016 to FF16 that is set to the UARTi bit rate generator. Note 2: fEXT is input from the CLKi pin. External clock cannot be selected in UART2. Note 3: If an overrun error occurs, the UARTi receive buffer will have the next data written in. Note also that the UARTi receive interrupt request bit is not set to "1" Rev. H Sep 18, 2003 Page 91 of 139 UART0 to UART2 M30240 Group UARTi transmit / receive mode registers b7 b6 b5 b4 b3 b2 b1 b0 Symbol UiMR(i=0,1) Bit symbol SMD0 Address 03A0 16, 03A8 16 Bit name Serial I/O mode select bit SMD1 SMD2 CKDIR When reset 0016 Function Internal / external clock select bit Stop bit length select bit 0 1 0 1 PRY Odd / even parity select bit Valid when bit 6 = "1" 0 : Odd parity 1 : Even parity PRYE Parity enable bit 0 : Parity disabled 1 : Parity enabled SLEP Sleep select bit 0 : Sleep mode deselected 1 : Sleep mode selected STPS R W b2 b1 b0 1 0 0 : Transfer data 7 bits long 1 0 1 : Transfer data 8 bits long 1 1 0 : Transfer data 9 bits long : : : : Internal clock External clock (Note) One stop bit Two stop bits Note: Set the corresponding port direction register to "0". UART2 transmit / receive mode register b7 b6 b5 b4 b3 b2 b1 b0 Symbol U2MR Address 037816 Bit symbol SMD0 Bit name Serial I/O mode select bit SMD1 SMD2 CKDIR When reset 0016 Function 1 0 0 : Transfer data 7 bits long 1 0 1 : Transfer data 8 bits long 1 1 0 : Transfer data 9 bits long Internal / external clock select bit Stop bit length select bit Must always be fixed to "0" PRY Odd / even parity select bit Valid when bit 6 = "1" 0 : Odd parity 1 : Even parity PRYE Parity enable bit 0 : Parity disabled 1 : Parity enabled IOPOL TxD, RxD I/O polarity reverse bit (Note) 0 : No reverse 1 : Reverse STPS R W b2 b1 b0 0 : One stop bit 1 : Two stop bits Note: Usually set to "0". Figure 1.87: UARTi transmit/receive mode register. Table 1.28 lists the functions of the input/output pins during UART mode. Note that for a period from when the UARTi operation mode is selected to when transfer starts, the TxDi pin outputs a "H". Table 1.28: Pin name Input/output pin functions in UART mode Function Method of selection TxDi (P63, P67, P70) Serial data output Outputs dummy data when performing reception. RxDi (P62, P66, P71) Serial data input Port P62, P66, and P71 direction register (bits 2 and 6 at address 03EE16 bit 1 at address 03EF16)= "0" (Can be used as an input port when performing transmission only.) Programmable I/ O port Internal/external clock select bit (bit 3 at address 03A016, 03A816, 037816) = "0" Transfer clock input Internal/external clock select bit (bit 3 at address 03A016, 03A816) = "1" Port P61, P65 direction register (bits 1 and 5 at address 03EE16) = "0" CTS input CTS/RTS disable bit (bit 4 at address 03A416, 03AC16, 037C16) = "0" CTS/RTS function select bit (bit 2 at address 03A416, 03AC16, 037C16) = "0" Port P60, P64 and P73 direction register (bits 0 and 4 at address 03EE16, bit 3 at address 03EF16) = "0" RTS output CTS/RTS disable bit (bit 4 at address 03A416, 03AC16, 037C16) = "0" CTS/RTS function select bit (bit 2 at address 03A416, 03AC16, 037C16) = "1" Programmable I/ O port CTS/RTS disable bit (bit 4 at address 03A416, 03AC16, 037C16) = "1" CLKi (P61, P65, P72) CTSi/RTSi (P60,P64,P73) Rev. H Sep 18, 2003 Page 92 of 139 UART0 to UART2 M30240 Group Figure 1.88 and Figure 1.89 show the typical UART mode transmit and receive timing diagrams. Example of receive timing when tranfer data is 8 bits long (parity disabled, one-stop bit) BRGi count source ....... "1" Receive enable bit "0" Start bit RxDi ....... Stop bit D1.......D7 D0 Sampled "L" Receive data taken in Transfer clock Receive complete flag RTSi Receive interrupt request bit "1" Reception triggered when transfer clock is generated by falling edge of start bit Transferred from UARTi receive register to UARTi receive buffer register "0" "H" "L" "1" "0" Cleared to "0" when interrupt request is accepted, or cleared by software The above timing applies to the following settings : *Parity is disabled. *One stop bit. *RTS function is selected. Figure 1.88: Typical receive timing in UART mode Rev. H Sep 18, 2003 Page 93 of 139 UART0 to UART2 M30240 Group Example of transmit timing when transfer data are 8 bits long (parity enabled, one stop bit) The transfer clock stops momentarily as CTS is "H" when the stop bit is checked. The transfer clock starts as the transfer starts immediately CTS changes to "L". Tc Transfer clock Transmit enable bit(TE) "1" Transmit buffer empty flag(TI) "1" "0" Data is set in UARTi transmit buffer register. "0" Transferred from UARTi transmit buffer register to UARTi transmit register "H" CTSi "L" Start bit TxDi Parity bit Stopped pulsing because transmit enable bit = "0" Stop bit ST D0 D1 D2 D3 D4 D5 D6 D7 P SP ST D0 D1 ST D0 D1 D2 D3 D4 D5 D6 D7 P SP "1" Transmit register empty flag (TXEPT) "0" Transmit interrupt request bit (IR) "1" "0" Cleared to "0" when interrupt request is accepted, or cleared by software Shown in ( ) are bit symbols. The above timing applies to the following settings : * Parity is enabled. * One stop bit. * CTS function is selected. * Transmit interrupt cause select bit = "1". Tc = 16 (n + 1) / fi or 16 (n + 1) / f EXT fi : frequency of BRGi count source (f 1, f8, f32) fEXT : frequency of BRGi count source (external clock) n : value set to BRGi Example of transmit timing when transfer data are 9 bits long (parity enabled, two stop bits) Tc Transfer clock Transmit enable bit(TE) "1" Transmit buffer empty flag(TI) "1" "0" Data is set in UARTi transmit buffer register "0" Transferred from UARTi transmit buffer register to UARTi transmit register Start bit TxDi Stop bit ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP SP Stop bit ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SPSP ST D0 D1 "1" Transmit register empty flag (TXEPT) "0" Transmit interrupt request bit (IR) "1" "0" Cleared to "0" when interrupt request is accepted, or cleared by software Shown in ( ) are bit symbols. The above timing applies to the following settings : * Parity is disabled. * Two stop bits. * CTS function is disabled. * Transmit interrupt cause select bit = "0". Tc = 16 (n + 1) / fi or 16 (n + 1) / f EXT fi : frequency of BRGi count source (f 1, f8, f32) fEXT : frequency of BRGi count source (external clock) n : value set to BRGi Figure 1.89: Typical transmit timings in UART mode Rev. H Sep 18, 2003 Page 94 of 139 UART0 to UART2 M30240 Group 1.2.23.2.1 Sleep mode (UART0, UART1) This mode is used to transfer data between specific microcomputers among multiple microcomputers connected using UARTi. The sleep mode is selected when the sleep select bit (bit 7 at addresses 03A016, 03A816) is set to "1" during reception. In this mode, the unit performs receive operation when the MSB of the received data = "1" and does not perform receive operation when the MSB = "0". 1.2.23.2.2 Function for switching serial data logic (UART2) When the data logic select bit (bit 6 of address 037D16) is assigned 1, data is inverted in writing to the transmission buffer register or reading the reception buffer register. Figure 1.90 shows the example of timing for switching serial data logic. Example of timing for switching serial data logic when LSB is first (parity enabled, one-stop bit) Transfer clock "H" "L" TxD2 "H" (no reverse) "L" TxD2 "H" (reverse) "L" ST D0 D1 D2 D3 D4 D5 D6 D7 P SP ST D0 D1 D2 D3 D4 D5 D6 D7 P SP ST : Start bit P : Even parity SP : Stop bit Figure 1.90: Timing for switching serial data logic 1.2.23.2.3 TxD, RxD I/O polarity reverse function (UART2) This function is to reverse TxD pin output and RxD pin input. The level of any data to be input or output (including the start bit, stop bit(s), and parity bit) is reversed. Set this function to "0" (not to reverse) for usual use. 1.2.23.2.4 Bus collision detection function (UART2) This function is to sample the output level of the TxD pin and the input level of the RxD pin at the rising edge of the transfer clock; if their values are different, then an interrupt request occurs. Figure 1.91 shows the example of detection timing of a buss collision (in UART mode). Transfer clock "H" "L" TxD2 "H" ST SP ST SP "L" RxD2 "H" "L" Bus collision detection interrupt request signal "1" Bus collision detection interrupt request bit "1" "0" "0" ST : Start bit SP : Stop bit Figure 1.91: Detection timing of a bus collision (in UART mode) Rev. H Sep 18, 2003 Page 95 of 139 UART0 to UART2 M30240 Group 1.2.23.3 Clock-asynchronous serial I/O mode (compliant with the SIM interface) The SIM interface is used for connecting the microcomputer with a memory card I/C or the like; adding some extra settings in UART2 clock-asynchronous serial I/O mode allows the user to effect this function. Table 1.29 shows the specifications of clock-asynchronous serial I/O mode (compliant with the SIM interface). Figure 1.92 shows the typical transmit/receive timing in UART mode. Table 1.29: Specifications of clock-asynchronous serial I/O mode (compliant with the SIM interface) Item Specification * Transfer data 8-bit UART mode (bit 2 through bit 0 of address 037816 = "1012") * One stop bit (bit 4 of address 037816 = "0") * With the direct format chosen Set parity to "even" (bit 5 and bit 6 of address 037816 = "1" and "1" respectively) Transfer data format Set data logic to "direct" (bit 6 of address 037D16 = "0"). Set transfer format to LSB (bit 7 of address 037C16 = "0"). * With the inverse format chosen Set parity to "odd" (bit 5 and bit 6 of address 037816 = "0" and "1" respectively) Set data logic to "inverse" (bit 6 of address 037D16 = "1") Set transfer format to MSB (bit 7 of address 037C16 = "1") Transfer clock * With the internal clock chosen (bit 3 of address 037816 = "0"): fi / 16 (n + 1) (Note 1): fi=f1, f8, f32 Transmission / reception control * Disable the CTS and RTS function (bit 4 of address 037C16 = "1") Other settings * The sleep mode select function is not available for UART2 * Set transmission interrupt factor to "transmission completed" (bit 4 of address 037D16 = "1") Transmission start condition Reception start condition Interrupt request generation timing Error detection * To start transmission, the following requirements must be met: Transmit enable bit (bit 0 of address 037D16) = "1" Transmit buffer empty flag (bit 1 of address 037D16) = "0" * To start reception, the following requirements must be met: Reception enable bit (bit 2 of address 037D16) = "1" Detection of a start bit * When transmitting When data transmission from the UART2 transfer register is completed (bit 4 of address 037D16 = "1") * When receiving When data transfer from the UART2 receive register to the UART2 receive buffer register is completed * Overrun error (see the specifications of clock-asynchronous serial I/O) (Note 3) * Framing error (see the specifications of clock-asynchronous serial I/O) * Parity error (see the specifications of clock-asynchronous serial I/O) On the reception side, an "L" level is output from the TxD2 pin by use of the parity error signal output function (bit 7 of address 037D16 = "1") when a parity error is detected On the transmission side, a parity error is detected by the level of input to the RxD2 pin when a transmission interrupt occurs * The error sum flag (see the specifications of clock-asynchronous serial I/O) Note 1: `n' denotes the value 0016 to FF16 that is set to the UARTi bit rate generator. Note 2: If an overrun error occurs, the UART2 receive buffer will have the next data written in. Also, the UARTi receive interrupt request bit is not set to "1". Rev. H Sep 18, 2003 Page 96 of 139 UART0 to UART2 M30240 Group Tc Transfer clock Transmit enable bit(TE) "1" Transmit buffer empty flag(TI) "1" "0" Note 1 Data is set in UART2 transmit buffer register "0" Transferred from UART2 transmit buffer register to UART2 transmit register Start bit TxD2 Parity bit ST D0 D1 D2 D3 D4 D5 D6 D7 P Stop bit ST D0 D1 D2 D3 D4 D5 D6 D7 SP P SP P SP RxD2 A "L" level returns from TxD 2 due to the occurrence of a parity error. Signal conductor level (Note 2) ST D0 D1 D2 D3 D4 D5 D6 D7 P SP ST D0 D1 D2 D3 D4 D5 D6 D7 The level is detected by the interrupt routine. The level is detected by the interrupt routine. "1" Transmit register empty flag (TXEPT) "0" Transmit interrupt request bit (IR) "1" "0" Cleared to "0" when interrupt request is accepted, or cleared by software Shown in ( ) are bit symbols. The above timing applies to the following settings : * Parity is enabled. * One stop bit. * Transmit interrupt cause select bit = "1". Tc = 16 (n + 1) / fi fi : frequency of BRG2 count source (f 1, f8, f32) n : value set to BRG2 Note 1: The transmit is started with overflow timing of BRG after having written in a value at the transmit buffer in the above timing. Note 2: Equal in waveform because TxD2 and RxD2 are connected. Tc Transfer clock Receive enable bit (RE) "1" "0" Start bit RxD2 Parity bit ST D0 D1 D2 D3 D4 D5 D6 D7 P Stop bit SP ST D0 D1 D2 D3 D4 D5 D6 D7 P SP TxD2 A "L" level returns from TxD 2 due to the occurrence of a parity error. Signal conductor level (Note 2) Receive complete flag (RI) "1" Receive interrupt request bit (IR) "1" ST D0 D1 D2 D3 D4 D5 D6 D7 P SP ST D0 D1 D2 D3 D4 D5 D6 D7 P SP "0" Read to receive buffer Read to receive buffer "0" Cleared to "0" when interrupt request is accepted, or cleared by software Shown in ( ) are bit symbols. The above timing applies to the following settings : * Parity is enabled. * One stop bit. * Transmit interrupt cause select bit = "0". Tc = 16 (n + 1) / fi fi : frequency of BRG2 count source (f 1, f8, f32) n : value set to BRG2 Note 2: Equal in waveform because TxD2 and RxD2 are connected. Figure 1.92: Typical transmit/receive timing in UART mode (compliant with the SIM interface) Rev. H Sep 18, 2003 Page 97 of 139 UART0 to UART2 M30240 Group 1.2.23.3.1 Function for outputting a parity error signal With the error signal output enable bit (bit 7 of address 037D16) assigned "1", you can output an "L" level from the TxD2 pin when a parity error is detected. In step with this function, the generation timing of a transmission completion interrupt changes to the detection timing of a parity error signal. Figure 1.93 shows the output timing of the parity error signal. * LSB first Transfer clock RxD 2 TxD2 Receive complete flag "H" "L" "H" ST D0 D1 D2 D3 D4 D5 D6 D7 P SP "L" "H" Hi-Z "L" "1" "0" ST : Start bit P : Even Parity SP: Stop bit Figure 1.93: Output timing of the parity error signal 1.2.23.3.2 Direct format/inverse format Connecting the SIM card allows you to switch between direct format and inverse format. If you choose the direct format, D0 data is output from TxD2. If you choose the inverse format, D7 data is inverted and output from TxD2. Figure 1.94 shows the SIM interface format. Transfer clock TxD2 (direct) D0 D1 D2 D3 D4 D5 D6 D7 P TxD2 (inverse) D7 D6 D5 D4 D3 D2 D1 D0 P P : Even parity Figure 1.94: SIM interface format Figure 1.95 shows the example of connecting the SIM interface with TxD2 and RxD2. Microcomputer TxD2 RxD2 Figure 1.95: Connecting the SIM interface Rev. H Sep 18, 2003 Page 98 of 139 SIM card A-D Converter M30240 Group 1.2.24 A-D Converter The A-D converter consists of one 10-bit successive approximation A-D converter circuit with a capacitive coupling amplifier. Pins P100 to P107 function as the analog signal input pins. The direction registers of these pins for A-D conversion must therefore be set to input. The Vref connect bit (bit 5 at address 03D716) can be used to isolate the resistance ladder of the A-D converter from the reference voltage input pin (VREF) when the A-D converter is not used. Doing so stops any current flowing into the resistance ladder from VREF, reducing the power dissipation. When using the A-D converter, start A-D conversion only after setting bit 5 of 03D716 to connect VREF. The result of A-D conversion is stored in the A-D registers of the selected pins. When set to 10-bit precision, the low 8 bits are stored in the even addresses and the high 2 bits in the odd addresses. When set to 8-bit precision, the low 8 bits are stored in the even addresses. Table 1.30 shows the performance of the A-D converter. Figure 1.96 shows the block diagram of the AD converter, and Figure 1.97 and Figure 1.98 show the A-D converter-related registers. Table 1.30: Performance of A-D Convertera Item Performance Method of A-D conversion Successive approximation (capacitive coupling amplifier) Analog input voltage (Note) 0V to AVCC (VCC) Operating clock fAD VCC = 5V Resolution 8-bit or 10-bit (selectable) fAD/divide-by-2 or fAD/divide-by-4 or fAD, fAD,f(XIN) * Without sample and hold function 3LSB * With sample and hold function (8-bit resolution) 2LSB * With sample and hold function (10-bit resolution) 3LSB Absolute precision VCC = 5V Operating modes One-shot mode, repeat mode, single sweep mode, repeat sweep mode 0, and repeat sweep mode 1 Analog input pins 8pins (AN0 to AN7) A-D conversion start condition *Software trigger A-D conversion starts when the A-D conversion start flag changes to "1" *External trigger (can be re-triggered) A-D conversion starts when the A-D conversion start flag is "1" and the ADTRG/P87 input changes from "H" to "L" Conversion speed per pin *Without sample and hold function 8-bit resolution: 49 AD cycles, 10-bit resolution: 59 AD cycles * With sample and hold function 8-bit resolution: 28 AD cycles, 10-bit resolution: 33 AD cycles a. Note: Does not depend on use of sample and hold function Rev. H Sep 18, 2003 Page 99 of 139 A-D Converter M30240 Group CKS1=1 AD CKS0=1 fAD 1/2 1/2 CKS0=0 CKS1=0 A-D conversion rate selection VREF VCUT=0 Resistor ladder AV SS VCUT=1 Successive conversion register A-D control register 1 (address 03D7 16) A-D control register 0 (address 03D6 16) Addresses (03C1 16, 03C0 16) A-D register 0(16) (03C3 16, 03C2 16) A-D register 1(16) (03C5 16, 03C4 16) A-D register 2(16) A-D register 3(16) (03C7 16, 03C6 16) (03C9 16, 03C8 16) A-D register 4(16) (03CB16, 03CA 16) A-D register 5(16) (03CD16, 03CC 16) A-D register 6(16) (03CF16, 03CE 16) A-D register 7(16) Data bus high-order Data bus low-order AN0 CH2,CH1,CH0=000 AN1 CH2,CH1,CH0=001 AN2 CH2,CH1,CH0=010 AN3 CH2,CH1,CH0=011 AN4 CH2,CH1,CH0=100 AN5 CH2,CH1,CH0=101 AN6 CH2,CH1,CH0=110 AN7 CH2,CH1,CH0=111 Figure 1.96: Block diagram of A-D converter Rev. H Sep 18, 2003 Page 100 of 139 Vref Decoder V IN Comparator A-D Converter M30240 Group A-D control register 0 (Note 1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol ADCON0 Bit symbol Address 03D616 When reset 00000XXX 2 Bit name R W Function b2 b1 b0 CH0 Analog input pin select bit CH1 CH2 MD0 A-D operation mode select bit 0 MD1 0 0 0 : AN 0 0 0 1 : AN 1 0 1 0 : AN 2 0 1 1 : AN 3 1 0 0 : AN 4 1 0 1 : AN 5 1 1 0 : AN 6 1 1 1 : AN 7 is selected is selected is selected is selected is selected is selected is selected is selected 0 0 : One-shot mode 0 1 : Repeat mode 1 0 : Single sweep mode 1 1 : Repeat sweep mode 0 Repeat sweep mode 1 Trigger select bit 0 : Software trigger 1 : AD TRG trigger ADST A-D conversion start flag 0 : A-D conversion disabled 1 : A-D conversion started CKS0 Frequency select bit 0 0 : f AD/4 is selected 1 : f AD/2 is selected TRG (Note 2) b4 b3 (Note 2) Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. Note 2: When changing A-D operation mode, set analog input pin again. A-D control register 1 (Note) b7 b6 0 0 b5 b4 b3 b2 b1 b0 Symbol ADCON1 Bit symbol Address 03D716 When reset 00 16 Bit name A-D sweep pin select bit SCAN0 Function R W When single sweep and repeat sweep mode 0 are selected b1 b0 0 0 : AN 0, AN1 (2 pins) 0 1 : AN 0 to AN 3 (4 pins) 1 0 : AN 0 to AN 5 (6 pins) 1 1 : AN 0 to AN 7 (8 pins) When repeat sweep mode 1 is selected SCAN1 b1 b0 0 0 : AN 0 (1 pin) 0 1 : AN 0, AN1 (2 pins) 1 0 : AN 0 to AN 2 (3 pins) 1 1 : AN 0 to AN 3 (4 pins) MD2 BITS CKS1 VCUT A-D operation mode select bit 1 0 : Any mode other than repeat sweep mode 1 1 : Repeat sweep mode 1 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode Frequency select bit 1 0 : f AD/2 or f AD/4 is selected 1 : f AD is selected Vref connect bit 0 : Vref not connected 1 : Vref connected Reserved bit Always set to "0" Note: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. Figure 1.97: A-D converter-related registers (1) Rev. H Sep 18, 2003 Page 101 of 139 A-D Converter M30240 Group A-D control register 2 (Note) b7 b6 b5 b4 b3 b2 b1 b0 0 0 0 Symbol Address ADCON2 03D4 16 Bit symbol SMP When reset 0000XXX0 2 Bit name Function A-D conversion method select bit RW 0 : Without sample and hold 1 : With sample and hold Always set to "0" Reserved bit Nothing is assigned. Write "0" when writing to these bits. When read, the value is "0". SSH Simultaneous sample and hold 0 : Disabled 1 : Enabled Note : If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. (b15) b7 Address 03C0 16 to 03CF 16 Symbol A-D register i ADi(i=0 to 7) (b8) b0 b7 When reset Indeterminate b0 Function Eight low-order bits of A-D conversion result * During 10-bit mode Two high-order bits of A-D conversion result * During 8-bit mode When read, the content is indeterminate Nothing is assigned. Write "0" when writing to these bits. When read, the value is "0". Figure 1.98: A-D converter-related registers (2) Rev. H Sep 18, 2003 Page 102 of 139 R W A-D Converter M30240 Group 1.2.24.1 One-shot mode In one-shot mode, the pin selected using the analog input pin select bit is used for one-shot A-D conversion.Table 1.31 shows the specifications of one-shot mode. Figure 1.99 shows the A-D control register in one-shot mode. Table 1.31: One-shot mode specification Item Specification Function The pin selected by the analog input pin select bit is used for one A-D conversion Start condition Writing "1" to A-D conversion start flag Stop condition *End of A-D conversion (A-D conversion start flag changes to "0", except when external trigger is selected) *Writing "0" to A-D conversion start flag Interrupt request generation timing End of A-D conversion Input pin One of AN0 to AN7, as selected Reading of result of A-D converter Read A-D register corresponding to selected pin A-D control register 0 (Note 1) b7 b6 b5 b4 b3 b2 b1 Symbol ADCON0 b0 0 0 Address 03D616 Bit symbol When reset 00000XXX 2 Bit name Function R W b2 b1 b0 CH0 CH1 Analog input pin select bit CH2 MD0 MD1 TRG A-D operation mode select bit 0 Trigger select bit ADST A-D conversion start flag CKS0 Frequency select bit 0 0 0 0 : AN 0 is selected 0 0 1 : AN 1 is selected 0 1 0 : AN 2 is selected 0 1 1 : AN 3 is selected 1 0 0 : AN 4 is selected 1 0 1 : AN 5 is selected 1 1 0 : AN 6 is selected 1 1 1 : AN 7 is selected (Note 2) b4 b3 0 0 : One-shot mode (Note 2) 0 : Software trigger 1 : AD TRG trigger 0 : A-D conversion disabled 1 : A-D conversion started 0: f AD/4 is selected 1: f AD/2 is selected Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. Note 2: When changing A-D operation mode, set analog input pin again. A-D control register 1 (Note) b7 b6 b5 0 0 1 b4 b3 b2 b1 Symbol ADCON1 b0 0 Address 03D716 Bit symbol SCAN0 SCAN1 When reset 0016 Bit name A-D sweep pin select bit Function MD2 A-D operation mode select bit 1 0 : Any mode other than repeat sweep mode 1 BITS 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode CKS1 Frequency select bit1 0 : f AD/2 or f AD/4 is selected 1 : f AD is selected VCUT Vref connect bit 1 : Vref connected Reserved bit RW Invalid in one-shot mode Always set to "0" Note: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. Figure 1.99: A-D conversion register in one-shot mode Rev. H Sep 18, 2003 Page 103 of 139 A-D Converter M30240 Group 1.2.24.2 Repeat mode In repeat mode, the pin selected using the analog input pin select bit is used for repeated A-D conversion.Table 1.32 shows the specifications of repeat mode. Figure 1.100 shows the A-D control register in repeat mode. Table 1.32: Repeat mode specification Item Specification Function The pin selected by the analog input pin select bit is used for repeated A-D Star condition Writing "1" to A-D conversion start flag Stop condition Writing "0" to A-D conversion start flag Interrupt request generation timing None generated Input pin One of AN0 to AN7, as selected Reading of result of A-D converter Read A-D register corresponding to selected pin A-D control register 0 (Note 1) b7 b6 b5 b4 b3 b2 b1 b0 0 1 Symbol ADCON0 Address 03D6 16 Bit symbol When reset 00000XXX 2 Bit name Function RW b2 b1 b0 CH0 Analog input pin select bit CH1 CH2 MD0 0 0 0 : AN 0 is selected 0 0 1 : AN 1 is selected 0 1 0 : AN 2 is selected 0 1 1 : AN 3 is selected 1 0 0 : AN 4 is selected 1 0 1 : AN 5 is selected 1 1 0 : AN 6 is selected 1 1 1 : AN 7 is selected 0 1 : Repeat mode TRG Trigger select bit 0 : Software trigger 1 : AD TRG trigger ADST A-D conversion start flag 0 : A-D conversion disabled 1 : A-D conversion started CKS0 Frequency select bit 0 0 : f AD/4 is selected 1 : f AD/2 is selected MD1 (Note 2) b4 b3 A-D operation mode select bit 0 (Note 2) Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. Note 2: When changing A-D operation mode, set analog input pin again. A-D control register 1 (Note) b7 b6 b5 001 b4 b3 b2 0 b1 b0 Symbol ADCON1 Address 03D7 16 Bit symbol SCAN0 When reset 0016 Bit name Function A-D sweep pin select bit Invalid in repeat mode MD2 A-D operation mode select bit 1 0 : Any mode other than repeat sweep mode 1 BITS 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode CKS1 Frequency select bit 1 0 : f AD/2 or f AD/4 is selected 1 : f AD is selected VCUT Vref connect bit 1 : Vref connected SCAN1 Reserved bit Always set to "0" Note: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. Figure 1.100: A-D conversion register in repeat mode Rev. H Sep 18, 2003 Page 104 of 139 RW A-D Converter M30240 Group 1.2.24.3 Single-sweep mode In single-sweep mode, the pins selected using the A-D sweep pin select bit are used for one-by-one A-D conversion. Table 1.33 shows the specifications of single-sweep mode. Figure 1.101 shows the A-D control register in single-sweep mode. Table 1.33: Single-sweep mode specification Item Specification Function The pins selected by the A-D sweep pin select bit are used for one-by-one A-D conversion Start condition Writing "1" to A-D converter start flag Stop condition *End of A-D conversion (A-D conversion start flag changes to "0", except when external trigger is selected) *Writing "0" to A-D conversion start flag Interrupt request generation timing End of A-D conversion Input pin AN0 and AN1 (2 pins), AN0 to AN3 (4 pins), AN0 to AN5 (6 pins), or AN0 to AN7 (8 pins) Reading of result of A-D converter Read A-D register corresponding to selected pin A-D control register 0 (Note) b7 b6 b5 b4 b3 b2 b1 b0 1 0 Symbol ADCON0 Address 03D616 Bit symbol When reset 00000XXX 2 Bit name Function RW CH0 Analog input pin select bit CH1 Invalid in single sweep mode CH2 b4 b3 MD0 A-D operation mode select bit 0 MD1 1 0 : Single sweep mode TRG Trigger select bit 0 : Software trigger 1 : AD TRG trigger ADST A-D conversion start flag 0 : A-D conversion disabled 1 : A-D conversion started CKS0 Frequency select bit 0 0 : f AD/4 is selected 1 : f AD/2 is selected Note: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. A-D control register 1 (Note) b7 b6 b5 0 0 1 b4 b3 b2 0 b1 b0 Symbol ADCON1 Address 03D716 Bit symbol When reset 0016 Bit name Function R W When single sweep and repeat sweep mode 0 are selected SCAN0 b1 b0 A-D sweep pin select bit SCAN1 0 0 1 1 0 1 0 1 : AN 0, AN 1 (2 pins) : AN 0 to AN 3 (4 pins) : AN 0 to AN 5 (6 pins) : AN 0 to AN 7 (8 pins) MD2 A-D operation mode select bit 1 BITS 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode CKS1 Frequency select bit 1 0 : f AD/2 or f AD/4 is selected 1 : f AD is selected VCUT Vref connect bit Reserved bit 0 : Any mode other than repeat sweep mode 1 1 : Vref connected Always set to "0" Note : If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. Figure 1.101: A-D conversion register in single-sweep mode Rev. H Sep 18, 2003 Page 105 of 139 A-D Converter M30240 Group 1.2.24.4 Repeat-sweep mode 0 In repeat-sweep mode 0, the pins selected using the A-D sweep pin select bit are used for repeat sweep A-D conversion. Table 1.34 shows the specifications of repeat-sweep mode 0. Figure 1.102 shows the A-D control register in repeat-sweep mode 0. Table 1.34: Repeat-sweep mode 0 specifications Item Specification Function The pins selected by the A-D sweep pin select bit are used for repeat sweep A-D conversion Start condition Writing "1" to A-D conversion start flag Stop condition Writing "0" to A-D conversion start flag Interrupt request generation timing None generated Input pin AN0 and AN1 (2 pins), AN0 to AN3 (4 pins), AN0 to AN5 (6 pins), or AN0 to AN7 (8 pins) Read A-D register corresponding to selected pin (at any time) Reading of result of A-D converter A-D control register 0 (Note) b7 b6 b5 b4 b3 b2 b1 b0 1 1 Symbol ADCON0 Address 03D6 16 Bit symbol When reset 00000XXX 2 Bit name Function RW CH0 Analog input pin select bit CH1 Invalid in repeat sweep mode 0 CH2 MD0 A-D operation mode select bit 0 b4 b3 1 1 : Repeat sweep mode 0 MD1 TRG Trigger select bit 0 : Software trigger 1 : AD TRG trigger ADST A-D conversion start flag 0 : A-D conversion disabled 1 : A-D conversion started CKS0 Frequency select bit 0 0 : f AD/4 is selected 1 : f AD/2 is selected Note: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. A-D control register 1 (Note) b7 b6 b5 0 0 1 b4 b3 b2 0 b1 b0 Symbol ADCON1 Address 03D7 16 Bit symbol When reset 0016 Bit name Function R W When single sweep and repeat sweep mode 0 are selected SCAN0 b1 b0 A-D sweep pin select bit SCAN1 0 0 1 1 0 1 0 1 : AN 0, AN 1 (2 pins) : AN 0 to AN 3 (4 pins) : AN 0 to AN 5 (6 pins) : AN 0 to AN 7 (8 pins) MD2 A-D operation mode select bit 1 0 : Any mode other than repeat sweep mode 1 BITS 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode CKS1 Frequency select bit 1 0 : f AD/2 or f AD/4 is selected 1 : f AD is selected VCUT Vref connect bit Reserved bit 1 : Vref connected Always set to "0" Note: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. Figure 1.102: A-D conversion register in repeat-sweep mode 0 Rev. H Sep 18, 2003 Page 106 of 139 A-D Converter M30240 Group 1.2.24.5 Repeat-sweep mode 1 In repeat-sweep mode 1, all pins are used for A-D conversion with emphasis on the pin or pins selected using the A-D sweep pin select bit. Table 1.35 shows the specifications of repeat-sweep mode 1. Figure 1.103 show the A-D control in repeat-sweep mode 1. Table 1.35: Repeat-sweep mode 1 specification Item Specification Function All pins perform repeat sweep A-D conversion, with emphasis on the pin or pins selected by the A-D sweep pin select bit Example: AN0 selected AN0 -> AN1 -> AN0 -> AN2 -> AN0 -> AN3, etc. Start condition Writing "1" to A-D conversion start flag Stop condition Writing "0" to A-D conversion start flag Interrupt request generation timing None generated Input pin AN0 (1 pin), AN0 and AN1 (2 pins), AN0 to AN2 (3 pins), AN0 to AN3 (4 pins) Reading of result of A-D converter Read A-D register corresponding to selected pin (at any time) A-D control register 0 (Note) b7 b6 b5 b4 b3 b2 b1 b0 1 1 Symbol ADCON0 Address 03D616 Bit symbol When reset 00000XXX 2 Bit name Function RW CH0 Analog input pin select bit CH1 Invalid in repeat sweep mode 1 CH2 b4 b3 A-D operation mode select bit 0 1 1 : Repeat sweep mode 1 TRG Trigger select bit 0 : Software trigger 1 : AD TRG trigger ADST A-D conversion start flag 0 : A-D conversion disabled 1 : A-D conversion started Frequency select bit 0 0 : f AD/4 is selected 1 : f AD/2 is selected MD0 MD1 CKS0 Note: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. A-D control register 1 (Note) b7 b6 b5 0 0 1 b4 b3 b2 1 b1 b0 Symbol ADCON1 Address 03D7 16 Bit symbol When reset 00 16 Bit name Function R W When repeat sweep mode 1 is selected SCAN0 b1 b0 A-D sweep pin select bit SCAN1 0 0 1 1 0 1 0 1 : AN 0 (1 pin) : AN 0, AN 1 (2 pins) : AN 0 to AN 2 (3 pins) : AN 0 to AN 3 (4 pins) MD2 A-D operation mode select bit 1 1 : Repeat sweep mode 1 BITS 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode CKS1 Frequency select bit 1 0 : f AD/2 or f AD/4 is selected 1 : f AD is selected VCUT Vref connect bit 1 : Vref connected Reserved bit Always set to "0" Note: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. Figure 1.103: A-D conversion register in repeat-sweep mode 1 Rev. H Sep 18, 2003 Page 107 of 139 M30240 Group A-D Converter 1.2.24.6 Sample and hold Sample and hold is selected by setting bit 0 of the A-D control register 2 (address 03D416) to "1". When sample and hold is selected, the rate of conversion of each pin increases. As a result, a 28 AD cycle is achieved with 8-bit resolution and 33 AD with 10-bit resolution. Sample and hold can be selected in all modes. However, in all modes, be sure to specify before starting A-D conversion whether sample and hold is to be used. Rev. H Sep 18, 2003 Page 108 of 139 CRC Calculation Circuit M30240 Group 1.2.25 CRC Calculation Circuit The Cyclic Redundancy Check (CRC) calculation circuit detects an error in data blocks. The microcomputer uses a generator polynomial of CRC_CCITT (X16 + X12 + X5 + 1) to generate CRC code. The CRC code is a 16-bit code generated for a block of a given data length in multiples of 8 bits. The CRC code is set in a CRC data register each time one byte of data is transferred to a CRC input register after writing an initial value into the CRC data register. Generation of CRC code for one byte of data is completed in two machine cycles. Figure 1.104 shows the block diagram of the CRC circuit. Figure 1.105 shows the CRC-related registers. Data bus high-order bits Data bus low-order bits Eight low-order bits Eight high-order bits (Addresses 03BD 16, 03BC 16) CRC data register (16) CRC code generating circuit x16 + x12 + x5 + 1 CRC input register (8) Figure 1.104: (Address 03BE 16) Block diagram of CRC circuit CRC data register (b15) b7 (b8) b0 b7 b0 Symbol CRCD Address 03BD 16, 03BC 16 When reset Indeterminate Values that can be set Function CRC calculation result output register R W 0000 16 to FFFF 16 CRC input register b7 Symbo CRCIN b0 Function Data input register Figure 1.105: CRC-related registers Rev. H Sep 18, 2003 Page 109 of 139 Address 03BE 16 When reset Indeterminate Values that can be set 0016 to FF 16 R W M30240 Group Programmable I/O Ports 1.2.26 Programmable I/O Ports There are 63 programmable I/O ports: P0 to P3, P6 to P8 (excluding P85), and P10. Each port can be set independently for input or output using the direction register. A pull-up resistance for each block of 4 ports can be set. P85 is an input-only port and has no built-in pull-up resistance. Figure 1.106, Figure 1.107 and Figure 1.108 show the programmable I/O ports. Each pin functions as a programmable I/O port and as the I/O for the built-in peripheral devices. To use the pins as the inputs for the built-in peripheral devices, set the direction register of each pin to input mode. When the pins are used as the outputs for the built-in peripheral devices, they function as outputs regardless of the contents of the direction registers. Unused I/O pins can be terminated as shown in Figure 1.113 and Table 1.36 . 1.2.26.1 Direction registers Figure 1.109 shows the direction registers. These registers are used to choose the direction of the programmable I/O ports. Each bit in these registers corresponds one for one to each I/O pin. Note: There is no direction register bit for P85. 1.2.26.2 Port registers Figure 1.110 shows the port registers. These registers are used to write and read data for input and output to and from an external device. A port register consists of a port latch to hold output data and a circuit to read the status of a pin. Each bit in port registers corresponds one for one to each I/O pin. 1.2.26.3 Pull-up control registers Figure 1.111 shows the pull-up control registers.The pull-up control register can be set to apply a pullup resistance to each block of 4 ports. When ports are set to have a pull-up resistance, the pull-up resistance is connected only when the direction register is set for input. 1.2.26.4 High drive capacity registers Figure 1.112 shows the Port 2 and PWM drive capacity register. Port 2 can be configured to drive an LED by increasing the drive strength of the corresponding bit's N-channel transistor. Each Timer output (TA0OUT toTA4OUT) can be configured for high-drive capability by increasing the drive strength of the corresponding bits. Rev. H Sep 18, 2003 Page 110 of 139 Programmable I/O Ports M30240 Group Pull-up selection P30 to P36 Direction register Data bus Port latch Pull-up selection P20 to P27 Direction register Data bus Port latch Drive capacity control register P70, P72 P74, P76, P80 Pull-up selection Direction register "1" Output Data bus Port latch Input respective peripheral functions Drive capacity control register P00 to P07, P10 to P17, P62, P66, P71, P73, P75, P77, P81, P82, P84, P87 Pull-up selection Data bus Direction register Port latch Input respective peripheral functions Figure 1.106: Programmable I/O ports (1) Rev. H Sep 18, 2003 Page 111 of 139 Programmable I/O Ports M30240 Group P37, P63, P67, P86 Pull-up selection Direction register "1" Output Data bus Port latch P60 7, P61, P64, P65 Pull-up selection Direction register "1" Output Data bus Port latch Input to respective peripheral functions P83 Pull-up selection Direction register "1" Output Data bus Port latch P83 Second ATTACH EXTCAP P85 Data bus NMI interrupt input P100 to P107 Pull-up selection Direction register Data bus Port latch Analog input Figure 1.107: Programmable I/O ports (2) Rev. H Sep 18, 2003 Page 112 of 139 Programmable I/O Ports M30240 Group (Note 2) BYTE BYTE Input (Note 1) (Note 2) CNVss CNVss Input (Note 1) (Note 2) RESET RESET Input (Note 1) Note 1: symbolizes parasitic diode. Note 2: A parasititc diode on the Vcc side is added to the mask ROM version. Do not apply a voltage higher than Vcc to each pin. Figure 1.108: Programmable I/O Ports (3) Port Pi direction register b7 b6 b5 b4 b3 b2 b1 b0 Symbol PDi (i = 0 to 3,6,7,10) Bit symbol PDi_0 Address 03E2 16, 03E3 16, 03E6 16, 03E7 16 , 03EE 16, 03EF 16, 03F6 16 Bit name When reset 0016 Function RW Port Pi 0 direction register PDi_1 Port Pi 1 direction register PDi_2 Port Pi 2 direction register PDi_3 Port Pi 3 direction register PDi_4 Port Pi 4 direction register PDi_5 Port Pi 5 direction register PDi_6 Port Pi 6 direction register PDi_7 Port Pi 7 direction register 0 : Input mode (Functions as an input port) 1 : Output mode (Functions as an output port) (i = 0 to 3,6,7,10) Port P8 direction register b7 b6 b5 b4 b3 b2 b1 b0 Symbol PD8 Bit symbol PD8_0 Address 03F2 16 Bit name When reset 00X00000 2 Function Port P8 0 direction register PD8_1 Port P8 1 direction register PD8_2 Port P8 2 direction register PD8_3 Port P8 3 direction register PD8_4 Port P8 4 direction register 0 : Input mode (Functions as an input port) 1 : Output mode (Functions as an output port) Nothing is assigned. This bit can either be set nor reset. When read, its content is indeterminate. PD8_6 Port P8 6 direction register PD8_7 Port P8 7 direction register Figure 1.109: Direction register Rev. H Sep 18, 2003 Page 113 of 139 0 : Input mode (Functions as an input port) 1 : Output mode (Functions as an output port) RW Programmable I/O Ports M30240 Group Port Pi register b7 b6 b5 b4 b3 b2 b1 Symbol Pi (i = 0 to 3,6,7,10) b0 Bit symbol Address 03E0 16, 03E1 16, 03E4 16, 03E5 16 03EC 16, 03ED 16, 03F4 16 Bit name Pi_0 Pi_1 Port Pi 0 register Port Pi 1 register Pi_2 Port Pi 2 register Pi_3 Pi_4 Port Pi 3 register Port Pi 4 register Pi_5 Port Pi 5 register Pi_6 Port Pi 6 register Pi_7 Port Pi 7 register When reset Indeterminate Indeterminate Function R W Data is input and output to and from each pin by reading and writing to and from each corresponding bit 0 : "L" level data 1 : "H" level data (i = 0 to 3,6,7,10) Port P8 register b7 b6 b5 b4 b3 b2 b1 b0 Symbol P8 Address 03F0 16 Bit symbol P8_0 When reset Indeterminate Bit name Function R W Port P8 0 register P8_1 Port P8 1 register P8_2 Port P8 2 register P8_3 Port P8 3 register P8_4 Port P8 4 register P8_5 Port P8 5 register P8_6 Port P8 6 register P8_7 Port P8 7 register Data is input and output to and from each pin by reading and writing to and from each corresponding bit (except for P8 5) 0 : "L" level data 1 : "H" level data Figure 1.110: Port register Pull-up control register 0 b7 b6 b5 b4 b3 b2 b1 Symbol PUR0 b0 Bit symbol PU00 Address 03FC16 Bit name When reset 0016 Function R W P00 to P03 pull-up PU01 P04 to P07 pull-up PU02 P10 to P13 pull-up PU03 P14 to P17 pull-up PU04 P20 to P23 pull-up PU05 P24 to P27 pull-up PU06 P30 to P33 pull-up P34 to P37 pull-up PU07 The corresponding port is pulled high with a pull-up resistor 0 : Not pulled high 1 : Pulled high Pull-up control register 1 b7 b6 b5 b4 b3 b2 b1 b0 Address 03FD16 Symbol PUR1 Bit symbol PU10 PU11 PU12 Bit name P64 to P67 pull-up P70 to P73 pull-up P74 to P77 pull-up P80 to P83 pull-up PU15 P84, P86, P87 pull-up PU16 P100 to P103 pull-up PU17 P104 to P107 pull-up Figure 1.111: Pull-up control register Rev. H Sep 18, 2003 Page 114 of 139 Function P60 to P63 pull-up PU14 PU13 When reset 0016 The corresponding port is pulled high with a pull-up resistor 0 : Not pulled high 1 : Pulled high R W Programmable I/O Ports M30240 Group Port 2 Drive Capacity register b7 b6 b5 b4 b3 b2 b1 b0 Symbol P2DR Address 03FA 16 Bit symbol When reset 00 16 Bit name P2DR0 P20 LED drive capacity P2DR1 P21 LED drive capacity P2DR2 P22 LED drive capacity P2DR3 P23 LED drive capacity P2DR4 P24 LED drive capacity P2DR5 P25 LED drive capacity P2DR6 P26 LED drive capacity P2DR7 P27 LED drive capacity Function RW The N-channel high-drive capacity is activated for the corresponding bit. 0 : Normal drive 1 : N-channel high drive Timer A Output Drive Capacity register b7 b6 b5 b4 b3 b2 b1 b0 Symbol TADR Bit symbol Address 03FB16 When reset 00 16 Bit name TADR0 TA0OUT drive capacity TADR1 TA1OUT drive capacity TADR2 TA2OUT drive capacity TADR3 TA3OUT drive capacity TADR4 TA4OUT drive capacity Function High-drive capacity is activated for the corresponding TAiOUT pin. 0 : Normal drive 1 : High drive Nothing is assigned. These bits can neither be set nor reset. When read, their contents are "0". Figure 1.112: Port 2 and Timer A Output drive capacity registers Rev. H Sep 18, 2003 Page 115 of 139 R W Programmable I/O Ports M30240 Group Microcomputer Port P0 to P3, P6-P8, P10 (except P83, P85, P86) (Input mode) * * * (Input mode) * * * (Output mode) Open USB D+ Open USB D- Open NMI XOUT Open P86/SOF Open P83/ATTACH Open VCC AV CC EXTCAP (Note 1) BYTE AV SS VREF VSS Note: This is an example when the DC-DC converter is disabled Figure 1.113: Example connection unused pins Table 1.36: Example connection of unused pins in single-chip mode Pin name Connection Ports P0 to P3, P6 to P8, P10 (excluding P83, P85, P86) After setting for input mode, connect every pin to Vss or Vcc via a resistor; or after setting for output mode, leave these pins open XOUT Open (When using external clock) NMI Connect via resistor to Vcc (pull-up) AVcc Connect to Vcc Avss, Vref, BYTE Connect to Vss USB D+, USB D- Open EXTCAP Connect to Vcc (when DC-DC converter is disabled) P86/SOF After setting for output mode in normal operation, leave this pin open P83/ATTACH After setting for output mode in normal operation, leave this pin open Rev. H Sep 18, 2003 Page 116 of 139 Precautions M30240 Group 1.3 Usage Precautions 1.3.1 Precautions 1.3.1.1 A-D Converter Connect a capacitor between: the VREF pin and the AVss pin; AVcc pin and AVss pin; and each analog input pin and AVss pin. * Write to each bit (except bit 6) of A-D control register 0, to each bit of A-D control register 1, and to bit 0 of A-D control register 2 when A-D conversion is stopped (before a trigger occurs). In particular, when the VREF connection bit is changed from "0" to "1", start A-D conversion after a lapse of 1s or longer. * When changing A-D operation mode, select analog input pin again. * Using one-shot mode or single sweep mode Read the corresponding A-D register after confirming the A-D conversion is finished. (It is known by A-D conversion interrupt request bit.) * Using repeat mode, repeat sweep mode 0 or repeat sweep mode 1 Use the undivided main clock as the internal CPU clock. 1.3.1.2 Built-in PROM version * All built-in PROM versions High voltage is required to program to the built-in PROM. Be careful not to apply excessive voltage. Be especially careful during power-on. * One Time PROM version One Time PROM versions shipped in blank, of which built-in PROMs are programmed by users, are also provided. For these microcomputers, a programming test and screening are not performed in the assembly process and the following processes. To improve their reliability after programming, we recommend to program and test as flow shown in Figure 1.114 before use. Wiring for the Vpp pin of the One-Time PROM version should be as follows (Vpp pin is also used as the CNVss pin): * Make the length of wiring between the Vpp pin and Vss pin or Vcc pin the shortest possible. * When the wiring length has to be longer, connect an approximately 5K ohm resistor in series from the Vpp pin to the Vss pin or Vcc pin with the shortest possible wiring. This is because the Vpp pin is the power source input pin for the built-in PROM. When programming in the built-in PROM, the impedance of the Vpp pin is low to allow the electric current for wiring flow into the PROM. Because of this, noise can enter easily. If noise enters the Vpp pin, abnormal instruction codes or data are read from the built-in PROM which may cause a program runaway. Programming with PROM programmer Screening (Note) (Leave at 150 C for 40 hours) Verify test PROM programmer Function check in target device Note: Never expose to 150 C exceeding 100 hours. Figure 1.114: Programming and test flow for One-time PROM (OTP) version Rev. H Sep 18, 2003 Page 117 of 139 M30240 Group Precautions 1.3.1.3 Dedicated Input Pins If a dedicated input pin is connected to a power supply different from the supply that Vcc is connected to, a resistor (approximately 1k ohm) should be added between the input pin and the connected power supply. However, if the dedicated input pin voltage is higher than Vcc, latch up could occur. A resistor is not required when using a Vcc voltage equal or greater than the voltage of the dedicated input pin. 1.3.1.4 DMAC DMA enable bit The DMA enable bit is assigned to bit 3 of the DMA0 and DMA1 control registers. DMA becomes active when the DMA enable bit is set to "1". Immediately after the DMA becomes active, the data transfers start and perform the following operations: * Reloads the value of the source pointer or destination pointer depending on which is specified for the forward direction address pointer * Reloads the value of the transfer counter reload register to the transfer counter. Thus overwriting "1" to the DMA enable bit with the DMAC being inactive carries out the operations given above, so the DMAC operates again from the initial state at the instant "1" is overwritten to the DMA enable bit. DMA request bit The DMA request bit turns to "1" if the DMA transfer request signal occurs regardless of the DMAC's state (regardless of weather the DMA enable bit is set to "1" or to "0"). It turns immediately before data transfer starts. In addition, it can be set to "0" by the use of a program, but cannot be set to "1". There can be instances in which a change in DMA request factor selection bit causes the DMA request bit to turn to "1". So be sure to set the DMA request bit to "0" after the DMA request factor selection bit is changed. The DMA request bit turns to "1" if a DMA transfer request signal occurs, and turns to "0" immediately before data transfer starts. If the DMAC is active, data transfer starts immediately, so the value of the DMA request bit, if read by use of a program, turns to be "0" in most cases. To examine whether the DMAC is active, read the DMA enable bit. To best judge the state of the DMAC, the DMA enable bit should be read instead of the DMA request bit. 1.3.1.5 Frequency Synthesizer * Refer to Section 1.5.1.2 for setup procedures required after a hardware reset. * Set the value of the Frequency Synthesizer Prescaler register (FSP) so that fPIN is 1 MHZ or higher. 1.3.1.6 Interrupt Reading address 0000016 * When a maskable interrupts occurs, the CPU reads the interrupt information (the interrupt number and interrupt request level) in the interrupt sequence. * The interrupt request bit of the corresponding interrupt written in address 0000016 is then set to "0". * Do not read address 0000016 by software. * Reading address 0000016 by software sets the highest priority enabled interrupt source request bit to "0" Therefore the interrupt routine may not be executed even though the interrupt is generated. Setting the stack pointer Rev. H Sep 18, 2003 Page 118 of 139 M30240 Group Precautions * The value of the stack pointer is initialized to 0000016 immediately after reset. Accepting an interrupt before setting a value in the stack pointer may cause program runaway. Be sure to set a value in the stack pointer before accepting an interrupt. * When using the NMI interrupt, initialize the stack pointer at the beginning of a program. Concerning the first instruction immediately after reset, generating any interrupts including the NMI interrupt is prohibited. Setting interrupts * Changing the Interrupt Priority Level select bit (ILVL) and clearing the Interrupt Request bit (IR) in the Interrupt Control Registers (ICR) while the Interrupt enable flag (I-FLAG) is "1", may result in unintended operations, such as BRK and other interrupts being generated. Disable the interrupts by clearing the I-FLAG before setting ILVL or clearing the IR bit. * To prevent the I-FLAG from being set before the ICR is rewritten due to the effects of the instruction queue, instructions that equal a minimum of 2 cycles should be inserted between writing to the ICR and setting the I-FLAG (2-NOPs, I MOV, I POP, etc.) Modifying interrupt control registers * Do not modify any interrupt control register when an interrupt request can be generated. * If an interrupt request occurs, modify the interrupt control register after the interrupt is disabled. External interrupts * When the polarity of the INT0 and INT1 pins is changed, the interrupt request bit can be set to "1". After changing the polarity, the interrupt request bit should be cleared to "0." The NMI interrupt * As for the NMI interrupt pin, an interrupt cannot be prohibited. Connect it to the Vcc pin if unused. * Do not get into stop mode or wait mode with the NMI pin set to "L". 1.3.1.7 Noise To reduce the possibility of noise problems: * Connect a bypass capacitor (approximately 0.1 F) across the Vss pin and the Vcc pin with the shortest possible wiring * Use circuit traces with a larger diameter than other signal traces for Vss and Vcc. Vpp connection of One-time PROM version * The Vpp (power input for PROM programming) connection for the internal PROM is connected to the CNVss pin on the One-time PROM version. Therefore, CNVss should be a short circuit trace to improve noise resistance. If the CNVss trace is long, insert a 5k resistor close to the CNVss pin and connect it to Vss. * Note: Inserting a 5k resistor will not cause any problem when switching to a mask ROM version. 1.3.1.8 Software reset Software reset with fSYN is selected as a clock source. If the Frequency Synthesizer related registers are written to while fSYN is selected as the clock source, the MCU will runaway. To avoid this: 1. Select f(XIN) as the clock source before the software reset 2. Perform software reset 3. Confirm software reset using Frequency Synthesizer Enable bit 4. Reselect fSYN as clock source. Rev. H Sep 18, 2003 Page 119 of 139 Precautions M30240 Group 1.3.1.9 Stop Mode and Wait Mode When returning from stop mode by hardware reset, RESET pin must be set to "L" level until main clock oscillation is stabilized. When entering either wait or stop mode, you must first enable any interrupts you want to cancel the wait or stop. Also, make sure to disable any interrupts that you don't want to cancel the wait or stop. If only hardware reset or NMI interrupts are desired to cancel wait or stop, all other interrupt priority levels should be set to "0" If using fSYN as the internal clock, switch it to f(XIN) before entering stop mode. When switching to either wait or stop mode, the WAIT instruction or the instruction that sets the all clock stop bit to "1" are prefetched within the instruction queue before the program stops. Put at least four NOPs in succession after the WAIT instruction or after the instruction that sets the all clock stop control bit to "1." 1.3.1.10 Timer A (Timer mode) Reading the Timer Ai register while a count is in progress allows reading, with arbitrary timing, the value of the counter. Reading the Timer Ai register with the reload timing gets "FFFF16". Reading the Timer Ai register after setting a value in the Timer Ai register with a count halted but before the counter starts counting gets a proper value. 1.3.1.11 Timer A (Event counter mode) 1. Reading the Timer Ai register while a count is in progress allows reading, with arbitrary timing, the value of the counter. Reading the Timer Ai register with the reload timing gets "FFFF16" by underflow or "000016" by overflow. Reading the Timer Ai register after setting a value in the Timer Ai register with a count halted but before the counter starts counting gets a proper value. 2. When counting has stopped in free-run type, set the timer again. 3. When using Free-run type, the timer's register contents may be undefined when counting starts. Set the timer value immediately after counting has started. * When the up/down count is not switched: *Enable the reload function and set a value to the timer register before counting starts. *Rewrite the value to the timer register immediately after counting has started. (This is the same operation as free-run type.) *If counting up, rewrite 000016. *If counting down, rewrite FFFF16. * When the up/down count is switched: *Use the reload type until the first count pulse is input. *Switch to free-run type afterwards. 1.3.1.12 Timer A (One-shot Timer mode) 1. Setting the count start flag to "0" while the count is in progress causes: * The counter to stop counting * The contents of the reload register are reloaded * The TAiOUT pin outputs "L" level * The interrupt request is generated 2. Timer Ai interrupt request bit goes to "1" if the operation mode is set by: * Selecting one-shot timer mode after reset * Changing operation mode from timer mode to one-shot timer mode * Changing operation mode from event counter mode to one-shot timer mode Note: To use Timer Ai interrupt request bit, clear the Timer Ai interrupt request bit to "0" after these changes have been made. Rev. H Sep 18, 2003 Page 120 of 139 M30240 Group Precautions 1.3.1.13 Timer A (Pulse-width Modulation mode) 1. The Timer Ai interrupt request bit becomes "1" if setting operation mode of the timer in compliance with any of the following procedures: * Selecting PWM mode after reset. * Changing operation mode from timer mode to PWM mode. * Changing operation mode from event counter mode to PWM mode. Therefore, to use Timer Ai interrupt (interrupt request bit), set Timer Ai interrupt request bit to "0" after the above listed changes have been made. 2. Setting the count start flag to "0" while PWM pulses are being output causes the counter to stop counting. If the TAiOUT pin is outputting an "H" level in this instance, the output level goes to "L", and the Timer Ai interrupt request bit goes to "1". If the TAiOUT pin is outputting an "L" level in this instance, the level does not change, and the Timer Ai interrupt request bit does not become "1". 1.3.1.14 Timer B (Timer mode) Reading the Timer Bi register while a count is in progress allows reading, with arbitrary timing, the value of the counter. Reading the Timer Bi register with the reload timing gets "FFFF16". Reading the Timer Bi register after setting a value in the Timer Bi register with a count halted but before the counter starts counting gets a proper value. 1.3.1.15 UART2 When using UART2 in clock asynchronous serial I/O mode (UART), use the internal clock only, otherwise, one of the following may occur: * The interrupt may not be issued at the end of the data transmission when the hardware transfers the data from the transmit buffer to the transmit register. * Data may be corrupted when the hardware transfers data fro the transmit buffer register to the transmit register. This only applies to UART2 asynchronous serial I/O mode and does not apply to UART0 or UART1. 1.3.1.16 USB * When the USB Reset Interrupt Status flag is set to "1", the contents in the USB internal register (addresses 030016-033516) will return to their reset values. However, the following registers are not affected by a USB Reset: * USB Control register (USBC) * Frequency Synthesizer Control register (FSC) * USB Endpoint x FIFO (addresses 033816 -033C16) * All LPF pin passive components must be located as close as possible to the LPF pin. * An insulation connector (Ferrite beads) must be connected between the AVss and digital Vss pins, and between AVcc and digital Vcc pins. * When using DC-DC converter to supply 3.3V to the drive, connect a capacitor between the EXTCAP pin and the Vss pin. The connection should consist of a 2.2F capacitor (tantalum capacitor) and a 0.1F capacitor (ceramic capacitor) connected in parallel. Use a ceramic capacitor equivalent to the X7R type as a 0.1 F capacitor. * Connect a 27-33 resistor between the USB D+ and USB D- pins to meet USB specification impedance requirements. * Connect a ceramic capacitor (33pF recommended) after the resistor between USB D+ and USB Dor between USB D+/D- pins and the Vss pin to control the slew rate and rise/fall timing. This cap should be placed after the 27-33 resistor. See section 1.5 for more details. * Connect a 1.5k resistor between the EXTCAP pin and the USB D+ pin during normal operation. * Connect a 1.5k resistor between the P83/ATTACH pin and the USB D+ pin and leave the EXTCAP open when using Attach/Detach function. * Read or write to the USB internal registers (address 030016-033C16) by 8-bit mode only. Accessing by 16-bit mode will cause incorrect read/write values. Rev. H Sep 18, 2003 Page 121 of 139 Precautions M30240 Group * When using an isochronous transfer, set the FLUSH bit by: * OUT FIFO data flush: When OUT_PKT_RDY flag is "1", set the FLUSH bit to "1" * IN FIFO data flush: Use AUTO_FLUSH bit. * Do not write to the USB internal registers (address 030016-033C16) when the USB clock is disabled in Suspend mode. * Precautions for accessing the USB Interrupt Status registers 1 & 2 (USBIS1, USBIS2) * When reading from/writing to both registers, access USBIS1 first and then USBIS2. * When writing to these registers, use transfer instructions such as the MOV instruction. Do not use Read Modify Write instructions such as OR or BSET because this could cause improper values to be written back. * Each status flag can be cleared to"0" by writing back the same value "1" which was read from the USB Interrupt Status register. Make sure to clear only the corresponding status flag in each USB interrupt routine. Mask the other status flags so that they are not accidentally cleared. * Example of USB Function Interrupt C Language ram1=USBIS1; /*Read from USB Interrupt Status register 1*/ ram2=USBIS2; /*Read from USB Interrupt Status register 2*/ ram2 &=0x1F; /*Mask flags except USB Function Interrupt status flags*/ USBIS1=ram1; /*Write to USB Interrupt Status register 1*/ USBIS2=ram2; /*Write to USB Interrupt Status register 2*/ Assembly Language: mov.b USBIS1, ram1 ;Read from USB Interrupt Status register 1 mov.b USBIS2, ram2 ;Read from USB Interrupt Status register 2 and.b #1Fh, ram2 ;Mask flags except USB Function Interrupt status flags mov.b ram1, USBIS1 ;Write to USB Interrupt Status register 1 mov.b ram2, USBIS2 ;Write to USB Interrupt Status register 2 * Do not use Read, Modify, Write instructions on the following USB Control and Status registers: * * * * USB Endpoint 0 Control and Status (EP0CS) USB Endpoint x IN Control and Status (EPxICS) USB Endpoint x OUT Control and Status (EPxOCS) Refer to Section 1.5.5.1 for more information on these registers and how to modify their contents. Rev. H Sep 18, 2003 Page 122 of 139 M30240 Group Precautions Items to be submitted when ordering masked ROM version Please submit the following when ordering masked ROM products: (1) Mask ROM confirmation form (2) Mark specification sheet (3) ROM data: EPROMs or floppy disks *: In the case of EPROMs, there are sets of EPROMs are required per pattern. *: In the case if floppy disks, 3.5-inch double-sided high-density disk (IBM format) is required per pattern. Rev. H Sep 18, 2003 Page 123 of 139 Electrical characteristics M30240 Group 1.4 Specifications 1.4.1 Electrical characteristics Table 1.37: Absolute maximum ratings only, not operating conditions Symbol Parameter Vcc Supply voltage AVcc Analog supply voltage VI Input voltage VI Input voltage VO Output voltage Condition Vcc=AVcc -0.3 to 6.5 Unit V VCC=AVCC -0.3 to 6.5 V -0.3 to Vcc+0.3 V Port0, Port1, Port2, Port3, Port6, Port7, Port8, Port10, RESET, VREF, XIN CNVss Port0, Port1, Port2, Port3, Port6, Port7, Port8 (except P85), Port10, RESET, VREF, XOUT Rated Value -0.3 to 6.5 -0.3 to Vcc+0.3 (Note 1) V V Pd Power dissipation Topr Operating ambient temperature 0 to 70 C Tstg Storage temperature -65 to 150 C Ta=25C Note 1: When writing to EPROM, CNVss rated value is -0.3 to 13 volts Rev. H Sep 18, 2003 Page 124 of 139 760 mW Electrical characteristics M30240 Group Table 1.38: Recommended operating conditions (Vcc=4.1~5.25V, Vss=0V, Ta= 0C 70C, f(Xin) = 12MHz) Standard Symbol Parameter Unit Min Typ Max 4.1 5.0 Vcc 0 0 5.25 V V V V Vcc AVcc Vss Avss Supply voltage Analog supply voltage Supply voltage Analog supply voltage VIH High input voltage Port0, Port1, Port2, Port3, Port6, Port7, Port8,Port10,RESET,VREF,XIN,CNVSS 0.8Vcc Vcc V VIL Low input voltage Port0, Port1, Port2, Port3, Port6, Port7, Port8,Port10,RESET,VREF,XIN,CNVSS 0 0.2Vcc V mA High peak output current Port0, Port1, Port3, Port6, P71, P73, P75, P77, P81 to P87, Port10 -10 Ioh (peak) P20 to P27, P70, P72, P74, P76, P80 -20 mA Port0, Port1, Port3, Port6, P71, P73, P75, P77, P81 to P87, Port10 -5 mA P20 to P27, P70, P72, P74, P76, P80 -10 mA P2, P3, P6, P7, P80~P82 -80 mA P0, P1, P83~P87, P10 -80 mA P2, P3, P6, P7, P80~P82 -40 mA P0, P1, P83~P87, P10 -40 mA Port0, Port1, Port3, Port6, P71, P73, P75, P77, P81 to P87, Port10 10 mA P20 to P27, P70, P72, P74, P76, P80 20 mA Port0, Port1, Port3, Port6, P71, P73, P75, P77, P81 to P87, Port10 5 mA P20 to P27, P70, P72, P74, P76, P80 10 mA P2, P3, P6, P7, P80~P82 80 mA P0, P1, P83~P87, P10 80 mA P2, P3, P6, P7, P80~P82 40 mA P0, P1, P83~P87, P10 40 mA 12 MHz Ioh (avg.) Ioh(peak) Ioh (avg.) Iol (peak) Iol (avg.) Iol (peak) Iol (avg. f(XIN) High avg output current High peak output current High avg output current Low peak output current Low avg output current Low peak output current Low avg output current Main clock input oscillation frequency 1 Note: The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average value measured over 100 ms. The total peak current is the peak value of all the currents. Rev. H Sep 18, 2003 Page 125 of 139 Electrical characteristics M30240 Group Table 1.39: Electrical Characteristics (Vcc=4.1~5.25V, Vss=0V, Ta= 0C 70C, f(Xin) = 12MHz) Symbol Parameter VOH High output voltage VOH High output voltage VOH High output voltage VOH High output voltage VOL Low output voltage VOL Low output voltage VOL Low output voltage VOL Low output voltage VOL Low output voltage VT+-VT- Hysteresis VT+-VT- Hysteresis Iih High input current Iil Low input current RPULLUP Pull-up resistance RXIN VRAM Feedback resistance, Xin RAM retention voltage Icc Port0, Port1, Port2, Port3, Port6, Port71, P73,P75,P77,Port8 (except P85), Port10 Port 70,P72,P74,P76,P80 Port0, Port1, Port2, Port3, Port6, Port71, P73,P75,P77,Port8 (except P85), Port10 high power Xout low power Port0, Port1, Port2, Port3, Port6, Port71, P73,P75,P77,Port8 (except P85), Port10 High-drive mode Port 2 Port 70,P72,P74,P76,P80 NOTE 1 Port0, Port1, Port2, Port3, Port6, Port71, P73,P75,P77,Port8 (except P85), Port10 high power Xout low power TA0in to TA4in, INT0 to INT1, ADTRG, CTS0, CTS1, CLK0, CLK1, TA2out to TA4out, NMI, KI0 to KI15 RESET Port0, Port1, Port2, Port3, Port6, Port7,Port8, Port10, RESET, CNVss Port0, Port1, Port2, Port3, Port6, Port7, Port8, Port10, RESET, CNVss Port0, Port1, Port2, Port3, Port6, Port7, Port8, Port10 Power supply current Measuring condition Standard Typ Max Unit IOH = -5mA, Vcc=5V 3.0 V IOH = -10mA, Vcc=5V 3.0 V IOH = -200A, Vcc=5V 4.7 V IOH = -1mA, Vcc=5V IOH = -0.5mA, Vcc=5V 3.0 3.0 V V IOL = 5mA, Vcc=5V 2.0 V IOL = 10mA, Vcc=5V 2.0 V IOL= 10mA, Vcc=5V 2.0 V IOL = 200A, Vcc=5V 0.45 V IOH = 1mA, Vcc=5V IOH = 0.5mA, Vcc=5V 2.0 2.0 V V Vcc=5V 0.2 0.8 V Vcc=5V 0.2 1.8 V VI = 5V, Vcc=5V 5.0 A VI = 0V -5.0 A 167 k VI = 0V, Vcc=5V 30 When clock is stopped Icc run with USB ON (Mask) Icc run with USB ON (OTP) Icc run with USB OFF Ta=25C clock stopped Output pins Ta=70C open, other clock stopped pins tied to Vss Ta=25C wait mode with internal clocks ON Ta=25C wait mode with internal clocks OFF 2.0 50 1.0 Note 1: Only high drive when Timer A is enabled and drive registers set for high drive mode. Rev. H Sep 18, 2003 Page 126 of 139 Min M V 80 mA 95 mA 50 mA 1 A 20 A 8 mA 4 mA Electrical characteristics M30240 Group Table 1.40: USB Electrical Characteristics (Vcc=4.1~5.25V, Vss=0V, Ta= 0C 70C, f(Xin) = 12MHz) Standard Symbol Parameter Measuring Condition Unit Min Typ Max VOH D+, D- I=18.3 mA, RX=33 , VXcap =3.0 V VOL D+, D- I=18.3 mA, RX=33 , VXcap =3.0 V 0.8 V Isusp Suspend current USB suspend mode, internal clock stopped 175 A Xcap DC-DC converter voltage DC-DC converter output voltage on Xcap pin 3.6 V 2.2 3.0 V 3.3 Note: See Fig. 1.120 for recommended configuration. Table 1.41: A-D conversion characteristics (Vcc, Avcc = 4.1~5.25V, Vss=0V, Ta= 0C~ 70C, f(Xin) = 12MHz) Symbol Parameter - Resolution - Absolute accuracy Measuring condition Standard Unit Min Typ Max VREF = Vcc 10 Bits Sample and hold function not available VREF = Vcc = 5V 3 LSB Sample and hold function available (10bit) VREF = Vcc = 5V 3 LSB Sample and hold function available (8bit) VREF = Vcc = 5V 2 LSB 40 k RLADDER Ladder resistance tCONV Conversion time (10bit) 2.75 s tCONV Conversion time (8bit) 2.34 s tSAMP Sampling time 0.25 s VREF Reference voltage 2 V VIA Analog input voltage (min. operating frequency =x) 0 VREF V AD A-D clock frequency 1 12 MHz Rev. H Sep 18, 2003 Page 127 of 139 VREF = Vcc = 5V 10 Timing M30240 Group 1.4.2 Timing Timing requirements referenced to Vcc = 4.1~5.25V, Vss=0V, Ta= 0C~70C unless otherwise specified. Table 1.42: External clock input Standard Symbol Parameter Unit Min tc External clock input cycle time tw(H) Max 83.3 ns External clock input HIGH pulse width 33 ns tw(L) External clock input LOW pulse width 33 ns tr External clock rise time 15 ns tf External clock fall time 15 ns Table 1.43: Timer A input (counter input in event counter mode) Symbol tc(TA) tw(TAH) tw(TAL) Table 1.44: Parameter TAiIN input cycle time TAiIN input HIGH pulse width TAiIN input LOW pulse width Standard Min Max 100 40 40 Unit ns ns ns Timer A input (gating input in timer mode) Standard Symbol Parameter Unit Min Max tc(TA) TAiIN input cycle time 400 ns tw(TAH) TAiIN input HIGH pulse width 200 ns tw(TAL) TAiIN input LOW pulse width 200 ns Table 1.45: Timer A input (external trigger input in one-shot timer mode) Standard Symbol Parameter Unit Min Max tc(TA) TAiIN input cycle time 200 ns tw(TAH) TAiIN input HIGH pulse width 100 ns tw(TAL) TAiIN input LOW pulse width 100 ns Table 1.46: Timer A input (external trigger input in pulse width modulation mode) Standard Symbol Parameter Unit Min Max tw(TAH) TAiIN input HIGH pulse width 100 ns tw(TAL) TAiIN input LOW pulse width 100 ns Rev. H Sep 18, 2003 Page 128 of 139 Timing M30240 Group Table 1.47: Timer A input (up/down input in event counter mode) Standard Symbol Parameter Unit Min Max tc(UP) TAiOUT input cycle time 2000 ns tw(UPH) TAiOUT input HIGH pulse width 1000 ns tw(UPL) TAiOUT input LOW pulse width 1000 ns tsu(UP-TIN) TAiOUT input setup time 400 ns th(TIN-UP) TAiOUT input hold time 400 ns Table 1.48: A-D trigger input Standard Symbol Parameter Unit Min Max tc(AD) ADTRG input cycle time (triggerable minimum) 1000 ns tw(ADL) ADTRG input LOW pulse width 125 ns Table 1.49: Serial I/O Standard Symbol Parameter Unit Min Max tc(CK) CLKi input cycle time 200 ns tw(CKH) CLKi input HIGH pulse width 100 ns tw(CKL) CLKi input LOW pulse width 100 ns td(C-Q) TxDi output delay time th(C-Q) TxDi hold time 0 ns tsu(D-C) RxDi input setup time 30 ns th(C-D) RxDi input hold time 90 ns Table 1.50: 80 ns External interrupt INTi inputs Standard Symbol Parameter Unit Min Max tw(INH) INTi input HIGH pulse width 250 ns tw(INL) INTi input LOW pulse width 250 ns Rev. H Sep 18, 2003 Page 129 of 139 Timing Diagram M30240 Group 1.4.3 Timing Diagram tc(TA) tw(TAH) TAiIN input tw(TAL) tc(UP) tw(UPH) TAiOUT input tw(UPL) TAiOUT input (Up/down input) During event counter mode TAiIN input th(TIN-UP) (When count on falling edge is selected) tsu(UP-T IN) TAiIN input (When count on rising edge is selected) t c(AD) tw(ADL) ADTRG input tc(CK) tw(CKH) CLKi tw(CKL) th(C-Q) TxDi td(C-Q) tsu(D-C) RxDi tw(INL) INTi input Figure 1.115: Peripheral/interrupt timing diagram Rev. H Sep 18, 2003 Page 130 of 139 tw(INH) th(C-D) Frequency Synthesizer M30240 Group 1.5 Applications 1.5.1 Frequency Synthesizer This section presents the recommended method of setting up and using the frequency synthesizer that generates the 48MHz clock needed by the USB FCU and the DC-DC converter that provides power to the D+/D- drivers. 1.5.1.1 Reset of USB-related registers The special function registers (SFRs) that govern the operation of the frequency synthesizer, DC-DC converter and USB FCU are affected by one or more reset events. The addresses of the special function registers (SFRs) that are affected by Hardware Reset, USB Reset, or both are shown in Figure 1.116. Hardware Reset SFR Registers: 000416 to 005F16, 000C (USBC), 037816 to 03FF16 03DC16 (FSC) USB Reset SFR Registers: 030016 to 033C16 (USB FCU registers) Figure 1.116: SFR Reset Venn Diagram All resetable SFRs, including SFRs and other registers internal to the USB FCU, are affected by a Hardware Reset, which occurs when the RESET pin is brought low or an undefined opcode is fetched. See Section 2.4 for a complete listing of SFRs and their reset values. Only registers internal to the USB FCU are reset when a USB Reset sent by the Host/Hub is detected. These USB registers are reset to their default values except for bit 5 of USBIS2 (USB Reset Interrupt Status Flag), which is set to a "1". USB FCU registers are registers from address 030016to 033C16 and all other registers within the USB FCU, many of which the MCU does not have direct access to (e.g. FIFO address pointers). The USB FIFO registers are empty after USB reset because the FIFO address pointers are reset. However, the physical contents of the FIFOs are not set to all `1`s or all `0`s. Other SFRs such as USBC, FSC, and CM0, CM1 are not affected by a USB Reset. Rev. H Sep 18, 2003 Page 131 of 139 Frequency Synthesizer M30240 Group 1.5.1.2 Set up of Frequency Synthesizer and DC-DC Converter Frequency USBC5 Synthesizer (enable) enable lock FSE LS DC-DC Converter enable USBC4 current mode USBC3 Ext Cap (enable) 2.2 F USB FCU USBCLK (48MHz) 0.1 F D+ 27-33 D- 27-33 USB Transceiver 1.5 k f(Xin) enable enable USBC7 USBC7 Figure 1.117: PLL, DC-DC Converter and USB Functional Block Diagram A functional block diagram of the USB system on the M30240 which shows how the control signals affect operation is given in Figure 1.117 1.5.1.3 Set up after Hardware Reset A Hardware Reset occurs when either the RESET pin is brought low for more than 2 s or an invalid opcode is fetched by the CPU. The frequency synthesizer (PLL) and DC-DC converter should be set up as follows in the Hardware Reset routine (see Figure 1.118), * Power up the M30240 and other components on the peripheral device for less than 100 mA operation. The current limit only applies for bus powered devices. * Configure the PLL for 48MHz f(VCO) operation. * Enable the PLL by setting FSE (bit 0 of the Frequency Synthesizer Control Register (FSC)) to a "1", then wait for 2 ms. * Check the lock status bit (LS, bit 7 of FSC). * If the bit is a "1", go on. * If the bit is a "0", wait 0.1 ms longer and then re-check the bit. * Enable the DC-DC converter in high current mode by setting USBC4 (bit 4 of the USB Control Register (USBC)) to a "1" and keeping USBC3 (bit 3 of USBC) a "0". High current mode should always be used during normal USB operation. Low current mode should only be used during a USB suspend. * Wait (C + 1)ms (where C equals the external capacitance connected to the Ext Cap pin in F) for the voltage on Ext Cap to reach a steady state voltage of approximately 3.3V. (Since the D+ pullup is connected to the Ext Cap pin, the upstream hub will detect that the peripheral device has been plugged in once the voltage on D+ reaches approximately 2.0 V.) * Example: A 2.2 F capacitor connected to Ext Cap requires 3.2 ms for the voltage on Ext Cap to be stable. * Enable the USB clock by setting USBC5 (bit 5 of USBC) to a "1". (If the USB clock and FCU are enabled before the voltage on Ext Cap is stable, a phantom USB Reset may be detected, or the actual USB Reset may not be detected.) * Wait at least 4 cycles of , then enable the USB FCU by setting USBC7 (bit 7 of USBC) to a "1". * Enable other blocks as necessary. Rev. H Sep 18, 2003 Page 132 of 139 Frequency Synthesizer M30240 Group Enable PLL RESET FSE Wait 2 ms LS Enable DC-DC converter USBC4 Wait (C+1) ms USBC5 Enable USB Clock Wait at least 4 cycles of USBC7 Enable USB FCU Figure 1.118: PLL and DC-DC Converter Set Up Timing after Hardware Reset 1.5.1.3.1 Precautions after Software Reset A software reset occurs after writing a `1' to bit `3' of the processor mode register 0 (address 000416). During software reset, the contents of the internal RAM are preserved as well as all USB, DC-DC converter, and PLL registers. If the PLL is used as the system clock source, it is important to note that after a software reset occurs, any writes to the frequency synthesizer register will cause it to freeze. This can cause erratic device behavior. In order to avoid this, it is recommended that the following procedure be used: * Prior to software reset, switch device clock source from `fsyn to f(Xin)'. Please see the Frequency Synthesizer specification for more details. * After software reset using firmware, evaluate the condition of the synthesizer control register (FSC register, address 03DC16, bit `0'). This bit is not effected by a software reset and can check to see if the PLL is still enabled. If so, any setup routine that involves writing to the PLL registers should not be called. At this point, the clock source can be changed back to fsyn. 1.5.1.4 Set up after USB Reset Signaling Detected A USB Reset is detected by the USB FCU when an SE0 is present on D+/D- for at least 2.5 s. Detection of a USB Reset results in bit 5 of USB Interrupt Status Register 2 (USBIS2) being set to a "1" and the registers within the USB FCU being reset to their default values. Register USBC and the PLL registers are not affected by a USB Reset. A USB Function Interrupt request is also generated when the USB Reset is detected. No modifications to the frequency synthesizer or DC-DC converter configuration should be made in the USB Function Interrupt routine. However, all USB FCU registers (addresses 30016 to 33C16) must be reconfigured to their pre-enumeration state. 1.5.1.5 Set up after USB Suspend Detected A USB Suspend occurs if the USB FCU does not detect any bus activity on D+/D- for at least 3 ms. Detection of a suspend results in bit 7 of USBIS2 and bit 0 of USBPM (SUSPEND) being set to a "1". This causes bit 3 of SUSPIC to be set to a "1". Bit 7 of USBIS2 then needs to be cleared by writing a "1" to the bit in order to allow a future suspend event. The configuration of the frequency synthesizer and DC-DC converter should be changed as follows in the USB Suspend Interrupt routine (if the device is bus powered): Rev. H Sep 18, 2003 Page 133 of 139 M30240 Group Frequency Synthesizer * Change the DC-DC converter from high current mode to low current mode by setting USBC3 (bit 3 of the USBC) to a "1" * Disable the USB clock by setting USBC5 (bit 5 of USBC) to a "0". Once the USB clock is disabled, registers internal to the USB FCU should not be written to. This includes all USB SFRs from address 030016 to 033C16. It does not include USBC or FSC. * Perform other tasks to reduce total current to below 500A. * Disable the PLL by setting FSE (bit 0 of FSC) to a "0". * Make sure the I-FLAG is set to "1". * Stop the system clock by setting CM10 (bit 0 of CM1) to a "1". Make sure to first enable writing to the system clock control register by setting PRCO (bit 0 of PRCR) to "1'. Also, make sure to enable the USB Resume Interrupt (RSMIC register) and clear or execute any pending interrupts prior to stopping the clock so the MCU can wake up once resume signaling is detected. If the clock is stopped using an interrupt routine, make sure to set the priority of the Resume Interrupt (RSMIC) higher than the current interrupt. * Note that no action may be necessary if the device is self powered. 1.5.1.6 Set up after USB Resume Signaling Detected A resume occurs when the USB FCU is in the suspend state and detects a non-idle signaling on D+/ D-. Detection of a resume results in bit 6 of USBIS2 and bit 1 of USBPM (RESUME) being set to a "1". This causes bit 3 of RSMIC to also be set to "1". If the MCU was in the stop state prior to the detection of the resume, the USB Resume Interrupt request will cause the MCU to wake up from the stop state. Bit 6 of USBIS2 needs to be cleared (by writing a "1" to the bit) in order to allow a future resume event. See section 2.9 "Stop Mode" for details on waking up from the stop state. The configuration of the frequency synthesizer and DC-DC converter should be changed as follows in the USB Resume Interrupt routine (if the device is bus powered): * Re-enable the PLL for 48MHz f(VCO) by setting FSE (bit 0 of the FSC) to a "1", then wait for 2 ms. * Wait for 2 ms. * Check the lock status bit (LS, bit 7 of FSC). * If the bit is a "1", continue. * If the bit is a "0", wait 0.1 ms longer and then re-check the bit. * Enable the USB clock by setting USBC5 (bit 5 of USBC) to a "1". * Wait for a minimum of 4 cycles. * Change the DC-DC converter from low current mode to high current mode by setting USBC3 (bit 3 of the USBC) to a "0". * Enable other blocks as necessary. Registers internal to the USB FCU should not be written to until the USB clock is re-enabled. This includes all USB SFRs from address 030016 to 033C16. It does not include USBC or FSC. Note that the configuration changes described above may not need to be made if the MCU was not placed in a suspend state as described in section 5.1.2.3 Set up after USB Suspend Detected. 1.5.1.7 PLL Lock Bit The PLL lock bit is used to indicate when the PLL is first locked. Accordingly, after the PLL is enabled and it has been given 2.0 ms to stabilize, the lock bit status should be checked. Once the lock bit is HIGH, the USB check should be enabled. After this stage, the lock bit is no longer valid and should not be monitored, unless the PLL is re-enabled. Rev. H Sep 18, 2003 Page 134 of 139 Attach/Detach Function M30240 Group 1.5.2 Attach/Detach Function The Attach/Detach Function can be used to attach or detach a USB function from the host without disconnecting the cable. When attaching a USB function, the connect registers should be set to 0316 at the same time on or before the DC-DC Converter is enabled. Similarly, when detaching the connect register, it should be set to 0116 when powering down the DC-DC Converter. If you do not set the connect (address 001F16) to HIGH, the system will default to its normal mode. Note: If the D+ is connected to EXTCAP, this mode will not work. D+ is connected to EXTCAP through a 1.5 K resistor in compliance with the USB specification. USB Suspend/Resume Function Hardware connections are shown below Attach is connected to D+ through 1.5 K resistor. ATTACH [P83] D+ (pin 9 M30240) 1.5 K Attach/Detach mode disabled EXTCAP D+ (pin 9 M30240) 1.5 K 1.5.3 Low Pass Filter Network All passive components should be in close proximity to pin 78 (LPF), capacitors should be X7R dielectric or better. The recommended values are listed in Table 1.51. See Figure 1.119 for schematic of the LPF. Analog Vss and Analog Vcc, pins 77 and 80 should have isolated connections to the digital Vss and Vcc ground planes. Figure 1.120 shows the power supply isolation. Table 1.51: Recommended values R = 1000 10% C2 = 680 pf 10% C1 = 0.1 f 10% Ferrite Beads Pin 78 (LPF) R C2 Digital Vcc (on card) Analog Vcc (Pin 80) C C Digital Vss Analog Vss (Pin 77) C1 Pin 77 AVss Figure 1.119 Figure 1.119: LPF Filter Schematic Rev. H Sep 18, 2003 Page 135 of 139 Decoupling Capacitors Figure 1.120 Figure 1.120: Power Supply USB Transceiver M30240 Group 1.5.4 USB Transceiver When using the on-chip voltage converter to supply the necessary 3.3V to the driver circuit, a capacitor network must be connected between Ext. Cap (pin 6) and VSS (pin 13). Two capacitors are required as shown in Figure 1.21. The high frequency 0.1 F capacitor should be an X7R type or better. The low frequency decoupling capacitor of 2.2 F should be of tantalum di-electric or better. The start-up time for this value of the capacitor is 3.2 ms, approximately (1ms/ F) + 1 ms. After enabling the on-chip voltage converter, a certain amount of time must pass before a wait or stop clock instruction is executed. The amount of time is given by (C+1) ms, when C is the value in F of the external capacitance connected to the Ext. Cap pin. For example, if the external capacitance is 2.2 F, at least 3.2 ms must elapse from the time that the on-chip voltage converter is enabled until a WAIT instruction or STOP command (CM10 = 1) is executed. In order to meet the impedance matching requirements of the USB Specification, a 27-33 resistor must be added to USB D+ (pin 9) and to USB D- (pin 10). In addition, capacitors connected between USB D+ and USB D- or USB D+/D- and Vss may need to be added for rise/fall time matching and edge control. These capacitors should be placed after the 33 resistors. Their configuration and values will depend on the PCs layout. The placement of external components is illustrated in Figure . Voltage Converter EXTCAP 2.2 F 0.1 F 10% 10% USB_Vp_out USB_Txen_n USB_Vm_out USB_Suspend USB_Rxd USB Block USB_Vp_in USB_Vm_in XCV_Vp_out D+ XCV_Txen_n 33 pF D- XCV_Vm_out XCV_Suspend XCV_Rxd +_ XCV_Vp_in XCV_Vm_in Note: Capacitor and resistor values and configuration may depend on PCB layout. Figure 1.121: Configuration of External USB components 22 pF 27-33 22 pF Transceiver Rev. H Sep 18, 2003 Page 136 of 139 27-33 (Note) Programming Notes M30240 Group 1.5.5 Programming Notes 1.5.5.1 Accessing USB IN/OUT Control and Status Registers Do not use read-modify-write instruction on these registers because they contain control and status bits that can be changed by both hardware and software. There is a possibility that using a read-modify-write instruction might cause incorrect data to be written back to these registers. See Table 1.52 for a list of bits that may have incorrect data written to them and the value you should write back in order to prevent this from occurring. Table 1.52: Bits that might have incorrect data Register name EP0CS Bit name Value to write for "No change" IN_PKT_RDY (b1) "0" DATA_END (b3) "0" FORCE_STALL (b4) "1" IN_PKT_RDY (b0) "0" UNDER_RUN (b1) "1" OUT_PKT_RDY (b0) "1" OVER_RUN (b1) "1" FORCE_STALL (b4) "1" DATA-ERR (b5) "1" EPxICS (x = 1-4) EPxOCS (x = 1-4) The Endpoint 1-4 IN CSR's (EPiICS, i = 1-4) have a bit IN_PKT_RDY (bit 0) that is set to a "1" by the firmware after a packet of data is loaded to the respective endpoint's FIFO. This signifies that a packet is ready for transmission. If the firmware wants to send a NULL packet to the host, it can simply write a "1" to the IN_PKT_RDY bit without loading data to the FIFO. This bit is cleared by the hardware. If the firmware manipulates (writes) the IN CSR for a purpose other than to signify to the hardware that a data packet is ready for transmission (for instance, set/reset ISO bit, set/reset SEND_STALL bit), it must make sure that a "0" is written back to the IN_PKT_RDY bit. Failure to do so could cause improper operation of the device. Writing a "0" to the IN_PKT_RDY bit has no effect on its state. The Endpoint 1-4 OUT CSRs (EPiICS, i = 1-4) have a bit OUT_PKT_RDY (bit 0) that is set to a "1" by the hardware after a packet of data is received from the host to the respective endpoint's FIFO. This signifies that a packet is ready for download. This bit is cleared by the firmware by writing a "0" to it after the data packet is unloaded from the FIFO. If the firmware manipulates (writes) the OUT CSR for a purpose other than to signify to the hardware that a data packet has been unloaded (for instance, set/reset ISO bit, set/reset SEND_STALL bit), it must make sure that a "1" is written back to the OUT_PKT_RDY bit. Failure to do so could cause improper operation. Writing a "1" to the OUT_PKT_RDY bit has no effect on its state. Rev. H Sep 18, 2003 Page 137 of 139 Programming Notes M30240 Group Below is an example of how to set/reset the ISO bit of the IN CSR register (for initializing the respective endpoint as an isochronous endpoint): [R1L] = [EPiICS].B OR.B #0AH, R1L ;set ISO bit = 1, write "1" back to UNDER_RUN bit AND.B #0FEH, R1L ;write "0" back to IN_PKT_RDY bit [EPiICS].B = [R1L] [R1L] = [EPiICS].B OR.B #02, R1L ;write "1" back to UNDER_RUN bit AND.B #0F6H, R1L ;reset ISO bit = 0, write "0" back to IN_PKT_RDY bit [EPiICS].B= [R1L] 1.5.5.2 USB Consecutive Set Address The USB Specification states that the host can send a SET_ADDRESS request for the following cases: 1. During enumeration when the device is in default state. (The host assigns a non-zero address.) 2. When the device is in the address state. (The host can re-assign a new address.) The device handles case #1 (when the device is in the default state) and case #2 (when the device is in the address state) differently. The following is a segment of code to illustrate the program flow to properly deal with these cases. DEFAULT_STATE: If [USBA].B ==0 [USBA.].B = wValue _ lo R1L = [EP0CS].B OR.B #58H, R1L [EP0CS].B = R1L wait for the completion of the status JMP ADDR_END else ADDR_STATE R1L [EP0CS].B OR.B #58H, R1L [EP0CS].B = R1L wait for the completion of the status [USBA].B= wValue_lo ;If the device is in default state, update address before STATUS completion ;USB ENDPOINT 0 CSR ;Set serviced_out_pkt_rdy & data_end, write "1" back to FORCE_STALL bit ;USB ENDPOINT 0 CSR ;Set serviced_out_pkt_rdy & data_end, write "1" back to FORCE_STALL bit ;If the device is in address state, update address before STATUS completion ADDR_END endif end of the set_address routine Note: wValue_lo = assigned address from the host in SET-ADDRESS request. Rev. H Sep 18, 2003 Page 138 of 139 Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Keep safety first in your circuit designs! 1. Renesas Technology Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials. 1. 2. 3. 4. 5. 6. 7. 8. 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If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. Please contact Renesas Technology Corporation for further details on these materials or the products contained therein. http://www.renesas.com Copyright 2003. Renesas Technology Corporation, All rights reserved. Printed in Japan. REVISION HISTORY Rev. M30240 Group Data Sheet Date Description Page G 10/23/2001 H 09/18/2003 Summary First Edition Issued -- Changed to new Renesas format 125 Table 1.38 : Removed reference to Table 2, added XIN and CNVSS to VIH, VIL 126 Table 1.39: Removed Icc typical measurements 125-137 Tables 1.1 to 1.14 numbering changed to Tables 1.39 to 1.52 ( 1 / 1)