REU03B0001-0100Z
Rev. H
Sep 18, 2003
M30240 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Rev. H Sep 18, 2003 Page 1 of 139
1.1 Description
The M30240 group is a 16-bit microcomputer based on the M16C family core technology. They are
single-chip USB peripheral microcontrollers based on the Universal Serial Bus (USB) Version 1.1
speci fication. They are packaged in an 80-p in, molde d plas tic QFP. These single- chip m icroc ontrolle rs
operate using sophisticated instructions featuring a high level of instruction efficiency, making them
capable of executing instructions at high speed. They also feature a built-in multiplier and DMAC,
making them ideal for controlling office communications, industrial equipment, and other high-speed
processing applications.
1.1.1 Features
• CPU .................................................... 16-bit (including a hardware multiplier)
• Number of instructions........................ 91
• Shortest instruction execution time..... 83ns (f(XIN)=12MHz)
• USB Features: .................................... 9 endpoints
FIFO Sizes (endpoints 0-4):32,128, 32, 32, 32
Confo rms to USB V1. 1 Spec if ic ation
• USB Transceiver................................. Conforms to USB V1.1 Specification-Internal Vref
• Frequency Synthesizer ....................... PLL for 48MHz clock
• Memory capacity (mask device):......... ROM (40K, 48K) / RAM (3.0 K)
• Memory capacity (OTP device):.......... PROM (128K) / RAM (5K)
• Supply Voltage.................................... 4.1 to 5.25V (f(XIN)=12MHz)
• Interrupts............................... ....... ....... 21 internal and 4 extern al inte rru pt sourc es,
4 software interrupt sources; 7 levels (including key input interrupt x 16)
• Multifunction timer............................... 5 X 16-bit, w/integrated 20mA (peak) PWM outputs
• General purpose timer ........................ 3 X 16-bit, internal interrupt only
• UART .................................................. 3 X 7/8/9 bits;
Configurable for synchronous or asynchronous mode
• DMAC ................................................. 2 channels (trigger: 19 sources)
• A-D Converter..................................... 10 bits X 8 channels
• CRC calculation circuit........................ 1 circuit (industry standard polynomial)
• Watchdog timer................................... 1 line (15 bit)
• Programmable I/O............................... 63 lines
• High current and LED Drivers............. 5 high current and 8 LED drivers
• Clock-generating circuit ...................... 1 built-in circuit including feedback resistor
• Package:............................................. 80P6N-A (0.8 mm pitch)
1.1.2 Applicati ons
USB peripherals, such as telephones, audio systems, scanners, and digital cameras.
Table of Contents
M30240 Group
Rev. H Sep 18, 2003 Page 2 of 139
1.1.3 Table of Contents
1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Performance outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.2 Operation of Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Central Processing Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Processor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
SFR Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Clock-Generating Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Status Transition Of Internal Clock Φ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Power Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
NMI Interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Key input interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Address Match Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Frequency Synthesizer Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Universal Serial Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
DMAC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Timers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Timer A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Timer B. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
UART0 to UART2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
A-D Converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
CRC Calculation Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Programmable I/O Ports. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
1.3 Usage Precautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Precautions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
1.4 Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
1.5 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Frequency Synthesizer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Attach/Detach Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Low Pass Filter Network. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
USB Transceiver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Programming Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Pin Configuration
M30240 Group
Rev. H Sep 18, 2003 Page 3 of 139
1.1.4 Pin Configuration
Figure 1.1 shows the pin configuration (top view).
Figure 1.1: Pin Configuration (top view)
41
40
24
65
P100/AN0
66
AVss
67
LPF
68
VREF
69
AVcc
70
P87/AD
TRG
71
P86/SOF
72
EXTCAP
73
74
75
76
77
78
79
80
23
2221
20
1918171615
P84/INT1
14
P85/NMI
13
Vcc
121110
XIN
9
Vss
8
XOUT
76
D-
5
D+
4321
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
P107/AN7
P106/AN6
P105/AN5 M30240Mx/EC
RESET
61
P104/AN4
62
P103/AN3
63
P102/AN2
64
P101/AN1
P83/ATTACH
P82/INT0
P81/TA4IN
P80/TA4OUT
P77/TA3IN
P75/TA2IN
P72/CLK2/TA1OUT
P73/CTS2/RTS2/TA1IN
P74/TA2OUT
P76/TA3OUT
P32
P33
P34
P35
P36
P37/CLKOUT
P60/CTS0/RTS0
P61/CLK0
P62/RxD0
P63/TxD0
P64/CTS1/RTS1/CLKS1
P65/CLK1
P66/RxD1
P67/TxD1
P70/TxD2/TA0OUT
P71/RxD2/TA0IN
P03/KI3
P02/KI2
P01/KI1
P00/KI0
P04/KI4
P05/KI5
P06/KI6
P07/KI7
P10/KI8
P11/KI9
P12/KI10
P13/KI11
P14/KI12
P15/KI13
P16/KI14
Vss
P17/KI15
Vcc
P20/LED0
P21/LED1
P22/LED2
P23/LED3
P24/LED4
P25/LED5
P26/LED6
P27/LED7
P30
P31
BYTE
CNVss
Block Diagram
M30240 Group
Rev. H Sep 18, 2003 Page 4 of 139
1.1.5 Block Diagram
Figure 1.2 is a block diagram of the M30240 group.
Figure 1.2: Block diagram of M30240 group
Timer
Timer TA0 (16 bits)
Timer TA1 (16 bits)
Timer TA2 (16 bits)
Timer TA3 (16 bits)
Timer TA4 (16 bits)
Timer TB0 (16 bits)
Timer TB1 (16 bits)
Timer TB2 (16 bits)
Watchdog timer
(1 line)
DMAC
(2 channels)
System clock generator
XIN - XOUT
A-D converter
10 bits x 8 channels
USB function control unit
Frequency Synthesizer
UART/clock synchronous S I/O
(8 bits x 3 channels) Note
CRC arithemetic circuit (CCITT)
(Polynomial: X16+X12+X5+1)
Internal peripheral functions
SB
FLG
PC
Registers Program counter
INTB
Vector table
Stack Pointer
ISP
USP
Multiplier
M16C series 16-bit CPU core
Memory
ROM RAM
Port P0 Port P1 Port P2 Port P3 Port P6 Port P7 Po rt P80~P84,
P86, P87
Port P85Port P10
I/O Ports
8
88 8 8 8 87
Note: One serial I/O can be used for SIM interface
R0H R0L
R0H R0L
R1H R1L
R2
R3
A0
A1
FB
Performance outline
M30240 Group
Rev. H Sep 18, 2003 Page 5 of 139
1.1.6 Performance outline
Table 1.1 is a performance outline of the M30240 group.
Table 1.1: Performance outline of M30240 group
Item Performance
Number of basic instructions 91 instructions
Shor test instruction execution time 83ns (f(XIN) =12MHz)
Memory capacity ROM (See Table 1.2: ROM capacity field)
RAM
I/O port P0 to P3, P6,P7, P8
(except P85), P10 8 bits x 7, 7 bits x 1
Input port P85 1 bit x 1
Multifunction Timer TA0, TA1, TA2, TA3, TA4 16 bits x 5
General purpose Timer TB0, TB1, TB2 16 bits x 3
Serial I/O UART0, UART1, UART2 (UART or clock synchronous) x 3
A-D converter 10 bits x 8 channels
DMAC 2 channels (trigger:19 sources)
CRC calculation circuit CRC-CCITT
Watchdog timer 15 bits x 1 (with prescaler)
Interrupt 21 interna l and 4 external s ources, 4 softwa re sources, 7 lev els
Clock-generating circuit Built-in clock generation circuit (built-in feedback resistor, and
external ceramic or quartz oscillator)
Supply voltage (typical) 4.1 to 5.25V, (f(XIN)=12MHz, without software wait)
Power consumption (typical) 250 mW, Vcc=5.0V, 12MHz
I/O characteristics
I/O withstand voltage 5V
Average output current 5 mA available on ports P0, P1, P3,P6, P71, P73, P75, P77,
P81~P84, P86, P87, P10
10 mA avail able on ports P2, P 70, P72, P74, P76, P80
Operati ng tem pera ture 0 to 70oC
Device configuration CMOS high performance silicon gate
Package 80-pin plastic molded QFP
Performance outline
M30240 Group
Rev. H Sep 18, 2003 Page 6 of 139
Renesas plans to release the following products in the M30240 group:
(1) Support for mask ROM version and one-time PROM version
(2) ROM capacity
(3) Pac kage
• 80P6N-A: Plastic molded QFP (mask ROM version and one-time PROM version)
Figure 1.3 shows the type number, memory size and package for the M30240 group.
Figure 1.3: Type number, memory size, and package
Table 1.2 shows the Package Number, type, ROM and RAM Capacity for M30240 Group.
Table 1.2: M30240 Group
Type ROM Capacity RAM Capacity Package Type Remarks
M30240M5-XXXXFP 40K bytes 3K bytes 80P6N-A Mask ROM Version
M30240M6-XXXXFP 48K bytes 3K bytes 80P6N-A Mask ROM Version
M30240ECFP 128K bytes 5K bytes 8 0P6N-A One-time PROM version
Type No. M 3 0 2 4 0 M 5 - X X X F P
Package type:
FP : Pac kage 80P6N-A
ROM No.
Omitted for b lank one-time PR OM version an d EPROM version
ROM capacity:
1 : 8K bytes 7 : 56K bytes
2 : 16K by tes 8 : 64K by te s
3 : 24K by tes 9 : 80K by te s
4 : 32K bytes A : 96K bytes
5 : 40K bytes C : 128K by tes
6 : 48K bytes
Memory type:
M : Mask ROM version
E : EPROM or on e-time versio n
Part type:
Specifies part variations with M 30240 gr oup
M30240 Group
M16C Family
Pin Description
M30240 Group
Rev. H Sep 18, 2003 Page 7 of 139
1.1.7 Pin Description
Table 1.3 shows the M30240 pin description.
Table 1.3: Figure pin description
Pin # Name I/O Descrip tion
1P87I/O CMOS I/O port . This pin als o functions as an external trigg er for A-D conversion.
2P86I/O CMO S I/O port. This pin also fun ctions as the start of frame (SO F) pulse for the
USB modul e.
3P85/(NMI)I CMOS input port. This pin also functions as a non-maskable external interrupt.
4,5 P84 ~ P83I/O CMOS I/O port. P84 also functions as external interrupt 1 and P83 is used to
enable the stealth detach function for the USB transceiver.
6EXTCAP _
An external capacitor (Ext. Cap) pin. When the USB transceiver voltage
converter is used, a 2.2 µF and a 0 .1 µF cap aci tor shou ld conne ct be tween this
pin and Vss to ensure proper operation of the USB line driver. This option is
enabled by setting bit 4 of the USB control register (000C16) to a “1”.
7 BYTE I Connect this pin to Vss
8CNVss I Connect this pin to Vss
9USB D+I/O USB D+ volt age line inter face, a series resi stor of 27 to 33 Ω i s connected t o this
pin.
10 USB D-I/O USB D- volt age line int erface, a seri es resist or of 27 to 33 Ω is connected to thi s
pin.
11 RESET I A “L” on this input resets the microcomputer.
12 XOUT OSee Xin
13 Vss -Ground: Vss = 0V
14 Xin I
Input and output signals to and from the internal clock generation circuit.
Conne ct a c erami c reso nator o r qu artz crys tal bet ween Xin and Xou t pins to se t
the oscillation frequency. If an external clock is used, connect the clock source
to the Xin pin and leave the Xout pin op en.
15 Vcc -Power: Vcc = 4.1~ 5.25V
16 P82I/O CMOS I/O port. This pin also functions as external interrupt 0.
17-18 P81 ~ P80I/O CMOS I/O port. Pins in this port also function as TimerA4 input and output as
selected by software.
19-22 P77 ~ P74I/O CMOS I/O port. Pins in this port also function as timer pins.
P77 and P76 can function as TimerA3 input and output as selected by software.
P75 and P7 4 c an func tion as T ime rA2 input and o utput as sel ected by softwa re.
23-26 P73 ~ P70I/O
CMOS I/O port. Pins in th is p ort al so function as U ART2 CTS, R TS, CLK , RXD,
and TXD as selected by software .
P73 and P7 2 c an func tion as T ime rA1 input and o utput as sel ected by softwa re.
P71 and P7 0 c an func tion as T ime rA0 input and o utput as sel ected by softwa re.
27-30 P67 ~ P64I/O C MOS I/ O port. Pi ns i n this port also funct ion a s UA RT1 CTS, R TS, CLK, Serial
Clock, RXD, and TXD as selected by software. TXD(OE~) and RTS(SUSPEND)
in addition to D+ and D- can be used to run the device in USB bypass mode.
31-34 P63 ~ P60I/O CMOS I / O p ort. Pins in this p ort al so function as UA RT0 CTS, R TS, CLK, RXD,
and TXD as selected by software .
35-42 P37 ~ P30I/O CMOS I/O port.
Pin Description
M30240 Group
Rev. H Sep 18, 2003 Page 8 of 139
43-50 P27/LED7
~ P20/LED0 I/O CMOS I/O port. These pins are capable of driving up to 20mA (peak) for LEDs.
51 Vcc IPower: Vcc = 4.1~ 5.25V
52 P17/KI15 I/O CMOS I/ O port . This port can a lso f unctio n as the k ey-on wakeup inte rrupt KI15.
53 Vss IGround: Vss = 0V
54-60 P16/KI14~ P10/KI8I/O CMOS I/O port. This port ca n also function as th e key-on wake up interrupt s (KI8
~ KI14).
61-68 P07/KI7~ P00/KI0I/O CMO S I/O port. This port ca n also function as the key-on wake up interrupt s (KI0
~ KI7).
69-76 P107 ~ P100I/O CMOS I/O port. These pins also function as Analog inputs 7-0 for A-D
conversion
77 AVss I This pin is a power supply input for the AD converter. (Connect to Vss)
78 LPF O Loop filter for the frequency synthesizer.
79 VREF I This pin is the reference voltage input for the A-D converter.
80 AVcc I This pin is a power supply input for the AD converter. (Connect to Vcc)
Pin # Name I/O Descrip tion
Overview
M30240 Group
Rev. H Sep 18, 2003 Page 9 of 139
1.1.8 Overview
The M30240 group is a single chip PC peripheral microcontroller based on the Universal Serial Bus
(USB) V ersion 1.1 specification. This device provides interface between a USB-equipped host computer
and PC peripherals such as telephones, audio systems, and digital cameras. The M30240 block
diagram is shown in Figure 1.4.
The USB function control unit of the M30240 group can support all four data transfer types listed in the
USB specification: Isochronous, Interrupt, Bulk, and Control. Each transfer type is used for controlling a
different se t of PC p eriph eral s. Iso chronou s tran sfer s provi de gua rantee d bus a ccess, a constant da ta
rate, and error tol eran ce fo r d evi ces suc h as co mputer-t elepho ne i nteg ra tio n ( CT I) and au dio systems .
Interrupt transfers are designed to support human input devices (HID) that communicate small amounts
of data infrequently. Bulk transfers are necessary for devices such as digital cameras and scanners that
communicate large amounts of data to the PC as bus bandwidth becomes free. Finally , control transfers
are s upported and ar e useful for bursty, h ost-initiated ty pe communica tion where bus managem ent is
the primary concern.
Figure 1.4: M30240 block diagram
frequency
RAM
DMAC x 2
M16C CPU
UART x 3
Timers x 8
Watchdog
CRC Circuit
I/O Ports (P0~P 3 , P6 ~ P8, P1 0)
FIFOs
USB Function Control Unit
Transceiver
D+
D-
(Normal MCU or DMA Transfer)
1 - 12MHz
48 MHz
Φ
synthesizer
LED Drivers
(X 8)
A-D
Converter
Timer
ROM
Central Processing Unit
M30240 Group
Rev. H Sep 18, 2003 Page 10 of 139
1.2 Operation of Functional Blocks
The M30240 group accommodates certain units in a single chip. These units include ROM and RAM to
store instructions and data, and the central processing unit (CPU) to execute arithmetic/logic operations.
Also inclu ded are pe riph eral u ni ts such as U SB, ti mers, se rial I/O, DM AC , CRC c alcu lat ion circuit, A-D
converter, and I/O ports.
The following explains each unit.
1.2.1 Central Processing Unit
The CPU has a total of 13 registers shown in Figure 1.5. Seven of these registers (R0, R1, R2, R3, A0,
A1, and FB) come in two sets; therefore, these have two register banks.
Figure 1.5: Central processing unit register
1.2.1.1 Data registers
Data registers (R0, R1, R2, and R3) are configured with 16 bits, a nd are used primarily for transfer
and arithmetic/logic operations.
Registers R0 and R1 each can be used as separate 8-bit data registers, high-order bits as (R0H/R1H),
and low-order bits as (R0L/R1L). In some instructions, registers R2 and R0, as well as R3 and R1, can
be used as 32-bit data registers (R2R0/R3R1).
1.2.1.2 Address registers (A0 and A1)
Address register s (A0 and A1) are co nfigured wi th 16 bits, and have func tions equ ivale nt to thos e of
data registers. These registers can also be used for address register indirect addressing and address
register relative addressing.
In some instructions, registers A1 and A0 can be combined for use as a 32-bit address register (A1A0).
HL
b15 b8 b7 b0
R0(Note)
HL
b15 b8 b7 b0
R1(Note)
R2(Note)
b15 b0
R3(Note)
b15 b0
A0(Note)
b15 b0
A1(Note)
b15 b0
FB(Note)
b15 b0
Data
registers
Address
registers
Frame base
registers
b15 b0
b15 b0
b15 b0
b15 b0
b0 b19
b0
b19
HL
Program counter
Interrupt table
register
User stack pointer
Interrupt stack
pointer
Static base
register
Flag register
PC
INTB
USP
ISP
SB
FLG
Note: These registers consist of two register banks.
CDZSBOIU
IPL
Central Processing Unit
M30240 Group
Rev. H Sep 18, 2003 Page 11 of 139
1.2.1.3 Frame base register (FB)
Frame base register (FB) is configured with 16 bits, and is used for FB relative addressing.
1.2.1.4 Program counter (PC)
Program counter (PC) is configured with 20 bits, indicating the address of an instruction to be execut-
ed.
1.2.1.5 Interrupt table register (INTB)
Interrupt table register (INTB) is configured with 20 bits, indicating the start address of an interrupt vec-
tor table. INTB can be used as separate registers of four high-order bits and 16 low-order bits.
1.2.1.6 Stack pointer (USP/ISP)
Stack pointer comes in two types: user stack pointer (USP) and interrupt stack pointer (ISP), each con-
figured with 16 bits.
Your desired type of stack pointer (USP or ISP) can be selected by a stack pointer select flag (U flag).
This flag is located at the position of bit 7 in the flag register (FLG).
1.2.1.7 Static base register (SB)
Static base register (SB) is configured with 16 bits, and is used for SB relative addressing.
1.2.1.8 Flag regist er (FLG)
Flag register (FLG) is configured with 11 bits, each bit is used as a flag. Figure 1.6 shows the flag reg-
ister (FLG). The following explains the function of each flag:
1.2.1.8.1 Bit 0: Carry flag (C flag)
This flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit.
1.2.1.8.2 Bit 1: Debug flag (D flag)
This flag enables a single-step interrupt.
When this fla g is “1”, a single-step int erru pt is ge nera ted after instruction e xe cu tion . Th is flag is cl eare d to “0”
when the interrupt is acknowledged.
1.2.1.8.3 Bit 2: Zero flag (Z flag)
This flag is set to “1” when an arithmetic operation resulted in 0; otherwise, cleared to “0”.
1.2.1.8.4 Bit 3: Sign flag (S flag)
This flag is set to “1” when an arithmetic operation resulted in a negative value; otherwise, cleared to “0”.
1.2.1.8.5 Bit 4: Register bank select flag (B flag)
This fla g choo ses a regis ter bank . Re gister bank 0 is se lecte d whe n this flag i s “0”; re gister bank 1 is se lecte d
when this flag is “1”.
1.2.1.8.6 Bit 5: Overflow flag (O flag)
This flag is set to “1” when an arithmetic operation resulted in overflow; otherwise, cleared to “0”.
1.2.1.8.7 Bit 6: Interrupt enable flag (I flag)
This flag enables a maskable interrupt.
An interrupt is disabled when this flag is “0”, and is enabled when this flag is “1”. This flag is cleared to “0”
when the interrupt is acknowledged.
1.2.1.8.8 Bit 7: Stack pointer select flag (U flag)
Interrupt stack pointer (ISP) is selected when this flag is “0”; user stack pointer (USP) is selected when this
flag is “1”.
This flag is cleared to “0” when a hardware interrupt is acknowledged or an INT instruction of s oftware inter-
rupts 0 to 31 is executed.
Central Processing Unit
M30240 Group
Rev. H Sep 18, 2003 Page 12 of 139
1.2.1.8.9 Bits 8 to 11: Reserved area
1.2.1.8.10 Bits 12 to 14: Processor interrupt priority level (IPL)
Processor interrupt priority level (IPL) is configured with three bits, for specification of up to eight processor
interrupt priority levels from level 0 to level 7.
If a requested inte rrupt has pri orit y gre ater th an the proc ess or interrupt priority level (IPL), the interru pt is en-
abled.
1.2.1.8.11 Bit 15: Reserved area
The C, Z, S, and O flags are changed when instructions are executed. See the M16C software manual
for details.
Figure 1.6: Flag register (FLG)
Carry flag
Debug flag
Zero flag
Sign flag
Register bank select flag
Overflow flag
Interrupt enable flag
Stack pointer select flag
Reserved area
Processor interrupt priori
t
Flag register (FLG)
CDZSBOIU
IPL
b0b15
Reserved area
Processor Mode
M30240 Group
Rev. H Sep 18, 2003 Page 13 of 139
1.2.2 Processor Mode
Figure 1.7 shows the processor mode registers 0 and 1.
Figure 1.7: Processor mode registers 0 and 1
Processor mode register 0 (Note
)
Symbol Address When reset
PM0 000416 0016 (Note)
Bit name FunctionBit symbol
WR
b7 b6 b5 b4 b3 b2 b1 b0
Reserved bit
Note : Set bit 1 of the protect register (address 000A 16) to “1” when writing new
values to this register.
Processor mode register 1 (Note)
Symbol Address When reset
PM1 000516 00XXXXX02
Bit name FunctionBit symbol
WR
b7 b6 b5 b4 b3 b2 b1 b0
Nothing is assigned.
These bits can neither be set nor reset. When read, their contents are
indeterminate.
Reserved bit Must always be set to “0”
0
Note : Set bit 1 of the protect register (address 000A 16) to “1” when writing new values
to this register.
PM17 Wait bit 0 : No wait state
1 : Wait state inserted
Must always be set to "0"
PM03 Software reset bit The device is reset when this bit is set
to “1”. The value of this bit is “0” when
read.
Nothing is assigned. These bits can neither be set nor reset. When read,
their contents are indeterminate.
0
0000
0
Memory
M30240 Group
Rev. H Sep 18, 2003 Page 14 of 139
1.2.3 Memory
Figure 1.8: Memory Map
Figure 1.8 is a memory map of the M30240 group. The address space extends the 1M bytes from
addres s 0000016 to FFFFF16. Addres ses abov e yyyyy16 are ROM. For example, in the M30240ECFP,
there is 128K bytes of internal ROM from E000016 to FFFFF16. The special page vector table is mapped
from FFE0016 to FFFDB16. If the starting addresses of subroutines or the destination addresses of jumps
are stored here, subroutine call instructions and jump instructions can be used as two-byte instructions,
reducing the number of program steps.
The vector table for fixed interrupts such as the reset and NMI are mapped from FFFDC16 to FFFFF16.
The starting addresses of the interrupt routines are stored here. The address of the vector table for
software interrupts can be set as desired using the internal register (INTB). See Section 2.12 on
interrupts for further details.
Addresses below xxxxx16 are RAM. For example, in M30240ECFP, 5K bytes of internal RAM are
mapped to the space from 0040016 to 017FF16. In addition to storing data, the RAM also stores the stack
used when calling subroutines and when interrupts are generated.The SFR area is mapped to 0000016
to 003FF16. This area accommodates control registers for peripheral devices such as I/O ports, A-D
converter, serial I/O, and timers. Section 2.4 describes the SFR area for peripheral unit control registers.
Any part of the SFR area that is unoccupied is reserved and cannot be used for other purposes.
yyyyy16
Overflow
BRK instruction
Address match
Single step
Watchdog timer
Reset
0000016
0040016
XXXXX16
ROM
unused
SFR
RAM
FFE0016
FFFDC16
FFFFF16
Undefined instruction
Special page
vector table
DBC
NMI
Type Address xxxxx16 Address yyyyy 16
M30240M5
00FFF16
F600016
M30240M6 00FFF16 F400016
M30240ECFP 017FF16 E000016
SFR Map
M30240 Group
Rev. H Sep 18, 2003 Page 15 of 139
1.2.4 SFR Map
The SFR tables show the peripheral control registers, their addresses, acronyms, and values after reset.
Address Register name Acronym Value after reset Figure number
000016
000116
000216
000316
000416 Processor mode register 0 PM0 0016 Figure 1.7
000516 Processor mode register 1 PM1 0 0 0 Figure 1.7
000616 System clock control register 0 CM0 4816 Figure 1.13
000716 System clock control register 1 CM1 2016 Figure 1.13
000816
000916 Address match interrupt enable register AIER 0 0 Figure 1.16
000A16 Protect re gister PRCR 0 0 0 Figure 1.14
000B16
000C16 US B control reg ister USBC 0016 Figure 1.31
000D16
000E16 Watchdog timer start register WDTS Figure 1.22
000F16 Watchdog timer control register WDC 0 0 0 ? ? ? ? ? Figure 1.22
001016 Address match interrupt register 0 RMAD0 0016 Figure 1.16
001116 0016
001216 0000
001316
001416 Address match interrupt register 1 RMAD1 0016 Figure 1.16
001516 0016
001616 0000
001716
001816
001916
001A16
001B16
001C16
001D16
001E16 Reserved
001F16 U SB attach / detach regist er USBAD 0016 Figure 1.30
002016 D MA0 sou rce poin t er SAR0 Figure 1.56
002116
002216
002316
002416 D MA0 destinat ion poin ter DAR0 Figure 1.56
002516
002616
002716
002816 DMA 0 tra nsfe r counter TCR0 Figure 1.56
002916
002A16
002B16
002C16 DMA 0 con t ro l regi ster DM0CON 0 0 0 0 0 ? 0 0 Figure 1.55
002D16
002E16
002F16
003016 D MA1 sou rce poin t er SAR1 Figure 1.56
003116
003216
003316
003416 D MA1 destinat ion poin ter DAR1 Figure 1.56
003516
003616
003716
SFR Map
M30240 Group
Rev. H Sep 18, 2003 Page 16 of 139
003816 DMA 1 tra nsfe r counter TCR1 Figure 1.56
003916
003A16
003B16
003C16 DMA 1 con t ro l regi ster DM1CON 0 0 0 0 0 ? 0 0 Figure 1.55
003D16
003E16
003F16
004016
004116
004216
004316
004416 U SB Suspe nd i nte rru pt cont rol reg ister SUSPIC ? 0 0 0 Figure 1.16
004516
004616 USB Resume interrupt control register RSMIC ? 0 0 0 Figure 1.16
004716 U SB SOF in ter ru pt contr ol register SOFIC 0 0 ? 0 0 0 Figure 1.16
004816
004916
004A16 Bus collision detection interrupt control register BCNIC ? 0 0 0 Figure 1.16
004B16 DMA0 interrupt control register DM0IC ? 0 0 0 Figure 1.16
004C16 DMA1 interrupt control register DM1IC ? 0 0 0 Figure 1.16
004D16 Key input interrupt control register KUPIC ? 0 0 0 Figure 1.16
004E16 A-D conversion interrupt control register ADIC ? 0 0 0 Figure 1.16
004F16 UART2 transmit interrupt control register S2TIC ? 0 0 0 Figure 1.16
005016 UART2 receive interrupt control register S2RIC ? 0 0 0 Figure 1.16
005116 UART0 transmit interrupt control register S0TIC ? 0 0 0 Figure 1.16
005216 UART0 receive interrupt control register S0RIC ? 0 0 0 Figure 1.16
005316 UART1 transmit interrupt control register S1TIC ? 0 0 0 Figure 1.16
005416 UART1 receive interrupt control register S1RIC ? 0 0 0 Figure 1.16
005516 Timer A0 interrupt control register TA0IC ? 0 0 0 Figure 1.16
005616 Timer A1 interrupt control register TA1IC ? 0 0 0 Figure 1.16
005716 Timer A2 interrupt control register TA2IC ? 0 0 0 Figure 1.16
005816 Timer A3 interrupt control register TA3IC ? 0 0 0 Figure 1.16
005916 Timer A4 interrupt control register TA4IC ? 0 0 0 Figure 1.16
005A16 Timer B0 interrupt control register TB0IC ? 0 0 0 Figure 1.16
005B16 Timer B1 interrupt control register TB1IC ? 0 0 0 Figure 1.16
005C16 USB Reset interrupt control register RSTIC ? 0 0 0 Figure 1.16
005D16 INT0 interrupt control register INT0IC 0 0 ? 0 0 0 Figure 1.16
005E16 INT1 interrupt control register INT1IC 0 0 ? 0 0 0 Figure 1.16
005F16 U SB fun ction inte rru pt cont rol reg i ster USBFIC ? 0 0 0 Figure 1.16
030016 USB function address register USBA 0016 Figure 1.32
030116 USB power management register USBPM 0016 Figure 1.33
030216 USB interrupt status register 1 USBIS1 0016 Figure 1.34
030316 USB interrupt status register 2 USBIS2 0016 Figure 1.35
030416 USB interrupt enable register 1 USBIE1 FF16 Figure 1.36
030516 USB interrupt enable register 2 USBIE2 3316 Figure 1.37
030616 U SB fra me num be r low registe r USBSOFL 0016 Figure 1.38
030716 U SB fra me num be r high register USBSOFH 0016 Figure 1.39
030816 USB ISO control register USBISOC 0016 Figure 1.40
030916 U SB DMA0 R equ est reg ister USBSAR0 0016 Figure 1.41
030A16 US B DMA1 Requ est reg i ster USBSAR1 0016 Figure 1.42
030B16 US B Endp oi nt ena ble USBEPEN FF16 Figure 1.43
030C16
030D16
030E16
030F16
031016 U S B rese rve d
031116 U SB Endp oi nt 0 contr ol/statu s register EP0CS 0016 Figure 1.44
031216 U S B rese rve d
031316 USB Endpoint 0 max packet size register EP0MP 0816 Figure 1.45
Address Register name Acronym Value after reset Figure number
SFR Map
M30240 Group
Rev. H Sep 18, 2003 Page 17 of 139
031416 U S B rese rve d
031516 U SB En dp oint 0 OU T writ e coun t EP0WC 0016 Figure 1.46
031616 U S B rese rve d
031716 U S B rese rve d
031816 U S B rese rve d
031916 U SB Endp oi nt 1 IN contro l/stat us regis ter EP1ICS 0016 Figure 1.47
031A16 USB Endpoint 1 OUT control/status register EP1OCS 0016 Figure 1.48
031B16 USB Endp oint 1 IN max packet size register EP1IMP 0016 Figure 1.49
031C16 US B Endp oint 1 OUT max packet size regist er EP1OMP 0016 Figure 1.50
031D16 US B Endp oint 1 O UT wri te coun t EP1WC 0016 Figure 1.51
031E16 US B rese rv e d
031F16 U SB rese rv e d
032016 U S B rese rve d
032116 USB Endp oint 2 IN cont ro l/status reg is ter EP2ICS 0016 Figure 1.47
032216 USB Endpoint 2 OUT control/status register EP2OCS 0016 Figure 1.48
032316 US B Endpoint 2 IN max packet size register EP2IMP 0016 Figure 1.49
032416 U SB Endp oint 2 O UT max packet size regist er EP2OMP 0016 Figure 1.50
032516 U SB En dp oint 2 OU T writ e coun t EP2WC 0016 Figure 1.51
032616 U S B rese rve d
032716 U S B rese rve d
032816 U S B rese rve d
032916 U SB Endp oi nt 3 IN contro l/stat us regis ter EP3ICS 0016 Figure 1.47
032A16 USB Endpoint 3 OUT control/status register EP3OCS 0016 Figure 1.48
032B16 USB Endp oint 3 IN max packet size register EP3IMP 0016 Figure 1.49
032C16 US B Endp oint 3 OUT max packet size regist er EP3OMP 0016 Figure 1.50
032D16 US B Endp oint 3 O UT wri te coun t EP3WC 0016 Figure 1.51
032E16 US B rese rv e d 0016
032F16 U SB rese rv e d
033016 U S B rese rve d
033116 USB Endp oint 4 IN cont ro l/status reg is ter EP4ICS 0016 Figure 1.47
033216 USB Endpoint 4 OUT control/status register EP4OCS 0016 Figure 1.48
033316 US B Endpoint 4 IN max packet size register EP4IMP 0016 Figure 1.49
033416 U SB Endp oint 4 O UT max packet size regist er EP4OMP 0016 Figure 1.50
033516 U SB En dp oint 4 OU T writ e coun t EP4WC 0016 Figure 1.51
033616 U S B rese rve d
033716 U S B rese rve d
033816 U SB Endpoint 0 FIFO EP0 Figure 1.52
033916 U SB Endpoint 1 FIFO EP1 Figure 1.52
033A16 US B Endp oi nt 2 FIFO EP2 Figure 1.52
033B16 US B Endp oi nt 3 FIFO EP3 Figure 1.52
033C16 US B Endp oint 4 FIF O EP4 Figure 1.52
033D16 Reserved
033E16 Reserved
033F16 Reserved
034016
034116
034216
034316
034416
034516
034616
034716
034816
034916
034A16
034B16
034C16
034D16
034E16
034F16
035016
Address Register name Acronym Value after reset Figure number
SFR Map
M30240 Group
Rev. H Sep 18, 2003 Page 18 of 139
035116
035216
035316
035416
035516
035616
035716
035816
035916
035A16
035B16
035C16
035D16
035E16
035F16
037016
037116
037216
037316
037416
037516
037616
037716 Reserved
037816 UART2 transmit / receive mode register U2MR 0016 Figure 1.77
037916 UART2 bit rate generator U2BRG Figure 1.76
037A16 UART2 transmit buffer register U2TB Figure 1.76
037B16
037C16 UART2 transmit / receive control register 0 U2C0 0816 Figure 1.78
037D16 UART2 transmit / receive control register 1 U2C1 0216 Figure 1.79
037E16 UA RT2 recei ve buffer reg i ster U2RB Figure 1.76
037F16
038016 TABSR 0016 Figure 1.61
038116 Count start flag
038216 Reserved ONSF 0 0 0 0 0 0 0 Figure 1.62
038316 One-shot start flag TRGSR 0016 Figure 1.62
038416 Trigger select register UDF 0016 Figure 1.61
038516 U p/d own flag
038616 Tim er A0 TA0 Figure 1.61
038716
038816 Tim er A1 TA1 Figure 1.61
038916
038A16 Time r A 2 TA2 Figure 1.61
038B16
038C16 Timer A3 TA3 Figure 1.61
038D16
038E16 Time r A 4 TA4 Figure 1.61
038F16
039016 Tim er B0 TB0 Figure 1.72
039116
039216 Tim er B1 TB1 Figure 1.72
039316
039416 Tim er B2 TB2 Figure 1.72
039516
039616 Timer A0 mode register TA0MR 0016
Figure 1.63
Figure 1.64
Figure 1.66
Figure 1.68
039716 Timer A1 mode register TA1MR 0016
Figure 1.63
Figure 1.64
Figure 1.66
Figure 1.68
Address Register name Acronym Value after reset Figure number
SFR Map
M30240 Group
Rev. H Sep 18, 2003 Page 19 of 139
039816 Timer A2 mode register TA2MR 0016
Figure 1.63
Figure 1.64
Figure 1.65
Figure 1.66
Figure 1.68
039916 Timer A3 mode register TA3MR 0016
Figure 1.63
Figure 1.66
Figure 1.65
Figure 1.68
039A16 Timer A4 mode register TA4MR 0016
Figure 1.63
Figure 1.65
Figure 1.66
Figure 1.68
039B16 Timer B0 mode register TB0MR 0 0 ? 0 0 0 0 Figure 1.71
039C16 Timer B1 mode register TB1MR 0 0 ? 0 0 0 0 Figure 1.71
039D16 Timer B2 mode register TB2MR 0 0 ? 0 0 0 0 Figure 1.71
039E16
039F16
03A016 UART0 transmit / receive mode register U0MR 0016 Figure 1.77
03A116 UART0 bit rate generator U0BRG Figure 1.76
03A216 UART0 transmit buffer register U0TB Figure 1.76
03A316
03A416 UART0 transmit / receive control register 0 U0C0 0816 Figure 1.78
03A516 UART0 transmit / receive control register 1 U0C1 0216 Figure 1.79
03A616 UA RT0 recei ve buffer reg i ster U0RB Figure 1.76
03A716
03A816 UART1 transmit / receive mode register U1MR 0016 Figure 1.77
03A916 UART1 bit rate generator U1BRG Figure 1.76
03AA16 UART1 transmit buffer register U1TB Figure 1.76
03AB16
03AC16 UART1 transmit / receive control register 0 U1C0 0816 Figure 1.77
03AD16 UART1 transmit / receive control register 1 U1C1 0216 Figure 1.79
03AE16 U A RT1 receiv e buffer reg ister U1RB Figur e 1.76
03AF16
03B016 UART transmit / receive control register 2 UCON 0 0 0 0 0 0 0 Figure 1.80
03B116
03B216
03B316
03B416
03B516
03B616
03B716
03B816 DMA0 Request cause select register DM0SL 0016 Figure 1.54
03B916
03BA16 DMA1 Request cause select register DM1SL 0016 Figure 1.54
03BB16
03BC16 CRC data register CRCD Figure 1.105
03BD16
03BE16 CRC input register CRCIN Figure 1.105
03BF16
03C016 A-D register 0 AD0 Figure 1.98
03C116
03C216 A-D register 1 AD1 Figure 1.98
03C316
03C416 A-D register 2 AD2 Figure 1.98
03C516
03C616 A-D register 3 AD3 Figure 1.98
03C716
03C816 A-D register 4 AD4 Figure 1.98
03C916
03CA16 A-D register 5 AD5 Figure 1.98
03CB16
Address Register name Acronym Value after reset Figure number
SFR Map
M30240 Group
Rev. H Sep 18, 2003 Page 20 of 139
03CC16 A-D register 6 AD6 Figure 1.98
03CD16
03CE16 A-D register 7 AD7 Figure 1.98
03CF16
03D016
03D116
03D216
03D316
03D416 A-D control register 2 ADCON2 0 Figure 1.98
03D516
03D616 A-D control register 0 ADCON0 0 0 0 0 0 ? ? ? Figure 1.97
03D716 A-D control register 1 ADCON1 0016 Figure 1.97
03D816
03D916
03DA16
03DB16 Frequency synthesizer clock control FSCCR 0016 Figure 1.28
03DC16 Frequency synthesizer control FSC 6016 Figure 1.27
03DD16 Frequency synthesizer multiplier control FSM FF16 Figure 1.25
03DE16 Frequency synthesizer prescaler control FSP FF16 Figure 1.24
03DF16 Frequency synthesizer divider FSD FF16 Figure 1.26
03E016 Port P0 P0 Figure 1.110
03E116 Port P1 P1 Figure 1.110
03E216 Port P0 direction register PD0 0016 Figure 1.109
03E316 Port P1 direction register PD1 0016 Figure 1.109
03E416 Port P2 P2 Figure 1.110
03E516 Port P3 P3 Figure 1.110
03E616 Port P2 direction register PD2 0016 Figure 1.109
03E716 Port P3 direction register PD3 0016 Figure 1.109
03E816
03E916
03EA16
03EB16
03EC16 Port P6 P6 Figure 1.110
03ED16 Port P7 P7 Figure 1.110
03EE16 Port P6 direction register PD6 0016 Figure 1.109
03EF16 Port P7 direction register PD7 0016 Figure 1.109
03F016 Port P8 P8 Figure 1 .110
03F116
03F216 Port P8 direction register PD8 0 0 0 0 0 0 0 Figure 1.109
03F316
03F416 Port P10 P10 Figur e 1.110
03F516
03F616 Port P10 direction register PD10 0016 Figure 1.109
03F716
03F816
03F916
03FA16 P2 drive capacity P2DR 0016 Figure 1.112
03FB16 Timer A Output Drive Capaci ty TADR 0016 Figure 1.112
03FC16 Pull-up control register 0 PUR0 0016 Figu re 1.111
03FD16 Pull-up control register 1 PUR1 0016 Figu re 1.111
03FE16
03FF16
Address Register name Acronym Value after reset Figure number
Reset
M30240 Group
Rev. H Sep 18, 2003 Page 21 of 139
1.2.5 Reset
There are two types of resets: hardware and software. In both case s, operation is the same after the
reset.
1.2.5.1 Hardware reset
When the supply voltage is within the range where operation is guaranteed, a reset is effected by hold-
ing the r eset pin le vel “ L” (0. 2Vcc max.) for at l east 20 f(X IN) cyc les. When the re set pi n level is the n
retur ned to the “H” level while main clock is stable, the reset status is cancelled and pr ogram exec ution
resumes from the address in the reset vector table.
Figure 1.9 shows an example of a reset circuit. Figure 1.10 shows the reset sequence.
.
Figure 1.9: Reset circuit
Figure 1.10: Reset sequence
When the RESET pin level = “L”, all ports change to input mode (floating.) Table 1.4 shows the status
of the other pins while the RESET pin level is “L”.
Table 1.4: Pin status when RESET pin level is “L”
Pin name Status
P0 Input port (floating)
P1 Input port (floating)
P2, P3 Input port (floating)
P6, P7, P80 to P8 4, P86, P87, P1 0 Input port (floating)
RESET V
CC
0.8V
RESET
V
CC
0V
0V
5V
5V
4.0V
Example when V
CC
= 5V
Address
Content of reset vector
Internal clock Φ
24 cycles
FFFFE
16
X
IN
RESET
FFFFC
16
At least 20 cycles are needed
Internal clock
Φ
Clock-Generating Circuit
M30240 Group
Rev. H Sep 18, 2003 Page 22 of 139
1.2.5.2 Software Reset
Writing a “ 1” to bit 3 of the pr ocessor mode register 0 ( address 000 416) appli es a (software) reset to
the microcomputer. A software reset has almost the same effect as a hardware reset with the following
exceptions:
The contents of internal RAM are preserved
USB registers (030016 to 033C16), USB attach/detach register (001F16), USB control register
(000C16), and Frequency synthesizer related registers (03DB16-03DF16) v alues are preserved.
1.2.6 Clock-Generating Circuit
The clo ck-generatin g circ uit contains one oscill ator circuit that supp lies the operati ng clock source s to
the CPU and internal peripheral units. Table 1.5 shows the main clock generating circuits.
Table 1.5: Main clock-generating circuits
Figure 1.11 shows some examples of the main clock circuit, one using an oscillato r connected to the
circuit, and the other one using an externally derived clock for input. Circuit constants in Figure 1.1 1 vary
with each oscillator used. Use circuit constant values recommended by the oscillator manufacturer.
Figure 1.11: Examples of clock source
1.2.6.1 Clock Control
Figure 1.12 shows the block diagram of the clock-generating circuit.
Functions Main clock-generating circuit
Use of clock • CPU’s operating clock source
• Internal peripheral units’ operating clock source
Usable oscillator Ceramic or crystal oscillator
Pins to connect oscillator Xin, Xout
Oscillation stop/restart function Available
Oscillator status immediately after reset Oscillating
Microcomputer
Xin Xout
Externally derived clock
Open
Vcc
Vss
Microcomputer
(Built-in feedback resistor)
Xin Xout
Rd
Cin Cout
(Note)
Note: Insert a damping resistor if required. The resistance will vary depending on the oscillator and the oscillation drive
capacity setting. Use the value recommended by the maker of the oscillator.
When the oscillation drive capacity is set to low, check that oscillation is stable.
(Built-in feedback resistor)
Clock-Generating Circuit
M30240 Group
Rev. H Sep 18, 2003 Page 23 of 139
Figure 1.12: Clock-generating circuit
1.2.6.2 Clocks generated by the clock-generating circuit.
Main clock
The main clock is generated by the main clock oscillation circuit. After a reset, the clock is divided by
8 to the internal clock Φ.
After the o scillatio n of the mai n clock osc illatio n circuit has s tabilize d, the driv e capacit y of the XOUT
pin can be reduced using the XIN - XOUT) drive capacity select bit (bit 5 at address 000716). Reducing
the drive capacity of the XOUT pin reduces the power dissipation. This bit defaults to “1” when shifting
to stop mode and after a reset.
Internal clock Φ
The inte r nal cl oc k Φ is the cloc k t hat d ri ves t he CP U, an d i s ei the r t he m ain cl oc k o r is d er ived by di-
viding the main cloc k by 2, 4, 8, or 16. The inter nal clock Φ is derived by dividing the main clock by 8
after a reset.
When shifting to stop mode, the main clock division select bit (bit 6 at 000616) is set to “1”.
Peripheral Function clock
• f1, f8, f32
The clock for the peripheral devices is derived from the main clock or by dividing it by 8 or 32. The
peripheral function clock is stopped by stopping the main clock or by setting the WAIT peripheral func-
tion clock stop bit (bit 2 at 000616) to “1” and then executing a WAIT instruction.
CM0i : Bit i at address 0006
16
CM1i : Bit i at address 0007
16
FSCCRi: Bit i at address 03DB
16
WAIT instruction
CM02
QS
R
NMI
Interrupt request
level judgment
output
RESET
Software reset
f
AD
Divider
ad
1/2 1/2 1/2 1/2
CM06=0
CM17,CM16=00
CM06=0
CM17,CM16=01
CM06=0
CM17,CM16=10
CM06=1
CM06=0
CM17,CM16=11
d
a
Details of divider
c
b
b
1/2
c
f
1
f
32
SIO2
f
8
SIO2
f
1
SIO2
f
8
f
32
φ
X
OUT
Main clock
CM10 “1”
Write signal QS
R
X
IN
Frequency
Synthesizer
Circuit
f
usb (48MHz)
FSCCR0=1
FSCCR0=0
BCLK
fsyn
Clock-Generating Circuit
M30240 Group
Rev. H Sep 18, 2003 Page 24 of 139
• fAD
This clock has the same frequency as the main clock and is used for A-D conversion.
• fUSB
This is the 4 8mHz c lock t hat is used for USB op eration. Thi s cloc k is generat ed f rom t he mai n clock
by the frequency synthesizer circuit.
1.2.6.3 Clock Output
In single-chip mode, the clock output function select bits (bits 0 and 1 at address 000616) enable f8 or
f32 to be output fr om the P3 7/CL KOUT pin. Whe n the W AIT per iphe ra l fun cti on clo ck stop bit (bi t 2 at
address 000616) is set to “1”, the output of f8 and f32 stops when a WAIT instruction is executed.
Figure 1.13 shows the system clock control registers 0 and 1.
Figure 1.13: System clock control registers 0 and 1
System clock control register 0 (Note 1)
System clock control register 1 (Note 1)
Symbol Address When reset
CM1 000716
20
16
Bit name FunctionBit symbol
b7 b6 b5 b4 b3 b2 b1 b0
CM10 All clock stop control bit 0 : Clock on
1 : All clocks off (stop mode)
CM15 X
IN
-X
OUT
drive capacity
select bit (Note 2)
0 : LOW
1 : HIGH
WR
CM16
CM17
Main clock division select
bit 1 (Note 3)
0 0 : No division mode
0 1 : Division by 2 mode
1 0 : Division by 4 mode
1 1 : Division by 16 mode
b7 b6
00
Reserved bit Always set to “0”
00
Symbol Address When reset
CM0 0006
16
48
16
Bit name FunctionBit symbol
b7 b6 b5 b4 b3 b2 b1 b0
0 0 : I/O port P37
0 1 : Invalid
1 0 : f8 output
1 1 : f32 output
b1 b0
CM01
CM02
CM00 Clock output function
select bit
WAIT peripheral function
clock stop bit
0 : Do not stop f1, f8, f32 in wait mode
1 : Stop f 1, f8, f32 in wait mode
WR
CM06 Main clock division select
bit 0 (Note 2)
0 : CM16 and CM17 valid
1 : Division by 8 mode
Reserved bit Always set to "1"
Reserved bit Always set to "0"
Reserved bit Always set to "0"
Reserved bit Always set to "0"
oo
oo
oo
oo
Note 1: Set bit 0 of the Protect register (address 000A
16
) to "1" before writing to this register.
Note 2: Changes to "1" when shifting to stop mode.
Note 3: Can be selected when bit 6 of the System clock control register 0 (address 0006
16
) is "0".
If "1", division mode is fiixed at "8".
Note 1: Set bit 0 of the Protect register (address 000A
16
) to "1" before writing to this register.
Note 2: Changes to "1" when shifting to stop mode.
Stop Mode
M30240 Group
Rev. H Sep 18, 2003 Page 25 of 139
1.2.7 Stop Mode
Writing “1” to the all-clock stop control bit (bit 0 at address 000716) stops all oscillation and the
microcomputer e nters stop mode. In sto p mode, the content of the internal RAM is retained provided
that VCC rem ain s abov e 2V.
Becaus e the oscilla tion of inte rnal clock Φ, f1 to f32, and fAD stops in stop mode, peripheral functions
such as the A-D converter and watchdog timer do not function. However , timer A operates, provided that
the event counter mode is set to an external pulse, and UART i (i = 0 to 2) functions provided an external
clock is selected. Table 1.6 shows the status of the ports in stop mode.
S top mode is cancelled by a hardware reset or interrupt. If an interrupt is to be used to cancel stop mode,
that interrupt must first have been enabled. The I flag must also be set prior to stopping for an interrupt
to cancel it. After coming out of stop mode, it is recommended that four “NOP” instructions be executed
to clear the instruction queue.
When shifting to stop mode, the main clock division select bit 0 (bit 6 at 000616) is set to “1”.
Table 1.6: Port status during stop mode
1.2.8 Wait Mode
When a W AIT instruction is executed, the internal clock Φ stops and the microcomputer enters the wait
mode . In this mode, osci llati on conti nues but the inter nal cloc k Φand watchd og tim er st op. Writin g “1”
to the WAIT peripheral function clock stop bit and e xecuting a WAIT instruction stops the clock being
supplied to the internal peripheral functions, allowing power dissipation to be reduced. Table 1.7 shows
the status of the ports in wait mode.
W ait mode is cancelled by a hardware reset or interrupt. If an interrupt is used to cancel wait mode, the
microcomputer restarts using as internal clock Φ the clock that had been selected when the WAIT
instruction was executed.
Table 1.7: Port status during wait mode
1.2.9 Status Transition Of Internal Clock Φ
Power dissipation can be reduced and low-voltage operation achieved by changing the count source for
internal clock Φ. Table 1.8 shows the operating modes corres ponding to th e settin gs of system clock
control registers 0 and 1.
After a reset, operation defaults to division by 8 mode. When shifting to stop mode, the main clock
division select bit 0 (bit 6 at address 000616) is set to “1”. The following shows the operational modes of
internal clock
• Division by 2 mode
The main clock is divided by 2 to obtain the internal clock Φ.
Pin Single-chip mode
Port Retains status before stop mode
CLKOUT Retains status before stop mode
Pin Single-chip mode
Port Retains status before stop mode
CLKOUT Does not stop when the WAIT peripheral function clock stop bit is “0”. When the
WAIT peripheral function clock stop bit is “1”, the status immediately prior to
entering WAIT mode is maintained.
Power Control
M30240 Group
Rev. H Sep 18, 2003 Page 26 of 139
• Division by 4 mode
The main clock is divided by 4 to obtain the internal clock Φ.
• Division by 8 mode
The main clock is divided b y 8 to obtain the internal clock Φ. Note that oscillat ion of the main clo ck
must have stabilized before transferring from this mode to another mode.
• Division by 16 mode
The main clock is divided by 16 to obtain the internal clock Φ.
• No-division mode
The m ain clock is used as internal clock .
Table 1.8: Operating modes dictated by settings of system clock control registers 0 and 1
1.2.10 Power Control
The following is a description of the three available power control modes:
1.2.10.1 Normal Operation Mode
• High-speed mode
Divide-by - 1 frequency of the m ain c lo ck b ec ome th e inter nal clo ck Φ. The CPU op erates with the in-
ternal clock selected. Each peripheral function operates according to its assigned clock.
• Medium-speed mode
Divide-by-2, divide-by-4, divide-by-8, or divide-by-16 frequency of the main clock becomes the internal
clock Φ. The CPU operates according to the internal clock selected. Each peripheral function operates
accord ing to i ts assi gned clock.
1.2.10.2 Wait mode
The CPU operation is stopped. The oscillators do not stop.
1.2.10.3 Stop Mode
All osc il lator s sto p. T he CPU and a ll bu il t-in peri pher a l f unc tio ns s top . O f the thr ee mo des lis te d, t his
mode is the most effective in decreasing power consumption.
CM17 CM16 CM06 Operating mode of internal clock
0 1 0 Division by 2 mode
1 0 0 Division by 4 mode
Invalid Invalid 1 Division by 8 mode
1 1 0 Division by 16 mode
0 0 0 No-division mode
Protection
M30240 Group
Rev. H Sep 18, 2003 Page 27 of 139
1.2.11 Protecti on
The pr otection function is provide d so that the valu es in importa nt registers cann ot be change d in the
event that the program runs out of control. Figure 1.14 shows the protect register. The values in the
processor mode register 0 (address 000416), processor mode register 1 (address 000516), system cl ock
control register 0 (address 000616), system clock control register 1 (address 000716) and frequency
synthesizer registers can only be changed when the respective bit in the protect register is set to “1”.
The system clock control registers 0 and 1 write-enable bit (bit 0 at 000A16) and processor mode register
0 and 1 write-enable bit (bit 1 at 000A16) do not automatically return to “0” after a value has been written
to an address. The program must therefore be written to return these bits to “0”.
Figure 1.14: Protect register
Protect register
Symbol Address When reset
PRCR 000A
16 XXXXX0002
Bit nameBit symbol
b7 b6 b5 b4 b3 b2 b1 b0
0 : Write-inhibited
1 : Write-enabled
PRC1
PRC0
Enables writing to processor mode
registers 0 and 1 (addresses 0004 16
and 000516)
Function
0 : Write-inhibited
1 : Write-enabled
Enables writing to system clock
control registers 0 and 1 (addresses
000616 and 000716
) and frequency
synthesizer registers (addresses
03DB16 to 03DF16
)
WR
Nothing is assigned.
These bits can neither be set nor reset. When read, their contents are
indeterminate.
Reserved bit Must always be set to "0"
O
Interrupts
M30240 Group
Rev. H Sep 18, 2003 Page 28 of 139
1.2.12 Interrupts
Tabl e 1.9 and Tab le 1.10 show the interrup t sources and vecto r table address es. Wh en an interr upt is
received, the program is executed from the address shown by the respective interrupt vector.
The vector table addresses for the interrupts in Table 1.9 are fixed (interrupt vector addresses). These
interrupts are not affected by the interrupt enable flag (I flag) (non-maskable interrupts).
The vector table addresses for the interrupts in Table 1.10 are variable, being determined as relative to
the fixed address in the interrupt table register (INTB). These interrupts can be enabled or disabled using
the interrupt enable flag (I flag) (maskable interrupts). Sixty four vectors can be set in the interrupt table
register (INTB). Any of software interrupts 0 to 63 can be assigned to each vector. By using the INT
instruction to specify a software interrupt number, the program can be executed starting at the address
indica ted by the r espectiv e ve ctor. The B RK ins tructio n inter rup t has i nterrup t vec tors in both th e fixe d
vector address and variable vector address. When the contents of FFFE416 through FFFE716 are all
“FF16”, the pr ogram is exe cuted from the add ress shown in t he BRK instr uction interr upt vector in th e
variable vector address.
Specify the starting address of the interrupt program in the interrupt vector . Figure 1.15 shows the format
for specifying the address.
Table 1.9: Interrupt vectors with fixed addresses
Note: In terrup ts used for debu g ging purposes on ly
Figure 1.15: Format for specifying interrupt vector addresses
Interrupt source Vector table addr ess es
Address(L) to Address(H) Remarks
Undefined instruction FFFDC16 to FFFDF16 Interrupt on UND instruction
Overflow FFFE016 to FFFE3 16 Interrupt on INTO instructio n
BRK instruction FFFE416 to FFFE716 If the vector is filled with FF16, program execution starts from
the address shown by the vector in the variable vector table
Address Ma tch FFFE816 to FFFEB16 There is an address-matching interrupt enable bit
Single Step (Note) FFFEC16 to FFFEF16 Do not use
Watchdog timer FFFF016 to FFF316
DBC (Note) FFFF416 to FFFF716 Do not use
NMI FFFF816 to FFFFB16 External interrupt by NMI pin
Reset FFFFC16 to FFFFF16
Vector address + 0
Vector address + 1
Vector address + 2
Vector address + 3
Low address
Mid address
0 0 0 0 High
address
0 0 0 0 0 0 0 0
MSB LSB
Interrupts
M30240 Group
Rev. H Sep 18, 2003 Page 29 of 139
Table 1.10: Interrupt vectors with variable addresses)
Note:Address relative to address in interrupt table base address register (INTB)
Software interrupt number Vector table addresses
Address(L) to
Address(H) (Note 1) Interrupt source Remarks
Software interrupt number 0 +0 to +3 BRK instruction Cannot be masked by I flag
Software interrupt number 4 +16 to +19 USB Suspend
Software interrupt number 6 +24 to +27 USB Resume
Software interrupt number 7 +28 to +31 USB Start of Frame
Software interrupt number 10 +40 to +43 Bus collision detection
Software in terrupt number 11 +44 to +47 DMA0
Software interrupt num ber 12 +48 to +51 DMA1
Software interrupt number 13 +52 to +55 Key input interrupt
Software i nterrupt num ber 14 +56 to +59 A-D
Software i nterrupt num ber 15 +60 to +63 UART 2 transmit
Software i nterrupt num ber 16 +64 to +67 UART 2 receive
Software i nterrupt num ber 17 +68 to +71 UART 0 transmit
Software i nterrupt num ber 18 +72 to +75 UART 0 receive
Software i nterrupt num ber 19 +76 to +79 UART 1 transmit
Software i nterrupt num ber 20 +80 to +83 UART 1 receive
Software interrupt num ber 21 +84 to +87 T i mer A0
Software interrupt num ber 22 +88 to +91 T i mer A1
Software interrupt num ber 23 +92 to +95 T i mer A2
Software interrupt num ber 24 +96 to +99 T i mer A3
Software interrupt number 25 +100 to +103 Timer A4
Software interrupt number 26 +104 to +107 Timer B0
Software interrupt number 27 +108 to +111 Timer B1
Software interrupt number 28 +112 to +115 USB Reset
Software interrupt num ber 29 +116 to +119 INT0
Software interrupt num ber 30 +120 to +123 INT1
Software interrupt number 31 +124 to +127 USB Function
Software i nterrupt num ber 32
to
Software i nterrupt num ber 63
+128 to +131
+252 to +255 Software inte rrupt Cannot be masked by I flag
Interrupts
M30240 Group
Rev. H Sep 18, 2003 Page 30 of 139
1.2.12.1 Interrupt control registers
Periph eral I/O interr upts have their own interrupt c ontrol regist ers. Table 1.11 shows the addre sses
of the interrupt control registers. Figur e 1.16 shows the interrupt control registers.
The interrupt request bit is set by hardware to “0” when an interrupt request is received. The interrupt
request bit can also be set by software to “0”. (Do not set to “1”.)
INT0 and INT1 are triggered b y the edges of externa l inpu ts. The edg e po larity i s selected u sing th e
polarity select bit. (Other interrupts are described elsewhere.)
An interrupt must first be enabled before it can be used to cancel stop mode.
Table 1.11: Addresses in interrupt control register
Interrupt control register Symbol
name Address Interrupt control register Symbol
name Address
USB Suspend Interrupt SUSPIC 004416 UART1 receive S1RIC 005416
USB Resume interrupt RSMIC 004616 Timer A0 TA0IC 005516
USB Start Of Frame SOFIC 004716 Timer A1 TA1IC 005616
Bus collision detection BCNIC 004A16 Timer A2 TA2IC 005716
DMA0 DM0IC 004B16 Timer A3 T A3IC 005816
DMA1 DM1IC 004C16 Timer A4 T A4IC 005916
Key input interrupt KUPIC 004D16 Timer B0 TB0IC 005A16
A-D ADIC 004E16 Timer B1 TB1IC 005B16
UART2 transmit S2TIC 004F16 USB Reset RSTIC 005C16
UART2 receive S2RIC 005016 INT0 INT0IC 005D16
UART0 transmit S0TIC 005116 INT1 INT1IC 005E16
UART0 receive S0RIC 005216 USB Function USBFIC 005F16
UART1 transmit S1TIC 005316
Interrupts
M30240 Group
Rev. H Sep 18, 2003 Page 31 of 139
Figure 1.16: Interrupt control registers
Symbol Address When reset
INTiIC ( i= 0, 1) 005D16, 005E16 XX00X0002
SOFIC 004716 XX00X0002
Interrupt control register
Symbol Address
When reset
SUSPIC 004416 XXXXX0002
RSMIC 004616 XXXXX0002
BCNIC 004A16 XXXXX0002
DMiIC(i=0, 1) 004B16, 004C16 XXXXX0002
KUPIC 004D16 XXXXX0002
ADIC 004E16 XXXXX0002
SiTIC(i=0 to 2) 005116, 005316, 004F16 XXXXX0002
SiRIC(i=0 to 2) 005216, 005416, 005016 XXXXX0002
TAiIC(i=0 to 4) 005516 to 005916 XXXXX0002
TBiIC(i=0 to 1) 005A16 to 005B16 XXXXX0002
RSTIC 005C16 XXXXX0002
USBFIC 005F16 XXXXX0002
b7 b6 b5 b4 b3 b2 b1 b0
Bit name FunctionBit symbol WR
ILVL0
IR
Interrupt priority level
select bit
Interrupt request bit 0 : Interrupt not requested
1 : Interrupt requested
ILVL1
ILVL2
Nothing is assigned.
These bits can neither be set nor reset. When read, their contents are
indeterminate.
(Note)
This bit can only be reset (= 0), but cannot be set ( = 1).
0 0 0 : Level 0 (interrupt disabled)
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
b2 b1 b0
Bit name FunctionBit symbol W
R
b7 b6 b5 b4 b3 b2 b1 b0
ILVL0
IR
POL
Nothing is assigned.
These bits can neither be set nor reset. When read, their contents are
indeterminate.
Interrupt priority level
select bit
Interrupt request bit
Polarity select bit
Reserved bit
0: Interrupt not requested
1: Interrupt requested
0 : Selects falling edge
1 : Selects rising edge
ILVL1
ILVL2
(Note 1)
0 0 0 : Level 0 (interrupt disabled)
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
b2 b1 b0
0
(Note 2)
Note 1: This bit can only be reset (=0), but cannot be set (=1).
Note 2: For SOFIC (address 0047 16
), a "0" should always be written.
Must always be set to "0"
When rewriting the interrupt control register, do so at a point that does not
generate an interrupt requst for that register. For details, see the interrupt
precaution section.
Note 3:
When rewriting the interrupt control register, do so at a point that does not
generate an interrupt requst for that register. For details, see the interrupt
precaution section.
Note 1:
Note 2:
Interrupts
M30240 Group
Rev. H Sep 18, 2003 Page 32 of 139
1.2.12.2 Interrupt priority
The order of priority when two or more interrupts are generated simultaneously is determined by both
hardware and software.
The interrupt priority levels determined by hardware are Reset > NMI > DBC > Watchdog timer > pe-
ripheral I/O interrupts > single-step > Address matching interrupt.
The interrupt priority levels determi ned by software are set in the interrupt control registers.
Figure 1.17 shows the circuit that judges the interrupt hardware priority level. When two or more inter-
rupts are generated simultaneously, the interrupt with the higher software priority is selected. Howev-
er, if the interrupts have the same software priority level, the interrupt is selected according to the
hardware pri orit y set in the circui t.
The se lected inte rrupt is accep ted only whe n the priority level is h igher than the processor interrupt
priority level (IPL ) in the flag regi ster (FLG) an d the interrupt ena ble flag (I fla g) is “1”. Note that th e
reset, NMI, DBC, wat chdog tim er, singl e-step, addres s-match, BRK instr uction, ove rflow, and un de-
fined instruction interrupts are accepted regardless of the interrupt enable flag (I flag).
Interrupts
M30240 Group
Rev. H Sep 18, 2003 Page 33 of 139
Figure 1.17: Interrupt resolution circuit
USB Reset
Timer A4
Timer A2
USB SOF
UART1 reception
UART0 reception
UART2 reception
A-D conversion
DMA1
Bus collision detection
Timer A0
UART1 transmission
UART0 transmission
UART2 transmission
Key input interrupt
DMA0
Processor interrupt priority level (IPL)
INT1
Timer B1
Level 0 (initial value)
Priority level of each interrupt
High
Low
Priority of peripheral I/O interrupts
(if priority levels are same)
Interrupt enable flag (I flag)
Watchdog timer
Reset
DBC
NMI
Interrupt
request
accepted
Address match
USB Suspend
USB Resume
USB Function
Timer A3
Timer A1
INT0
Timer B0
NMI Interrupt
M30240 Group
Rev. H Sep 18, 2003 Page 34 of 139
1.2.12.3 Flag changes
When an interrupt request is received, the stack pointer select flag (U flag) changes to “0” and the flag
register (FLG) and pr ogra m cou nte r (PC) ar e saved to the sta ck area in dic at ed by the inte rru pt sta ck
pointer (ISP). Thereafter, the interrupt enable flag (I flag) and debug flag (D flag) change to “0” and the
process or interrup t prio rity lev el (IPL) a t the flag reg ister (FL G) is repl aced by the prior ity lev el of the
received interrupt. However, when interrupt requests are received for software interrupts 32 to 63, the
flag register (FLG) and program counter (PC) are saved to the stack shown by the stack pointer select
flag (U flag) at the time the interrupt was received. The stack pointer select flag (U flag) does not
change. The value of the processor interrupt priority level (IPL) in the flag register (FLG) differs in the
case of re set, NM I, DBC, watchdog timer, single-step, address-match, BRK instruction, overflow, and
undefined instruction interrupts. Table 1.12 shows how the IPL changes when interrupt requests are
received.
Table 1.12: Change of IPL state when interrupt request are accepted
1.2.13 NMI Interrupt
An NMI interrupt is generated when the input to the P85/NMI pin changes from “H” to “L”. The NMI
interrupt is a non-maskable external interrupt. The pin level can be checked in the Port P85 register (bit
5 at address 03F016).
This pin cannot be used as a normal port input.
Notes:
1. When not intending to use the NMI function, be sure to connect the NMI pin to VCC. Because the NMI
interrupt is non-maskable, it cannot be disabled.
2. When the NM I pin input is “L”, do not se t the microc omputer in stop mode or wai t mode. The NMI
interrupt is triggered by the falling edge, so the “L” level does not need to be maintained longer than
necessary.
Interrupt Change of IPL
Reset Level 0 ( 0002), is set
NMI Lev el 7 (1112), is set
DBC Does not ch ang e
Watchdog timer Level 7 (1112), is set
Single step Does not change
Address ma tch Does not ch ang e
Software interru pt Does not chang e
Key input interrupt
M30240 Group
Rev. H Sep 18, 2003 Page 35 of 139
1.2.14 Key input interrupt
If the d irection reg ister of any of pin of P ort0 or Po rt1 is set fo r input a nd a falling e dge is in put to that
port, a key-input interrupt is generated. A key-input interrupt can also be used as a key-on wakeup
function for cancelling the wait mode or stop mode. Figure 1.18 shows the block diagram of the key-input
interrupt.
Figure 1.18: Block diagram of key input interrupt
1.2.14.1 Enable/Disable
The key -input interrupt can be enabled a nd disabled us ing the key-in put interrup t regi ster (004D16).
The key-input inte rrupt is affected by the interrupt priority level (IPL) and the interrupt enable flag (I
flag).
1.2.14.2 Occurrence timing of the key-input interrupt
With key-input interrupt acceptance enab led, ports P0 and P1, which are set to input, become ke y-
input in terrupt pins (KI0 through KI15). A key-inp ut interrupt occurs when a falling edge is input to a
key-inpu t inte rrupt p in. A t this mome nt, the leve l of othe r key- inpu t interr upt pins mus t be “ H”. No in-
terrupt occurs when the level of any other key-input interrupt pins is “L”.
1.2.14.3 How to determine a key-input interrupt
A key-input interrupt occurs when a falling edge is input to one of 16 pins, but each pin has the same
vector ad dr es s. Therefore, re ad the i np ut l evel of port s P 0 a nd P 1 i n th e key -input interr up t r outi ne to
determine the interrupted pin.
1.2.14.4 Related registers
Figure 1.19 shows the memory map of key-input interrupt-related registers
Figure 1.19: Memory Map of key input interrupt related registers
pull-up select bit
Port P1i
direction register
Port P1i/KIj
(Pull-up transistor)
i=0~7; j=8~15
Port PXi
Port P0i
pull-up select bit
Por t P0i
direction register
Port P0i/KIj
(Pull-up transistor)
i=0; j=0~7
KI15
KI0
Interrupt control circuit
Key input interrupt control circuit
Key input
interrupt request
(address 004D16)
Address Register name Acronym
004E16
004D16 Key input interrupt register KUPIC
03E016
03E116
03E216
03E316
03E416
Port 0 P0
Port 1 P1
03FA16
03FB16
03FC16
03FD16
03FE16
Pull-up control register 1 PUR1
03FF16
Port 0 direction register
Port 1 direction register
PD0
PD1
Pull-up control register 0 PUR0
~
~~
~
~
~~
~
Address Match Interrupt
M30240 Group
Rev. H Sep 18, 2003 Page 36 of 139
1.2.15 Address Match Interrupt
An address match interrupt is generat ed when the address match interrupt address register contents
match the program counter value. Two address match interrupts can be set, each of which can be
enabled and disabled by an address match interrupt enable bit. Address match interrupts are not
affected by the interrupt enable flag (I flag) and processor interrupt priority level (IPL).
Figure 1.20 shows the address match interrupt-related registers.
Figure 1.20: Address match interrupt-related registers
1.2.16 Wa tchdog Timer
The watchdog timer has the function of detecting when the program is out of control. The watchdog timer
is a 15-bit counter that decrements using the clock derived by dividing the internal clock Φ using the
prescaler. A watchdog timer interrupt is generated when an underflow occurs in the watchdog timer . Bit
7 of the wat chdog timer contr ol registe r (addres s 000F16) selec ts the presca ler divis ion ratio (by 16 or
128). Table 1.13 shows the periodic table for the watchdog timer.
Table 1.13: Watchdog timer periodic table (f(XIN)=12MHz)
Note: The watchdog timer’s period is subject to some error due to the prescaler.
CM06 CM17 CM16 Internal clock ΦWDC7 Period (Note)
000 12MHz 0 Approx. 43.7ms
1 Approx. 349.5ms
001 6MHz 0 Approx. 87.4ms
1 Approx. 699.1ms
010 3MHz 0 Approx. 174.8ms
1 Approx. 1.40s
0 1 1 0.75MHz 0 Approx. 699.1ms
1 Approx. 5.59s
1 Invalid Invalid 1.5MHz 0 Approx. 349.5ms
1 Approx. 2.80s
Bit nameBit symbol
Symbol Address When reset
AIER 0009
16
XXXXXX00
2
Address match interrupt enable register
Function WR
Address match interrupt 0
enable bit 0 : Interrupt disabled
1 : Interrupt enabled
AIER0
Address match interrupt 1
enable bit
AIER1
Symbol Address When reset
RMAD0 0012
16
to 0010
16
X00000
16
RMAD1 0016
16
to 0014
16
X00000
16
Nothing is assigned.
b7 b6 b5 b4 b3 b2 b1 b0
WR
Address setting register for address match interrupt
Function Values that can be set
Address match interrupt register i (i = 0, 1)
00000
16
to FFFFF
16
Nothing is assigned.
0 : Interrupt disabled
1 : Interrupt enabled
b0 b7 b0b3
(b19) (b16)
b7 b0
(b15) (b8)
b7
(b23)
Write 0 when writing to these bits. If read, the value is indeterminate.
Write 0 when writing to these bits. If read, the value is indeterminate.
Watchdog Timer
M30240 Group
Rev. H Sep 18, 2003 Page 37 of 139
The watchdog timer is initialized by writing to the watchdog timer start register (address 000E16) and
when a watchdog timer interrupt request is generated. The prescaler is initialized only when the
microcomputer is reset. After a reset, the watchdog timer and prescaler are both stopped. The count is
started by writing to the watchdog timer start register (address 000E16).
Figure 1.21 shows the block diagram of the watchdog timer. Figure 1.22 shows the watchdog timer-
related registers.
Figure 1.21: Block diagram of watchdog timer
Figure 1.22: Watchdog timer control and start registers
1/16
1/128
W atchdog timer
Set to 7FFF
16
WDC7 = 0
WDC7 = 1
RESET
Write to the watchdog
timer start register
(address 000E
16
)
Internal clock
Φ
Prescaler
Watchdog timer
interrupt requ est
Watchdog timer control register (Note)
Symbol Address When reset
WDC 000F16 000XXXXX2
FunctionBit symbol WR
b7 b6 b5 b4 b3 b2 b1 b0
High-order bit of Watchdog timer
WDC7
Bit name
Prescaler select bit 0 : Divided by 16
1 : Divided by 128
Watchdog timer start register
Symbol Address When reset
WDTS 000E16 Indeterminate
WR
b7 b0
Function
Reserved bit Must always be set to “0”
00
Note: Set the desired prescale value before initializing the Watchdog timer.
The Watchdog timer is initialized and starts counting after the first write instruction
to this register after reset. Writing any value to this register resets the counter to
7FFF16.
Frequency Synthesizer Circuit
M30240 Group
Rev. H Sep 18, 2003 Page 38 of 139
1.2.17 Frequency Synthesizer Circuit
The Frequency Synthesizer Circuit generates a 48MHz clock needed by the USB block and a clock fSYN
that are both a multiple of the external input reference clock f(XIN). A block diagram of the circuit is shown
in Figure 1.23.
Figure 1.23: Frequency Synthesizer Circuit
The frequency synthesizer consists of a prescaler, frequency multiplier macro, a frequency divider
macro , and five registers, nam ely FSP, FSM, FSC , FSD, an d FSCCR. Clock f(XIN) is presc aled down
using FSP to generate fPIN. fPIN is multiplied using FSM to generate an fVCO clock which is then divided
using FSD to produce the clock fSYN. The fVCO clock is optimized for 48 MHz operation and is buffered
and sent out of the frequency synthesizer block as signal fUSB. This signal is used by the USB block.
1.2.17.1 Prescaler
Clock fPIN is a divid ed down version of c lock f(XIN) (see Figur e 1.24). The relatio nship betwe en fPIN
and the clock input to the prescaler f(XIN) is as follows:
• fPIN = f(XIN) / 2(n+1) where n is a decimal number between 0 and 254.
Setting FSP to 255 disables the prescaler and fPIN = f(XIN).
• Note: f(XIN) frequency below 1 MHz is not recommended.
Figure 1.24: Frequency Synthesizer Prescaler Register (FSP)
FSP
Data Bus
FSM FSC FSD
03DE 03DD 03DC 03DF
Frequency
Multiplier Frequency
Divider
8 Bit
LS
8 Bit
f(X
IN
)f
VCO
f
SYN
f
USB
Prescaler
8 Bit
f
PIN
FSCCR
FSCCR0
03DB
EN
USBC5
2
fPIN FSP f(Xin)
Dec(n) Hex(n)
12 MHz 255 FF 12.00 MHz
1 MHz 5 05 12.00 MHz
2 MHz 2 02 12.00 MHz
3 MHz 1 01 12.00 MHz
6 MHz 0 00 12.00 MHz
MSB
7LSB
0
Bit 6 Bit 1 Bit 0
Bit 2
Bit 5 Bit 4 Bit 3Bit 7 Acces s: R/W
Addre ss: 03DE
16
Reset: FF
16
f(XIN)/2(n+1) = fPIN
Frequency Synthesizer Circuit
M30240 Group
Rev. H Sep 18, 2003 Page 39 of 139
1.2.17.2 Multiplier
Clock fVCO is a multi plied up version of clock fPIN (See Figu re 1.25). The r elationship between fVCO
and the clock input to the multiplier (fPIN) from the prescaler is as follows:
• fVCO = fPIN x 2(n+1) where n is the decimal equivalent of the value loaded in FSM.
Setting FSM to 255 disables the multiplier and fVCO = fPIN.
Note 1: n must be chosen such that fVCO equals 48 MHz.
Note 2: Minimum fPIN is 1 MHz.
Figure 1.25: Frequency Synthesizer Multiply Register (FSM)
1.2.17.3 Divider
Clock fSYN is a d iv id ed down ver sion of cl ock fVCO (See Figu re 1.26) . The rela tions hip betwe en fSYN
and the clock input to the divider (fVCO) from the multiplier is as follows:
• fSYN = fVCO / 2(m+1) where m is the decimal equivalent of the value loaded in FSD.
Setting FSD to 255 disables the divider and fSYN = fVCO.
Figure 1.26: Frequency Synthesizer Divide Register (FSD)
fPIN x 2(n+1) = fVCO
fPIN FSM fVCO
Dec(n) Hex(n)
1 MHz 23 17 48.00 MHz
2 MHz 11 0B 48.00 MHz
4 MHz 5 05 48.00 MHz
6 MHz 3 03 48.00 MHz
12 MHz 1 01 48.00 MHz
MSB
7 LSB
0
Bit 6 Bit 1 Bit 0
Bit 2
Bit 5Bit 4Bit 3Bit 7 Address: 03DD16
Access: R/W
Reset: FF16
fVCO/2(m+1) = fSYN
fVCO FSD fSYN
Dec(m) Hex(m)
48.00 MHz 1 01 12.00 MHz
48.00 MHz 127 7F 187.50 KHz
MSB
7LSB
0
Bit 6 Bit 1 Bit 0 Address: 03DF16
Access: R/W
Reset: FF16
Bit 2
Bit 5Bit 4Bit 3
Bit 7
Frequency Synthesizer Circuit
M30240 Group
Rev. H Sep 18, 2003 Page 40 of 139
The FSC0 bit in the FSC Control Register enables the frequency synthesizer block. When disabled
(FSC0 = “0”), fVCO is held at either a high or low state. When the frequency synthesizer control bit is
active (FSC0 = “1”), a lock status (LS = “1”) indicates that fSYN and fVCO are the correct frequency. The
LS and FSCO control bits in the FSC Control register are shown in Figure 1.27.
When using the frequency synthesizer, a low-pass filter must be connected to the LPF pin.
Once the frequency sy nth esiz er is enabl ed , a dela y of 2- 5m s i s rec omm end ed bef or e the ou tput of the
frequency synthesizer is used. This is done to allow the output to stabilize. It is also recommended that
none of the register s be modified on ce the freq uency synthe sizer is enab led as it wil l cause the ou tput
to be tem porarily (2-5 ms) unstable. The M CU clock sourc e is selecte d via the Frequen cy Synthes izer
Clock Control register (FSCCR). See Figure 1.28.
Note: N one of t he re gisters must be writte n to once the frequ ency synth esizer is enab led an d use d as
the syste m clock sour ce (FSCCR reg ister, addr ess 03DB16, bit “0” se t to “ 1”) be caus e it will ca use the
output of the PLL to freeze. Switch system back to f(XIN) and disable before modifying PLL registers.
Figure 1.27: Frequency Synthe sizer Control Register (FSC)
Figure 1.28: Frequency Synthesizer Clock Control Register (FSCCR)
Frequency Synthesizer Control Register
Symbol Address When reset
FSC 03DC
16
60
16
Bit nameBit symbol
b7 b6 b5 b4 b3 b2 b1 b0
0 : Disable
1 : Enabled
VCO0
FSE
VCO Gain Control
Function
Bit 2 Bit 1
0 0: Lowest Gain (Note)
0 1: Low Gain
1 0: High Gain
1 1: Highest Gain
Frequency Synthesizer Enable
W
R
Reserved bit Must always be set to "0"
VCO1
CHG0
CHG1
LPF Current Control
Bit 6 Bit 5
0 0: Disabled
0 1: Low Current
1 0: Intermediate Current (Note)
1 1: High Current
LS Frequency Synthesizer
Lock Status
0: Unlocked
1: Locked
Note :
Recommended
00
Frequency Synthesizer Clock Control Register
Symbol Address When reset
FSCCR 03DB
16
00
16
Bit nameBit symbol
b7 b6 b5 b4 b3 b2 b1 b0
0 : X
IN
1 : fsyn
FSCCR0
Function WR
Reserved Must always be set to "0"
Clock source selection
0
0
0
0
0
0
0
Universal Serial Bus
M30240 Group
Rev. H Sep 18, 2003 Page 41 of 139
1.2.18 Universal Serial Bus
The Universal Serial Bus (USB) has the following features:
• Complete USB Specification (version 1.1) Compatibility
• Error-h and li ng cap abi li tie s
• FI FO s :
• Endpoint 0:IN/OUT 32-byte
• Endpoint 1:IN 128-byteOUT 128-byte
• Endpoint 2:IN 32-byteOUT 32-byte
• Endpoint 3:IN 32-byteOUT 32-byte
• Endpoint 4:IN 32-byteOUT 32-byte
• Nine endpoints - control endpoint (Endpoint 0 - bi-directional) plus four IN and four OUT endpoints
• Complete device configuration
• Support of all device commands
• Supports of full-sp eed function s
• Support of all USB transfer types:
• Isochronous
• Bulk
• Control
• Interrupt
• Suspend/Resume ope ra tio n
• On-chip USB transceiver with voltage converter
• Start-of-frame interrupt and output pin
1.2.18.1 USB Function Control Unit (USB FCU)
The implementation of the USB by this device is accomplished chiefly through the device’s USB Func-
tion Control Unit (See Figure 1.29). The Function Control Unit’s overall purpose is to handle the USB
packet protocol layer. The Function Control Unit notifies the MCU that a valid token has been received.
When this occurs, the data portion of the token is routed to the appropriate FIFO. The MCU transfers
the data to, or from, the host by interacting with that endpoint’s FIFO and CSR register.
The U SB Function Control Unit is composed of five sections:
• Serial Interface En gine (SIE)
• Ge neric Function Interface (GFI)
• Serial Engine Interface Unit (SIU)
• Microcontroller Interface ( MCI)
• USB Transceiver
1.2.18.1.1 Serial Interface Engine
The SIE interfac es to the USB serial dat a and handles des erializatio n/serialization of data, NRZI encodi ng de-
coding, clock extraction, CRC gene ration and checking, bit stuffi ng, and other i tems pertaining to th e USB pro-
tocol such as handling inter-packet time-outs and packet ID (PID) decoding.
Universal Serial Bus
M30240 Group
Rev. H Sep 18, 2003 Page 42 of 139
1.2.18.1.2 Generic Function Interface
The GFI handles all USB standard requests from the host through the control endpoint (endpoint zero), han-
dles Bulk, Isochronous and Interrupt transfers through Endpoints 1-4. The GFI handles read po inter reversal
for re-trans miss ion the c urrent d ata set; wr ite poin ter reve rsal for re cepti on of the last da ta set ag ain and data
toggle synchronization.
1.2.18.1.3 Serial Engine Interface Unit
The SIU block decodes the Address and Endpoint fields from the USB host.
1.2.18.1.4 Microcontroller Interface
The MCI block handles the Microcontroller interfac e and performs address decoding and synchronization of
control signals.
1.2.18.1.5 USB Transceiver
The USB transceiver, designed to i nterface with the physical layer of the USB, is compliant with th e USB Spec-
ification (version 1.1) for full-speed devices. It consists of two 6-ohm drivers, a receiver, and Schmitt triggers
for single-ended receive signals.
The transceiver also includes a voltage converter. The voltage converter can supply 3.0 - 3.6V to the trans-
mitter when the rest of the chip (CPU, USB FCU) operates at 4.15 - 5.25V. To enable the voltage converter,
set bit 4 of th e USB C ont rol Re gis ter (U SBC) to a “1”. To dis ab le th e vo lta ge c on verter, s et bi t 4 of t he U SBC
to a “0”. Refer to Section 1.5.4 “USB Transceiver” for more detailed information.
Figure 1.29: USB Function Control Unit Block Diagram
1.2.18.2 USB Interrupts
There are five USB interrupts in this device:
• USB Function interrupt
• USB Reset interrupt
• USB Suspend interrupt
• USB Resume interrupt
• USB Start-of-Frame (SOF) interrupt.
The first fou r interrupts ar e used to control the data flow and USB power. The SOF int errupt is used
to monitor the transfer of isochronous (ISO) data. Each of the five USB interrupts is enabled by setting
the corresponding bit in the Interrupt Control Register of the Interrupt Control Unit. Because the USB
Function Interrupt has multiple interrupt sources, another level of enabling is within the USB Interrupt
Registers 1 & 2.
CPU MCI
SIU
GFI
FIFOs
SIE
Transceiver
D+
D-
Universal Serial Bus
M30240 Group
Rev. H Sep 18, 2003 Page 43 of 139
1.2.18.2.1 USB Function Interrupt
The USB F unctio n Interru pt can be trig gered b y 10 sour ces; many o f these may be cau se by seve ral dif ferent
events. Interrupt status flags associated with each source are contained in USBIS1 and USBIS2.
Endpoints 1-4 have two interrupt status flags associated with it to control data transfer or to report a STALL/
UNDER_RUN/OVER RUN condition.
The USB Endpoint x Out Interrupt Status Flag is set when
• USB FCU successfully receives a packet of data OR
• USB FCU sets the FORCE_STALL flag or OVER_RUN flag of the Endpoint x OUT CSR.
The USB Endpoint x In Interrupt Status Flag is set when
• USB FCU successfully sends a packet of data OR
• USB FCU sets the UNDER_RUN flag of the Endpoint x IN CSR.
The USB Endpoint 0 (control endpoint) has one interrupt status bit associated with it to control data transfer
or report a STALL condition.
The USB Endpoint 0 Interrupt Status Flag is set when
• USB FCU successfully receives/sends a packet of data
• Sets th e SETUP_EN D fl ag or the FORCE _ST ALL fl ag, OR clears the DATA_END bit in the Endp oin t 0 IN
CSR.
The Overrun/Underrun Interrupt Status Flag is set when (applicable to endpoints used for isochronous data
transfer)
• Overrun condition occurs in a endpoint (CPU is too slow to unload the data from the FIFO), OR
• Underrun condition occurs in an endpoint (CPU is too slow to load the data to the FIFO).
Each endpo int interrupt an d overrun/un derrun int errupt is enabled by setting the co rrespondi ng bit in the USB
Interrupt Enable Register 1 and 2.
1.2.18.2.2 USB Reset Interrupt
The USB Reset Interrupt Status Flag is set when the USB FCU sees a SE0 present on D+/D- for at least 2.5µs.
When this bit is set, all USB internal registers except INTST13 (bit5 of USBIS2) are reset to their default val-
ues. INTST13, the USB reset Interrupt Status Flag, is set to a “1” when the USB Reset is detected.
When the CPU recognizes a USB Reset Interrupt, it needs to re initialize the USB FCU so that the USB op-
eration ca n behav e prope rly. It m ust als o clear IN TST13 by writing a “1 ” to this bi t to allo w a USB Rese t Inter-
rupt request to occur the next time a USB Reset is detected.
Register RSTIC contains the USB Reset Interrupt’s request bit and its interrupt priority select bits which are
used to enable the interrupt and set its software priority level.
1.2.18.2.3 USB Suspend and Resume Interrupts
The USB Suspend Interrupt is set when the USB FCU does not detect any bus activity on D+/D- (in J-state)
for at least 3ms.
The USB Suspend Signaling Interrupt Status Flag (INTST15, bit 7 of USBIS2) is set to a “1” when the USB
Suspend is detected. The CPU must clear INTST1 5 by writing a “1” to t his bit to allow a USB Suspend Interrupt
request to occur the next time a USB Suspend is detected.
The USB Res ume Signa ling In terrupt St atus Fl ag is s et when a USB FCU is in the susp end sta te and d etects
non-idle signaling on the D+/D-.
Register SUSPIC contains the USB Suspend Interrupt’s request bit and its interrupt priority select bits which
are used to enable the interrupt and set its software priority level.
The USB Resume Interrupt request is set when the USB FCU is in the suspend state and detects non-idle
signali ng on D+ /D-.
The USB Signaling Interrupt Status Flag (INTST14, bit 6 of USBIS2) is set to a “1” when the USB Resume is
detected. The CPU must clear INTST14 by writing a “1” to this bit to allow a USB Resume Interrupt request
to occur the next time a USB Resume is detected.
Register RSMIC contains the USB Resume Interrupt’s request bit and its interrupt priority select bits, which
are used to enable the interrupt an set its software priority level.
Universal Serial Bus
M30240 Group
Rev. H Sep 18, 2003 Page 44 of 139
1.2.18.2.4 USB SOF Interrupt
The USB SOF (Start-Of-Frame) Interrupt is used to control the transfer of isochronous data. The USB FCU
generates a USB SOF Interrupt request when a start-of-frame packet is received.
Register SOFIC contains the USB SOF Interrupt’s request bit and its interrupt priority select bits, which are
used to enable the interrupt and set its software priority level.
1.2.18.3 USB Endpoint FIFOs
The USB FCU has an IN (transmit) FIFO and an OUT (receive) FIFO for each endpoint. Each endpoint (except
endpoint 0) can be configured to support either single packet mode (in which only a single data packet is al-
lowed to reside in the endpoint’s FIFO) or dual packet mode (in which up to two data packets are allowed to
reside in th e end poi nt’ s FIFO ). Dua l pac ke t mod e pro vid es support for back-to-ba ck trans mi ssio n or bac k-t o-
back reception. The mode is automatically determined by the MAXP value. When MAXP > 1/2 of the end-
point’s FIFO size, single packet mode is set. When MAXP <= 1/2 of the endpoint’s FIFO size, dual packet
mode is set.
In the event of a bad transmission/reception, the USB FCU handles all the FIFO read/write pointer reversal
and data set management tasks required.
Throughou t this speci ficati on, the terms “IN FIFO” and “OUT FIFO” u sually re fer t o the FIF Os ass ociated w ith
a specific endpo int.
1.2.18.3.1 IN (Transmit) FIFOs
The CPU/ DMA write s data to the en dpoint’ s IN FIFO locati on spec ified by the FIFO write po int er, which aut o-
matically increments by “1” after a write. The CPU/DMA should only write data to the IN FIFO when the
IN_PKT_RDY bit of the associated IN CSR is a “0”.
• Endpoint 0 IN FIFO Operation:
The CPU wri tes a “1” to the IN_PKT_ RDY bit of Endpo int 0 CSR after it finishes writ ing a packe t of data to the
IN FIFO. The U SB FCU clears the IN_ PKT_RDY bi t after the pa cket has been succe ssfully transm itted to th e
host (i.e., ACK is received from the host) or the SETUP_END flag of the Endpoint O CSR is set to a “1”.
• Endpoint 1-4 IN FIFO Operation when AUTO_SET (bit 7 of Endpoint x IN CSR) = “0” (disabled):
MAXP > 1/2 of the IN FIFO size: The CPU writes a “1” to the IN _PKT_RDY bit of the associat ed IN CSR after
the CPU/DMAC finishes writing a packet of data to the IN FIFO. The USB FCU clears the IN_PKT_RDY bit
after the packet has been successfully transmitted to the host (w hich is assumed for isochronous transfers
and is concluded when an ACK is received from the host for non-isochronous transfers).
MAXP <= 1/2 of th e IN FIFO size: The CPU writes a “1” to the IN_PKT_RDY bit of the assoc iated IN CSR after
the CPU/DMAC finishes writing a packet of data to the IN FIFO. The USB FCU clears the IN_PKT_RDY bit
as soon as the IN FIFO is rea dy to accep t another da ta pack et. (The FIFO can hol d up to two data pa ckets at
the same time in this configuration for back-to-back transmission.)
• Endpoint 1-4 IN FIFO Operation when AUTO_SET (bit 7 of Endpoint x IN CSR) = “1” (enabled):
MAXP > 1/2 of th e IN FIFO size: When the number of bytes of data equal to the MAXP (maximum pa cket size)
has bee n written to the IN FIFO b y the CPU/DMAC, th e USB FCU sets th e IN_PKT_RDY bit of the associ ated
IN CSR to a “1” automatic ally . The USB FCU clears the IN_PKT_R DY bit after the pack et has bee n success -
fully transmitted to the host (which is assumed for isochronous transfers and is concluded when an ACK is
received from the host for non-isochronous transfers).
MAXP <= 1/2 of the IN FIFO size: When the number of bytes of data equal to the MAXP (maximum packet
size) has been written to the IN FIFO by the CPU/DMAC, the USB FCU sets the IN_PKT_RDY bit to a “1”
automatically. The USB FCU clears the IN_PKT_RD Y bit as soon as the IN FIFO is ready to accept another
data pack et. (The FIFO can hold up to two data packets at the same time in this configurati on for back-to-b ack
transmission.)
A software or a hardware flush causes the USB FCU to act as if a packet has been successfully transmitted
out to t he host. When there i s one pack et in the IN FI FO, a flush causes the IN FI FO to be e mpty. When there
are two packets in the IN FIFO, a flush causes the older packet to be flushed out from the IN FIFO. A flush
also updates the IN FIFO status bits IN_PKT_RDY and TX_NOT_EPT of the associated IN CSR.
Universal Serial Bus
M30240 Group
Rev. H Sep 18, 2003 Page 45 of 139
The statu s of e ndp oi nt 1 - 4 IN FIFO s for both of the above cases ca n b e o btai ne d fro m the IN CS R of the c or-
responding IN FIFO as shown in Table 1.14 .
1.2.18.3.2 Out (Receive) FIFOs
The USB FCU writ es data to the endpo int’s O UT FIFO loc ation specified by the FIFO write poin ter, whi ch au-
tomatically increments by one after a write. When the USB FCU has successfully received a data packet, it
sets the OUT_PKT_RDY bit of the corresponding OUT CSR to a “1”. The CPU/DMAC should only read data
from the OUT FIFO when the OUT_PKT_RDY bit of the OUT CSR is a “1”.
• Endpoint 0 OUT FIFO Operation:
The USB FCU s ets the OUT_ PKT_RDY bit to a “1” after it has s uccessful ly received a packet o f data from th e
host. The CPU sets bit SERVICED_OUT_PKT_RDY to a “1” to cl ear the OUT_PKT_RDY bit afte r the pac ke t
of data has been unloaded from the OUT FIFO by the CPU.
• Endpoint 1-4 OUT FIFO O peration when AUTO_CLR (bit 7 of Endp oint x OUT CSR) = “0” (disabled):
MAXP > 1/2 of the OUT FIFO size: The USB FCU sets the OUT_PKT_RDY bit of the associated IN CSR to
a “1” after it has successfully received a packet of data from the host. The CPU writes a “0” to the
OUT_PKT_RDY bit after the packet of data has been unloaded from the OUT FIFO by the CPU/DMAC.
MAXP <= 1/2 of th e OUT FIF O size: Th e USB FCU se ts the OUT_PKT _RDY bi t of th e as soci ated IN CSR to
a “1” after it has successfully received a packet of data from the host. The CPU writes a “0” to the
OUT_PKT_R DY bit af ter th e packe t of data has b een un loaded from the O UT FI FO by the CPU/D MAC. If a n-
other packet is in the OUT FIFO, the OUT_PKT_RDY bit will be set to a “1” again almost immediately (such
that it may appear that the OUT_PKT_RDY bit remains a “1”). In this configuration, the FIFO can store up to
two data packets at the same time for back-to-back reception.
• Endpoint 1-4 OUT FIF O Operation when AUTO_CLR (bit 7 of Endpo int x OUT CSR) = “1” (enabled):
MAXP > 1/2 of the OUT FIFO size: The USB FCU sets the OUT_PKT_RDY bit of the associated IN CSR to
a “1” after it has successfully received a packet of data from the host. The USB FCU clears the
OUT_PKT_RDY bit to a “0” automatically when the number of bytes of data equal to the M AXP (m aximum
packet size) has been unloaded from the OUT FIFO by the CPU/DMAC.
MAXP <= 1/2 of th e OUT FIF O size: Th e USB FCU se ts the OUT_PKT _RDY bi t of th e as soci ated IN CSR to
a “1” after it has successfully received a packet of data from the host. The USB FCU clears the
OUT_PKT_RDY bit to a “0” automatically when the number of bytes of data equal to the M AXP (m aximum
packet size) ha s been u nloaded from the O UT FIFO b y the CP U/DMAC. If another pa cket is in the O UT FIFO,
the OUT_PKT_RDY bit will be set to a “1” again almost immediately (such that it may appear that the
OUT_PKT_RDY bit remains a “1”). In this configuration, the FIFO can store up to two data packets a t the same
time for back-to-back reception.
A softw are flu sh c aus es the USB FCU to a ct as i f a packet has been un lo ade d from the OUT FIFO . If there is
one pack et in the OUT FIFO, a flu sh will cause the OUT FIFO to be empty . If there are two pac kets in the OUT
FIFO, a flush will cause the older packet to be flushed out from the OUT FIFO.
Table 1.14: TA FIFO Status
IN_PKT_RD Y TX_NOT_EPT IN FIFO Status
00
No data p acket in IN FIFO
01
One data p ac ket in IN FIFO if MAXP <= 1/2 of the FIFO size./
Invalid when MAXP>1/2 of the FIFO size
10
Invalid
11
Two data pac ket s in IN FIFO when M AXP <=1/2 of the FIFO size
One data p ac ket in IN FIFO when MAXP > 1/2 of the FIFO size
Universal Serial Bus
M30240 Group
Rev. H Sep 18, 2003 Page 46 of 139
1.2.18.3.3 Interrupt Endpoints
Any endpo int can be us ed for in terru pt tra ns fers . For norm al interrupt transfers, the interru pt tra ns act ion s be-
have t he same as bulk tra nsac tions, i.e., no special se tting is require d. The IN end points may al so be used to
commu nicate rate feedba ck inf ormatio n for ce rtain ty pes of i soch ronous functions . This is don e by se tting th e
INTPT bit in the IN CSR register of the corresponding endpoint.
The following outlines the operation sequence for an IN endpoint used to communicate rate feedback infor-
mation:
1. Set MAXP > 1/2 of the endpoint’s FIFO size;
2. Set INTPT bit of the IN CSR;
3. Flush the old data in the FIFO;
4. Load in terrupt status information and set IN_PKT_RDY bit in the IN CSR;
5. Repeat steps 3 & 4 for all subsequent interrupt status updates.
1.2.18.4 USB Special Function Registers
The MCU controls USB operation through the use of special function registers (SFR). This section de-
scribes each US B related SFR. So me USB s pecial fun ction regi sters hav e a mix of rea d/write, rea d
only, and write only register bits. Additionally, the bits may be configured to allow the user to write only
a “0” or a “1” to individual bits.
• When ac cess ing the se regis ters, writing a “0” to a r egister that ca n only be set to a “1” by the CPU
has no effect on that register bit.
• Writing a “1” to a register that can only be set to a “0” by the CPU has not effect on that register bit.
Each figure and description of the special function registers details this operation.
All USB Special Function Registers, with the exception of USB Attach/Detach (001F16) and USB con-
trol (000C16) must use byte access. Work access is prohibited for USB internal registers (030016 -
033C16).
The contents of all USB Special Functions Registers, including USB Attach/Detach and USB Control,
are preserved on a software reset.
1.2.18.4.1 USB Attach/Detach Register
The US B Attach / Detac h Regis ter is shown in Fi gure 1 .30. T he regist er is used t o attach and detac h the USB
funct ion from a USB ho st without ph ysicall y disconnec ting the U SB cable. Th is functio nality is ena bled by se t-
ting P83_Second to a “1”. Doing this forces P83 to operate as a pull-up for D+ (through an external 1.5k ohm
resistor). The port drive r is tri-stated and a “1” is always read from the port bit in this mode. When the ATTACH/
DETACH bit is a “1” (and P83_Second is a “1”), P83 is drive n wi th the vo lta ge on EXTCAP, cau si ng D + to be
pulled up and th e host t o detect an attach . When th e ATTACH/DE TACH bit is a “0” (an d P83_Sec ond is a “1”),
P83 is tri-sta ted, cau sing D+ to be pul led dow n (throug h the ca ble and 15 k ohm resi stor on the host/hub side)
and a detach to be reg istere d by the host. A 1.5k ohm pull -up resi stor mus t be conn ected ex ternal ly from P83
to D+ when this functionality is used. When it is not used, the 1.5k ohm resistor should be placed between
EXTCAP and D+.
Figure 1.30: USB Attach/Detach Register
USB Attach/Detach Register
Symbol Address When reset
USBAD 001F16 0016
Bit nameBit symbol
b7 b6 b5 b4 b3 b2 b1 b0
0 : Normal mode for Port
1 : Forces Port to operate as pull up for D+.
P83_2nd
Function
Reserved Must always be set to "0"
Port 83-Second
Attach/
Detach Attach/Detach
0 : Tri-states, causing the host to detect a detach
1 : Drives with voltage on EXTCAP, causing the host
to detect an attach
WR
0
0
0
0
0
0
P83
P83
P83
P83
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1.2.18.4.2 USB Control Register
The US B Control Re gister, shown in Figure 1.31, is used t o con trol t he U SB FCU. This register is not reset by
a USB reset sign aling. After th e USB is enabled (U SBC7 set to “1”), a min imum delay of 250 ns (three 12 MHz
clock periods) is needed before performing any other USB register read/write operations.
Figure 1.31: USB Control Register
1.2.18.4.3 USB Function Address Register
The USB Fun ction Addre ss Regi ster, sh own in Figure 1 .32, ma intain s the 7-bi t USB addres s assign ed by th e
host. The USB FCU uses this reg ister value to decode USB token packet a ddresses. At reset, when the device
is not yet co nfigure d, the val ue is 0016. For the p roce du res on how to update t his r egi ste r, refer to Applica tio n
Notes USB Consecutive Set Address.
Figure 1.32: USB Function Address Register
USB Control Register
Symbol Address When reset
USBC 000C16 0016
Bit name
Bit symbol
b7 b6 b5 b4 b3 b2 b1 b0
Function W
R
Must always be set to "0"
Reserved
USBC3
USBC4
USBC5
USBC6
USBC7
Tranceiver voltage converter
High/Low current mode selection
USB tranceiver voltage converter
enable bit
USB clock enable bit
USB SOF port select bit
USB enable bit
0: High current mode (Note 1)
1: Low current mode (Note 2)
0: Disabled
1: Enabled
0: Disabled
1: Enabled
0: Disabled (Note 3)
1: Enabled
0: Disabled (Note 4)
1: Enabled
Note 1: For USB normal operation
Note 2: For USB suspend operation
Note 3: P8
6
is used as GPIO pin
Note 4: All USB internal registers are held at their default values.
0
0 0
USB Function Address Register
Symbol Address When reset
USBA 0300
16
00
16
Bit nameBit symbol
b7 b6 b5 b4 b3 b2 b1 b0
FUNAD0-6
Function WR
Reserved Must always be set to "0"
7-bit programmable
Function Address
Function Address
0
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1.2.18.4.4 USB Power Management Register
The USB Power Management Register, shown in Figure 1.33, is used for power management in the USB
FCU.
• SUSPEND Detection Flag:
When the U SB FC U d oes n ot det ect any bus activity on D+/D - fo r at le as t 3 ms (a nd D+/D - are in th e J-s tate),
it sets the Sus pend Detection Fla g and generates an in terrupt. This bit is clea red when signaling from the host
is detected on D+/D- (which sets the Resume Detection Flag and generates an interrupt), or the Remote
Wake-up Bit is set and the n c le ared by th e C PU . If the U SB c loc k was di sabled during the suspend state, th e
SUSPEND Detection Flag is not cleared until after the USB clock is re-enabled.
• RESUME Detec tion F lag:
When the USB FCU is in the suspend state and detects activity on D+/D- from the host, it sets the Resume
Detection Flag and generates an interrupt. The CPU writes a “1” to INTST14 (bit 6 of USB Interrupt Status
Register 2) to clear this flag.
• WAKEUP Control Bit:
The CPU writes a “1” to the WAKEUP Control Bit for remote wake-up. While this bit is set and the USB FCU
is in suspend mode, resume signaling is sent to the host. The CPU must keep this bit set for a minimum of
10ms and a maximum of 15ms before writing a “0” to this bit.
Figure 1.33: USB Power Management Register
USB Power Management Register
Symbol Address When reset
USBPM 0301
16
00
16
Bit nameBit symbol
b7 b6 b5 b4 b3 b2 b1 b0
Function W
R
Reserved Must always be set to "0"
SUSPEND
RESUME
WAKEUP
USB Suspend Detection Flag
USB Resume Detection Flag
USB Remote Wakeup Bit
0 : No USB suspend signal detected
1 : USB suspend signal detected
0 : No USB resume signal detected
1 : USB resume signal detected
0 : End remote resume signaling
1 : Remote resume signaling (Note 2)
Note 1: Write "0" only or Read
Note 2: If SUSPEND = "1"
Note 1
Note 1
0
0
0
0
0
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1.2.18.4.5 USB Interrupt Status Registers 1 and 2
USB Interrupt Status Registers 1 and 2, shown in Figure 1.34 and Figure 1.35, are used to indicate the con-
dition that caused a USB function interrupt and USB Reset, Suspend and Resume Interrupts to the CPU. A
“1” indicates the corresponding condition caused an interrupt. The USB Interrupt Status Regi ster bits can be
cleared by writing a “1” to the corresponding bit.
INTST0 is set to a “1” by the USB FCU when (in Endpoint 0 CSR):
• A packet of data is successfully received (EP0CSR0 - OUT_PKT_RDY is set by the USB FCU)
• A packet of data is successfully sent (EP0CSR - IN_PKT_RDY is cleared by the USB FCU)
• EP0CSR3 (DATA_END) bit is cleared by the USB FCU
• EP0CSR4 (FORCE_STALL) bit is set by the USB FCU
• EP0CSR5 (SETUP_END) bit is set by the USB FCU
INTST2, INTST4, INTST6 or INTST8 is set to a “1” by the USB FCU when (in Endpoint x IN CSR):
• A packet of data is successfully sent (INXCSR0 - IN_PKT_RDY is cleared by the USB FCU)
• INXCSR1 (UNDER_RUN) bit is set by the USB FCU
INTST3, INTST5, INTST7 or INTST9 is set to a “1” by the USB FCU when (in Endpoint xOUT CSR):
• A packet of data is successfully received (OUTXCSR0 - OUT_PKT_RDY is set by the USB FCU)
• OUTXCSR1 (OVER_RUN) bit is set by the USB FCU
• OUTXCSR4 (FORCE_STALL) bit is set by the USB FCU
INTST12 is set to a “1” by the USB FCU when an overrun or und errun condition occurs in any of the endpoints.
INTST13 is set to a “1” by the USB FCU when a U SB reset signaling from the host is received. All internal
register bits except this bit are reset to their default values when the USB reset is received.
INTST14 i s set to a “1” by the U SB FCU whe n the USB FC U is in the s uspend state and non-idl e si gna li ng is
received from D+/D-.
INTST15 is set to a “1” by the USB FCU when D+/D- are in the idle state for more than 3ms.
Figure 1.34: USB Interrupt Status Register 1
USB Interrupt Status Register 1
Symbol Address When reset
USBIS1 0302
16
00
16
Bit nameBit symbol
b7 b6 b5 b4 b3 b2 b1 b0
Function W
R
Reserved Must always be set to "0"
INTST0
INTST2
INTST3
INTST4
INTST5
INTST6
INTST7
USB Endpoint 0 Interrupt
Status Flag
USB Endpoint 1 IN
Interrupt Status Flag
USB Endpoint 1 OUT
Interrupt Status Flag
USB Endpoint 2 IN
Interrupt Status Flag
USB Endpoint 2 OUT
Interrupt Status Flag
USB Endpoint 3 IN
Interrupt Status Flag
USB Endpoint 3 OUT
Interrupt Status Flag
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 :
Interrupt request issued
0
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Figure 1.35: USB Interrupt Status Register 2
1.5.0.0.1 Clearing USB Interrupt Status Registers
The USB Interrupt Status Register 1 and 2 are used to indicate pending interrupts for a given source.
The USB FCU sets the interrupt status bits. The CPU writes a “1” to each status bit to clear it.
Because the USB Function Interrupt has multiple sources that can generate an interrupt, it is recom-
mended that the user first read the two status registers and store them in variables then write back the
same va lue for clearing all the ex isting interrup ts that were pending when the status reg isters were read.
This proc edu re prev en ts any inte rrup t that oc cu rs after the status regi ste rs are rea d from bein g cle are d
by the ‘w ri te-b ac k’ op erat ion . The CPU must r ead, then write b oth s tatu s reg is ters , w ri tin g to status reg-
ister 1 firs t and status register 2 se cond to guara ntee proper op eration. The upper three bi ts of the valu e
written back to USBIS2 s hould always be “000” to prev ent any of t he USB Reset, Sus pend and Res ume
Status Flags from being cleared.
The USB Res et, Suspend a nd Resum e Status Flags are co ntaine d in USBIS2 along wit h the USB End-
point 4 In/Out Interr upt Status Flags and the USB Overrun/Underrun Interrupts Status Flag. Because the
flags are not all sources for the same interrupt, use caution when clearing one or more of the flags to
avoid inadvertently clearing other flags. The Reset, Suspend and Resume Status Flags should be
cleared indivi duall y by wri ting a by te valu e with at “1” on ly at the positio n corres pondi ng to the fl ag to be
cleared . The USB Endpoint 4 In/Out Interrupt s tatus Flags a nd the USB Overru n/Underrun Interru pt Sta-
tus Flag should be cleared as described in the preceding paragraph because they are sourced for the
USB Function Interrupt.
“Read-modify-write” instructions, such as “BCLR” and “BSET”, should not be used to clear any of the
interr upt status bits in U SBIS1 or USBIS2. U sing th ese instruc tions co uld cause pending i nterrupts t o be
cleared without the firmware’s knowledge.
USB Interrupt Status Register 2
Symbol Address When reset
USBIS2 0303
16
00
16
Bit nameBit symbol
b7 b6 b5 b4 b3 b2 b1 b0
Function W
R
Reserved Must always be set to "0"
INTST8
INTST9
USB Endpoint 4 IN
Interrupt Status Flag
USB Endpoint 4 OUT
Interrupt Status Flag
USB Overrun/Underrun
Interrupt Status Flag
USB Reset
Interrupt Status Flag
USB Resume Signaling
Interrupt Status Flag
USB Suspend Signaling
Interrupt Status Flag
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
Reserved
INTST12
INTST13
INTST14
INTST15
0
0
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1.2.18.4.6 USB Interrupt Enable Registers 1 and 2
The USB Interrupt Enable Registers 1 and 2, shown in Figure 1.36 and Figure 1.37, are used to enable the
corresponding interrupt status conditions that can generate a USB Function Interrupt. When the bit to a cor-
responding interrupt condition is “0”, that condition does not generate a USB function interrupt. When the bit
is a “1”, that co nditio n can gen erate a USB f unction in terrupt. At res et, all USB fun ction in terrupt s tatus co ndi-
tions are enabled.
Figure 1.36: USB Interrupt Enable Register 1
Figure 1.37: USB Interrupt Enable Register 2
USB Interrupt Enable Register 1
Symbol Address When reset
USBIE1 0304
16
FF
16
Bit nameBit symbol
b7 b6 b5 b4 b3 b2 b1 b0
Function W
R
Reserved Must always be set to "1"
INTEN0
INTEN2
INTEN3
INTEN4
INTEN5
INTEN6
INTEN7
USB Endpoint 0 Interrupt
Enable Bit
USB Endpoint 1 IN
Interrupt Enable Bit
USB Endpoint 1 OUT
Interrupt Enable Bit
USB Endpoint 2 IN
Interrupt Enable Bit
USB Endpoint 2 OUT
Interrupt Enable Bit
USB Endpoint 3 IN
Interrupt Enable Bit
USB Endpoint 3 OUT
Interrupt Enable Bit
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 :
Interrupt enabled
1
USB Interrupt Enable Register 2
Symbol Address When reset
USBIE2 030516 3316
Bit nameBit symbol
b7 b6 b5 b4 b3 b2 b1 b0
Function W
R
Reserved Must always be set to "0"
INTEN8
INTEN9
USB Endpoint 4 IN
Interrupt Enable Bit
USB Endpoint 4 OUT
Interrupt Enable Bit
USB Overrun/Underrun
Interrupt Enable Bit
0 : Interrupt disabled
1 : Interrupt enabled
INTEN12
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
Reserved Must always be set to "1"
Reserved Must always be set to "0"
0
0
1
0
0
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1.2.18.4.7 USB Frame Number Registers
The USB Frame Number Low Register, shown in Figure 1.38, contains the lower 8 bits of the 11-bit frame
number received from the host. The USB Frame Number High Register, shown in Figure 1.39 contains the
upper 3 bits of the 11-bit frame number received from the host.
Figure 1.38: USB Frame Number Low Register
Figure 1.39: USB Frame Number High Register
1.2.18.4.8 USB ISO Control Register
The USB ISO Control Register, shown in Figure 1.40, contains two global bits, ISO_UPD and AUTO_FL for
controlling endpoints 1-4 isochronous data transfer.
When ISO_ UPD = “0”, a data pa cket i n an e ndpoin t’s IN FI FO is alwa ys ‘re ady to tran smit ’ upon receiv ing th e
next IN_TOKEN from the host (with matched address and endpoint number) if the endpoint’s IN_PKT_RDY
is set.
When ISO_UPD = “1” and the ISO/TOGGLE_INIT bit of the corresponding endpoint’s IN CSR is set, the in-
ternal ‘rea dy to trans mit’ sign al to the trans mit control lo gic is no t activate d when the end point’s IN_PK T_RDY
is set. Instead, it is activa ted when the next SOF i s received, th is way, t he data loa ded in frame n is trans mitted
out in frame n+1. The ISO_UPD bit is a global bit for endpoints 1-4 and works with isochronous pipes only.
When AUTO_FL = “1”, ISO_UPD = “1”, a particular IN endpoint’s ISO/TOGGLE_INIT bit is set, and the IN
endpoint’s IN_PKT_RDY = “1”, the USB FCU detects a SOF packet and the USB FCU automatically flushes
the oldest packet from the IN FIFO. In this case, IN_PKT_RD Y = “1”, indicates that two data packets are in
the IN FIFO. Because double buffering is a requirement for ISO transfer, MAXP must be set to less than or
equal to 1/2 of the FIFO size.
Figure 1.40: USB ISO Control Register
USB Frame Number Low Register
Symbol Address When reset
USBSOFL 0306
16
00
16
Bit nameBit symbol
b7 b6 b5 b4 b3 b2 b1 b0
FN0 to FN7
Function WR
Lower 8 bits of the 11-bit
frame number issued with a
SOF token
X
USB Frame Number High Register
Symbol Address When reset
USBSOFH 0307
16
00
16
Bit nameBit symbol
b7 b6 b5 b4 b3 b2 b1 b0
FN8
FN9
FN10
Function WR
Upper 3 bits of the 11-bit
frame number issued with a
SOF token
Reserved Must always be set to "0"
X
X
0
0
0
0
0
USB ISO Control Register
Symbol Address When reset
USBISOC 0308
16
00
16
Bit name
Bit symbol
b7 b6 b5 b4 b3 b2 b1 b0
Function WR
Reserved Must always be set to "0"
AUTO_FL
ISO_UPD
AUTO_FLUSH Bit
ISO_UPDATE Bit
0 : Hardware auto FIFO flush diabled
1 : Hardware auto FIFO flush enabled
0 : ISO_UPDATE disabled
1 : ISO_UPDATE enabled
0
0
0
0
0
0
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1.2.18.4.9 USB DMAx Request Registers
The USB DM Ax Request Regis ters, shown in Fi gure 1.41 and F igure 1.42, are u sed to select w hich USB End-
point x FIFO read/write requests are s el ec ted as the DMAC channe l 0 or c han nel 1 request source. The USB
DMA0 (DMA1) Request Register should have only one bit set at any given time. When multiple bits are set,
no request is selected.
Figure 1.41: USB DMA0 Request Register
Figure 1.42: USB DMA1 Request Register
1.2.18.4.10 USB Endpoint Enable Register
The USB Endpoint Enable Register, shown in Figure 1.43, is used to enable/disable an individual endpoint.
Endpoint 0 is always enabled and cannot be disabled by firmware. All endpoints are enabled after reset.
Figure 1.43: USB Endpoint Enable Register
USB DMA0 Request Register
Symbol Address When reset
USBSAR0 0309
16
00
16
Bit nameBit symbol
b7 b6 b5 b4 b3 b2 b1 b0
Function W
R
DMA0R0
DMA0R1
DMA0R2
DMA0R3
DMA0R4
DMA0R5
DMA0R6
DMA0R7
Endpoint 1 IN FIFO write request selection bit
Endpoint 2 IN FIFO write request selection bit
Endpoint 3 IN FIFO write request selection bit
Endpoint 4 IN FIFO write request selection bit
Endpoint 1 OUT FIFO read request selection bit
Endpoint 2 OUT FIFO read request selection bit
Endpoint 3 OUT FIFO read request selection bit
Endpoint 4 OUT FIFO read request selection bit
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 : Not selected
1 :
Selected
USB DMA1 Request Register
Symbol Address When reset
USBSAR1 030A
16
00
16
Bit nameBit symbol
b7 b6 b5 b4 b3 b2 b1 b0
Function W
R
DMA1R0
DMA1R1
DMA1R2
DMA1R3
DMA1R4
DMA1R5
DMA1R6
DMA1R7
Endpoint 1 IN FIFO write request selection bit
Endpoint 2 IN FIFO write request selection bit
Endpoint 3 IN FIFO write request selection bit
Endpoint 4 IN FIFO write request selection bit
Endpoint 1 OUT FIFO read request selection bit
Endpoint 2 OUT FIFO read request selection bit
Endpoint 3 OUT FIFO read request selection bit
Endpoint 4 OUT FIFO read request selection bit
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 : Not selected
1 :
Selected
USB Endpoint Enable Register
Symbol Address When reset
USBEPEN 030B16 FF16
Bit nameBit symbol
b7 b6 b5 b4 b3 b2 b1 b0
Function W
R
EP1_OUT
EP1_IN
EP2_OUT
EP2_IN
EP3_OUT
EP3_IN
EP4_OUT
EP4_IN
Endpoint 1OUT FIFO Enable bit
Endpoint 1 IN FIFO Enable bit
Endpoint 2OUT FIFO Enable bit
Endpoint 2 IN FIFO Enable bit
Endpoint 3 OUT FIFO Enable bit
Endpoint 3 IN FIFO Enable bit
Endpoint 4 OUT FIFO Enable bit
Endpoint 4 IN FIFO Enable bit
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 : Disabled
1 :
Enabled
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1.2.18.4.11 USB Endpoint 0 Control and Status Register
The Endpoint 0 CSR (Control and Status Register), shown in Figure 1.44 contains the control and status in-
formation of Endpoint 0.
• EP0CSR0 (OUT_PKT_RDY):
The USB FCU sets this bit to a “1” after it receives a valid SETUP/OUT token from the host. The CPU clears this
bit after unloading the packet from the FIFO by writing a “1” to EP0CSR6. The CPU should not clear the
OUT_PKT_RDY bit before it finishes dec oding the host reques t. When EP0CSR2 (SEND_STALL) needs to be
set (because the CPU decodes an invalid or unsupported request) a “1” should be written to EP0CSR6 and
EP0CSR2 at the same time using the sam e instructio n.
• EP0CSR1 (IN_PKT_RDY):
The CPU w rit es a “1 ” to this bit after it fin is hes wri t ing a p acke t of d ata to the endpoint 0 FIFO . T he U S B FCU
clears this bit after the packet is successfully transmitted to the host, or the EP0CSR5 (SETUP_END) bit is set.
• EP0CSR2 (SEND_STALL):
The CPU writes a “1” to this bit when it decodes an invalid or unsupported standard device request from the
host. Wh en the OUT-PKT_ RDY bi t is a “1” at the ti me the CPU wa nts to set t he SEND_STAL L bit to a “1 ”, the
CPU must also set SERVICED_OUT _PKT_RDY to a “1” to clear the O UT-PKT_RDY at the same ti me as set-
ting the SEND_STALL b it. The U SB FCU returns a STALL handsha ke for al l subseq uent IN/OUT transa ctions
(during control transfer data or status stages) while this bit is set. The CPU writes a “0” to clear it after it re-
ceives a new SETUP packet. It is up to the firmware to decide what SETUP packet should lead the clearing
of the SEND_STALL bit.
• EP0CSR3 (DATA_END):
The CPU writes a “1” to this bit when it writes (IN data phase) or reads (OUT data phase) the last packet of
data to or from the FIFO. The CPU sets this bit at the same time as it sets the last IN_PKT_RDY bit or sets
the last SER VICED_OU T_PKT_RDY bit.Th is bit indi cates to the US B FC U th at the sp ecific am ount of d ata in
the setup pha se is transfe rred. The US B F CU adva nces to the stat us phase once thi s bit is set. Whe n the sta-
tus phase complete s, the USB FCU clears th is bit. When this bit is set to a “1”, an d the host reque sts or sends
more data, the USB FCU returns a STALL handshake and terminates the current control transfer.
• EP0CSR4 (FORCE_STALL):
The USB FCU sets this bit to a “1” to report an error status when one of the following occur:
• Host sends an IN to ken in the absence of a SETUP stage
• Host sends a bad data toggle in the STATUS stage, (i.e. DATA0 is used)
• Host sends a bad data toggle in the SETUP stage, (i.e. DATA1 is used)
• Host request more data than specified in the SETUP state,
• (i.e. IN token comes after DATA_END bi t is set)
• Host sends more data than specified in the SETUP state,
• (i.e. OUT token comes after DATA_END bit is set)
• Host sends larger data packet than MAXP size
All of the conditions stated (except bad data toggle in the SETUP stage) cause the device to send a STALL
handsha ke for the current IN/OUT t rans ac tio n. F or th e bad data toggle in th e SETU P s ta te, the device sends
ACK for the SETUP stage and then sends STALL for the next IN/OUT transaction. A STALL handshake
caused by the above listed conditions lasts for one transaction and terminates the ongoing control transfer.
Any packet after the STALL handshake will be seen as the beginning of a new control transfer.
The CPU writes a “0” to clear the FORCE_STALL status bit.
• EP0CSR5 (SETUP_END):
The USB FCU sets this bit to a “1” if a control transfer has ended before the specific length of data is trans-
ferred duri ng the data phase (st atus phas e starts before DATA_END b it is set) or a c ontrol tran sfer has e nded
before a new SETUP has arrived and before successfully completing the status phase. The CPU clears this
bit by wri ting a “ 1” to I N0CSR 7 . On ce the C PU dete cts the SETUP _ EN D flag as se t, it sh oul d stop accessing
the FIFO to service the prev ious set up transaction . If the SETUP_END is caused b y the recept ion of the SET-
UP packet prior to the end of the current control transfer, the OUT_PKT_RDY bit is set once the reception of
the SETUP packet has completed (without errors). After the OUT_PKT_RDY bit is set, the new SETUP packet
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data will be in the FIFO. For this case, because the SETUP_END bit is set near the beginning of the packet
when the SETUP PID is encountered and the OUT_PKT_RDY bit is set at the end of the packet, the value
read from EP0IN_C SR in the USB functional inte rrupt routine may onl y show that the SETUP_END flag as “1”
instead of both the SETUP_END and OUT_PKT_RDY bits.
•EP0CSR6 and EP0CSR7:
These bits are used to clear EP0CSR0 and EP0CSR5 respectively. Writing a “1” to these bits clears the cor-
responding register bit.
Figure 1.44: USB Endpoint 0 CSR
1.2.18.4.12 USB Endpoint 0 MAXP Register
The USB Endpoint 0 MAXP Register, shown in Figure 1.45, indicates the maximum packet size (MAXP) of
Endpoint 0 IN/OUT packet. The default value for Endpoint 0 MAXP is 8 bytes.
Figure 1.45: USB Endpoint 0 MAXP
USB Endpoint 0 Control and Status Register (Note 5)
Symbol Address When reset
EP0CS 031116 0016
Bit nameBit symbol
b7 b6 b5 b4 b3 b2 b1 b0
Function W
R
EP0CSR0
EP0CSR1
EPOCSR2
EPOCSR3
EP0CSR4
EPOCSR5
EP0CSR6
EPOCSR7
OUT_PKT_RDY Flag
IN_PKT_RDY Bit
SEND_STALL Bit
DATA_END Bit
FORCE_STALL Flag
SETUP_END Flag
SERVICED_OUT_PKY_RDY Bit
SERVICED_SETUP_END Bit
0 : Not ready
1 : Ready
0 : Not ready
1 : Ready
0 : No action
1 : Stall Endpoint 0 by CPU
0 : No action
1 : Last packet transferred from/to FIFO
0 : No action
1 : Stall Endpoint 0 by USB FCU
0 : No action
1 : Control transfer ended before specific
length of data transferred during data phase
0 : No change
1 : Clear the OUT_PKT_RDY bit (EPOCSR0)
0 : No change
1 : Clear the STUP-END bit (EP0CSR5)
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
Note 1: Read only
Note 2: Write "1" only or Read
Note 3: Write "0" only or Read
Note 4: Write only - Read "0"
Note 5: Refer to Section 1.5.5 "Programming Notes" for this register
Note 1
Note 1
Note 2
Note 3
Note 2
Note 4
Note 4
USB Endpoint 0 MAXP Register
Symbol Address When reset
EP0MP 0313
16
08
16
Bit nameBit symbol
b7 b6 b5 b4 b3 b2 b1 b0
EP0MXP0 to
EP0MXP5
Function WR
Maximum packet size (MAXP)
of Endpoint 0 IN/OUT packet
Reserved Must always be set to "0"
0
0
Universal Serial Bus
M30240 Group
Rev. H Sep 18, 2003 Page 56 of 139
1.2.18.4.13 USB Endpoint 0 OUT Write Count Register
The USB Endpoint 0 OUT Write Count (WRT CNT) Register, shown in Figure 1.46, contains the number of
byt es o f th e cu rr en t d ata se t i n t he OUT FI FO . The USB FCU sets the value in the Write Count Register after
having successfully received a packet of data from the host. The CPU reads the register to determine the number
of bytes to be read from the FIFO.
Figure 1.46: USB Endpoint 0 OUT WRT CNT
1.2.18.4.14 USB Endpoint x IN Control and Status Register
The USB Endpoin t x IN C SR (Co ntrol a nd Statu s Regi ster), s hown in Figure 1.47, contai ns c ontrol a nd st atus
information of the respective IN endpoint 1-4.
•INxCSR0 (IN_PKT_RDY) and INxCSR5 (TX_FIFO_NOT_EMPTY):
These t wo b its are for IN FIFO status when in rea d o per atio n (se e “IN (Trans mit ) FIFO” operation fo r d etai ls ).
The CPU writes a “1” to the INxCSR0 bit to inform the USB FCU that a packet of data is written to the FIFO.
The USB FCU updat es the p ointers up on th is bit set. The USB FCU also upda tes the p ointers upon a packe t
of data successfully sent to the host. When the pointer updates are completed, the IN FIFO status is shown
on INxCSR 0 and INxCSR 5 bits for the CPU to rea d. The CPU mu st allow at l east one wai t state betw een writ-
ing and reading these bits for proper FIFO status.
• INxCSR1 (UNDER_RUN):
This bit is used in ISO mode only to indicate to the CPU that a FIFO underrun has occurred. The USB FCU
sets th is bi t t o a “1 ” at the beginning of an IN token if no da ta pac k et is in th e F I FO. Se tti ng this bit caus es th e
INST12 bit of the Interrupt Status Register 2 to set. The CPU writes a “0” to clear this bit.
• INxCSR2 (SEND_STALL):
The CPU w rites a “1” to this bit w hen the e ndpoin t is s talled (transm itter h alt). Th e USB FCU re turns a STALL
handshake while this bit is set. The CPU writes a “0” to clear this bit.
• INxCSR3 (ISO/TOGGLE_INIT):
When the endpoint is used for isochronous data transfer, the CPU sets this bit to a “1” for the entire duration
of the is ochronou s transfe r. With the ISO bit s et to a “1 ”, the devic e uses DAT A0 as t he pid fo r all packe ts sent
back to the host.
When the endpoint is required to initialize the data toggle, this set/reset of the TOGGLE_INIT bit method as-
sumes tha t there is no activity IN transaction to the respectiv e endpoint on the bus at the time the initializatio n
process is ongoing. Set/reset of the TOGGLE_INIT bit is performed only when an endpoint experiences a con-
figuration event.
•INxCSR4 (INTPT):
The CPU write s a “1” to this bit to init ializ e this end point as a statu s chang e endpoi nt for IN transac tions . This
bit is set only when the corresponding end poi nt is to be used to communicate rate feedbac k info rma tio n (se e
Chapter. IN (Transmit) FIFOs for details).
•INxCSR5 (TX_FIFO_NOT_EPT):
The USB FCU se ts this bit to a “1” when there is at least one data packet in the IN FIFO. This bit, in conjunction
with IN_PKT_RDY b it, prov ides the transm it IN FIF O sta tus inform ation (see “I N (Transm it) FIFO” f or detai ls).
• INxCSR6 (FLUSH):
USB Endpoint 0 OUT Write Count Register
Symbol Address When reset
EP0WC 031516 0016
Bit nameBit symbol
b7 b6 b5 b4 b3 b2 b1 b0
W_CNT0 to
W_CNT4
Function WR
Receive byte count
Reserved Must always be set to "0" X
X
0
0
0
Universal Serial Bus
M30240 Group
Rev. H Sep 18, 2003 Page 57 of 139
The CPU w rite s a “1” to this bit to flush the IN FIFO . W hen the r e is one packet in the IN FIFO , a flus h c au ses
the IN FIFO to be empty. When there are two packets in the IN FIFO, a flush causes the older packet to be
flushed out from the IN FIFO . Setting t he INXCSR6 ( FLUSH) bit during tran smission could p roduce unpredict-
able results.
• INxCSR7 (AUTO_SET):
When the CPU sets this bit to a “1”, the IN_PKT_RDY bit is set automatica lly by the USB FCU after the nu mber
of bytes of data equal to the maximum packet size (MAXP) is written into the IN FIFO (see “IN (Transmit)
FIFO” operati on for deta ils).
Figure 1.47: USB Endpoint x IN CSR
1.2.18.4.15 USB Endpoint x OUT Control and Status Register
The USB Endpoi nt x OUT CSR (Control an d Status R egiste r), shown in Fi gure 1.48 co ntains control and sta-
tus information of the respective OUT Endpoint 1-4.
•OUTxCSR0 ( OUT_PKT _RDY):
The OUTxCSR0 bit for the OUT FIFO status (see “OUT (Receive) FIFOs” for details).
The USB FCU sets this bit to a “1” and updates the FIFO pointers after a data packet has been successfully
received from the host. The CPU writes a “0” to this bit to inform the USB FCU that a data packet has been
unloade d. The USB FCU upd ates the FIFO poin ters when thi s occurs. The C PU must allow at lea st one clock
cycle between writing and reading bit OUTxCSR0.
• OUTXxCSR1 (OVER_RUN):
This bit is used in ISO mode only to indicate to the CPU that a FIFO overrun has occurred. The USB FCU sets this
bit to a “1” at the beginning of an OUT token when two data packets are already present in the FIFO. Setting
this bit causes the INST12 bit of the Interrupt Status Register 2 to set. The CPU writes a “0” to clear
OUTXCSR1.
• OUTxCSR2 (SEND_STALL):
The CPU wri tes a “1” to this bit when the end point is st alled. The USB FC U returns a STALL h andshake while
this bit is set. The CPU writes a “0” to clear this bit.
• OUTxCSR3 (ISO/TOGGLE_INIT):
When the endpoint is used for isochronous data transfer, the CPU sets this bit to a “1” for the entire duration
of the isochronous transfer. With the ISO/TOGGLE_INIT bit set to a “1”, the device accepts either DATA0 or
DATA1 for the PID sent by the host.
USB Endpoint x IN Control and Status Register (Note 5)
Symbol Address When reset
EPiICS (i= 1-4) 0319
16,
0321
16,
0329
16,
0331
16
00
16
Bit nameBit symbol
b7 b6 b5 b4 b3 b2 b1 b0
Function W
R
INxCSR0
INxCSR1
INxCSR2
INxCSR3
INxCSR4
INxCSR5
INxCSR6
INxCSR7
IN_PKT_RDY Bit
UNDER_RUN Flag
SEND_STALL Bit
ISO Bit
INTPT
TX_NOT_EPT Flag
FLUSH Bit
AUTO_SET Bit
0 : Not ready
1 : Ready
0 : No FIFO underrun
1 : FIFO underrun has occured
0 : No action
1 : Stall IN Endpoint x by CPU
0 : Select non-isochronous transfer
1 : Select isochronous transfer
0 : Select non-rate feedback interrupt transfer
1 : Select rate feedback interrupt transfer
0 : Transmit FIFO is empty
1 : Transmit FIFO is not empty
0 : No action
1 : Flush the FIFO
0 : AUTO-SET disabled
1 : AUTO-SET enabled
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
Note 1: Write "1" only or read
Note 2: Write "0" only or read
Note 3: Read only
Note 4: Write only - Read "0"
Note 5: Refer to section 1.5.5
"Programming Notes" for this register
Note 1
Note 2
Note 3
Note 4
Universal Serial Bus
M30240 Group
Rev. H Sep 18, 2003 Page 58 of 139
When endp oint is requi red to initiali ze the data tog gle sequenc e bit (i.e. reset to DATA0 for the n ext data pack-
et), the CPU sets this bit to a “1” and then resets it to a “0” to initialize the respective endpoint’s data toggle.
Successful initialization of the data toggle sequence bit can only be guaranteed if no active OUT transaction
to the respective endpoint is ongoing when the initialization process is taking place. Set/reset of the ISO/
TOGGLE_INIT bit should only be performed when an endpoint experiences a configuration event.
•OUTxCSR4 (FORCE_STALL):
The USB FCU sets this bit to a “1” when the host sends out a larger data packet than the MAXP size. The
USB FCU returns a STALL handshake while this bit is set. The CPU writes a “0” to clear this bit.
• OUTxCSR5 (DATA_ERR):
The USB FCU sets this bit to a “1” to indicate that a CRC error or a bit stuffing error was received in an ISO
packet. The CPU writes a “0” to clear this bit.
• OUTxCSR6 (FLUSH):
The CPU w rites a “1” to this to flu sh the OUT FIFO. W hen there is one packet in the O UT FIFO, a flush cau ses
the OUT FIFO to b e em pty . Wh en th ere a r e two p ac ket s in the OUT FIFO, a flush cause s the ol der packet to
be flushed out from the OUT FIFO. Setting the OUTXCSR6 (FLUSH) bit during reception could produce un-
predictable results.
•OUTxCSR7 (AUTO_CLR):
When the C PU sets thi s bit to a “1”, the OUT_PKT_RDY bit is clea red automat ically b y the USB FCU af ter the
number of bytes of data equal to the maximum packet size (MAXP) is unloaded from the OUT FIFO (see “OUT
(Receive) FIFO” for details).
Figure 1.48: USB Endpoint x OUT CSR
1.2.18.4.16 USB Endpoint x IN MAXP Register
The USB Endp oint x IN MAXP Reg ister, sh own in Figure 1.49, i ndicates the m aximum pac ket siz e (MAXP) of
an Endpoint x IN packet. The default values for Endpoints 1-4 are 0 bytes. The setting of this register also
affects the configuration of single/dual packet operation. When MAXP > 1/2 of the FIFO size, single packet
mode is set. When MAXP <= 1/2 of the FIFO size, dual packet mode is set.
Figure 1.49: USB Endpoint x IN MAXP
USB Endpoint x OUT Control and Status Register (Note 3)
Symbol Address When reset
EPiOCS (i = 1-4) 031A16, 032216, 032A16, 033216 0016
Bit nameBit symbol
b7 b6 b5 b4 b3 b2 b1 b0
Function W
R
OUTxCSR0
OUTxCSR1
OUTxCSR2
OUTxCSR3
OUTxCSR4
OUTxCSR5
OUTxCSR6
OUTxCSR7
OUT_PKT_RDY Flag
OVER_RUN Flag
SEND_STALL Bit
ISO Bit
FORCE-STALL Flag
DATA-ERR Flag
FLUSH Bit
AUTO_CLR Bit
0 : Not ready
1 : Ready
0 : No FIFO overrun
1 : FIFO overrun occured
0 : No action
1 : Stall OUT Endpoint x by CPU
0 : Select non-isochronous transfer
1 : Select isochronous transfer
0 : No action
1 : Stall Endpoint X by the USB FCU
0 : No error
1 : CRC or bit stuffing error received in ISO packet
0 : No action
1 : Flush the FIFO
0 : AUTO-CLR disabled
1 : AUTO-CLR enabled
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
Note 1: Write "0" only or read
Note 2: Write only - Read "0"
Note 3: Refer to section 1.5.5 "Programming Notes" for this register
Note 1
Note 2
Note 1
Note 1
Note 1
USB Endpoint x IN MAXP Register
Symbol Address When reset
EPiIMP (i = 1-4) 031B16, 032316, 032B16, 033316 0016
Bit nameBit symbol
b7 b6 b5 b4 b3 b2 b1 b0
IMAXP0 to
IMAXP7
Function WR
Maximum packet size
(MAXP) of Endpoint x IN
packet.
For endpoints that support smaller
FIFO size, unused bits are not
implemented, (always write "0" to
these bits).
Universal Serial Bus
M30240 Group
Rev. H Sep 18, 2003 Page 59 of 139
1.2.18.4.17 USB Endpoint x OUT MAXP Register
The USB Endp oint x OUT MAXP Register, s hown i n Figure 1.50, i ndica tes the m aximum packet size (M AXP)
of an Endpoi nt x OUT packet . The default val ues for endpoin ts 1-4 are 0 bytes. The setting of this re gister also
affects the c onf igu r ati on of si ngl e/d ual pa ck et op erati on . Wh en M AXP > 1/2 of the FIFO size, sin gl e p acket is
set. When MAXP <= 1/2 of the FIFO size, dual packet mode is set.
Figure 1.50: USB Endpoint x OUT MAXP
1.2.18.4.18 USB Endpoint x OUT Write Count Register
The USB Endpoint x OUT Write Count (WRT CNT) Register, shown in Figure 1.51, contains the number of
byt es o f th e cu rr en t d ata se t i n t h e O UT FI F O. The USB FCU sets the value in the Write Count Register after
having successfully received a packet of data from the host. The CPU reads the register to determine the number
of bytes to be read from the FIFO.
Figure 1.51: USB Endpoint x OUT WRT CNT
1.2.18.4.19 USB Endpoint x FIFO Register
The U SB Endpo int x FIF O Regis ter, show n in Fig ure 1.52 i s the USB IN (transmit) and OUT (receive) FIFO
data register. The CPU writes data to this regis ter for the correspond ing Endpoint IN FIFO and reads d ata from
this register for the corresponding Endpoint OU T FIFO.
Figure 1.52: USB Endpoint x FIFO Register
USB Endpoint x OUT MAXP Register
Symbol Address When reset
EPiOMP (i = 1-4) 031C
16,
0324
16,
032C
16,
0334
16
00
16
Bit nameBit symbol
b7 b6 b5 b4 b3 b2 b1 b0
OMAXP0
to
OMAXP7
Function WR
Maximum packet size
(MAXP) of Endpoint x
OUT packet.
For endpoints that support smaller
FIFO size, unused bits are not
implemented, (always write "0" to
these bits).
USB Endpoint x OUT Write Count Register
Symbol Address When reset
EPiWC (i = 1-4) 031D
16,
0325
16,
032D
16,
0335
16
00
16
Bit nameBit symbol
b7 b6 b5 b4 b3 b2 b1 b0
W_CNT0
to
W_CNT7
Function WR
Receive Byte Count
X
USB Endpoint x FIFO Register
Symbol Address When reset
EPi (i = 0-4) 0338
16,
0339
16,
033A
16,
033B
16,
033C
16
Indeterminate
Bit name
Bit symbol
b7 b6 b5 b4 b3 b2 b1 b0
DATA_0
to
DATA_7
Function WR
Endpoint x IN/OUT FIFO
O
DMAC
M30240 Group
Rev. H Sep 18, 2003 Page 60 of 139
1.2.19 DMAC
This mic ro compu ter has two DMA C (di rec t mem or y acce ss co ntr ol ler) ch anne ls that allo w data to be
sent to memory without using the CPU.Table 1.15 shows the DMAC specifications. Figure 1.53 shows
the block diagram of the DMAC. Figure 1.54, Figure 1.55 and Figure 1.56 show the registers used by
the DMAC.
Table 1.15: DMAC Specifications
Note: DMA transfers are not affected by the interrupt enable flag (I-FLAG) of any interrupt or by the interrupt priority level.
Item Specification
Number of channels 2 (cycle steal method)
Transfer memory space
•From any SFR, RAM, or ROM address to a fixed address
•From a fixed address to any SFR or RAM address
•From a fixed address to a fixed address
(Note that DMA-related registers [002016 to 003F16] cannot be accessed)
Maximum number of bytes
transferred 128K bytes (with 16-bit transfers) or 64K bytes (with 8-bit transfers)
DMA request sources
Falling edge of INT0 or INT1 (INT0 can be selected by DMA0, INT1 by DMA1)
Timer A0 to ti mer A4
Timer B0 to ti mer B1
UART0 transmission and reception
UART1 transmission and reception
UART2 transmission and reception
A-D conversion complete
USB function
Software triggers
Channel priority DMA0 takes precedence if DMA0 and DMA1 requests are generated simultaneously
Transfer unit 8 bits or 16 bits
Transfer address direction forward/fixed (forward direction cannot be specified for both source and destination
simultaneously)
Transfer modes
•Single transfer mode
The DMA enable bit is cleared and transfer ends when an underflow occurs in the
t rans fer counter.
•Repeat transfer mode
When an underflow occurs in the transfer counter, the value in the transfer counter
reload register is loaded into the transfer counter and the DMA transfer is repeated
DMA interrupt request generation
timing When an underflow occurs in the transfer counter
DMA startup
•Single transfer mode
Transfer starts when the DMA is requested after “1” is written to the DMA enable bit
•Repeat transfer mode
Transfer starts when the DMA is requested after “1” is written to the DMA enable bit
or after an underflow occurs in the transfer counter
DMA shutdown •When “0” is written to the DMA enable bit
•When, in single transfer mode, an underflow occu rs in the transfer counter
Forward address pointer and
reload timing for transfer counter
When DMA transfer starts, the value of whichever of the source or destination pointer that is set
up as the forward pointer is loaded into the forward address pointer. The value in the transfer
counter reload register is loaded into the transfer counter.
Writing to register Reg isters specified for forward direction transfer are always write-enabled.
Registers specified for fixed address transfer are write-enabled when the DMA enable bit is “0”.
Reading the register Can be read at any time. However , when the DMA enable bit is “1”, reading the register set s up
as the forward register is the same as reading the value of the forward address pointer.
DMAC
M30240 Group
Rev. H Sep 18, 2003 Page 61 of 139
Figure 1.53: Block diagram of DMAC
Figure 1.54: DMAC register (1)
Data bus low-order bits
DMA latch high-order bits DMA latch low-order bits
DMA0 source pointer SAR0(20)
DMA0 destination pointer DAR0 (20)
DMA0 forward address pointer (20)
Data bus high-order bits
Address bus
DMA1 destination pointer DAR1 (20)
DMA1 source pointer SAR1 (20)
DMA1 forward address pointer (20)
DMA0 transfer counter reload register TCR0 (16)
DMA0 transfer counter TCR0 (16)
DMA1 transfer counter reload register TCR1 (16)
DMA1 transfer counter TCR1 (16)
(addresses 0029
16
, 0028
16
)
(addresses 0039
16
, 0038
16
)
(addresses 0022
16
to 0020
16
)
(addresses 0026
16
to 0024
16
)
(addresses 0032
16
to 0030
16
)
(addresses 0036
16
to 0034
16
)
Note: Pointer is incremented by
a
a DMA request.
(Note)
(Note)
DMAi request cause select register
Symbol Address When reset
DMiSL (i=0,1) 03B8
16
, 03BA
16
00
16
Function (Note)
Bit symbol
b7 b6 b5 b4 b3 b2 b1 b0
DMA request cause
select bits
DSEL0
RW
DSEL1
DSEL2
DSEL3
Nothing is assigned.
Software DMA
request bit
If software trigger is selected, a DMA request is generated by
setting this bit to “1” (When read, the value of this bit is always “0”)
DSR
b3 b2 b1 b0
0 0 0 0 : Falling edge of INT0 /INT1pin (Note 1)
0 0 0 1 : Software trigger
0 0 1 0 : Timer A0
0 0 1 1 : Timer A1
0 1 0 0 : Timer A2
0 1 0 1 : Timer A3
0 1 1 0 : Timer A4
0 1 1 1 : Timer B0
1 0 0 0 : Timer B1
1 0 0 1 :
1 0 1 0 : UART0 transmit
1 0 1 1 : UART0 receive
1 1 0 0 : UART2 transmit
1 1 0 1 : UART2 receive
1 1 1 0 : A-D conversion
1 1 1 1 : UART1 transmit/UART receive (Note 2)
Bit name
Write "0" when writing to these bits. If read, the value is "0".
USB0/USB1 (Note 3)
Note 1: Address 03B8
16
is for INT0, 3BA
16
is for INT1.
Note 2: Address 03B8
16
is for UART1 transmit, 03BA
16
is for UART1 receive.
Note 3: Address 03B8
16
is for USB0, 03BA
16
is for USB1.
DMAC
M30240 Group
Rev. H Sep 18, 2003 Page 62 of 139
Figure 1.55: DMAC register (2)
DMAi control register
Symbol Address When reset
DMiCON(i=0,1) 002C16, 003C16 00000X002
Bit name FunctionBit symbol
Transfer unit bit select bit
b7 b6 b5 b4 b3 b2 b1 b0
0 : 16 bits
1 : 8 bits
DMBIT
RW
DMASL
DMAS
DMAE
Repeat transfer mode
select bit
0 : Single transfer
1 : Repeat transfer
DMA request bit (Note 1) 0 : DMA not requested
1 : DMA requested
0 : Disabled
1 : Enabled
0 : Fixed
1 : Forward
DMA enable bit
Source address direction
select bit (Note 3)
Destination address
direction select bit (Note 3) 0 : Fixed
1 : Forward
DSD
DAD
Nothing is assigned.
Note 1: DMA request can be cleared by resetting the bit.
Note 2: This bit can only be set to “0”.
Note 3: Source address direction select bit and destination address direction select bit
cannot be set to “1” simultaneously.
(Note 2)
Write "0" when writing to these bits. If read, the value is "0".
DMAC
M30240 Group
Rev. H Sep 18, 2003 Page 63 of 139
Figure 1.56: DMAC register (3)
• Transfer cycle
The transfe r c ycle consi sts of the bus cyc le in which data is read from memory or from the SFR are a
(sou rce re ad) and the bus cycle in wh ich the data is writte n to memo ry or to the SFR ar ea (des tinat ion
write). The number of read and write bus cycles depends on the source and destination addresses
and the software waits are inserted.
• Effect of source and destination addresses
When 16-b it data is trans ferred on a 16-b it data bus, an d the source an d destinatio n both start at o dd address-
es, ther e is one more so urce read cycl e and destinati on write cycl e than when the sou rce and dest ination both
start at even addresses.
• Calculations
Any combination of even or odd transfer read and write addresses is possible. Table 1.16 show the number
of DMAC transfer cycles. Table 1.17 shows the corresponding coefficient values. Figure 1.57 shows an ex-
ample of the transfer cycle for a source read.
The number of DMAC transfer cycles can be calculated as follows:
b7 b0 b7 b0
(b8)(b15)
Function
RW
• Transfer counter
Set a value one less than the transfer count
Symbol Address When reset
TCR0 002916, 002816 Indeterminate
TCR1 003916, 003816 Indeterminate
DMAi transfer counter (i = 0, 1)
Transfer count
specification
000016 to FFFF16
b7
(b23)
b3 b0 b7 b0 b7 b0
(b8)(b16)(b15)(b19)
Function
RW
• Source pointer
Stores the source address
Symbol Address When reset
SAR0 002216 to 002016 Indeterminate
SAR1 003216 to 003016 Indeterminate
DMAi source pointer (i = 0, 1)
Transfer count
specification
0000016 to FFFFF16
Nothing is assigned.
Symbol Address When reset
DAR0 002616 to 002416 Indeterminate
DAR1 003616 to 003416 Indeterminate
b3 b0 b7 b0 b7 b0
(b8)(b15)(b16)(b19)
Function
RW
• Destination pointer
Stores the destination address
DMAi destination pointer (i = 0, 1)
Transfer count
specification
0000016 to FFFFF16
b7
(b23)
Nothing is assigned.
Write "0" when writing to these bits. If read, the value is "0".
Write "0" when writing to these bits. If read, the value is "0".
DMAC
M30240 Group
Rev. H Sep 18, 2003 Page 64 of 139
Number of transfer cycles per transfer unit = Number of read cycles x j + Number of write cycles x k
Figure 1.57: Example of the transfer cycle for a source read
Table 1.16: Number of DMAC transfer cycles
Transfer unit Acces s address Single-chip mode
Number of read cycles Number of write cycles
8-bit tran sfe rs (DMB IT= ”1”) Even 1 1
Odd 1 1
16-bit transfers (DMBIT=”0”) Even 1 1
Odd 2 2
Table 1.17: Coefficients j,k
Internal memory
Internal ROM/RAM No wait Internal ROM/RAM with wait SFR area
122
Internal
clock Φ
Address
bus
Data
bus
CPU use
CPU use CPU use
CPU useSource
Source
Destination
Destination
(1) 8-bit transfers
16-bit transfers from even address and the source address is even.
Address
bus
Data
bus
CPU use
CPU use CPU use
CPU useSource
Source
Destination
Destination
(3) One wait is inserted into the source read under the conditions in (1)
Address
bus
Data
bus
CPU use
CPU use CPU use
CPU useSource
Source
Destination
Destination
Source + 1
Source + 1
(2) 16-bit transfers and the source address is odd
Address
bus
Data
bus
CPU use
CPU use CPU use
CPU useSource
Source
Destination
Destination
Source + 1
Source + 1
(4) One wait is inserted into the source read under the conditions in (2)
Note : The same timing changes occur with the respective conditions at the destination as at the source.
(When 16-bit data is transfferred on an 8-bit data but, there are two destination write cycles.)
Internal
clock Φ
Internal
clock Φ
Internal
clock Φ
Timers
M30240 Group
Rev. H Sep 18, 2003 Page 65 of 139
1.2.20 Timers
There a re ei ght 16 -bit timer s. T he se timer s can be c lass ifi ed by functio n i nto time rs A ( fi ve) an d ti me rs
B (three). All these timers function independently. Figure 1.58 shows the block diagram of T imers A and
B.
Figure 1.58: Timer A and Timer B block diagram
Timer A3 interrupt
Timer A4 interrupt
Timer A1 interrupt
Timer A2 interrupt
Timer A0 interrupt
Timer B1 interrupt
• Timer mode
• One-shot mode
• PWM mode
• Timer mode
• One-shot mode
• PWM mode
• Timer mode
• One-shot mode
• PWM mode
• Timer mode
• One-shot mode
• PWM mode
• Timer mode
• One-shot mode
• PWM mode
• Event counter mode
• Event counter mode
• Event counter mode
• Event counter mode
• Event counter mode
TA 0 IN
TA 1 IN
TA 2 IN
TA 3 IN
TA 4 IN
Timer A0
Timer A1
Timer A2
Timer A3
Timer A4
f1 f8f32
Noise
filter
Noise
filter
Noise
filter
Noise
filter
Noise
filter
1/8
1/4
f1
f8
f32
XIN
Timer B0 interrupt
• Timer mode
• Timer mode
• Timer mode
Timer B0
Timer B1
Timer B2
Timer B2
overflow
Timer A
M30240 Group
Rev. H Sep 18, 2003 Page 66 of 139
1.2.21 Timer A
Figure 1.59, Figure 1.60,Figure 1.61, and Figure 1.62 show the timer A-related registers.
Except in event counter mode, timers A0 through A4 all have the same function. Use the timer Ai mode
register (i = 0 to 4) bits 0 and 1 to choose the desired mode.
Timer A has the four operation modes listed as follows:
• Timer mode: The timer counts an internal count source.
• Event counter mode: The timer counts pulses from an external source or a timer over flow.
• One-shot timer mode: The timer stops counting when the count reaches “000016”.
• Pulse width modulation (PWM) mode: The timer outputs pulses of a given width.
Figure 1.59: Block diagram of Timer A
Figure 1.60: Timer A related Registers (1)
Count start flag
(Address 0380
16
)
Up count/down count
TA i
Addresses TAj TAk
Timer A0 0387
16
0386
16
Timer A4 Timer A1
Timer A1 0389
16
0388
16
Timer A0 Timer A2
Timer A2 038B
16
038A
16
Timer A1 Timer A3
Timer A3 038D
16
038C
16
Timer A2 Timer A4
Timer A4 038F
16
038E
16
Timer A3 Timer A0
Always down count except
in event counter mode
Reload register (16)
Counter (16)
Low-order
8 bits
High-order
8 bits
Clock source
selection
• Timer
(gate function)
• Timer
• One shot
• PWM
f
1
f
8
f
32
External
trigger
TA i
IN
(i = 0 to 4)
TB2 overflow
• Event counter
Clock selection
TAj overflow
(j = i – 1. Note that j = 4 when i = 0)
Pulse output
Toggle flip-flop
TA i
OUT
(i = 0 to 4)
Data bus low-order bits
Data bus high-order bits
Up/down flag
Down count
(Address 0384
16
)
TAk overflow
Polarity
selection
(k = i + 1. Note that k = 0 when i = 4)
Timer Ai mode register
Symbol Address When reset
TAiMR(i=0 to 4) 0396
16
to 039A
16
00
16
Bit name FunctionBit symbol WR
b7 b6 b5 b4 b3 b2 b1 b0
Operation mode
select bit
0 0 : Timer mode
0 1 : Event counter mode
1 0 : One-shot timer mode
1 1 : Pulse width modulation (PWM) mode
b1 b0
TMOD1
TMOD0
MR0
MR2
MR1
MR3
TCK1
TCK0 Count source select bit
Function varies with each operation mode
Function varies with each operation mode
Timer A
M30240 Group
Rev. H Sep 18, 2003 Page 67 of 139
Figure 1.61: Timer A-related registers (2)
Timer A4 up/down flag
Timer A3 up/down flag
Timer A2 up/down flag
Timer A1 up/down flag
Timer A0 up/down flag
Timer A2 two-phase pulse
signal processing select bit
Timer A3 two-phase pulse
signal processing select bit
Timer A4 two-phase pulse
signal processing select bit
Symbol Address When reset
UDF 0384
16
00
16
TA 4 P
TA 3 P
TA 2 P
Up/down flag
Bit name FunctionBit symbol WR
b7 b6 b5 b4 b3 b2 b1 b0
TA4UD
TA3UD
TA2UD
TA1UD
TA0UD 0 : Down count
1 : Up count
This specification becomes valid
when the up/down flag content is
selected for up/down switching
cause
0 : two-phase pulse signal
processing disabled
1 : two-phase pulse signal
processing enabled
When not using the two-phase
pulse signal processing function,
set the select bit to “0”
Symbol Address When reset
TABSR 0380
16
00
16
Count start flag
Bit name FunctionBit symbol WR
b7 b6 b5 b4 b3 b2 b1 b0
Timer B2 count start flag
Timer B1 count start flag
Timer B0 count start flag
Timer A4 count start flag
Timer A3 count start flag
Timer A2 count start flag
Timer A1 count start flag
Timer A0 count start flag 0 : Stops counting
1 : Starts counting
TB2S
TB1S
TB0S
TA 4 S
TA 3 S
TA 2 S
TA 1 S
TA 0 S
Symbol Address When reset
TA0 0387
16
,0386
16
Indeterminate
TA1 0389
16
,0388
16
Indeterminate
TA2 038B
16
,038A
16
Indeterminate
TA3 038D
16
,038C
16
Indeterminate
TA4 038F
16
,038E
16
Indeterminate
b7 b0 b7 b0
(b15) (b8)
Timer Ai register (Note)
WR
• Timer mode 0000
16
to FFFF
16
Counts an internal count source
Function
Values that can be set
• Event counter mode 0000
16
to FFFF
16
Counts pulses from an external source or timer overflow
• One-shot timer mode 0000
16
to FFFF
16
Counts a one shot width
• Pulse width modulation mode (16-bit PWM)
Functions as a 16-bit pulse width modulator
• Pulse width modulation mode (8-bit PWM)
Timer low-order address functions as an 8-bit
prescaler and high-order address functions as an 8-bit
pulse width modulator
00
16
to FE
16
(Both high-order
and low-order
addresses)
0000
16
to FFFE
16
Note: Read and write data in 16-bit units.
Timer A
M30240 Group
Rev. H Sep 18, 2003 Page 68 of 139
Figure 1.62: Timer A-related registers (3)
TA1TGL
Symbol Address When reset
TRGSR 0383
16
00
16
Timer A1 event/trigger
select bit
0 0 : Input on TA1
IN
is selected (Note)
0 1 : TB2 overflow is selected
1 0 : TA0 overflow is selected
1 1 : TA2 overflow is selected
Trigger select register
Bit name FunctionBit symbol
b7 b6 b5 b4 b3 b2 b1 b0
0 0 : Input on TA2
IN
is selected (Note)
0 1 : TB2 overflow is selected
1 0 : TA1 overflow is selected
1 1 : TA3 overflow is selected
0 0 : Input on TA3
IN
is selected (Note)
0 1 : TB2 overflow is selected
1 0 : TA2 overflow is selected
1 1 : TA4 overflow is selected
0 0 : Input on TA4
IN
is selected (Note)
0 1 : TB2 overflow is selected
1 0 : TA3 overflow is selected
1 1 : TA0 overflow is selected
Timer A2 event/trigger
select bit
Timer A3 event/trigger
select bit
Timer A4 event/trigger
select bit
WR
TA1TGH
TA2TGL
TA2TGH
TA3TGL
TA3TGH
TA4TGL
TA4TGH
b1 b0
b3 b2
b5 b4
b7 b6
Note: Set the corresponding port direction register to “0”.
TA1OS
TA2OS
TA0OS
One-shot start flag
Symbol Address When reset
ONSF 0382
16
00X00000
2
Timer A0 one-shot start flag
Timer A1 one-shot start flag
Timer A2 one-shot start flag
Timer A3 one-shot start flag
Timer A4 one-shot start flag
TA3OS
TA4OS
Bit name FunctionBit symbol
b7 b6 b5 b4 b3 b2 b1 b0
TA0TGL
TA0TGH
0 0 : Input on TA0
IN
is selected (Note)
0 1 : TB2 overflow is selected
1 0 : TA4 overflow is selected
1 1 : TA1 overflow is selected
Timer A0 event/trigger
select bit
b7 b6
Note: Set the corresponding port direction register to “0”.
WR
1 : Timer start
When read, the value is “0”
Nothing is assigned.
Write "0" when writing to this bit. When read, the value is indeterminate.
Timer A
M30240 Group
Rev. H Sep 18, 2003 Page 69 of 139
1.2.21.1 Timer mode
In this mod e, the tim er counts an inter nally ge nerate d count source. S ee Table 1 .18 below. Figure
1.63 shows the timer Ai mode register in timer mode.
Figure 1.63: Timer Ai mode register in timer mode
Table 1.18: Specifications of timer mode
Item Specification
Count source f1, f8, f32
Count ope rati on • Down count
• When the timer underflows, it loads the reload register contents before continuing counting
Divide ratio 1/(n+1) n: Set value
Count st a r t
condition Count start flag is set (= 1)
Count sto p
condition Count start flag is reset (= 0)
Interrupt request
generati on tim ing When the timer underflows
TAiIN pin function Programmable I/O port or gate input
TAiOUT pin function Programmable I/O port or pulse output
Read from timer Count value can be read out by reading timer Ai register
Write to timer
• When co unting is stopped a nd a value is writte n to timer Ai regi ster, it is written to both reload
register and counter
• When counting is in progress and a value is written to timer Ai register, it is written only to
reload register (to be transferred to counter at the next reload time)
Select function
• Gate function
Counting can be started and stopped by TAiIN pin’s input signal
• Pulse output function
Each time the timer underflows, the TAiOUT pin’ s pol arity is reverse d
Note 1: The settings of the corresponding port register and port direction register
are invalid.
Note 2: The bit can be “0” or “1”.
Note 3: Set the corresponding port direction register to “0”.
Timer Ai mode register
Symbol Address When reset
TAiMR(i=0 to 4) 039616 to 039A16 00
16
Bit name FunctionBit symbol WR
b7 b6 b5 b4 b3 b2 b1 b0
Operation mode
select bit 0 0 : Timer mode
b1 b0
TMOD1
TMOD0
MR0 Pulse output function
select bit
0 : Pulse is not output
(TA
iOUT
pin is a normal port pin)
1 : Pulse is output (Note 1)
(TA
iOUT
pin is a pulse output pin)
Gate function select bit 0 X
(Note 2)
: Gate function not available
(TAi
IN
pin is a normal port pin)
1 0 : Timer counts only when TA
iIN
pin is
held “L” (Note 3)
1 1 : Timer counts only when TA
iIN
pin is
held “H” (Note 3)
b4 b3
MR2
MR1
MR3 0 (Must always be fixed to “0” in timer mode)
0 0 : f
1
0 1 : f
8
1 0 : f
32
1 1 : Reserved
b7 b6
TCK1
TCK0
Count source select bit
00
0
Timer A
M30240 Group
Rev. H Sep 18, 2003 Page 70 of 139
1.2.21.2 Event counter mode
In this mode, the timer counts an external signal or an internal timer’s overflow. Timers A0 and A1 can
count a single-phase external signal. Timers A2, A3, and A4 can count a single-phase and a two-
phase external signal. Table 1.19 lists the timer specifications when counting a single-phase external
signal. Figure 1.64 shows Timer Ai mode register in event counter mode, Note: Timer Ai register’s val-
ue can be indeterminate when the count starts.
Table 1.19: Timer specification in event counter mode (when not processing two-phase pulse signal)
Note: Timer Ai register ’s value can be indeterminate when the count starts.
Figure 1.64: Timer Ai mode register in event counter mode, single signal
Item Specification
Count source • External signals input to TAiIN pin (effective edge can be selected by software)
• TB2 overflow, TAj overflow
Count operation • Up count or down count can be selected by external signal of software
• When the timer overflows or underflows, it loads the reload register contents before continuing counting
(However, this does not apply when the free-run function is selected)
Divide ratio 1/(FFFF16-n+1) for up count
1/(n+1) for down count n: Set value
Count start condition Count start flag is set (= 1)
Count stop condition Count start flag is reset (= 0)
Interrupt request
generation timing When the timer underflows or underflows
TAiIN pin function Programmable I/O port or count source input
TAiOUT pin function Programmable I/O port, pulse output, or up/down count select input
Read from timer Count value can be read out by reading Timer Ai register
Write to timer
• When counting is stopped and a value is written to Timer Ai register , it is written to both reload register and
counter
• When counting is in progress and a value is written to Timer Ai register, it is written only to reload register
(to be transferred to counter at the next reload time)
Select function
• Free-run count function (Note)
When the timer overflows or underflows, the reload register’s content is not reloaded.
• Pulse output function
Each time the timer underflows, the TAiOUT pin’s polarity is reversed
Note 1: In event counter mode, the count source is selected by the event / trigger select bit
(addresses 038216 and 038316).
Note 2: The settings of the corresponding port register and port direction register are invalid.
Note 3: Valid only when counting an external signal.
Note 4: When an “L” signal is input to the TAiOUT
pin, the downcount is activated. When “H”,
the upcount is activated. Set the corresponding port direction register to “0”.
Note 5: This value can be indeterminate when the count starts.
Timer Ai mode register
Symbol Address When reset
TAiMR(i = 0, 1) 039616, 039716 0016
WR
b7 b6 b5 b4 b3 b2 b1 b0
Operation mode select bit
0 1 : Event counter mode (Note 1)
b1 b0
TMOD0
MR0 Pulse output function
select bit
0 : Pulse is not output
(TA iOUT pin is a normal port pin)
1 : Pulse is output (Note 2)
(TA iOUT pin is a pulse output pin)
Count polarity
select bit (Note 3)
MR2
MR1
MR3 0 (Must always be fixed to “0” in event counter mode)
TCK0 Count operation type
select bit
01
0
0 : Counts external signal's falling edge
1 : Counts external signal's rising edge
Up/down switching
cause select bit
0 : Up/down flag's content
1 : TA iOUT pin's input signal (Note 4)
0 : Reload type
1 : Free-run type (Note 5)
Bit symbol Bit name Function RW
TCK1 Invalid in event counter mode
Can be “0” or “1”
TMOD1
Note 1: In event counter mode, the count source is selected by the event / trigger select bit
(addresses 038216 and 038316).
Note 2: The settings of the corresponding port register and port direction register are invalid.
Note 3: Valid only when counting an external signal.
Note 4: When an “L” signal is input to the TAiOUT
pin, the downcount is activated. When “H”,
the upcount is activated. Set the corresponding port direction register to “0”.
Note 5: This value can be indeterminate when the count starts.
Timer Ai mode register
Symbol Address When reset
TAiMR(i = 0, 1) 039616, 039716 0016
WR
b7 b6 b5 b4 b3 b2 b1 b0
Operation mode select bit
0 1 : Event counter mode (Note 1)
b1 b0
TMOD0
MR0 Pulse output function
select bit
0 : Pulse is not output
(TA iOUT pin is a normal port pin)
1 : Pulse is output (Note 2)
(TA iOUT pin is a pulse output pin)
Count polarity
select bit (Note 3)
MR2
MR1
MR3 0 (Must always be fixed to “0” in event counter mode)
TCK0 Count operation type
select bit
01
0
0 : Counts external signal's falling edge
1 : Counts external signal's rising edge
Up/down switching
cause select bit
0 : Up/down flag's content
1 : TA iOUT pin's input signal (Note 4)
0 : Reload type
1 : Free-run type (Note 5)
Bit symbol Bit name Function RW
TCK1 Invalid in event counter mode
Can be “0” or “1”
TMOD1
Timer A
M30240 Group
Rev. H Sep 18, 2003 Page 71 of 139
Table 1.20: Timer specification in ev ent counter mode (when processing tw o-phase pulse signal with
Timers A2, A3, A4.)
Figure 1.65 shows Timer Ai mode register in event counter mode when processing two-phase signal.
Item Specification
Count Sour c e •Two-phase pulse signals input to TAiIN or TAiOUT pin
Count operat ion •Up count or down count can be selected by two-phase pulse signal
•When the timer overflows or underflows, the reload register content is loaded and the timer starts over
again (Note 1)
Divide ratio 1/ (FFFF16 - n + 1) for up count
1/ (n+1) for down count n: Set value
Count start condit ion Count sta rt fl a g i s se t ( = 1 )
Count stop condition C o unt sta r t fl a g i s r e s e t (= 0 )
Inter r upt request
generat ion timin g Timer overf low or underflows
TAiIN pin function Two-phase pulse input
TAiOUT pin function Two-phase pulse input
Read from timer Count value can be read out by reading timer A2, A3, or A4 register
Writer to timer
•When counting is stopped and a val ue is written to t imer A2, A3, or A4 register, it is written to both the
reload register and counter
•When counting is in progress and a value is written to timer A2, A3, or A4 register, it is written to only
reload register to be transferred to counter at the next reload time.
Select function
•Normal processing operation
The timer counts up rising edges or counts down falling edges on the TAiIN pin when input signal on
the TAiOUT pin is “H”
•Multiply-by-4 processing operation
If the phase relationship is such that the TAiIN pin goes “H” when the input signal on the TAiOUT pin
is “H”, the timer counts up rising and falling edges on the TAiOUT and TAiIN pins. If the phase
relationship is such that the TAiIN pin goes “L” when the input signal on t he TAiOUT pin is “H”, the timer
counts down rising and falling edges on the TAiOUT and TAiIN pins.
TAiOUT
TAiIN
(i=2,3)
Up
count
Up
count
Up
count Down
count Down
count Down
count
Count up all edges Count down all edges
Count down all edgesCount up all edges
TAiOUT
TAiIN
(i=3,4)
Timer A
M30240 Group
Rev. H Sep 18, 2003 Page 72 of 139
Figure 1.65: Timer Ai mode register in event counter mode, two-phase signal
Note 1: The settings of the corresponding port register and port direction register are invalid.
Note 2: This bit is valid when only counting an external signal.
Note 3: Set the corresponding port direction register to “0”.
Note 4: This bit is valid for the Timer A3 mode register.
For Timer A2 and A4 mode registers, this bit can be “0 ”or “1”.
Note 5: When performing two-phase pulse signal processing, make sure the two-phase pulse
signal processing operation select bit (address 038416) is set to “1”. Also, always be
sure to set the event/trigger select bit (addresses 038216 and 038316) to “00”.
Note 6: This value can be indeterminate when the count starts.
Timer Ai mode register
(When not using two-phase pulse signal processing)
Symbol Address When reset
TAiMR(i = 2 to 4) 039816 to 039A16 0016
b7 b6 b5 b4 b3 b2 b1 b0
Operation mode select bit 0 1 : Event counter mode
b1 b0
TMOD1
TMOD0
MR0 Pulse output function
select bit
0 : Pulse is not output
(TAi OUT pin is a normal port pin)
1 : Pulse is output (Note 1)
(TAi OUT pin is a pulse output pin)
Count polarity
select bit (Note 2)
MR2
MR1
MR3 0 : (Must always be “0” in event counter mode)
TCK1
TCK0
010
0 : Counts external signal's falling edges
1 : Counts external signal's rising edges
Up/down switching
cause select bit
0 : Up/down flag's content
1 : TA iOUT pin's input signal (Note 3)
Bit symbol Bit name Function
WR
Count operation type
select bit
Two-phase pulse signal
processing operation
select bit (Note 4)(Note 5)
0 : Reload type
1 : Free-run type (Note 6)
0 : Normal processing operation
1 : Multiply-by-4 processing operation
Note 1: This bit is valid for Timer A3 mode register.
For Timer A2 and A4 mode registers, this bit can be “0” or “1”.
Note 2: When performing two-phase pulse signal processing, make sure the two-phase pulse
signal processing operation select bit (address 038416) is set to “1”. Also, always be
sure to set the event/trigger select bit (addresses 038216 and 038316) to “00”.
Note 3: This value can be indeterminate when the count starts.
Timer Ai mode register
(When using two-phase pulse signal processing)
Symbol Address
When reset
TAiMR(i = 2 to 4) 039816 to 039A16 0016
b7 b6 b5 b4 b3 b2 b1 b0
Operation mode select bit 0 1 : Event counter mode
b1 b0
TMOD1
TMOD0
MR0 0 (Must always be “0” when using two-phase pulse signal
processing)
0 (Must always be “0” when using two-phase pulse signal
processing)
MR2
MR1
MR3 0 (Must always be “0” when using two-phase pulse signal
processing)
TCK1
TCK0
010
1 (Must always be “1” when using two-phase pulse signal
processing)
Bit symbol Bit name Function
WR
Count operation type
select bit
Two-phase pulse
processing operation
select bit (Note 1)(Note 2)
0 : Reload type
1 : Free-run type (Note 3)
0 : Normal processing operation
1 : Multiply-by-4 processing operation
001
Timer A
M30240 Group
Rev. H Sep 18, 2003 Page 73 of 139
1.2.21.3 One-shot timer mode
In this mode, the timer operates only once (See Table 1.21 ). When a trigger occurs, the timer starts
up and co ntinues oper ati ng for a g iv en p er io d. Fig ur e 1 .66 s ho ws t he T i mer A i m ode re gi ste r in o ne-
shot mode.
Figure 1.66: Timer Ai mode register in one-shot mode
Table 1.21: Timer specifications in one-shot time r mode
Item Specification
Count source f1, f8, f32
Count ope rati on •The timer counts down
•When the cou nt reac he s 0000 16, the timer stops counting after reloading a new count
• If a trigger occurs when counting, the timer reloads a new count and restarts counting
Divide ratio 1/n n: Set value
Count st a r t condition • An external trigger is input
• The selected timer overf low s
• The one-shot start flag is set (= 1)
Count sto p cond iti on • A new count is reloaded after the count has reached 000016
• The coun t start flag is reset (= 0)
Interrupt request
generati on tim ing The count reaches 000016
TAiIN pin function Programmable I/O port or trigger input
TAiOUT pin function Programmable I/O port or pulse output
Read from timer When timer Ai register is read, it indicates an indeterminate value
Write to timer
•When counting is stopped and a value is written to timer Ai register, it is written to both
reload register and counter
•When counting is in progress and a value is written to timer Ai register, it is written to the
reload register to be transferred to counter at next load ti me
Note 1: The settings of the corresponding port register and port direction register are invalid.
Note 2: Valid only when the TAi
IN
pin is selected by the event/trigger select bit.
(addresses 0382
16
and 0383
16
). If timer overflow is selected, this bit can be "1", or "0".
Note 3: Set the corresponding port direction register to “0”.
Timer Ai mode register
Symbol Address When reset
TAiMR(i=0 to 4) 0396
16
to 039A
16
00
16
Bit name FunctionBit symbol
b7 b6 b5 b4 b3 b2 b1 b0
Operation mode
select bit 1 0 : One-shot timer mode
b1 b0
TMOD1
TMOD0
MR0 Pulse output function
select bit
0 : Pulse is not output
(TA
iOUT
pin is a normal port pin)
1 : Pulse is output (Note 1)
(TA
iOUT
pin is a pulse output pin)
External trigger select bit
(Note 2)
0 : Falling edge of TAi
IN
pin's input signal
(Note 3)
1 : Rising edge of TAi
IN
pin's input signal
(Note
3)
MR2
MR1
MR3 0 (Must always be fixed to “0” in timer mode)
0 0 : f
1
0 1 : f
8
1 0 : f
32
1 1 : Reserved
b7 b6
TCK1
TCK0
Count source select bit
100
WR
Trigger select bit 0 : One-shot start flag is valid
1 : Selected by event/trigger select register
Timer A
M30240 Group
Rev. H Sep 18, 2003 Page 74 of 139
1.2.21.4 Pulse-wid th modulation (PWM) mode
In this mode, the timer outputs pulses of a given width in succession (See Table 1.22 ). In this mode,
the counter functions as either a 16-bit pulse-width modulator or an 8-bit pulse-width modulator. Figure
1.67 shows an example of how a 16-bit pulse-width modulator operates. Figure 1.68 shows the Timer
Ai mode register in pulse-width modulation mode. Figure 1.69 shows the example of how an 8-bit
pulse width modulator operates.
Figure 1.67: Example of how a 16-bit pulse-width modulator operates
Table 1.22: Timer specifications in pulse-width modulation mode
Item Specification
Count source f1, f8, f32
Count ope rati on •The timer counts down (operating as an 8-bit or a 16-bit pulse-width modulator)
•The timer reloads a new count at a rising edge of PWM pulse and continues counting
• The timer is not affected by a trigger that occurs when counting
16-bit PWM •High level width n / fi n: Set value
•Cycle time (216-1) / fi fixed
8-bit PWM •High level width n (m+1) /fi n: values set to timer Ai register’s high-order address
•Cycle time (28-1) (m+1) /fi m: values set to timer Ai register’s low-order address
Count st a r t condition •External trigger is input
•The timer overflows
•The count start flag is set (= 1)
Count stop condition •The count start flag is reset (= 0)
Interrupt request
generati on tim ing PWM pulse goes “L”
TAiIN pin function Programmable I/O port or trigger input
TAiOUT pin function Pulse output
Read from timer When Timer Ai register is read, it indicates an indeterminate value
Write to timer
•When counting is stopped and a value is written to Timer Ai register, it is written to both
reload register and the counter
•When counting in progress and a value is written to Timer A register, it is written to only
reload register to be transferred to the counter at next reload timer.
1 / f
i
X
(2 – 1)
16
Count source
TA
i
IN
pin
input signal
PWM pulse output
from TA
iOUT
pin
Condition : Reload register = 0003
16
, when external trigger
(rising
edge of TA iIN
pin input signal) is selected
Trigger is not generated by this signal
“H”
“H”
“L”
“L”
Timer Ai interrupt
request bit
“1”
“0”
Cleared to “0” when interrupt request is accepted, or cleared by software
f
i
: Frequency of count source
(f
1
, f
8
, f
32
)
16
to FFFE
16
1 / f
i
X
n
Note: n = 0000
Timer A
M30240 Group
Rev. H Sep 18, 2003 Page 75 of 139
Figure 1.68: Timer Ai mode register in pulse-width modulation mode
Figure 1.69: Example of how an 8-bit pulse-width modulator operates
Note 1: Valid only when the TAi
IN
pin is selected by the event/trigger select bit.
(addresses 0382
16
and 0383
16
). If timer overflow is selected, this bit can be "1", or "0".
Note 2: Set the corresponding port direction register to “0”.
Timer Ai mode register
Symbol Address
When reset
TAiMR(i=0 to 4) 039616 to 039A16
0016
Bit name FunctionBit symbol
b7 b6 b5 b4 b3 b2 b1 b0
Operation mode
select bit 1 1 : PWM mode
b1 b0
TMOD1
TMOD0
MR0
External trigger select bit
(Note 1)
0 : Falling edge of TAi IN pin's input signal
(Note 2)
1 : Rising edge of TAi IN pin's input signal
(Note 2)
MR2
MR1
MR3
Must always be "1" in PWM mode)
0 0 : f1
0 1 : f8
1 0 : f32
1 1 : Reserved
b7 b6
TCK1
TCK0
Count source select bit
111
WR
Trigger select bit
0 : Functions as a 16-bit pulse width modulator
1 : Functions as an 8-bit pulse width modulator
16/8 PWM mode select bit
0 : Count start flag is valid
1 : Selected by event /trigger select register
Count source (Note1)
TA
iIN
pin input signal
Underflow signal of
8-bit prescaler (Note 2)
PWM pulse output
from TA
iOUT
pin
“H”
“H”
“H”
“L”
“L”
“L”
“1”
“0”
Timer Ai interrupt
request bit
Cleared to “0” when interrupt request is accepted, or cleared by software
f
i
: Frequency of count source
(f
1
, f
8
, f
32
)
Note 1: The 8-bit prescaler counts the count source.
Note 2: The 8-bit pulse width modulator counts the 8-bit prescaler's underflow signal.
Condition : Reload register high-order 8 bits = 0216
Reload register low-order 8 bits = 0216
External trigger (falling edge of TAiIN pin input signal) is selected
1 / f
i
X (m
+ 1) X (2 – 1)
8
1 / f
i
X (m + 1) X n
1 / f
i
X (m + 1)
Note 3: m = 00
16
to FE
16
; n = 00
16
to FE
16
Timer B
M30240 Group
Rev. H Sep 18, 2003 Page 76 of 139
1.2.22 Timer B
Figure 1.70 shows the block diagram of timer B. Figure 1.71 and Figure 1.72 show the Timer B-related
regist ers . Use the Timer Bi mode regi ster (i = 0 to 2) bi ts 0 and 1 to choo se t he de sire d mod e. Timer B
works in Timer mode only (i.e., the timer counts an in internal count source).
Figure 1.70: Block diagram of Timer B
Figure 1.71: Timer B-related registers (1)
Clock source selection
(address 0380
16
)
Reload register (16)
Low-order 8 bits
Data bus low-order bits
Data bus high-order bits
f1
f8
f32
TBj overflow
j = i – 1.
Note, however,
Count start flag
Counter reset circuit
Counter (16)
TBi Address TBj
Timer B0 0391
16
0390
16
Timer B2
Timer B1 0393 0392 Timer B0
j = 2 when i = 0 Timer B2 0395
16
0394
16
Timer B1
16 16
High-order 8-bits
Note 1: Timer B0.
Note 2: Timer B1, Timer B2.
Timer Bi mode register
Symbol Address
When reset
TBiMR(i=0 to 2) 039B16 to 039D16 00XX0000 2
Bit name Function
Bit symbol WR
b7 b6 b5 b4 b3 b2 b1 b0
Operation mode select bit 0 0 : Timer mode
b1 b0
TMOD1
TMOD0
MR0 Invalid in timer mode
Can be “0” or “1”
MR2
MR1
MR3
0 0 : f1
0 1 : f8
1 0 : f32
1 1 : Reserved
TCK1
TCK0
Count source select bit
0
0
0 (Fixed to “0” in timer mode ; i = 0)
(Note 1)
(Note 2)
b7 b6
Nothing is assigned (i=1,2). In an attempt to write to this bit, write "0".
The value, if read, turns out to be indeterminate.
Invalid in timer mode. In an attempt to write to this bit, write "0".
The value, if read, turns out to be indeterminate.
Timer B
M30240 Group
Rev. H Sep 18, 2003 Page 77 of 139
Figure 1.72: Timer B-related registers (2)
1.2.22.1 Timer mode
In this mode, the timer counts an internally generated count source as shown in Table 1.23 .
Table 1.23: Timer B timer specifications in timer mode
Note: Timer B2 does not generate an interrupt; it is used as a prescaler only.
Item Specification
Count source f1, f8, f32
Count ope rati on • Counts down
• When the t imer underf lows, it r eloads the reload regi ster co ntents before cont inuing co unting
Divide ratio 1/(n+1) n: Set value
Count start condition Count start flag is set (= 1)
Count stop condition Count start flag is reset (= 0)
Interrupt request
generati on tim ing The timer underflows (see Note)
Read from timer Count value is read out by reading timer Bi register
Write to timer
• When counting stopped
When a value is written to Timer Bi register, it is written to both reload register and counter
• When counting is in progress
When a value is written to Timer Bi register, it is written to only reload register
(Transferred to counter at the next reload time)
Symbol Address When reset
TABSR 038016 0016
Count start flag
Bit name
Bit symbol WR
b7 b6 b5 b4 b3 b2 b1 b0
Timer B2 count start flag
Timer B1 count start flag
Timer B0 count start flag
Timer A4 count start flag
Timer A3 count start flag
Timer A2 count start flag
Timer A1 count start flag
Timer A0 count start flag 0 : Stops counting
1 : Starts counting
TB2S
TB1S
TB0S
TA 4 S
TA 3 S
TA 2 S
TA 1 S
TA 0 S
Function
Symbol Address When reset
TB0 039116, 039016 Indeterminate
TB1 039316, 039216 Indeterminate
TB2 039516, 039416 Indeterminate
b7 b0 b7 b0
(b15) (b8)
Timer Bi register (Note)
WR
• Timer mode 000016 to FFFF16
Counts the timer's period
Function
Note: Read and write data in 16-bit units.
Values that can be set
UART0 to UART2
M30240 Group
Rev. H Sep 18, 2003 Page 78 of 139
1.2.23 UART0 to UART2
Serial I/O is c on fig ured a s t hr ee cha nne ls : UA RT0, UART1, and UA RT2. UA RT0, UART1, and U ART2
each have an exclusive timer to generate a transfer clock, so they operate independently of each other .
Figure 1.73 shows the block diagram of UART0, UART1, and UART2. Figure 1.74 and Figure 1.75 show
the block diagram of the transmit/receive unit.
Figure 1.73: Block diagram of UARTi (i=0 to 2)
n0 : Values set to UART0 bit rate generator (BRG0)
n1 : Values set to UART1 bit rate generator (BRG1)
n2 : Values set to UART2 bit rate generator (BRG2)
RxD2
Reception
control circuit
Transmission
control circuit
1 / (n
2
+1)
1/16
1/16
1/2
Bit rate generator
(address 0379
16
)
Clock synchronous type
(when internal clock is selected)
UART reception
Clock synchronous type
UART transmission
Clock synchronous type
Clock synchronous type
(when internal clock is selected)
Clock synchronous type
(when external clock is
selected)
Receive
clock
Transmit
clock
CLK2
CTS2 / RTS2
f
1
f
8
f
32
Vcc
RTS2
CTS2
TxD2
(UART2)
RxD polarity
reversing circuit
TxD
polarity
reversing
circuit
RxD0
1 / (n
0
+1)
1/2
Bit rate generator
(address 03A1
16
)
Clock synchronous type
(when internal clock is selected)
UART reception
Clock synchronous type
UART transmission
Clock synchronous type
Clock synchronous type
(when internal clock is selected)
Clock synchronous type
(when external clock is
selected)
Receive
clock
Transmit
clock
CLK0
Clock source selection
CTS0 / RTS0
f
1
f
8
f
32
Reception
control circuit
Transmission
control circuit
Internal
External
RTS0
CTS0
TxD0
Transmit/
receive
unit
RxD1
1 / (n
1
+1)
1/16
1/16
1/2
Bit rate generator
(address 03A9
16
)
Clock synchronous type
(when internal clock is selected)
UART reception
Clock synchronous type
UART transmission
Clock synchronous type
Clock synchronous type
(when internal clock is selected)
Clock synchronous type
(when external clock is
selected)
Receive
clock
Transmit
clock
CLK1
Clock source selection
f
1
f
8
f
32
Reception
control circuit
Transmission
control circuit
Internal
External
RTS1
CTS1
TxD1
(UART1)
(UART0)
CLK
polarity
reversing
circuit
CLK
polarity
reversing
circuit
CTS/RTS disabled
Clock output pin
select switch
CTS1 / RTS1
CLKS1
CTS/RTS disabled
CTS/RTS selected
CTS/RTS disabled
V
CC
CTS/RTS disabled
CTS/RTS disabled
CTS/RTS disabled
CTS/RTS
selected
CLK
polarity
reversing
circuit
Internal
External
Clock source selection
Transmit/
receive
unit
Transmit/
receive
unit
1/16
1/16
V
CC
UART0 to UART2
M30240 Group
Rev. H Sep 18, 2003 Page 79 of 139
Figure 1.74: Block diagram of UARTi (i=0,1) transmit/receive circuit
Figure 1.75: Block diagram of UART2 transmit/receive circuit
SP SP
PA R
2SP
1SP
UART
UART (7 bits)
UART (8 bits)
UART (7 bits)
UART (9 bits)
Clock
synchronous
type
Clock synchronous
type
TxDi
UARTi transmit register
PAR
enabled
PAR
disabled
D8D7D6D5D4D3D2D1D0
SP: Stop bit
PAR: Parity bit
UARTi transmit
buffer register
MSB/LSB conversion circuit
UART (8 bits)
UART (9 bits)
Clock synchronous
type
UARTi receive
buffer register
UARTi receive register
2SP
1SP
PAR
enabled
PAR
disabled
UART
UART (7 bits)
UART (9 bits)
Clock
synchronous
type
Clock
synchronous type
UART (7 bits)
UART (8 bits)
RxDi
Clock
synchronous type
UART (8 bits)
UART (9 bits)
Address 03A6
16
Address 03A7
16
Address 03AE
16
Address 03AF
16
Address 03A2
16
Address 03A3
16
Address 03AA
16
Address 03AB
16
Data bus low-order bits
MSB/LSB conversion circuit
D7D6D5D4D3D2D1D0D8
0000000
SP SP
PA R
“0”
SP SP
PA R
2SP
1SP
UART
UART
(7 bits)
UART
(8 bits)
UART(7 bits)
UART
(9 bits)
Clock
synchronous
type
Clock
synchronous type
Data bus low-order bits
TxD2
UART2 transmit register
PAR
disabled
PAR
enabled
D8D7D6D5D4D3D2D1D0UART2 transmit
buffer register
UART
(8 bits)
UART
(9 bits)
Clock
synchronous type
UART2 receive
buffer register
UART2 receive register
2SP
1SP
UART
(7 bits)
UART
(8 bits) UART(7 bits)
UART
(9 bits)
Clock
synchronous type
Clock
synchronous type
RxD2
UART
(8 bits)
UART
(9 bits)
Address 037E16
Address 037F16
Address 037A16
Address 037B16
Data bus high-order bits
D7D6D5D4D3D2D1D0D8
0000000
SP SP
PA R
“0”
Reverse
No reverse
Error signal
output circuit
RxD data
reverse circuit
Error signal output
enable
Error signal output
disable
Reverse
No reverse
Logic reverse circuit + MSB/LSB conversion circuit
Logic reverse circuit + MSB/LSB conversion circuit
PAR
enabled
PAR
disabled
UART
Clock
synchronous
type
TxD data
reverse circuit
SP: Stop bit
PAR: Parity bit
PAR: Parity bit
UART0 to UART2
M30240 Group
Rev. H Sep 18, 2003 Page 80 of 139
UARTi (i = 0 to 2) has two operation modes: a clock synchronous serial I/O mode and a clock
asynchronous serial I/O mode (UART mode). The contents of the serial I/O mode select bits (bits 0 to 2
at ad dresses 03A 016, 03A816 and 037816) d etermine whe ther UARTi i s used as a clock sy nchronous
serial I/O or as a UART. Although a few functions are different, UART0 and UART1 have almost the
same functions.
UART0 through UART2 are almost equal in their functions with minor exceptions.Table 1.24 shows the
comparison o f functions o f UART0 thro ugh UART2, and Figure 1 .76, Figure 1.77 , Figure 1.78, F igure
1.79, and Figure 1.80 show the registers related to UARTi.
Note 1: Only during clock synchronous serial I/O mode.
Note 2: Only during clock synchronous serial I/O mode and 8-bit UART mode.
Note 3: Only during UART mode.
Note 4: Used for SIM interface.
Table 1.24: Comparison of functions of UART0 through UART2
Function UART0 UART1 UART2
CLK polarity selection Possible (Note 1) Possible (Note 1) Possible (Note 1)
LSB first / MSB first selection Possible (Note 1) Possible (Note 1) Possible (Note 2)
Continuous receive mode selection Possible (Note 1) Possible (Note 1) Possible (Note 1)
Transfer clock output from multiple pins selection Impossible Possible (Note 1) Impossible
Serial data logic switch Impossible Impossible Possible (Note 4)
Sleep mode selection Possible (Note 3) Possible (Note 3) Impossible
TxD, RxD I/O polarity switch Impossible Impossible Possible
TxD, RxD port output format CMOS output CMOS output CMOS output
Parity error signal output Impossible Impossible Possible (Note 4)
Bus collision detection Impossible Impossible Possible
UART0 to UART2
M30240 Group
Rev. H Sep 18, 2003 Page 81 of 139
Figure 1.76: Serial I/O-related registers (1)
b7
UARTi bit rate generator
b0
Symbol Address When reset
U0BRG 03A1
16
Indeterminate
U1BRG 03A9
16
Indeterminate
U2BRG 0379
16
Indeterminate
Function
Assuming that set value = n, BRGi divides the count source by
n + 1 00
16
to FF
16
Values that can be set WR
b7 b0
(b15) (b8)
b7 b0
UARTi transmit buffer register
Function
Transmit data
Nothing is assigned.
These bits can neither be set nor reset. When read, their contents are indeterminate.
Symbol Address When reset
U0TB 03A3
16
, 03A2
16
Indeterminate
U1TB 03AB
16
, 03AA
16
Indeterminate
U2TB 037B
16
, 037A
16
Indeterminate
WR
(b15)
Symbol Address When reset
U0RB 03A7
16
, 03A6
16
Indeterminate
U1RB 03AF
16
, 03AE
16
Indeterminate
U2RB 037F
16
, 037E
16
Indeterminate
b7 b0
(b8)
b7 b0
UARTi receive buffer register
Function
(During UART mode)
Function
(During clock synchronous
serial I/O mode)
Bit name
Bit
symbol
0 : No framing error
1 : Framing error found
0 : No parity error
1 : Parity error found
0 : No error
1 : Error found
Note : Bits 15 through 12 are set to “0” when the serial I/O mode select bit (bits 2 to 0 at addresses 03A0
16
,
03A8
16
and 0378
16
) are set to “000
2
” or the receive enable bit is set to “0”.
(Bit 15 is set to “0” when bits 14 to 12 all are set to “0”.) Bits 14 and 13 are also set to “0” when the
lower byte of the UARTi receive buffer register (addresses 03A6
16
, 03AE
16
and 037E
16
) is read out.
Invalid
Invalid
Invalid
OER
FER
PER
SUM
Overrun error flag (Note)
Framing error flag
Parity error flag
Error sum flag
0 : No overrun error
1 : Overrun error found
0 : No overrun error
1 : Overrun error found
Nothing is assigned.
These bits can neither be set nor reset. When read, the value of these bits is “0”.
WR
Receive data Receive data
(Note)
(Note)
(Note)
UART0 to UART2
M30240 Group
Rev. H Sep 18, 2003 Page 82 of 139
Figure 1.77: Serial I/O-related registers (2)
UARTi transmit/receive mode register
Symbol Address When reset
UiMR(i=0,1) 03A0
16
, 03A8
16
00
16
b7 b6 b5 b4 b3 b2 b1 b0
Bit name
Bit
symbol WR
Must be fixed to 001
0 0 0 : Serial I/O invalid
0 1 0 : Inhibited
0 1 1 : Inhibited
1 1 1 : Inhibited
b2 b1 b0
CKDIR
SMD1
SMD0 Serial I/O mode select bit
SMD2
Internal/external clock
select bit
STPS
PRY
PRYE
SLEP
Parity enable bit
0 : Internal clock
1 : External clock
Stop bit length select bit
Odd/even parity select bit
Sleep select bit
0 : One stop bit
1 : Two stop bits
0 : Parity disabled
1 : Parity enabled
0 : Sleep mode deselected
1 : Sleep mode selected
1 0 0 : Transfer data 7 bits long
1 0 1 : Transfer data 8 bits long
1 1 0 : Transfer data 9 bits long
0 0 0 : Serial I/O invalid
0 1 0 : Inhibited
0 1 1 : Inhibited
1 1 1 : Inhibited
b2 b1 b0
0 : Internal clock
1 : External clock
Invalid
Valid when bit 6 = “1”
0 : Odd parity
1 : Even parity
Invalid
Invalid
Must always be “0”
Function
(During UART mode)
Function
(During clock synchronous
serial I/O mode)
UART2 transmit/receive mode register
Symbol Address When reset
U2MR 0378
16
00
16
b7 b6 b5 b4 b3 b2 b1 b0
Bit name
Bit
symbol WR
Must be fixed to 001
0 0 0 : Serial I/O invalid
0 1 1 : Inhibited
1 1 1 : Inhibited
b2 b1 b0
CKDIR
SMD1
SMD0 Serial I/O mode select bit
SMD2
Internal/external clock
select bit
STPS
PRY
PRYE
IOPOL
Parity enable bit
0 : Internal clock
1 : External clock
Stop bit length select bit
Odd/even parity select bit
TxD, RxD I/O polarity
reverse bit
0 : One stop bit
1 : Two stop bits
0 : Parity disabled
1 : Parity enabled
0 : No reverse
1 : Reverse
Usually set to “0”
1 0 0 : Transfer data 7 bits long
1 0 1 : Transfer data 8 bits long
1 1 0 : Transfer data 9 bits long
0 0 0 : Serial I/O invalid
0 1 1 : Inhibited
1 1 1 : Inhibited
b2 b1 b0
Invalid
Valid when bit 6 = “1”
0 : Odd parity
1 : Even parity
Invalid
Invalid
0 : No reverse
1 : Reverse
Usually set to “0”
Function
(During UART mode)
Function
(During clock synchronous
serial I/O mode)
Must always be "0"
UART0 to UART2
M30240 Group
Rev. H Sep 18, 2003 Page 83 of 139
Figure 1.78: Serial I/O-related registers (3)
UARTi transmit/receive control register 0
Symbol Address When reset
UiC0(i=0,1) 03A4
16
, 03AC
16
08
16
b7 b6 b5 b4 b3 b2 b1 b0
Function
(During UART mode) WR
Function
(During clock synchronous
serial I/O mode)
TXEPT
CLK1
CLK0
CRS
CRD
CKPOL
BRG count source
select bit
Transmit register empty
flag
0 : Transmit data is output at
falling edge of transfer clock
and receive data is input at
rising edge
1 : Transmit data is output at
rising edge of transfer clock
and receive data is input at
falling edge
CLK polarity select bit
CTS/RTS function
select bit
CTS/RTS disable bit
0 0 : f
1
is selected
0 1 : f
8
is selected
1 0 : f
32
is selected
1 1 : Reserved
b1 b0
0 : LSB first
1 : MSB first
0 : Data present in transmit
register (during transmission)
1 : No data present in transmit
register (transmission
completed)
0 : CTS/RTS function enabled
1 : CTS/RTS function disabled
(P6
0
and P6
4
function as
programmable I/O port)
UFORM Transfer format select bit
0 0 : f
1
is selected
0 1 : f
8
is selected
1 0 : f
32
is selected
1 1 : Reserved
b1 b0
Valid when bit 4 = “0”
0 : CTS function is selected (Note 1)
1 : RTS function is selected (Note 2)
Valid when bit 4 = “0”
0 : CTS function is selected (Note 1)
1 : RTS function is selected (Note 2)
0 : Data present in transmit register
(during transmission)
1 : No data present in transmit
register (transmission completed)
Must always be “0”
Bit name
Bit
symbol
Must always be “0”
Note 1: Set the corresponding port direction register to “0”.
Note 2: The settings of the corresponding port register and port direction register are invalid.
0 : CTS/RTS function enabled
1 : CTS/RTS function disabled
(P6
0
and P6
4
function as
programmable I/O port)
UART2 transmit/receive control register 0
Symbol Address When reset
U2C0 037C
16
08
16
b7 b6 b5 b4 b3 b2 b1 b0
Function
(During UART mode) WR
Function
(During clock synchronous
serial I/O mode)
TXEPT
CLK1
CLK0
CRS
CRD
CKPOL
BRG count source
select bit
Transmit register empty
flag
0 : Transmit data is output at
falling edge of transfer clock
and receive data is input at
rising edge
1 : Transmit data is output at
rising edge of transfer clock
and receive data is input at
falling edge
CLK polarity select bit
CTS/RTS function
select bit
CTS/RTS disable bit
0 0 : f
1
is selected
0 1 : f
8
is selected
1 0 : f
32
is selected
1 1 : Reserved
b1 b0
0 : LSB first
1 : MSB first
0 : Data present in transmit
register (during transmission)
1 : No data present in transmit
register (transmission
completed)
0 : CTS/RTS function enabled
1 : CTS/RTS function disabled
(P7
3
functions
programmable I/O port)
UFORM Transfer format select bit
(Note 3)
0 0 : f
1
is selected
0 1 : f
8
is selected
1 0 : f
32
is selected
1 1 : Reserved
b1 b0
Valid when bit 4 = “0”
0 : CTS function is selected (Note 1)
1 : RTS function is selected (Note 2)
Valid when bit 4 = “0”
0 : CTS function is selected (Note 1)
1 : RTS function is selected (Note 2)
0 : Data present in transmit register
(during transmission)
1 : No data present in transmit
register (transmission completed)
Must always be “0”
Bit name
Bit
symbol
Note 1: Set the corresponding port direction register to “0”.
Note 2: The settings of the corresponding port register and port direction register are invalid.
Note 3: Only clock synchronous serial I/O mode and 8-bit UART mode are valid.
0 : CTS/RTS function enabled
1 : CTS/RTS function disabled
(P7
3
functions programmable
I/O port)
Nothing is assigned.
This bit can neither be set nor reset. When read, the value of this bit is “0”.
0 : LSB first
1 : MSB first
Nothing is assigned.
This bit can neither be set nor reset. When read, the value of this bit is “0”.
UART0 to UART2
M30240 Group
Rev. H Sep 18, 2003 Page 84 of 139
Figure 1.79: Serial I/O-related registers (4)
UARTi transmit/receive control register 1
Symbol Address When reset
UiC1(i=0,1) 03A5
16,
03AD
16
02
16
b7 b6 b5 b4 b3 b2 b1 b0
Bit name
Bit
symbol WR
Function
(During UART mode)
Function
(During clock synchronous
serial I/O mode)
TE
TI
RE
RI
Transmit enable bit
Receive enable bit
Receive complete flag
Transmit buffer
empty flag
0 : Transmission disabled
1 : Transmission enabled
0 : Data present in
transmit buffer register
1 : No data present in
transmit buffer register
0 : Reception disabled
1 : Reception enabled
0 : Transmission disabled
1 : Transmission enabled
0 : Data present in
transmit buffer register
1 : No data present in
transmit buffer register
0 : Reception disabled
1 : Reception enabled
0 : No data present in
receive buffer register
1 : Data present in
receive buffer register
0 : No data present in
receive buffer register
1 : Data present in
receive buffer register
UART2 transmit/receive control register 1
Symbol Address When reset
U2C1 037D
16
02
16
b7 b6 b5 b4 b3 b2 b1 b0
Bit name
Bit
symbol WR
Function
(During UART mode)
Function
(During clock synchronous
serial I/O mode)
TE
TI
RE
RI
Transmit enable bit
Receive enable bit
Receive complete flag
Transmit buffer
empty flag
0 : Transmission disabled
1 : Transmission enabled
0 : Data present in
transmit buffer register
1 : No data present in
transmit buffer register
0 : Reception disabled
1 : Reception enabled
0 : Transmission disabled
1 : Transmission enabled
0 : Data present in
transmit buffer register
1 : No data present in
transmit buffer register
0 : Reception disabled
1 : Reception enabled
0 : No data present in
receive buffer register
1 : Data present in
receive buffer register
0 : No data present in
receive buffer register
1 : Data present in
receive buffer register
U2IRS UART2 transmit interrupt
cause select bit
0 : Transmit buffer empty
(TI = 1)
1 : Transmit is completed
(TXEPT = 1)
0 : Transmit buffer empty
(TI = 1)
1 : Transmit is completed
(TXEPT = 1)
U2RRM UART2 continuous
receive mode enable bit
0 : Continuous receive
mode disabled
1 : Continuous receive
mode enabled
Invalid
Data logic select bit 0 : No reverse
1 : Reverse
0 : No reverse
1 : Reverse
U2LCH
U2ERE Error signal output
enable bit
Must be fixed to “0” 0 : Output disabled
1 : Output enabled
Nothing is assigned. Write "0" when writing to these bits.
If read, the value is "0".
UART0 to UART2
M30240 Group
Rev. H Sep 18, 2003 Page 85 of 139
Figure 1.80: Serial I/O-related registers (5)
1.2.23.1 Clock synchronous serial I/O mode
The clock synchronous serial I/O mode uses a transfer clock to transmit and receive data. Figure 1.81
shows t he U ART i trans mi t/r ecei ve mo de re gi ste r. T able 1.25 li st s the specifi ca tio ns of the cl ock sy n-
chronous serial I/O mode.
Figure 1.81: UARTi transmit/receive mode register in clock synchronous serial I/O mode
Note: When using multiple pins to output the transfer clock, the following requirements must be met:
• UART1 internal/external clock select bit (bit 3 at address 03A8
16
) = “0”.
UART transmit/receive control register 2
Symbol Address When reset
UCON 03B0
16
X0000000
2
b7 b6 b5 b4 b3 b2 b1 b0
Bit name
Bit
symbol WR
Function
(During UART mode)
Function
(During clock synchronous
serial I/O mode)
CLKMD0
CLKMD1
UART0 transmit
interrupt cause select bit
UART0 continuous
receive mode enable bit
0 : Continuous receive
mode disabled
1 : Continuous receive
mode enable
UART1 continuous
receive mode enable bit
CLK/CLKS select bit 0
UART1 transmit
interrupt cause select bit
0 : Transmit buffer empty (Tl = 1)
1 : Transmission completed
(TXEPT = 1)
0 : Transmit buffer empty (Tl = 1)
1 : Transmission completed
(TXEPT = 1)
0 : Normal mode
(CLK output is CLK1 only)
1 : Transfer clock output
from multiple pins
function selected
0 : Continuous receive
mode disabled
1 : Continuous receive
mode enabled
Nothing is assigned.
This bit can neither be set nor reset. When read, its content is indeterminate.
0 : Transmit buffer empty (Tl = 1)
1 : Transmission completed
(TXEPT = 1)
0 : Transmit buffer empty (Tl = 1)
1 : Transmission completed
(TXEPT = 1)
Must always be “0”
U0IRS
U1IRS
U0RRM
U1RRM
Invalid
Invalid
Invalid
CLK/CLKS select
bit 1 (Note)
Valid when bit 5 = “1”
0 : Clock output to CLK1
1 : Clock output to CLKS1
Must always be “0”
Reserved Must always be “0”
0
Symbol Address When reset
UiMR(i=0,1) 03A0
16
, 03A8
16
00
16
CKDIR
UARTi transmit/receive mode registers
Internal/external clock
select bit
STPS
PRY
PRYE
SLEP
0 : Internal clock
1 : External clock
Bit name FunctionBit symbol WR
b7 b6 b5 b4 b3 b2 b1 b0
0 (Must always be “0” in clock synchronous serial I/O mode)
010
SMD0
SMD1
SMD2
Serial I/O mode select bit 0 0 1 : Clock synchronous serial
I/O mode
b2 b1 b0
0
Invalid in clock synchronous serial I/O mode
Symbol Address When reset
U2MR 0378
16
00
16
CKDIR
UART2 transmit/receive mode register
Internal/external clock
select bit
STPS
PRY
PRYE
IOPOL
0 : Internal clock
1 : External clock
Bit name FunctionBit symbol WR
b7 b6 b5 b4 b3 b2 b1 b0
010
SMD0
SMD1
SMD2
Serial I/O mode select bit 0 0 1 : Clock synchronous serial
I/O mode
b2 b1 b0
0
Invalid in clock synchronous serial I/O mode
TxD, RxD I/O polarity
reverse bit (Note)
0 : No reverse
1 : Reverse
Note 1: Usually set to "0".
UART0 to UART2
M30240 Group
Rev. H Sep 18, 2003 Page 86 of 139
Table 1.25: Specifications of Clock synchronous serial I/O mode
Note 1: “n” denotes the value 0016 to FF16 that is set to the UART bit rate generator.
Note 2: The UARTi receive buffer has the next data written when an overrun error occurs. Note: the UARTi receive interrupt
request bit is set to “0”.
Item Specification
Transfer data format •Transfer data length: 8 bits
Transfer clock
•When internal clock is selected (bit 3 at addresses 03A016, 03A816, 037816 = “0”):
fi/2( n +1) (Note 1) fi = f1, f8, f32
•When external clock is selected (bit 3 at addresses 03A016, 03A816, 037816 = “1”):
Input from CLKi pin (Maximum 5 Mbps.)
Transmission/reception
control CTS function/RTS function/CTS, RTS function chosen to be invalid
Transmission start
condition
•To start transmission, the following requirements must be met:
Transmit enable bit (bit 0 at addresses 03A516, 03AD16, 037D16) = “1”
Transmit buffer empty flag (bit 1 at addresses 03A516, 03AD16, 037D16) = “0”
When CTS function selected, CTS input level = “L”
•Furthermore, if external clock is selected, the following requirements must also be met:
CLKi polarity select bit (bit 6 at addresses 03A4 16, 03AC16, 037C16) = “0”: CLKi input level = “H”
CLKi polarity select bit (bit 6 at addresses 03A4 16, 03AC16, 037C16) = “1”: CLKi input level = “L”
Reception start condition
•To start reception, the following requirements must be met:
Receive enable bit (bit 2 at addresses 03A516, 03AD16, 037D16) = “1”
Transmit enable bit (bit 0 at addresses 03A516, 03AD16, 037D16) = “1”
Transmit buffer empty flag (bit 1 at addresses 03A516, 03AD16, 037D16) = “0”
•Furthermore, if external clock is selected, the following requirements must also be met:
CLKi polarity select bit (bit 6 at addresses 03A4 16, 03AC16, 037C16) = “0”: CLKi input level = “H”
CLKi polarity select bit (bit 6 at addresses 03A4 16, 03AC16, 037C16) = “1”: CLKi input level = “L”
Interrupt request
generation timing
•When transmitting
Transmit interrupt cause select bit (bits 0, 1 at address 03B016, bit 4 at address 037D16) = “0”:
Interrupts requested when data transfer from UARTi
Transmit interrupt cause select bit (bits 0, 1 at address 03B016, bit 4 at address 037D16) = “1”:
Interrupts requested when data transmission from
•When receiving
Interrupt requested when the data transfer from the UARTi receive register to the UART i receive
buffer register is complete.
Error detection •Overrun error (Note 2)
This error occurs when the next data is ready before contents of UARTi receive buffer is read.
Select function
•CLK polarity selection
Whether transmit data is output/input at the rising edge or falling edge of the transfer clock can be
selected
•LSB fi r st/MSB first sele c t io n
Whether transmission/reception begins with bit 0 or bit 7 can be selected
•Continuous receive mode selection
Reception is enabled simultaneously by a read from the receive buffer register
•Transfer clock output from multiple pins selection (UART1)
UART1 transfer clock can be chosen by software to be output from one of the two pins set
•Switching serial data logic (UART2)
Whether to reverse data in writing to the transmission buffer register or reading the reception buffer
register can be selected.
•Switching serial data logic (UART2)
This function is reversing TxD port output and RxD port input. All I/O data level is reversed.
UART0 to UART2
M30240 Group
Rev. H Sep 18, 2003 Page 87 of 139
Table 1.26 lists the functions of the input/output pins during clock synchronous serial I/O mode. This
table shows the pin functions when the transfer clock output from multiple pins function is not selected.
Note that for a period from when the UARTi op eration mode is selected to when transfer star ts, the
TxD pin outputs a “H”. The typical clock synchronous timing diagrams are shown in Figure 1.82.
Table 1.26: IART mode input/output pin functions
Pin name Function Method of selectio n
TxDi
(P63, P67, P7 0)Serial data
output (Outputs dummy data when performing reception only)
RxDi
(P62, P66, P71)Serial data input Port P 62, P66, and P71 direction register (bits 2 and 6 at address 03EE16 bit 1 at address
03EF16)= “0”
(Can be used as an input port when performing transmission only.)
CLKi
(P61, P65, P72)
Transfer clock
output Internal/external clock select bit (bit 3 at address 03A016, 03A816, 037816) = “0”
Transfer clock
input
Internal/external clock select bit (bit 3 at address 03A016, 03A816, 037816) = “1”
Port P 61, P65, and P72 direction register (bits 1 and 5 at address 03EE16, bit 2 at address
03EF16) = “0”
CTSi/RTSi
(P60,P64,P73)
CTS input
CTS/RTS disable bit (bit 4 at address 03A416, 03AC16, 037C16) = “0”
CTS/RTS function select bit (bit 2 at address 03A416, 03AC16, 037C16) = “0”
Port P 60, P 64 and P73 direction regi ster (bit s 0 and 4 at address 03EE16, bit 3 at address
03EF16) = “0”
RTS output CTS/RTS disable bit (bit 4 at address 03A416, 03AC16, 037C16) = “0”
CTS/RTS function select bit (bit 2 at address 03A416, 03AC16, 037C16) = “1”
Programmable I/
O port CTS/RTS disable bit (bit 4 at address 03A416, 03AC16, 037C16) = “1”
UART0 to UART2
M30240 Group
Rev. H Sep 18, 2003 Page 88 of 139
Figure 1.82: Typical transmit/receive timings in clock synchronous serial I/O mode Polarity select function
Stopped pulsing because transfer enable bit = “0”
1 / f
EXT
Dummy data is set in UARTi transmit buffer register
Transmit enable
bit (TE)
Transmit buffer
empty flag (Tl)
CLKi
RxDi
Receive complete
flag (Rl)
RTSi
“H”
“L”
“0”
“1”
“0”
“1”
“0”
“1”
Receive enable
bit (RE)
“0”
“1”
Receive data is taken in
Transferred from UARTi transmit buffer register to UARTi transmit register
Read out from UARTi receive buffer register
The above timing applies to the following settings:
• External clock is selected.
• RTS function is selected.
• CLK polarity select bit = “0”.
f
EXT
: frequency of external clock
Transferred from UARTi receive register
to UARTi receive buffer register
Receive interrupt
request bit (IR)
“0”
“1”
D0D1D2D3D4D5D6D7D0D1D2D3D4D5
Shown in ( ) are bit symbols.
Meet the following conditions are met when the CLK
input before data reception = “H”
• Transmit enable bit “1”
• Receive enable bit “1”
• Dummy data write to UARTi transmit buffer register
Cleared to “0” when interrupt request is accepted, or cleared by software
D0D1D2D3D4D5D6D7D0D1D2D3D4D5D6D7D0D1D2D3D4D5D6D7
Tc
TCLK
Data is set in UARTi transmit buffer register
Tc = TCLK = 2(n + 1) / fi
fi: frequency of BRGi count source (f
1
, f
8
, f
32
)
n: value set to BRGi
Transfer clock
Transmit enable
bit (TE)
Transmit buffer
empty flag (Tl)
CLKi
TxDi
Transmit
register empty
flag (TXEPT)
“H”
“L”
“0”
“1”
“0”
“1”
“0”
“1”
CTSi
The above timing applies to the following settings:
• Internal clock is selected.
• CTS function is selected.
• CLK polarity select bit = “0”.
• Transmit interrupt cause select bit = “0”.
Transmit interrupt
request bit (IR)
“0”
“1”
Stopped pulsing because CTS = “H”
Transferred from UARTi transmit buffer register to UARTi transmit register
Shown in ( ) are bit symbols.
Cleared to “0” when interrupt request is accepted, or cleared by software
Example of transit timing (when internal clock is selected)
Example of receive timing (when external clock is selected)
UART0 to UART2
M30240 Group
Rev. H Sep 18, 2003 Page 89 of 139
1.2.23.1.1 Polarity select function
As shown in Figure 1.83, the CLK polarity select bit (bit 6 at addresses 03A416, 03AC16, 037C16) allows se-
lection of the polarity of the transfer clock.
Figure 1.83: Polarity of transfer clock
1.2.23.1.2 LSB first/MSB first select function
As shown in Figure 1.84, when the transfer format select bit (bit 7 at addresses 03A416, 03AC16, 037C16) =
“0”, the tran sfer format is “LSB firs t”; when the bit = “1”, the transfer format is “MSB first”.
Note: This applies CLK polarity select bit = “0”.
Figure 1.84: Transfer format
1.2.23.1.3 Transfer clock output from multiple pins function (UART1)
This function allows using two transfer cloc k output pins and choosing one of th e two to output a clock by using
the CLK and CLKS select bit (bits 4 and 5 at address 03B016). See Figure 1.85. The multiple pins function is
valid o nly w he n th e i nte rnal c loc k is se lec ted for UART1. Note that when this fun ct ion is se le cte d, the UART1
CTS/RTS function cannot be used.
Figure 1.85: The transfer clock output from th e multiple pins function usage
• When CLK polarity select bit = “1”
Note 2: The CLK pin level when not
transferring data is “L”.
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
0
D
0
T
X
D
i
R
X
D
i
CLK
i
• When CLK polarity select bit = “0”
Note 1: The CLK pin level when not
transferring data is “H”.
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
0
T
X
D
i
R
X
D
i
CLK
i
LSB first
• When transfer format select bit = “0”
D0
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
1
D
2
D
3
D
4
D
5
D
6
D
7
T
X
D
i
R
X
D
i
CLK
i
• When transfer format select bit = “1”
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D
7
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
T
X
D
i
R
X
D
i
CLK
i
MSB first
Microcomputer
T
X
D
1
(P6
7
)
CLKS
1
(P6
4
)
CLK
1
(P6
5
)IN
CLK
IN
CLK
Note: This applies when the internal clock is selected and transmission
is performed only in clock synchronous serial I/O mode.
UART0 to UART2
M30240 Group
Rev. H Sep 18, 2003 Page 90 of 139
1.2.23.1.4 Continuous receive mode
If the continuous receive mode enable bit (bits 2 and 3 at address 03B016, bit 5 at address 037D16) is set to
“1”, the unit is placed in continuous receive mode. In this mode, when the receive buffer register is read out,
the unit si multaneo usly goes to a receiv e enable st ate witho ut having to set dummy data to the tra nsmit buff er
register bac k aga in.
1.2.23.1.5 Serial data logic switch function (UART2)
When the data logic se lec t b it (b it6 at ad dres s 037D16) = “1”, an d w ri ting to tran sm it buffer register or rea din g
from rece ive buffer reg ister, data is reversed. Fi gure 1.86 sho ws the examp le of serial data logic s witch timing .
Figure 1.86: Serial data logic switch timing
D0 D1 D2 D3 D4 D5 D6 D7
D0 D1 D2 D3 D4 D5 D6 D7
Transfer clock
TxD
2
(no reverse)
TxD
2
(reverse)
“H”
“L”
“H”
“L”
“H”
“L”
•When LSB first
UART0 to UART2
M30240 Group
Rev. H Sep 18, 2003 Page 91 of 139
1.2.23.2 Clock asynchronous serial I/O (UART) mode
The UART mode allows transmitting and receiving data after setting the desired transfer rate and
transfer data format. Table 1.27 lists the specifications of the UART mode.
Table 1.27: Specifications of UART mode
Note 1: ‘n’ denotes the value 0016 to FF16 that is set to the UARTi bit rate generator.
Note 2: fEXT is input from the CLKi pin. External clock cannot be selected in UART2.
Note 3: If an overrun error occurs, the UARTi receive buf fer will have the next data written in. Note also that the UARTi receive interrupt
request bit is not set to “1”
Item Specification
Transfer data format
• Character bit (transfer data): 7 bits, 8 bits, or 9 bits as selected
• Start bit: 1 bit
• Parity bit: Odd, even, or nothing as selected
• Stop bit: 1 bit or 2 bits as selected
Transfer clock
• When internal clock is selected (bit 3 at addresses 03A016, 03A816, 037816 = “0”):
fi/16(n+1) (Note 1) fi = f1, f8, f32
• When external clock is selected (bit 3 at addresses 03A016, 03A816=“1”):
fEXT/16(n+1)(Note 1) (Note 2)
Transmission/reception
control • CTS function/RTS fun cti o n / CTS, RTS function disabled
Transmission start condition
• To start transmiss ion, the following requirements must be met:
Transmit enable bit (bit 0 at addresses 03A516, 03AD16, 037D16) = “1”
Transmit buffer empty flag (bit 1 at addresses 03A516, 03AD16, 037D16) = “0”
When CTS function selected, CTS input level = “L”
Reception start condition • To start reception, the following requirements must be met:
Receive enable bit (bit 2 at addresses 03A516, 03AD16, 037D16) = “1”
Start bit detection
Interrupt request generation
timing
• When transmitting
Transmit interrupt cause select bits (bits 0,1 at address 03B016, bit4 at address 037D16) = “0”:
Interrupts requested when data transfer from UARTi transfer buffer register to UARTi transmit
register is completed
Transmit interrupt cause select bits (bits 0, 1 at address 03B016, bit4 at address 037D16) = “1”:
Interrupts requested when data transmiss ion from UARTi transfer register is completed
• When receiving
Interrupts requested when data transfer from UARTi receive register to UARTi receive buffer
register is completed
Error detection
• Overrun error (Note 3)
This error occurs when the next data is ready before contents of UART i receive buffer register are
read out
• Framing error
This error occurs when the number of stop bits set is not detected
• Parity error
This error occurs when if parity is enabled, the number of 1’s in parity and character bits does not
match the number of 1’s set
• Error sum flag
This flag is set (= 1) when any of the overrun, framing, and parity errors is encountered
Select function
• Sleep mode selection (UART0, UART1)
This mode is used to transfer data to and from one of multiple slave micro-computers
•Serial data logic switch (UART2)
This function is reversing logic value of transferring data. Start bit, parity bit and stop bit are not
reversed.
•TxD, RxD I/O polarity switch (UART2)
This function is reversing TxD port output and RxD port input. All I/O data level is reversed.
UART0 to UART2
M30240 Group
Rev. H Sep 18, 2003 Page 92 of 139
Figure 1.87: UARTi transmit/receive mode register.
Table 1.28 lis ts the fun ction s of t he input/o utpu t pi ns d uring UA RT m ode. Note th at f or a per io d f rom
when the UARTi operation mode is selected to when transfer starts, the TxDi pin outputs a “H”.
Table 1.28: Input/output pin functions in UART mode
Pin name Function Method of selectio n
TxDi
(P63, P67, P7 0)Serial data
output Outputs dummy data when performing reception.
RxDi
(P62, P66, P71)Serial data input Port P 62, P66, and P71 direction register (bits 2 and 6 at address 03EE16 bit 1 at address
03EF16)= “0”
(Can be used as an input port when performing transmission only.)
CLKi
(P61, P65, P72)
Programmable I/
O port Internal/external clock select bit (bit 3 at address 03A016, 03A816, 037816) = “0”
Transfer clock
input Internal/external clock select bit (bit 3 at address 03A016, 03A816) = “1”
Port P61, P65 direction register (bits 1 and 5 at address 03EE16) = “0”
CTSi/RTSi
(P60,P64,P73)
CTS input
CTS/RTS disable bit (bit 4 at address 03A416, 03AC16, 037C16) = “0”
CTS/RTS function select bit (bit 2 at address 03A416, 03AC16, 037C16) = “0”
Port P60, P64 and P73 direction register (bits 0 and 4 at address 03EE16, bit 3 at address
03EF16) = “0”
RTS output CTS/RTS disable bit (bit 4 at address 03A416, 03AC16, 037C16) = “0”
CTS/RTS function select bit (bit 2 at address 03A416, 03AC16, 037C16) = “1”
Programmable I/
O port CTS/RTS disable bit (bit 4 at address 03A416, 03AC16, 037C16) = “1”
Symbol Address When reset
UiMR(i=0,1) 03A016, 03A816 0016
CKDIR
UARTi transmit / receive mode registers
Internal / external clock
select bit
STPS
PRY
PRYE
SLEP
0 : Internal clock
1 : External clock (Note)
Bit name FunctionBit symbol WR
b7 b6 b5 b4 b3 b2 b1 b0
SMD0
SMD1
SMD2
Serial I/O mode select bit
b2 b1 b0
0 : One stop bit
1 : Two stop bits
0 : Parity disabled
1 : Parity enabled
0 : Sleep mode deselected
1 : Sleep mode selected
1 0 0 : Transfer data 7 bits long
1 0 1 : Transfer data 8 bits long
1 1 0 : Transfer data 9 bits long
Valid when bit 6 = “1”
0 : Odd parity
1 : Even parity
Stop bit length select bit
Odd / even parity
select bit
Parity enable bit
Sleep select bit
Symbol Address When reset
U2MR 037816 0016
CKDIR
UART2 transmit / receive mode register
Internal / external clock
select bit
STPS
PRY
PRYE
IOPOL
Must always be fixed to “0”
Bit name FunctionBit symbol WR
b7 b6 b5 b4 b3 b2 b1 b0
SMD0
SMD1
SMD2
Serial I/O mode select bit
b2 b1 b0
0 : One stop bit
1 : Two stop bits
0 : Parity disabled
1 : Parity enabled
0 : No reverse
1 : Reverse
1 0 0 : Transfer data 7 bits long
1 0 1 : Transfer data 8 bits long
1 1 0 : Transfer data 9 bits long
Valid when bit 6 = “1”
0 : Odd parity
1 : Even parity
Stop bit length select bit
Odd / even parity
select bit
Parity enable bit
TxD, RxD I/O polarity
reverse bit (Note)
Note: Usually set to “0”.
Note: Set the corresponding port direction register to "0".
UART0 to UART2
M30240 Group
Rev. H Sep 18, 2003 Page 93 of 139
Figure 1.88 and Figure 1.89 show the typical UART mode transmit and receive timing diagrams.
Figure 1.88: Typical receive timing in UART mode
D0
Start bit
Sampled “L”
Receive data taken in
BRGi count
source
Receive enable bit
RxDi
Transfer clock
Receive
complete flag
RTSi
Stop bit
“1”
“0”
“0”
“1”
“H”
“L”
The above timing applies to the following settings :
•Parity is disabled.
•One stop bit.
•RTS function is selected.
Receive interrupt
request bit “0”
“1”
Transferred from UARTi receive register to
UARTi receive buffer register
Reception triggered when transfer clock
is generated by falling edge of start bit
D7D1
Cleared to “0” when interrupt request is accepted, or cleared by software
Example of receive timing when tranfer data is 8 bits long (parity disabled, one-stop bit)
.......
.......
.......
UART0 to UART2
M30240 Group
Rev. H Sep 18, 2003 Page 94 of 139
Figure 1.89: Typical transmit timings in UART mode
Transmit enable
bit(TE)
Transmit buffer
empty flag(TI)
TxDi
Transmit register
empty flag (TXEPT)
“0”
“1”
“0”
“1”
“0”
“1”
The above timing applies to the following settings :
• Parity is disabled.
• Two stop bits.
• CTS function is disabled.
Transfer clock
Tc
Tc = 16 (n + 1) / fi or 16 (n + 1) / f
EXT
fi : frequency of BRGi count source (f 1, f8, f32)
f
EXT : frequency of BRGi count source (external clock)
n : value set to BRGi
Transmit interrupt
request bit (IR) “0”
“1”
Shown in ( ) are bit symbols.
Start
bit
Data is set in UARTi transmit buffer register
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
ST SP
D
8
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
ST D
8
D
0
D
1
ST
SPSP
Transferred from UARTi transmit buffer register to UARTi transmit register
Stop
bit
Stop
bit
SP
Cleared to “0” when interrupt request is accepted, or cleared by software
Transmit enable
bit(TE)
Transmit buffer
empty flag(TI)
Transmit register
empty flag (TXEPT)
Start
bit
Parity
bit
TxDi
CTSi
The above timing applies to the following settings :
• Parity is enabled.
• One stop bit.
• CTS function is selected.
• Transmit interrupt cause select bit = “1”.
“1”
“0”
“1”
“L”
“H”
“0”
“1”
Tc = 16 (n + 1) / fi or 16 (n + 1) / f
EXT
fi : frequency of BRGi count source (f 1, f8, f32)
f
EXT : frequency of BRGi count source (external clock)
n : value set to BRGi
Transmit interrupt
request bit (IR) “0”
“1”
Cleared to “0” when interrupt request is accepted, or cleared by software
Shown in ( ) are bit symbols.
Tc
Transfer clock
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
ST P D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
SP ST PSP D
0
D
1
ST
Stopped pulsing because transmit enable bit = “0”
Stop
bit
Transferred from UARTi transmit buffer register to UARTi transmit register
The transfer clock stops momentarily as CTS is “H” when the stop bit is checked.
The transfer clock starts as the transfer starts immediately CTS changes to “L”.
Data is set in UARTi transmit buffer register.
“0”
• Transmit interrupt cause select bit = "0".
Example of transmit timing when transfer data are 8 bits long (parity enabled, one stop bit)
Example of transmit timing when transfer data are 9 bits long (parity enabled, two stop bits)
UART0 to UART2
M30240 Group
Rev. H Sep 18, 2003 Page 95 of 139
1.2.23.2.1 Sleep mode (UART0, UART1)
This mode is used to transfer data between specific microcomputers among multiple microcomputers con-
nected u sing UARTi. The sleep mode is selected when the sleep select bit (bit 7 at addresses 03A016, 03A816)
is set t o “1” duri ng rec eption. In this mod e, t he u nit pe rform s rece iv e o pera tio n w he n t he M SB o f th e rec ei ve d
data = “1” and does not perform receive operation when the MSB = “0”.
1.2.23.2.2 Function for switching serial data logic (UART2)
When the data logic select bit (bit 6 of address 037D16) is assigned 1, data is inverted in writing to the trans-
mission buffer register or reading the reception buffer register. Figure 1.90 shows the example of timing for
switching serial data logic.
Figure 1.90: Timing for switching serial data logic
1.2.23.2.3 TxD, RxD I/O polarity reverse function (UART2)
This function is to reverse TxD pin output and RxD pin input. The level of any data to be input or output (in-
cluding the st art bit, stop bit(s), an d parity bit) is reverse d. Set this functio n to “0” (not to reverse) for usua l use.
1.2.23.2.4 Bus collision detection function (UART2)
This function is to sample the output level of the TxD pin and the input level of the RxD pin at the rising edge
of the transfer clock; if their values are different, then an interrupt request occurs. Figure 1.91 shows the ex-
ample of detection timing of a buss collision (in UART mode).
Figure 1.91: Detection timing of a bus collision (in UART mode)
ST : Start bit
P : Even parity
SP : Stop bit
D0 D1 D2 D3 D4 D5 D6 D7 P SPST
SPST D3 D4 D5 D6 D7 PD0 D1 D2
Transfer clock
TxD2
(no reverse)
TxD2
(reverse)
“H”
“L”
“H”
“L”
“H”
“L”
Example of timing for switching serial data logic when LSB is first (parity enabled, one-stop bit)
ST : Start bit
SP : Stop bit
ST
ST
SP
SP
Transfer clock
TxD2
RxD2
Bus collision detection
interrupt request signal
“H”
“L”
“H”
“L”
“H”
“L”
“1”
“0”
Bus collision detection
interrupt request bit
“1”
“0”
UART0 to UART2
M30240 Group
Rev. H Sep 18, 2003 Page 96 of 139
1.2.23.3 Clock-asynchronous serial I/O mode (compliant with the SIM interface)
The SIM interface is used for connecting the microcomputer with a memory card I/C or the like; adding
some extra settings in UART2 clock-asynchronous serial I/O mode allows the user to effect this func-
tion. Table 1.2 9 shows the speci fications of clock- asynchrono us serial I/O mode (compl iant with the
SIM interface). Figure 1.92 shows the typical transmit/receive timing in UART mode.
Note 1: ‘n’ denotes the value 0016 to FF16 that is set to the UARTi bit rate generator.
Note 2: If an overrun error occurs, the UART2 receive buffer will have the next data written in. Also, the UARTi receive interrupt request bit
is no t se t to “1”.
Table 1.29: Specifications of clock-asynchronous serial I/O mode (compliant with the SIM interface)
Item Specification
Transfer data
format
• Transfer data 8-bit UART mode (bit 2 through bit 0 of address 037816 = “1012”)
• One stop bit (bit 4 of address 037816 = “0”)
• With the direct format chosen
Set parity to “even” (bit 5 and bit 6 of address 037816 = “1” and “1” respectively)
Set data logic to “direct” (bit 6 of address 037D16 = “0”).
Set transfer format to LSB (bit 7 of address 037C16 = “0”).
• With the inverse format chosen
Set parity to “odd” (bit 5 and bit 6 of address 037816 = “0” and “1” respectively)
Set data logic to “inverse” (bit 6 of address 037D16 = “1”)
Set transfer format to MSB (bit 7 of address 037C16 = “1”)
Transfer clock • With the internal clock chosen (bit 3 of address 037816 = “0”): fi / 16 (n + 1) (Note 1): fi=f1, f8, f32
Transmission /
reception control • Disable the CTS and RTS function (bit 4 of address 037C16 = “1”)
Other settings • The sleep mode select function is not available for UART2
• Set transmission interrupt factor to “transmission completed” (bit 4 of address 037D16 = “1”)
Transmission start
condition
• To start transmission, the following requirements must be met:
Transmit enable bit (bit 0 of address 037D16) = “1”
Transmit buf f er empty flag (bit 1 of address 037D16) = “0”
Reception start
condition
• To start reception, the following requirements must be met:
Reception enable bit (bit 2 of address 037D16) = “1”
Detection of a start bit
Interrupt request
generation timing
• When transmitting
When data transmission from the UART2 transfer register is completed (bit 4 of address 037D16 = “1”)
• When receiving
When data transfer from the UART2 receive register to the UART2 receive buffer register is completed
Error detection
• Overrun error (see the specifications of clock-asynchronous serial I/O) (Note 3)
• Framing error (see the specifications of clock-asynchronous serial I/O)
• Parity error (see the specifications of clock-asynchronous serial I/O)
On the reception side, an “L” level is output from the TxD2 pin by use of the parity error signal output
function (bit 7 of address 037D16 = “1”) when a parity error is detected
On the transmission side, a parity error is detected by the level of input to the RxD2 pin when a
transmission interrupt occurs
• The error sum flag (see the specifications of clock-asynchronous serial I/O)
UART0 to UART2
M30240 Group
Rev. H Sep 18, 2003 Page 97 of 139
Figure 1.92: Typical transmit/receive timing in UART mode (compliant with the SIM interface)
Transmit enable
bit(TE)
Transmit buffer
empty flag(TI)
Transmit register
empty flag (TXEPT)
D0D1D2D3D4D5D6D7ST P
Start
bit Parity
bit
The above timing applies to the following settings :
• Parity is enabled.
• One stop bit.
• Transmit interrupt cause select bit = “1”.
“0”
“1”
“0”
“1”
“0”
“1”
Tc = 16 (n + 1) / fi
fi : frequency of BRG2 count source (f
1
, f
8
, f
32
)
n : value set to BRG2
Transmit interrupt
request bit (IR)
“0”
“1”
D0D1D2D3D4D5D6D7ST P
Shown in ( ) are bit symbols.
Tc
Transfer clock
SP
Stop
bit
Data is set in UART2 transmit buffer register
SP
A “L” level returns from TxD
2
due to
the occurrence of a parity error.
The level is detected by the
interrupt routine.
The level is
detected by the
interrupt routine.
Receive enable
bit (RE)
Receive complete
flag (RI)
D0D1D2D3D4D5D6D7
ST P
Start
bit
Parity
bit
RxD2
The above timing applies to the following settings :
• Parity is enabled.
• One stop bit.
• Transmit interrupt cause select bit = “0”.
“0”
“1”
“0”
“1”
Tc = 16 (n + 1) / fi
fi : frequency of BRG2 count source (f
1
, f
8
, f
32
)
n : value set to BRG2
Receive interrupt
request bit (IR)
“0”
“1”
D0D1D2D3D4D5D6D7
ST PSP
Shown in ( ) are bit symbols.
Tc
Transfer clock
SP
Stop
bit
A “L” level returns from TxD
2
due to
the occurrence of a parity error.
TxD2
Read to receive buffer Read to receive buffer
D0D1D2D3D4D5D6D7
ST P
Signal conductor level
(Note 2)
D0D1D2D3D4D5D6D7
ST PSP
SP
D0D1D2D3D4D5D6D7ST PD0D1D2D3D4D5D6D7ST PSP
SP
TxD2
RxD2
Signal conductor level
(Note 2)
Transferred from UART2 transmit buffer register to UART2 transmit register
Cleared to “0” when interrupt request is accepted, or cleared by software
Cleared to “0” when interrupt request is accepted, or cleared by software
Note 1: The transmit is started with overflow timing of BRG after having written in a value at the transmit buffer in the above timing.
Note 1
Note 2: Equal in waveform because TxD2 and RxD2 are connected.
Note 2: Equal in waveform because TxD2 and RxD2 are connected.
UART0 to UART2
M30240 Group
Rev. H Sep 18, 2003 Page 98 of 139
1.2.23.3.1 Function for outputting a parity error signal
With the error sign al output enabl e bit (bit 7 of address 037D 16) assig ned “1 ”, you can o utput an “L” l evel from
the TxD 2 pi n when a pa rity e rror is detec ted. In step wit h this func tion, the g enerati on tim ing of a tr ansmi ssio n
comple tion i nterrupt chang es to the det ection timi ng of a pa rity er ror sig nal. Fi gure 1. 93 sho ws the out put tim -
ing of the parity error signal.
Figure 1.93: Output timing of the parity error signal
1.2.23.3.2 Di rec t format /inver se for mat
Connecting the SIM card allows you to switch between direct format and inverse format. If you choose the
direct format, D0 data is output from TxD2. If you choose the inverse format, D7 data is inverted and ou tput
from TxD2.
Figure 1.94 shows the SIM interface format.
Figure 1.94: SIM interface format
Figure 1.95 shows the example of connecting the SIM interface with TxD2 and RxD2.
Figure 1.95: Connecting the SIM interface
ST : Start bit
P : Even Parity
D0 D1 D2 D3 D4 D5 D6 D7 P SPST
Hi-Z
Transfer
clock
RxD
2
TxD
2
Receive
complete flag
“H”
“L”
“H”
“L”
“H”
“L”
“1”
• LSB first
“0”
SP: Stop bit
P : Even parity
D0 D1 D2 D3 D4 D5 D6 D7 P
Transfer
clock
TxD2
(direct)
TxD2
(inverse) D7 D6 D5 D4 D3 D2 D1 D0 P
Microcomputer
SIM card
TxD
2
RxD
2
A-D Converter
M30240 Group
Rev. H Sep 18, 2003 Page 99 of 139
1.2.24 A-D Converter
The A-D converter consists of one 10-bit successive approximation A-D converter circuit with a
capaci tive co upli ng ampl ifier. Pins P100 to P 107 func tion as th e ana log sign al inpu t pins . The dir ectio n
regist ers of these pins for A-D co nversion mu st therefore be se t to input. The Vref connect bit (bit 5 at
addres s 03D716) can be used to is olate the r esistance ladder of the A-D converter fr om the refe rence
voltage input pin (VREF) when the A-D converter is not used. Doing so stops any current flowing into the
resistance ladder fr om VREF, re ducing the power dis sipation. When using the A-D converter, start A-D
conversion only after setting bit 5 of 03D716 to connect VREF.
The result of A-D conversion is stored in the A-D registers of the selected pins. When set to 10-bit
precision, the low 8 bits are stored in the even addresses and the high 2 bits in the odd addresses. When
set to 8-bit precision, the low 8 bits are stored in the even addresses.
Table 1.30 shows the performance of the A-D converter . Figure 1.96 shows the block diagram of the A-
D converter, and Figure 1.97 and Figure 1.98 show the A-D converter-related registers.
Table 1.30: Performance of A-D Convertera
a.
Item Performance
Method of A-D conve r si on Successive app rox im ati on (capac iti ve coupl ing ampl ifi er)
Analog input voltage (Note) 0V to AVCC (VCC)
Operati ng clo ck fAD VCC = 5V fAD/div id e-by -2 or fAD/divide-by-4 or fAD, fAD,f(XIN)
Resolution 8-bit or 10-bit (selectable)
Absolute precision VCC = 5V
• Without sample and hold function
±3LSB
• With sample and hold function (8-bit resolution)
±2LSB
• With sample and hold function (10-bit resolution)
3LSB
Operati ng modes One-shot mode, repeat mode, single sweep mode, repeat sweep mode 0, and
repeat sweep mode 1
Analog input pins 8pins (AN0 to AN7)
A-D conversion start condition
•Softw are trig ger
A-D conversion starts when the A-D conversion start flag changes to “1”
•External trigger (can be re-triggered)
A-D convers ion st arts when the A-D convers ion sta rt flag is “1” an d the ADTRG/P87
input changes from “H” to “L”
Conversion speed per pin
•Without sample and hold function
8-bit resolu tio n: 49 φAD cycles, 10-bit resolution: 59 φAD cycl es
• With sample and hold function
8-bit resolu tio n: 28 φAD cycles, 10-bit resolution: 33 φAD cycl es
Note: Does not depend on use of sample and hold function
A-D Converter
M30240 Group
Rev. H Sep 18, 2003 Page 100 of 139
Figure 1.96: Block diagram of A-D converter
1/2
φ
AD
1/2
fAD
A-D conversion rate
selection
(03C1
16
, 03C0
16
)
(03C3
16
, 03C2
16
)
(03C5
16
, 03C4
16
)
(03C7
16
, 03C6
16
)
(03C9
16
, 03C8
16
)
(03CB
16
, 03CA
16
)
(03CD
16
, 03CC
16
)
(03CF
16
, 03CE
16
)
CKS1=1
CKS0=0
A-D register 0(16)
A-D register 1(16)
A-D register 2(16)
A-D register 3(16)
A-D register 4(16)
A-D register 5(16)
A-D register 6(16)
A-D register 7(16)
Resistor ladder
Successive conversion register
AN
0
AN
1
AN
2
AN
3
AN
5
AN
6
AN
7
A-D control register 0 (address 03D6
16
)
A-D control register 1 (address 03D7
16
)
V
ref
V
IN
Data bus high-order
Data
bus low-order
VREF
AN
4
VCUT=0
AV SS
VCUT=1
CKS0=1
CKS1=0
CH2,CH1,CH0=000
CH2,CH1,CH0=001
CH2,CH1,CH0=010
CH2,CH1,CH0=011
CH2,CH1,CH0=100
CH2,CH1,CH0=101
CH2,CH1,CH0=110
CH2,CH1,CH0=111
Decoder
Comparator
Addresses
A-D Converter
M30240 Group
Rev. H Sep 18, 2003 Page 101 of 139
Figure 1.97: A-D converter-related registers (1)
A-D control register 0 (Note 1)
Symbol Address When reset
ADCON0 03D616 00000XXX2
b7 b6 b5 b4 b3 b2 b1 b0
Analog input pin select bit 0 0 0 : AN
0
is selected
0 0 1 : AN
1
is selected
0 1 0 : AN
2
is selected
0 1 1 : AN
3
is selected
1 0 0 : AN
4
is selected
1 0 1 : AN
5
is selected
1 1 0 : AN
6
is selected
1 1 1 : AN
7
is selected (Note 2)
CH0
Bit symbol Bit name Function
CH1
CH2
A-D operation mode
select bit 0 0 0 : One-shot mode
0 1 : Repeat mode
1 0 : Single sweep mode
1 1 : Repeat sweep mode 0
Repeat sweep mode 1 (Note 2)
MD0
MD1
Trigger select bit 0 : Software trigger
1 : AD
TRG
trigger
TRG
ADST A-D conversion start flag 0 : A-D conversion disabled
1 : A-D conversion started
Frequency select bit 0 0 : f
AD
/4 is selected
1 : f
AD
/2 is selected
CKS0
WR
A-D control register 1 (Note)
Symbol Address When reset
ADCON1 03D716 0016
Bit name FunctionBit symbol
b7 b6 b5 b4 b3 b2 b1 b0
A-D sweep pin select bit
SCAN0
SCAN1
MD2
BITS 8/10-bit mode select bit 0 : 8-bit mode
1 : 10-bit mode
VCUT Vref connect bit
A-D operation mode
select bit 1
0 : Any mode other than repeat sweep
mode 1
1 : Repeat sweep mode 1
0 : Vref not connected
1 : Vref connected
WR
b2 b1 b0
b4 b3
When single sweep and repeat sweep
mode 0 are selected
0 0 : AN
0
, AN
1
(2 pins)
0 1 : AN
0
to AN
3
(4 pins)
1 0 : AN
0
to AN
5
(6 pins)
1 1 : AN
0
to AN
7
(8 pins)
b1 b0
When repeat sweep mode 1 is selected
0 0 : AN
0
(1 pin)
0 1 : AN
0
, AN
1
(2 pins)
1 0 : AN
0
to AN
2
(3 pins)
1 1 : AN
0
to AN
3
(4 pins)
b1 b0
Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result is
indeterminate.
Note 2: When changing A-D operation mode, set analog input pin again.
Frequency select bit 1 0 : f
AD
/2 or f
AD
/4 is selected
1 : f
AD
is selected
CKS1
Note: If the A-D control register is rewritten during A-D conversion, the conversion result is
indeterminate.
Reserved bit Always set to "0"
0
0
A-D Converter
M30240 Group
Rev. H Sep 18, 2003 Page 102 of 139
Figure 1.98: A-D converter-related registers (2)
A-D control register 2 (Note)
Symbol
Address When reset
ADCON2 03D416 0000XXX02
b7 b6 b5 b4 b3 b2 b1 b0
A-D conversion method
select bit
0 : Without sample and hold
1 : With sample and hold
Bit symbol Bit name Function R W
Note : If the A-D control register is rewritten during A-D conversion, the conversion
result is indeterminate.
A-D register i Symbol
Address When reset
ADi(i=0 to 7) 03C0
16
to 03CF
16
Indeterminate
Eight low-order bits of A-D conversion result
Function R W
(b15)
b7b7 b0 b0
(b8)
• During 10-bit mode
Two high-order bits of A-D conversion result
• During 8-bit mode
When read, the content is indeterminate
SMP
Reserved bit Always set to “0”
000
SSH Simultaneous sample and
hold
0 : Disabled
1 : Enabled
Nothing is assigned. Write "0" when writing to these bits.
When read, the value is "0".
Nothing is assigned. Write "0" when writing to these bits.
When read, the value is "0".
A-D Converter
M30240 Group
Rev. H Sep 18, 2003 Page 103 of 139
1.2.24.1 One-shot mode
In one-shot mode, the pin selected using the analog input pin select bit is used for one-shot A-D con-
version.Table 1.31 shows the specifications of one-shot mode. Figure 1.99 shows the A-D control reg-
ister in one-shot mode.
Figure 1.99: A-D conversion register in one-shot mode
Table 1.31: One-shot mode specification
Item Specification
Function The pin selected by the analog input pin select bit is used for one A-D conversion
Start condition Writing “1” to A-D conversion start flag
Stop condition •End of A-D conversion (A-D conversion start flag changes to “0”, except when
external trigger is selected)
•Wri ting “0” to A-D conversi on st a rt flag
Interrupt request generation
timing End of A-D con ve rsi on
Input pin One of AN0 to AN7, as selec ted
Readi ng of result of A-D converter Read A-D register corresp onding to select ed pin
A-D control register 0 (Note 1)
Symbol Address When reset
ADCON0 03D616 00000XXX2
b7 b6 b5 b4 b3 b2 b1 b0
Analog input pin select
bit
Bit symbol Bit name Function
CH1
CH2
A-D operation mode
select bit 0
MD0
MD1
Trigger select bit 0 : Software trigger
1 : AD
TRG
trigger
TRG
ADST A-D conversion start flag 0 : A-D conversion disabled
1 : A-D conversion started
Frequency select bit 0 0: f
AD
/4 is selected
1: f
AD
/2 is selected
CKS0
WR
00
A-D control register 1 (Note)
Symbol Address When reset
ADCON1 03D716 0016
Bit name FunctionBit symbol
b7 b6 b5 b4 b3 b2 b1 b0
A-D sweep pin
select bit
SCAN0
SCAN1
MD2
BITS 8/10-bit mode select bit 0 : 8-bit mode
1 : 10-bit mode
VCUT Vref connect bit
A-D operation mode
select bit 1
0 : Any mode other than repeat sweep
mode 1
1 : Vref connected
WR
Invalid in one-shot mode
0
0 0 0 : AN
0
is selected
0 0 1 : AN
1
is selected
0 1 0 : AN
2
is selected
0 1 1 : AN
3
is selected
1 0 0 : AN
4
is selected
1 0 1 : AN
5
is selected
1 1 0 : AN
6
is selected
1 1 1 : AN
7
is selected (Note 2)
b2 b1 b0
0 0 : One-shot mode (Note 2)
b4 b3
CH0
1
Note 1: If the A-D control register is rewritten during A-D conversion, the conversion
result is indeterminate.
Note 2: When changing A-D operation mode, set analog input pin again.
Frequency select bit1 0 : f
AD
/2 or f
AD
/4 is selected
1 : f
AD
is selected
CKS1
Note: If the A-D control register is rewritten during A-D conversion, the conversion
result is indeterminate.
Reserved bit Always set to "0"
0
0
A-D Converter
M30240 Group
Rev. H Sep 18, 2003 Page 104 of 139
1.2.24.2 Repeat mode
In repeat mode, the pin selected using the analog input pin select bit is used for repeated A-D conver-
sion.Table 1.32 shows the specifications of repeat mode. Figure 1.100 shows the A-D control register
in repeat mode.
Figure 1.100: A-D conversion register in repeat mode
Table 1.32: Repeat mode specification
Item Specification
Function The pin selected by the analog input pin select bit is used for repeated A-D
Star condition Writing “1” to A-D conversion start flag
Stop condition Writing “0” to A-D conversion start flag
Interrupt request generation timing None generated
Input pin One of AN0 to AN7, as selected
Reading of result of A-D converter Read A-D register corresponding to selected pin
A-D control register 0 (Note 1)
Symbol
Address
When reset
ADCON0
03D6
16
00000XXX
2
b7 b6 b5 b4 b3 b2 b1 b0
Analog input pin
select bit
CH0
Bit symbol Bit name Function
CH1
CH2
A-D operation mode
select bit 0
MD0
MD1
Trigger select bit 0 : Software trigger
1 : ADTRG trigger
TRG
ADST A-D conversion start flag 0 : A-D conversion disabled
1 : A-D conversion started
Frequency select bit 0 0 : fAD/4 is selected
1 : fAD/2 is selected
CKS0
WR
A-D control register 1 (Note)
Symbol
Address
When reset
ADCON1
03D7
16
00
16
Bit name FunctionBit symbol
b7 b6 b5 b4 b3 b2 b1 b0
A-D sweep pin
select bit
SCAN0
SCAN1
MD2
BITS 8/10-bit mode select bit 0 : 8-bit mode
1 : 10-bit mode
VCUT Vref connect bit
A-D operation mode
select bit 1
1 : Vref connected
WR
01
Invalid in repeat mode
0
0 0 0 : AN0 is selected
0 0 1 : AN1 is selected
0 1 0 : AN2 is selected
0 1 1 : AN3 is selected
1 0 0 : AN4 is selected
1 0 1 : AN5 is selected
1 1 0 : AN6 is selected
1 1 1 : AN7 is selected (Note 2)
b2 b1 b0
0 1 : Repeat mode (Note 2)
b4 b3
1
Note 1: If the A-D control register is rewritten during A-D conversion, the conversion
result is indeterminate.
Note 2: When changing A-D operation mode, set analog input pin again.
Frequency select bit 1 0 : fAD/2 or fAD/4 is selected
1 : fAD is selected
CKS1
0 : Any mode other than repeat sweep mode 1
Note: If the A-D control register is rewritten during A-D conversion, the conversion
result is indeterminate.
Reserved bit Always set to "0"
0
0
A-D control register 0 (Note 1)
Symbol
Address
When reset
ADCON0
03D6
16
00000XXX
2
b7 b6 b5 b4 b3 b2 b1 b0
Analog input pin
select bit
CH0
Bit symbol Bit name Function
CH1
CH2
A-D operation mode
select bit 0
MD0
MD1
Trigger select bit 0 : Software trigger
1 : ADTRG trigger
TRG
ADST A-D conversion start flag 0 : A-D conversion disabled
1 : A-D conversion started
Frequency select bit 0 0 : fAD/4 is selected
1 : fAD/2 is selected
CKS0
WR
A-D control register 1 (Note)
Symbol
Address
When reset
ADCON1
03D7
16
00
16
Bit name FunctionBit symbol
b7 b6 b5 b4 b3 b2 b1 b0
A-D sweep pin
select bit
SCAN0
SCAN1
MD2
BITS 8/10-bit mode select bit 0 : 8-bit mode
1 : 10-bit mode
VCUT Vref connect bit
A-D operation mode
select bit 1
1 : Vref connected
WR
01
Invalid in repeat mode
0
0 0 0 : AN0 is selected
0 0 1 : AN1 is selected
0 1 0 : AN2 is selected
0 1 1 : AN3 is selected
1 0 0 : AN4 is selected
1 0 1 : AN5 is selected
1 1 0 : AN6 is selected
1 1 1 : AN7 is selected (Note 2)
b2 b1 b0
0 1 : Repeat mode (Note 2)
b4 b3
1
Note 1: If the A-D control register is rewritten during A-D conversion, the conversion
result is indeterminate.
Note 2: When changing A-D operation mode, set analog input pin again.
Frequency select bit 1 0 : fAD/2 or fAD/4 is selected
1 : fAD is selected
CKS1
0 : Any mode other than repeat sweep mode 1
Note: If the A-D control register is rewritten during A-D conversion, the conversion
result is indeterminate.
Reserved bit Always set to "0"
0
0
A-D Converter
M30240 Group
Rev. H Sep 18, 2003 Page 105 of 139
1.2.24.3 Single-sweep mode
In single -sweep mo de, th e pins sele ct ed using the A -D swee p pin se lect bi t are use d for one-b y-on e
A-D conversion. Table 1.33 shows the specifications of single-sweep mode. Figure 1.101 shows the
A-D contr ol regi ste r in si ngle- sw eep mode.
Figure 1.101: A-D conversion register in single-sweep mode
Table 1.33: Single-sweep mode specification
Item Specification
Function The pins selected by the A-D sweep pin select bit are used for one-by-one A-D conversion
Start condition Writing “1” to A-D converter start flag
Stop condition •End of A-D conversio n (A-D con ver sio n start flag changes to “0”, ex ce pt w hen external trigger is
selected)
•Wri ting “0” to A-D conversi on st a rt flag
Interrupt request
generati on tim ing End of A-D conve r si on
Input pin AN0 and AN1 (2 pins), AN0 to AN3 (4 pins), AN0 to AN5 (6 pins), or AN0 to AN7 (8 pins)
Reading of result
of A-D converter Read A-D register corresponding to selected pin
A-D control register 0 (Note)
Symbol
Address
When reset
ADCON0
03D6
16
00000XXX
2
b7 b6 b5 b4 b3 b2 b1 b0
Analog input pin
select bit
CH0
Bit symbol Bit name Function
CH1
CH2
A-D operation mode
select bit 0
1 0 : Single sweep mode
MD0
MD1
Trigger select bit 0 : Software trigger
1 : AD
TRG
trigger
TRG
ADST A-D conversion start flag 0 : A-D conversion disabled
1 : A-D conversion started
Frequency select bit 0 0 : f
AD
/4 is selected
1 : f
AD
/2 is selected
CKS0
WR
A-D control register 1 (Note)
Symbol
Address
When reset
ADCON1
03D7
16
00
16
Bit name FunctionBit symbol
b7 b6 b5 b4 b3 b2 b1 b0
A-D sweep pin select bit
SCAN0
SCAN1
MD2
BITS 8/10-bit mode select bit 0 : 8-bit mode
1 : 10-bit mode
VCUT Vref connect bit
0 : Any mode other than repeat sweep mode 1
A-D operation mode
select bit 1
1 : Vref connected
WR
10
Invalid in single sweep mode
0
Note : If the A-D control register is rewritten during A-D conversion, the conversion result
is indeterminate.
b4 b3
When single sweep and repeat sweep mode 0
are selected
0 0 : AN
0
, AN
1
(2 pins)
0 1 : AN
0
to AN
3
(4 pins)
1 0 : AN
0
to AN
5
(6 pins)
1 1 : AN
0
to AN
7
(8 pins)
b1 b0
1
Note: If the A-D control register is rewritten during A-D conversion, the conversion result
is indeterminate.
Frequency select bit 1 0 : f
AD
/2 or f
AD
/4 is selected
1 : f
AD
is selected
CKS1
Reserved bit Always set to "0"
0
0
A-D Converter
M30240 Group
Rev. H Sep 18, 2003 Page 106 of 139
1.2.24.4 Repeat -sweep mode 0
In repeat-sweep mode 0, the pins selected using the A-D sweep pin select bit are used for repeat
sweep A-D conversion. Table 1.34 shows the specifications of repeat-sweep mode 0. Figure 1.102
shows the A-D control register in repeat-sweep mode 0.
Figure 1.102: A-D conversion register in repeat-sweep mode 0
Table 1.34: Repeat-sweep mode 0 specifications
Item Specification
Function The pins selecte d by the A-D sweep pin s elect bit are used for re peat sweep A-D
conversion
Start condition Writing “1” to A-D conversi on start flag
Stop condition Writing “0” to A-D conversion start flag
Interrupt request generation timing None generated
Input pin AN0 and AN1 (2 pins), AN0 to AN3 (4 pins), AN0 to AN5 (6 pins), or AN0 to AN7 (8
pins)
Reading of result of A-D converter Read A-D register corresponding to selected pin (at any time)
A-D control register 0 (Note)
Symbol
Address
When reset
ADCON0
03D6
16
00000XXX
2
b7 b6 b5 b4 b3 b2 b1 b0
Analog input pin
select bit
CH0
Bit symbol Bit name Function
CH1
CH2
A-D operation mode
select bit 0 1 1 : Repeat sweep mode 0
MD0
MD1
Trigger select bit 0 : Software trigger
1 : ADTRG trigger
TRG
ADST A-D conversion start flag 0 : A-D conversion disabled
1 : A-D conversion started
Frequency select bit 0 0 : fAD/4 is selected
1 : fAD/2 is selected
CKS0
WR
A-D control register 1 (Note)
Symbol
Address
When reset
ADCON1
03D7
16
00
16
Bit name FunctionBit symbol
b7 b6 b5 b4 b3 b2 b1 b0
A-D sweep pin select bit
SCAN0
SCAN1
MD2
BITS 8/10-bit mode select bit 0 : 8-bit mode
1 : 10-bit mode
VCUT Vref connect bit
0 : Any mode other than repeat sweep mode 1A-D operation mode
select bit 1
1 : Vref connected
WR
11
Invalid in repeat sweep mode 0
0
Note: If the A-D control register is rewritten during A-D conversion, the conversion result
is indeterminate.
b4 b3
When single sweep and repeat sweep mode 0
are selected
0 0 : AN 0, AN1 (2 pins)
0 1 : AN 0 to AN3 (4 pins)
1 0 : AN 0 to AN5 (6 pins)
1 1 : AN 0 to AN7 (8 pins)
b1 b0
1
Note: If the A-D control register is rewritten during A-D conversion, the conversion result
is indeterminate.
Frequency select bit 1 0 : fAD/2 or fAD/4 is selected
1 : fAD is selected
CKS1
Reserved bit
Always set to "0"
0
0
A-D Converter
M30240 Group
Rev. H Sep 18, 2003 Page 107 of 139
1.2.24.5 Repeat -sweep mode 1
In repeat-sweep mode 1, all pins are used for A-D conversion with emphasis on the pin or pins select-
ed using the A-D swe ep pin sel ect bit. Table 1. 35 shows the sp ecifi cations of repeat-swe ep mode 1.
Figure 1.103 show the A-D control in repeat-sweep mode 1.
Table 1.35: Repeat-sweep mode 1 specification
Figure 1.103: A-D conversion register in repeat-sweep mode 1
Item Specification
Function All pins perform repeat sweep A-D conversion, with emphasis on the pin or
pins selected by the A-D sweep pin select bit
Example: AN0 selected AN0 -> AN1 -> AN0 -> AN2 -> AN0 -> AN3, etc.
Start condition Writing “1” to A-D conversion start flag
Stop condition Writing “0” to A-D conversion start flag
Interrupt request generation timing None generated
Input pin AN0 (1 pin), AN0 and AN1 (2 pins), AN0 to AN2 (3 pins), AN0 to AN3 (4 pins)
Reading of result of A-D converter Read A-D register corresponding to selected pin (at any time)
A-D control register 0 (Note)
Symbol
Address
When reset
ADCON0
03D6
16
00000XXX
2
b7 b6 b5 b4 b3 b2 b1 b0
Analog input pin
select bit
CH0
Bit symbol Bit name Function
CH1
CH2
A-D operation mode
select bit 0 1 1 : Repeat sweep mode 1
MD0
MD1
Trigger select bit 0 : Software trigger
1 : AD
TRG
trigger
TRG
ADST A-D conversion start flag 0 : A-D conversion disabled
1 : A-D conversion started
Frequency select bit 0 0 : f
AD
/4 is selected
1 : f
AD
/2 is selected
CKS0
WR
A-D control register 1 (Note)
Symbol
Address
When reset
ADCON1
03D7
16
00
16
Bit name FunctionBit symbol
b7 b6 b5 b4 b3 b2 b1 b0
A-D sweep pin select bit
SCAN0
SCAN1
MD2
BITS 8/10-bit mode select bit 0 : 8-bit mode
1 : 10-bit mode
VCUT Vref connect bit
1 : Repeat sweep mode 1
A-D operation mode
select bit 1
1 : Vref connected
WR
11
Invalid in repeat sweep mode 1
1
Note: If the A-D control register is rewritten during A-D conversion, the conversion result
is indeterminate.
b4 b3
When repeat sweep mode 1 is selected
0 0 : AN
0
(1 pin)
0 1 : AN
0
, AN
1
(2 pins)
1 0 : AN
0
to AN
2
(3 pins)
1 1 : AN
0
to AN
3
(4 pins)
b1 b0
1
Note: If the A-D control register is rewritten during A-D conversion, the conversion result
is indeterminate.
Frequency select bit 1 0 : f
AD
/2 or f
AD
/4 is selected
1 : f
AD
is selected
CKS1
0
0
Reserved bit Always set to "0"
A-D Converter
M30240 Group
Rev. H Sep 18, 2003 Page 108 of 139
1.2.24.6 Sample and hold
Sample and hold is selected by setting bit 0 of the A-D control register 2 (address 03D416) to “1”. When
sample and hold is selected, the rate of conversion of each pin increases. As a result, a 28 φ AD cycle
is a chieved with 8-bit resolution and 33 φ AD with 10-bit resolution. Sample and hold can be selected
in all modes. However, in all modes, be sure to specify before starting A-D conversion whether sample
and hold is to be used.
CRC Calculation Circuit
M30240 Group
Rev. H Sep 18, 2003 Page 109 of 139
1.2.25 CRC Calculation Circuit
The Cyclic Redundancy Check (CRC) calculation circuit detects an error in data blocks. The
microcomputer uses a generator polynomial of CRC_CCITT (X16 + X12 + X5 + 1) to generate CRC code.
The CRC code is a 16-bit code g enerated for a block of a giv en data length in m ultiples of 8 bi ts. The
CRC code is set in a CRC data register each time one byte of data is transferred to a CRC input register
after writing an initia l value into the CRC data register. Generat ion of CRC code for one byte of data is
comple ted in two m achine cycles .
Figure 1.104 shows the block diagram of the CRC circuit. Figure 1.105 shows the CRC-related registers.
Figure 1.104: Block diagram of CRC circuit
Figure 1.105: CRC-related registers
Eight low-order bits Eight high-order bits
Data bus high-order bits
Data bus low-order bits
CRC data register (16)
CRC input register (8)
CRC code generating circuit
x16 + x12 + x5 + 1
(Addresses 03BD16, 03BC
(Address 03BE
16)
16)
Symbol
Address
When reset
CRCD
03BD
16
, 03BC
16
Indeterminate
b7 b0 b7 b0
(b15) (b8)
CRC data register
WR
CRC calculation result output register
Function Values that
can be set
0000
16
to FFFF
16
Symbo
Address
When reset
CRCIN
03BE
16
Indeterminate
b7 b0
CRC input register
WR
Data input register
Function Values that
can be set
00
16
to FF
16
Programmable I/O Ports
M30240 Group
Rev. H Sep 18, 2003 Page 110 of 139
1.2.26 Programmable I/O Ports
There ar e 63 prog rammabl e I/O ports : P0 to P3, P6 to P8 (exc ludi ng P85), and P10. Each port can be
set inde pendent ly for input or outp ut usin g the directi on regist er. A pu ll-up re sist ance for ea ch block of
4 ports can be set. P85 is an input-only port and has no built-in pull-up resistance.
Figure 1.106, Figure 1.107 and Figure 1.108 show the programmable I/O ports.
Each pin functions as a programmable I/O port and as the I/O for the built-in peripheral devices.
To use the pin s a s t he i npu ts f or the built- in per ipheral d evi ce s, set the di re cti on regis ter o f eac h p in to
input mode . When the pins are us ed as the ou tputs fo r the built-in perip heral dev ices, they function as
outputs regardless of the contents of the direction registers. Unused I/O pins can be terminated as
shown in Figure 1.113 and Table 1.36 .
1.2.26.1 Direction registers
Figure 1.109 shows the direction registers.
These registers are used to choose the direction of the programmable I/O ports. Each bit in these reg-
isters corresponds one for one to each I/O pin.
Note: There is no direction register bit for P85.
1.2.26.2 Port registers
Figure 1.110 shows the port registers.
These registe rs are used to write and r ead da ta for in put and ou tput to and from an ex ternal de vic e.
A port register consists of a port latch to hold output data and a circuit to read the status of a pin. Each
bit in port registers corresponds one for one to each I/O pin.
1.2.26.3 Pull-up control registers
Figure 1.111 shows the pull-up control registers.The pull-up control register can be set to apply a pull-
up resistance t o each block o f 4 ports. When ports are set t o have a pull-up resistance, the pull-up
resistance is connected only when the direction register is set for input.
1.2.26.4 High drive capacity registers
Figure 1.112 shows the Port 2 and PWM drive capacity register. Port 2 can be configured to drive an
LED by increasing the drive strength of the corresponding bit’s N-channel transistor. Each Timer out-
put (TA0OUT toTA4OUT) can be configured for high-drive capability by increasing the drive strength of
the corresponding bits.
Programmable I/O Ports
M30240 Group
Rev. H Sep 18, 2003 Page 111 of 139
Figure 1.106: Programmable I/O ports (1)
P3
0
to P3
6
Port latch
Pull-up selection
Direction register
Data bus
Port latch
Pull-up selection
Direction register
Data bus
Input respective peripheral functions
P7
0,
P7
2
P7
4,
P7
6,
P8
0
“1”
Output
P2
0
to P2
7
Port latch
Pull-up selection
Direction register
Data bus
Drive capacity control register
Drive capacity control register
Port latch
Pull-up selection
Direction register
Data bus
Input respective peripheral functions
P0
0
to P0
7
,
P1
0
to P1
7
,
P6
2
, P6
6
, P7
1
,
P7
3
, P75, P7
7
,
P8
1
, P8
2
,
P8
4
, P8
7
Programmable I/O Ports
M30240 Group
Rev. H Sep 18, 2003 Page 112 of 139
Figure 1.107: Programmable I/O ports (2)
Pull-up selection
Direction register
Port latch
Data bus
P37, P63, P67, P8
6
“1”
Output
NMI interrupt input
Data bus
P85
Pull-up selection
Direction register
Port latch
Data bus
Input to respective peripheral functions
P607, P61, P64, P6
5
“1”
Output
Pull-up selection
Direction register
Port latch
ATTACH
Data bus
P83
“1”
Output
Pull-up selection
Direction register
Port latch
Data bus
Analog input
P8
3
Second
EXTCAP
P100 to P107
Programmable I/O Ports
M30240 Group
Rev. H Sep 18, 2003 Page 113 of 139
Figure 1.108: Programmable I/O Ports (3)
Figure 1.109: Direction register
BYTE Input
CNVss Input
RESET Input
BYTE
CNVss
RESET
(Note 1)
(Note 1)
(Note 1)
(Note 2)
(Note 2)
(Note 2)
Note 1: symbolizes parasitic diode.
Note 2: A parasititc diode on the Vcc side is added to the mask ROM version.
Do not apply a voltage higher than Vcc to each pin.
Port Pi direction register
Symbol
Address
PDi (i = 0 to 3,6,7,10)
03E2
16
, 03E3
16
, 03E6
16
, 03E7
16
,
03EE
16,
03EF
16
, 03F6
16
Bit name FunctionBit symbol WR
b7 b6 b5 b4 b3 b2 b1 b0
PDi_0 Port Pi
0
direction register
PDi_1 Port Pi
1
direction register
PDi_2 Port Pi
2
direction register
PDi_3 Port Pi
3
direction register
PDi_4 Port Pi
4
direction register
PDi_5 Port Pi
5
direction register
PDi_6 Port Pi
6
direction register
PDi_7 Port Pi
7
direction register
0 : Input mode
(Functions as an input port)
1 : Output mode
(Functions as an output port)
(i = 0 to 3,6,7,10)
Port P8 direction register
Symbol
Address
When reset
PD8
03F2
16
00X00000
2
Bit name FunctionBit symbol WR
b7 b6 b5 b4 b3 b2 b1 b0
PD8_0 Port P8
0
direction register
PD8_1 Port P8
1
direction register
PD8_2 Port P8
2
direction register
PD8_3 Port P8
3
direction register
PD8_4 Port P8
4
direction register
Nothing is assigned.
This bit can either be set nor reset. When read, its content is indeterminate.
PD8_6 Port P8
6
direction register
PD8_7 Port P8
7
direction register
0 : Input mode
(Functions as an input port)
1 : Output mode
(Functions as an output port)
0 : Input mode
(Functions as an input port)
1 : Output mode
(Functions as an output port)
When reset
0016
Programmable I/O Ports
M30240 Group
Rev. H Sep 18, 2003 Page 114 of 139
Figure 1.110: Port register
Figure 1.111: Pull-up control register
Port Pi register
Symbol Address When reset
Pi (i = 0 to 3,6,7,10) 03E016, 03E116, 03E416, 03E516 Indeterminate
03EC16, 03ED16, 03F416 Indeterminate
Bit name FunctionBit symbol WR
b7 b6 b5 b4 b3 b2 b1 b0
Pi_0 Port Pi
0
register
Pi_1 Port Pi
1
register
Pi_2 Port Pi
2
register
Pi_3 Port Pi
3
register
Pi_4 Port Pi
4
register
Pi_5 Port Pi
5
register
Pi_6 Port Pi
6
register
Pi_7 Port Pi
7
register
Data is input and output to and from
each pin by reading and writing to
and from each corresponding bit
0 : “L” level data
1 : “H” level data
(i = 0 to 3,6,7,10)
Port P8 register
Symbol Address When reset
P8 03F016 Indeterminate
Bit name FunctionBit symbol WR
b7 b6 b5 b4 b3 b2 b1 b0
P8_0 Port P8
0
register
P8_1 Port P8
1
register
P8_2 Port P8
2
register
P8_3 Port P8
3
register
P8_4 Port P8
4
register
P8_5 Port P8
5
register
P8_6 Port P8
6
register
P8_7 Port P8
7
register
Data is input and output to and from
each pin by reading and writing to
and from each corresponding bit
(except for P8
5
)
0 : “L” level data
1 : “H” level data
Pull-up control register 0
Symbol
Address
When reset
PUR0
03FC16
0016
Bit name FunctionBit symbol WR
b7 b6 b5 b4 b3 b2 b1 b0
PU00 P0
0
to P0
3
pull-up
PU01
PU02
PU03
PU04
PU05
PU06
PU07
The corresponding port is pulled high
with a pull-up resistor
0 : Not pulled high
Pulled high
1 :
Pull-up control register 1
Symbol
Address
When reset
PUR1 03FD
16
Bit name FunctionBit symbol WR
b7 b6 b5 b4 b3 b2 b1 b0
PU10
PU11
PU12
PU13
PU14
PU15
PU16
PU17
P0
4
to P0
7
pull-up
P1
0
to P1
3
pull-up
P1
4
to P1
7
pull-up
P2
0
to P2
3
pull-up
P2
4
to P2
7
pull-up
P3
0
to P3
3
pull-up
P3
4
to P3
7
pull-up
0016
P6
4
to P6
7
pull-up
P6
0
to P6
3
pull-up
P7
0
to P7
3
pull-up
P8
0
to P8
3
pull-up
P10
0
to P10
3
pull-up
P7
4
to P7
7
pull-up
P8
4
, P8
6
, P8
7
pull-up
P10
4
to P10
7
pull-up
The corresponding port is pulled high
with a pull-up resistor
0 : Not pulled high
Pulled high
1 :
Programmable I/O Ports
M30240 Group
Rev. H Sep 18, 2003 Page 115 of 139
Figure 1.112: Port 2 and Timer A Output drive capacity registers
Port 2 Drive Capacity register
Symbol
Address When reset
P2DR 03FA 16 0016
Bit name Function Bit symbol WR
b7 b6 b5 b4 b3 b2 b1 b0
P2DR0 P2
0
LED drive capacity
P2DR1 P2
1
LED drive capacity
P2DR2 P2
2
LED drive capacity
P2DR3 P2
3
LED drive capacity
P2DR4 P2
4
LED drive capacity
P2DR5 P2
5
LED drive capacity
P2DR6 P2
6
LED drive capacity
P2DR7 P2
7
LED drive capacity
The N-channel high-drive capacity
is activated for the corresponding
bit.
0 : Normal drive
1 : N-channel high drive
Timer A Output Drive Capacity register
Symbol
Address When reset
TADR 03FB16 0016
Bit name Function Bit symbol WR
b7 b6 b5 b4 b3 b2 b1 b0
TADR0 TA 0 OUT drive capacity
TADR1 TA1OUT drive capacity
TADR2 TA2OUT drive capacity
TADR3 TA3OUT drive capacity
TADR4 TA4OUT drive capacity
High-drive capacity is activated for
the corresponding TAiOUT pin.
0 : Normal drive
1 : High drive
Nothing is assigned. These bits can neither be set nor reset.
When read, their contents are "0".
Programmable I/O Ports
M30240 Group
Rev. H Sep 18, 2003 Page 116 of 139
Figure 1.113: Example connection unused pins
Table 1.36: Example connection of unused pins in single-chip mode
Pin name Connection
Ports P0 to P3, P6 to P8, P10
(exc luding P 83, P85, P86)After setting for input mode, connect every pin to Vss or Vcc via a resistor; or
after setting for output mode, leave these pins open
XOUT Open (When using external clock)
NMI Connect via resistor to Vcc (pull-up)
AVcc Connect to Vcc
Avss, Vref, BYTE Connect to Vss
USB D+, USB D- Open
EXTCAP Connect to Vcc (when DC-DC converter is disabled)
P86/SOF After setting for output mode in normal operation, leave this pin open
P83/ATTACH After setting for output mode in normal operation, leave this pin open
Port P0 to P3, P6-P8, P10
(except P83, P85, P86)
(Input mode)
·
·
·
(Input mode)
(Output mode)
USB D+
USB D-
Microcomputer
AV CC
EXTCAP (Note 1)
VCC
XOUT
P86/SOF
P83/ATTACH
Open
BYTE
AV SS
VREF
VSS
Open
NMI
·
·
·
Open
Open
Open
Open
Note: This is an example when the DC-DC converter is disabled
Precautions
M30240 Group
Rev. H Sep 18, 2003 Page 117 of 139
1.3 Usage Precautions
1.3.1 Precautions
1.3.1.1 A-D Converter
Connect a capacitor between: the VREF pin and the AVss pin; AVcc pin and AVss pin; and each analog
input pin and AVss pin.
• Wr ite to eac h b it (exc ep t bi t 6) of A-D co ntr ol r egi st er 0, to eac h bi t o f A- D co ntrol r egi ste r 1, a nd to
bit 0 of A-D control register 2 when A-D conversion is stopped (before a trigger occurs). In particular,
when the VREF connection bit is changed from “0” to “1”, start A-D conversion after a lapse of 1µs or
longer.
• When changing A-D operation mode, select analog input pin again.
• Using one-shot mode or single sweep mode
Read the correspond ing A-D register after con firming the A-D convers ion is finished. (It is known b y A-D con-
version interrupt request bit.)
• Using repeat mode, repeat sweep mode 0 or repeat sweep mode 1
Use the undivided main clock as the internal CPU clock.
1.3.1.2 Built-in PROM version
• All built-in PROM versions
High vo ltage is required to program to the buil t-in PROM . Be careful not to appl y exce ssive vo ltage. Be espe-
cially careful during power-on.
• One Time PROM version
One Ti me PR OM ve rsions shi pped in bl ank, o f whic h bui lt-in PR OMs are pro gramm ed by use rs, are also pr o-
vided. For these microcomputers, a programming test and screening are not performed in the assembly pro-
cess and the following processes. To improve their reliability after programming, we recommend to program
and test as flow shown in Figure 1.114 before use.
Wiring for t he Vpp pin of the On e-Time PROM version should be as follows (Vpp pi n is also used as the CNVss
pin):
• Make the length of wiring between the Vpp pin and Vss pin or Vcc pin the shortest possible.
• When the w iring le ngth has to be long er, conn ect an app roxim ately 5 K ohm resi stor in se ries from the Vpp
pin to the Vss pin or Vcc pin with the shortest possible wiring. This is because the Vpp pin is the power
source input pin for the bu ilt-in PROM . When pro gramming in the built -in PROM , the impeda nce of th e Vpp
pin is low to al low the electric cu rrent for wiring flow into the PROM. Because of thi s, noise can enter easily .
If noise en ters the Vpp pin, abno rmal in struc tion c odes o r data a re read f rom the bui lt-in PRO M whic h may
cause a program runaway.
Figure 1.114: Programming and test flow for One-time PROM (OTP) version
Programming with PROM programmer
Screening (Note)
(Leave at 150 C for 40 hours)
Verify test PROM programmer
Function check in target device
Note: Never expose to 150 C exceeding 100 hours.
Precautions
M30240 Group
Rev. H Sep 18, 2003 Page 118 of 139
1.3.1.3 Dedicated Input Pins
If a dedicated input pin is connected to a power supply different from the supply that Vcc is connected
to, a resistor (approximately 1k ohm) should be added between the input pin and the connected power
supply. However, if the dedicated input pin voltage is higher than Vcc, latch up could occur.
A resistor is not required when using a Vcc voltage equal or greater than the voltage of the dedicated
input pin.
1.3.1.4 DMAC
DMA enable bit
The DMA enable bit is assigned to bit 3 of the DMA0 and DMA1 control registers. DMA becomes ac-
tive when the DMA enable bit is set to “1”. Immediately after the DMA becomes active, the data trans-
fers start and perform the following operations:
• Reloads the value of the source pointer or destination pointer depending on which is specified for the
forward direc ti on address point er
• Reloads the value of the transfer counter reload register to the transfer counter.
Thus o verwri ting “1” to the DM A enable bit with t he DMAC being i nactive carri es out the oper ations
given ab ov e, s o th e DMA C op erates agai n from the i ni tia l s tate at th e i nst ant “1 ” is o ve rw ritten to th e
DMA enable bit.
DMA request bit
The DMA request bit turns to “1” if the DMA tr ansfer re que st sign al occur s rega rd less of the DMA C’s
state (regardless of weather the DMA enable bit is set to “1” or to “0”). It turns immediately before data
tran sfe r starts.
In addition, it can be set to “0” by the use of a program, but cannot be set to “1”.
There can be instances in which a change in DMA request factor selection bit causes the DMA request
bit to turn to “1”. So be sure to set the DMA request bit to “0” after the DMA request factor selection bit
is changed.
The DMA request bit turns to “1” if a DMA transfer request signal occurs, and turns to “0” immediately
before data transfer starts. If the DMAC is active, data transfer starts immediately, so the value of the
DMA req ues t b it, if read by u se of a pr og ram, tu rn s to b e “ 0” in mo st ca se s. T o examine whe ther th e
DMAC is active, read the DMA enable bit.
To best judge the state of the DMAC, the DMA enable bit should be read instead of the DMA request
bit.
1.3.1.5 Frequency Synthesizer
• Refer to Section 1.5.1.2 for setup procedures required after a hardware reset.
• Set the value of the Frequency Synthesizer Prescaler register (FSP) so that fPIN is 1 MHZ or higher.
1.3.1.6 Interrupt
Reading address 0000016
• When a maskable i nterrupts o ccurs, th e CPU reads the interru pt informatio n (the in terrupt num ber
and interrupt request level) in the interrupt sequence.
• The interrupt request bit of the corresponding interrupt written in address 0000016 is then set to “0”.
• Do not read address 0000016 by software.
• Reading address 0000016 by software sets the highest priority enabled interrupt source request bit to “0”
Therefore the interrupt routine may not be executed even though the interrupt is generated.
Setting the stack pointer
Precautions
M30240 Group
Rev. H Sep 18, 2003 Page 119 of 139
• The value of the stack pointer is initialized to 0000016 immediately after reset. Accepting an interrupt
before setting a value in the stack pointer may cause program runaway. Be sure to set a value in the
stack pointer before accepting an interrupt.
• When using the NMI interrupt, initialize the stack pointer at the beginning of a program. Concerning
the fir st inst ruction i mmediatel y after reset, generating any i nterrupt s includi ng the NMI inter rupt is
prohibited.
Settin g interrupts
• Chang ing the Interr upt Priority Le vel select bi t (ILVL) and cl earing the In terrupt Request bi t (IR) in
the Interrupt Control Registers (ICR) while the Interrupt enable flag (I-FLAG) is “1”, may result in un-
intended op erations, such as BRK and other int errupts being generated. Disable the interrupts by
clearing the I-FLAG before setting ILVL or clearing the IR bit.
• To prevent the I-FLAG from being set before the ICR is rewritten due to the effects of the instruction
queue, instructions that equal a minimum of 2 cycles should be inserted between writing to the ICR
and setting the I-FLAG (2-NOPs, I MOV, I POP, etc.)
Modifying interrupt control registers
• Do not modify any interrupt control register when an interrupt request can be generated.
• If an interrupt request occurs, modify the interrupt control register after the interrupt is disabled.
External interrupts
• When th e pola rity of the INT 0 and INT1 pins is ch anged, the int erru pt reques t bit can be set to “ 1”.
After changing the polarity, the interrupt request bit should be cleared to “0.”
The NMI interrupt
• As for the NMI interrupt pin, an interrupt cannot be prohibited. Connect it to the Vcc pin if unused.
• Do not get into stop mode or wait mode with the NMI pin set to “L”.
1.3.1.7 Noise
To reduce the possibility of noise problems:
• Connect a bypass capacitor (approximately 0.1 µF) across the Vss pin and the Vcc pin with the shortest
possible wiring
• Use circuit traces with a larger diameter than other signal traces for Vss and Vcc.
Vpp connection of One-time PROM version
• The Vpp (power inp ut for PRO M program m ing ) connec tio n for the internal PROM is conne cte d to the CN-
Vss pin on the One-time PROM versio n. Therefor e, CNVss should be a short circuit trac e to improve nois e
resistance. If the CNVss trace is long, insert a 5kΩ resistor close to the CNVss pin and connect it to Vss.
• Note: Inserting a 5kΩ resistor will not cause any problem when switching to a mask ROM version.
1.3.1.8 Software reset
Software reset with fSYN is selected as a clock source. If the Frequency Synthesizer related registers
are written to while fSYN is selected as the clock source, the MCU will runaway. To avoid this:
1. Select f(XIN) as the clock source before the software reset
2. Perform software reset
3. Confirm software reset using Frequency Synthesizer Enable bit
4. Reselect fSYN a s cl oc k sou rc e.
Precautions
M30240 Group
Rev. H Sep 18, 2003 Page 120 of 139
1.3.1.9 Stop Mode and Wait Mode
When returning from stop mode by hardware reset, RESET pin must be set to “L” level until main clock
oscillation is stabilized.
When ente ring either wait or stop m ode, you mu st first ena ble any in terrupts y ou want to ca ncel the
wait or sto p. Also, mak e sure to di sable any interru pts that y ou don’t want to cancel the wait or sto p.
If only har dware reset or NMI interrupts ar e desired to can cel wait or stop, al l other interr upt priority
levels should be set to “0”
If using fSYN as the internal clock, switch it to f(XIN) before entering stop mode.
When switching to either wait or stop mode, the WAIT instruction or the instruction that sets the all
clock stop bit to “1” are prefetched within the instruction queue before the program stops. Put at least
four NO Ps in su cc ess ion afte r the W A IT ins tr uc ti on o r a fter th e i nstructi on that se ts the all cl ock sto p
control bit to “1.”
1.3.1.10 Timer A (Timer mode)
Reading the Timer Ai register while a count is in progress allows reading, with arbitrary timing, the val-
ue of the counter. Reading the Timer Ai register with the reload timing gets “FFFF16”. Reading the Tim-
er Ai re gister after setting a v alue in the T imer Ai re gister with a count ha lted but be fore the cou nter
starts counting gets a proper value.
1.3.1.11 Timer A (Event counter mode)
1. Reading the Timer Ai register while a count is in progress allows reading, with arbitrary timing, the
value of the counter. Reading the Timer Ai register with the re load timing gets “FFFF16” by underflow
or “000016” by overflow. Reading the Timer Ai register after setting a value in the Timer Ai register with
a count halted but before the counter starts counting gets a proper value.
2. When counting has stopped in free-run type, set the timer again.
3. When using Free-run type, the timer’s register contents may be undefined when counting starts. Set
the timer value immediately after counting has started.
• When the up/down count is not switched:
•Enable the reload function and set a value to the timer register before counting starts.
•Rewri te the va lue to the timer reg ister imm ediately a fter counti ng has s tarted. (This is the same o peration
as free-run type.)
•If counti ng up, rewr it e 000016.
•If counti ng down , rewri te FFFF16.
• When the up/down count is switched:
•Use the reload type until the first count pulse is input.
•Switch to free-run type afterwards.
1.3.1.12 Timer A (One-shot Timer mode)
1. Setting the count start flag to “0” while the count is in progress causes:
• The counter to stop counting
• The contents of the reload register are reloaded
• The TAiOUT pin outputs “L” level
• The interrupt request is generated
2. Timer Ai interrupt request bit goes to “1” if the operation mode is set by:
• Selecting one-shot timer mode after reset
• Changing operation mode from timer mode to one-shot timer mode
• Changing operation mode from event counter mode to one-shot timer mode
Note: To use Timer Ai interrupt reque st bit, clea r the Timer Ai i nterrupt reques t bit to “0” after th ese
changes have been made.
Precautions
M30240 Group
Rev. H Sep 18, 2003 Page 121 of 139
1.3.1.13 Timer A (Pulse-width Modulation mode)
1. The Timer Ai interrupt request bit becomes “1” if setting operation mode of the timer in compliance
with any of the following procedures:
• Selecting PWM mode after reset.
• Changing operation mode from timer mode to PWM mode.
• Changing operation mode from event counter mode to PWM mode.
Therefore, to use Timer Ai interrupt (interrupt request bit), set Timer Ai interrupt request bit to “0” after
the above listed changes have been made.
2. Setting the count start flag to “0” while PWM pulses are being output causes the counter to stop
countin g. If th e TAi OUT pin i s outpu tting an “H” le ve l in thi s ins tanc e, th e ou tput lev el goes to “L” , an d
the Timer Ai interrupt request bit goes to “1”. If the TAiOUT pin is outputting an “L” level in this instance,
the level does not change, and the Timer Ai interrupt request bit does not become “1”.
1.3.1.14 Timer B (Timer mode)
Reading the Timer Bi register while a count is in progress allows reading, with arbitrary timing, the val-
ue of the counter. Reading the Timer Bi register with the reload timing gets “FFFF16”. Reading the Tim-
er Bi re gister after setting a v alue in the T imer Bi re gister with a count ha lted but be fore the cou nter
starts counting gets a proper value.
1.3.1.15 UART2
When us ing UA RT2 in c lock as ynchr onous serial I/O mo de (UAR T), use t he inte rnal clock o nly, oth-
erwise, one of the following may occur:
• The interrupt may not be issued at the end of the data transmission when the hardware transfers the
data from the transmit buffer to the transmit register.
• Data may be corrupted when the hardware transfers data fro the transmit buffer register to the trans-
mit register. This only applies to UART2 asynchronous serial I/O mode and does not apply to UART0
or UART1.
1.3.1.16 USB
• When the USB Reset Interrupt Status flag is set to “1”, the contents in the USB internal register (ad-
dresses 030016-033516) will return to their reset values. However, the following registers are not af-
fected by a USB Reset:
• USB Control register (USBC)
• Frequency Synthesizer Control register (FSC)
• USB Endpoint x FIFO (addresses 033816 -033C16)
• All LPF pin passive components must be located as close as possible to the LPF pin.
• An insul ation conn ector (Ferrit e beads) must be connected between the AVss and digi tal Vss pi ns,
and between AVcc and digital Vcc pins.
• When using DC-DC converter to supply 3.3V to the drive, connect a capacitor between the EXTCAP
pin and the Vss pin. The connection should consist of a 2.2µF capacitor (tantalum capacitor) and a
0.1µF capacitor (ceramic capacitor) connected in parallel. Use a ceramic capacitor equivalent to the
X7R type as a 0.1 µF capacitor.
• Connect a 27-33Ω resistor between the USB D+ and USB D- pins to meet USB specification imped-
ance require men ts .
• Connect a ce ra mi c ca paci tor (33pF recommende d) after the r es istor bet ween USB D+ and USB D-
or between USB D+/D- pins an d the Vss pin to control the slew rate and rise/fall timing. This cap
should be placed after the 27-33Ω resistor. See section 1.5 for more details.
• Connect a 1.5kΩ resistor between the EXTCAP pin and the USB D+ pin during normal operation.
• Connect a 1.5kΩ resistor between the P83/ATTACH pin and the USB D+ pin and leave the EXTCAP
open when using Attach/Detach function.
• Read or write to the USB internal registers (address 030016-033C16) by 8-bit mode only. Accessing
by 16-bit mode will cause incorrect read/write values.
Precautions
M30240 Group
Rev. H Sep 18, 2003 Page 122 of 139
• When using an isochronous transfer, set the FLUSH bit by:
• OUT FIFO data flush: When OUT_PKT_RDY flag is “1”, set the FLUSH bit to “1”
• IN FIFO data flush: Use AUTO_FLUSH bit.
• Do not write to the USB internal registers (address 030016-033C16) when the USB clock is disabled
in Suspend mode.
• Precautions for accessing the USB Interrupt Status registers 1 & 2 (USBIS1, USBIS2)
• When reading from/writing to both registers, access USBIS1 first and then USBIS2.
• When writing to these registers, use transfer instructions such as the MOV instruction. Do not use Read
Modify Write instructions such as OR or BSET because this could cause improper values to be written
back.
• Each status flag can be cleared to”0” by writing back the same value “1” which was read from the USB
Interrupt Status register. Make sure to clear only the corresponding status flag in each USB interrupt rou-
tine. Mask the other status flags so that they are not accidentally cleared.
• Example of USB Functi on Interrupt
• Do not use Read, Modify, Write instructions on the following USB Control and Status registers:
• USB Endpoint 0 Control and Status (EP0CS)
• USB Endpoint x IN Control and Status (EPxICS)
• USB Endpoint x OUT Control and Status (EPxOCS)
• Refer to Section 1.5.5.1 for more information on these registers and how to modify their contents.
C Language
ram1=USBIS1; /*Read from USB Interrupt Status register 1*/
ram2=USBIS2; /*Read from USB Interrupt Status register 2*/
ram2 &=0x1F; /*Mask flags except USB Function Interrupt status flags*/
USBIS1=ram1; /*Write to USB Interrupt Status register 1*/
USBIS2=ram2; /*Write to USB Interrupt Status register 2*/
Assembly Language:
mov.b USBIS1, ram1 ;Read from USB Interrupt Status register 1
mov.b USBIS2, ram2 ;Read from USB Interrupt Status register 2
and.b #1Fh, ram2 ;Mask flags except USB Function Interrupt status flags
mov.b ram1, USBIS1 ;Write to USB Interrupt Status register 1
mov.b ram2, USBIS2 ;Write to USB Interrupt Status register 2
Precautions
M30240 Group
Rev. H Sep 18, 2003 Page 123 of 139
Items to be submitted when ordering masked ROM version
Please submit the following when ordering masked ROM products:
(1) Mask ROM confirmation form
(2) Mark specification sheet
(3) ROM data: EPROMs or floppy disks
*: In the case of EPROMs, there are sets of EPROMs are required per pattern.
*: In the case if floppy disks, 3.5-inch double-sided high-density disk (IBM format) is required per pat-
tern.
Electrical characteristics
M30240 Group
Rev. H Sep 18, 2003 Page 124 of 139
1.4 Specificati ons
1.4.1 Electrical chara cter i stic s
Note 1: When writing to EPROM, CNVss rated value is -0.3 to 13 volts
Table 1.37: Absolute maximum ratings only, not operating conditions
Symbol Paramet er Condition Rated Value Unit
Vcc Supply voltage Vcc=AVcc -0.3 to 6.5 V
AVcc Analog supply voltage VCC=AVCC -0.3 to 6.5 V
VIInput voltage
Port0, Port1, Port2, Port3,
Port6,
Port7, Port8, Port10,
RESET, VREF, XIN
-0.3 to Vcc+0.3 V
VIInput voltage CNVss -0.3 to 6.5 (Note 1) V
VOOutput voltage
Port0, Port1, Port2, Port3,
Port6,
Port7, Port8 (ex cep t P85 ),
Port10, RESET, VREF,
XOUT
-0.3 to Vcc+0.3 V
PdPow er dissipation Ta=25 °C760 mW
Topr Ope rating ambient temperature 0 to 70 °C
Tstg Storage temperature -65 to 150 °C
Electrical characteristics
M30240 Group
Rev. H Sep 18, 2003 Page 125 of 139
Table 1.38: Recommended operating condition s (Vcc=4.1~5.25V, Vss=0V, Ta= 0°C∼ 70°C, f(Xin) = 12MHz)
Note: The tot al outpu t current i s the sum of all t he cu rrents flowing th rough all the appl icable ports. The tot al avera ge curre nt
is an average value measured over 100 ms. The total peak current is the peak value of all the currents.
Symbol Parameter Standard Unit
Min Typ Max
Vcc Supply voltage 4.1 5.0 5.25 V
AVcc Analog supply voltage Vcc V
Vss Supply voltage 0 V
Avss Analog supply voltage 0 V
VIH High input voltage Port0, Port1, Port2, Port3, Port6, Port7,
Port8,Port10,RESET,VREF,XIN,CNVSS 0.8Vcc Vcc V
VIL Low input voltage Port0, Port1, Port2, Port3, Port6, Port7,
Port8,Port10,RESET,VREF,XIN,CNVSS 00.2Vcc V
Ioh (peak) High peak out put c urrent Port0, Port1, Port3, Port6, P71, P73,
P75, P77, P81 to P87, Port10 -10 mA
P20 to P27, P70, P72, P74, P76, P80 -20 mA
Ioh (avg.) High avg output current Port0, Port1, Port3, Port6, P71, P73,
P75, P77, P81 to P87, Port10 -5 mA
P20 to P27, P70, P72, P74, P76, P80 -10 mA
ΣIoh(pe ak) High peak out put current P2, P3, P6, P7, P80~P82-80 mA
P0, P1, P83~P87, P10 -80 mA
ΣIoh (avg.) High avg output current P2, P3, P6, P7, P80~P82-40 mA
P0, P1, P83~P87, P10 -40 mA
Iol (peak) Low peak output current Port0, Port1, Port3, Port6, P71, P73,
P75, P77, P81 to P87, Port10 10 mA
P20 to P27, P70, P72, P74, P76, P80 20 mA
Iol (avg.) Low avg output current Port0, Port1, Port3, Port6, P71, P73,
P75, P77, P81 to P87, Port10 5mA
P20 to P27, P70, P72, P74, P76, P80 10 mA
ΣIol (peak) Low peak output current P2, P3, P6, P7, P80~P8280 mA
P0, P1, P83~P87, P10 80 mA
ΣIol (avg. Low avg output current P2, P3, P6, P7, P80~P8240 mA
P0, P1, P83~P87, P10 40 mA
f(XIN)Main clock input oscillation frequency 1 12 MHz
Electrical characteristics
M30240 Group
Rev. H Sep 18, 2003 Page 126 of 139
Table 1.39: Electrical Characteristics (Vcc=4.1~5.25V, Vss=0V, Ta= 0°C∼ 70°C, f(Xin) = 12MHz)
Note 1: Only high drive when Timer A is enab led and drive registers set for high drive mode.
Symbol P arameter Measuring cond ition Standard Unit
Min Typ Max
VOH High output volta ge Port0, Port1, Po rt2, Port 3, Port6,
Port71, P73,P75,P77,Port8
(except P85), Port10 IOH = -5mA, Vcc=5V 3.0 V
VOH High output vol tage Port 70, P7 2,P 7 4,P76 ,P 80 IOH = -10mA, Vcc=5V 3.0 V
VOH High output vol tage Port0, Port1, Po rt2, Port 3, Port6,
Port71, P73,P75,P77,Port8
(except P85), Port10 IOH = -200µA, Vcc=5V 4.7 V
VOH High output vol tage Xout high power I OH = -1mA, Vcc=5V 3.0 V
low power IOH = -0.5mA, Vcc=5V 3.0 V
VOL Low output voltage Port0, Po rt1, Port2 , Port3, Port6,
Port71, P73,P75,P77,Port8
(except P85), Port10 IOL = 5mA, Vcc=5V 2.0 V
VOL Low output voltage High-drive mode Port 2 IOL = 10mA, Vcc=5V 2.0 V
VOL Low output voltage Port 70,P72,P74,P76,P80
NOTE 1 IOL= 10mA, Vcc=5V 2.0 V
VOL Low output voltage Port0, Po rt1, Port2 , Port3, Port6,
Port71, P73,P75,P77,Port8
(except P85), Port10 IOL = 200µA, Vcc=5V 0.45 V
VOL Low output voltage Xout high pow er I OH = 1mA, Vcc=5V 2.0 V
low power IOH = 0. 5mA, Vcc=5V 2.0 V
VT+-VT- Hysteresis TA0in to TA4in, INT0 to INT1,
ADTRG, CTS0, CTS1, CLK0, CLK1,
TA2out to TA4out, NMI, KI0 to KI15 Vcc=5V 0.2 0.8 V
VT+-VT- Hysteresis RESET Vcc=5V 0.2 1.8 V
Iih High input current Port0, Por t1, Port2, Port3, Por t6,
Port7,Port8, Port10, RESET,
CNVss VI = 5V, Vcc=5V 5.0 µA
Iil Low inpu t curre nt Port0, Po rt1, Port2 , Port3, Port6,
Port7, Po rt 8, Port10, RESET,
CNVss VI = 0V -5.0 µA
RPULLUP Pull-up resistance Port0, Po rt1, Port2 , Port3, Port6,
Port7, Po rt 8, Port10 VI = 0V, Vcc=5V 30 50 167 kΩ
RXIN Feedback resistan ce, Xin 1.0 MΩ
VRAM RAM retention voltage When clock is stopped 2.0 V
Icc Power supply current Output pins
open, other
pins tied to Vss
Icc run with USB
ON (Mask) 80 mA
Icc run with USB
ON (OTP) 95 mA
Icc run with
USB OFF 50 mA
Ta=25°C
clock stopped 1µA
Ta=70°C
clock stopped 20 µA
Ta=25°C
wait mode
with internal
clocks ON
8mA
Ta=25°C
wait mode
with internal
clocks OFF
4mA
Electrical characteristics
M30240 Group
Rev. H Sep 18, 2003 Page 127 of 139
Table 1.40: USB Electrical Characteristics (Vcc=4.1~5.25V, Vss=0V, Ta= 0°C∼ 70°C, f(Xin) = 12MHz)
Note: See Fig. 1.120 for recommended configuration.
Symbol Parameter Measuring Condition Standard Unit
Min Typ Max
VOH D+, D- I=18.3 mA, RX=33 Ω, VXcap =3.0 V 2.2 V
VOL D+, D- I=18.3 mA, RX=33 Ω, VXcap =3.0 V 0.8 V
Isusp Suspend
current USB suspend mode, internal clock
stopped 175 µA
Xcap DC-DC
converter
voltage
DC-DC converter output voltage on
Xcap pin 3.0 3.3 3.6 V
Table 1.41: A-D conversion characteristics (Vcc, Avcc = 4.1~5.25V, V ss=0V, Ta= 0°C~ 70°C, f(Xin) = 12MHz)
Symbol Parameter Measuring
condition Standard Unit
Min Typ Max
- Resolution VREF = Vcc 10 Bits
-Absolute
accuracy
Sample and hold function not available VREF = Vcc = 5V ±3 LSB
Sample and hold function available (10bit) VREF = Vcc = 5V ±3 LSB
Sample and hold function available (8bit) VREF = Vcc = 5V ±2 LSB
RLADDER Ladder resistance VREF = Vcc = 5V 10 40 kΩ
tCONV Conversion time (10bit) 2.75 µs
tCONV Conversion time (8bit) 2.34 µs
tSAMP Sampling time 0.25 µs
VREF Reference voltage 2 V
VIA Analog input voltage (min. operating frequency =x) 0 VREF V
φAD A-D clock frequency 1 12 MHz
Timing
M30240 Group
Rev. H Sep 18, 2003 Page 128 of 139
1.4.2 Timing
Timing requirements referenced to Vcc = 4.1~5.25V , Vss=0V , Ta= 0°C~70°C unless otherwise specified.
Table 1.42: External clock input
Symbol Parameter Standard Unit
Min Max
tc External clock input cycle time 83.3 ns
tw(H) External clock input HIGH pulse width 33 ns
tw(L) External clock input LOW pulse width 33 ns
tr External clock rise time 15 ns
tf External clock fall time 15 ns
Table 1.43: Timer A input (c ounter input in event counter mode)
Symbol Parameter Standard Unit
Min Max
tc(TA)TAiIN input cycle time 100 ns
tw(TAH)TAiIN input HIGH pulse width 40 ns
tw(TAL)TAiIN input LOW pulse width 40 ns
Table 1.44: Timer A input (gating input in timer mode)
Symbol Parameter Standard Unit
Min Max
tc(TA)TAiIN input cycle time 400 ns
tw(TAH)TAiIN input HIGH pulse width 200 ns
tw(TAL)TAiIN input LOW pulse width 200 ns
Table 1.45: Timer A input (external trigger input in one-shot timer mode)
Symbol Parameter Standard Unit
Min Max
tc(TA)TAiIN input cycle time 200 ns
tw(TAH)TAiIN input HIGH pulse width 100 ns
tw(TAL)TAiIN input LOW pulse width 100 ns
Table 1.46: Timer A input (external trigger input in pulse width modulation mode)
Symbol Parameter Standard Unit
Min Max
tw(TAH)TAiIN input HIGH pulse width 100 ns
tw(TAL)TAiIN input LOW pulse width 100 ns
Timing
M30240 Group
Rev. H Sep 18, 2003 Page 129 of 139
Table 1.50: External interrupt INTi inputs
Table 1.47: Ti mer A input (up/down input in event counter mode)
Symbol Parameter Standard Unit
Min Max
tc(UP)TAiOUT input cycle time 2000 ns
tw(UPH)TAiOUT input HIGH pulse width 1000 ns
tw(UPL)TAiOUT input LOW pulse width 1000 ns
tsu(UP-TIN)TAiOUT input setup tim e 400 ns
th(TIN-UP)TAiOUT input hold time 400 ns
Table 1.48: A-D trigger input
Symbol Parameter Standard Unit
Min Max
tc(AD) ADTRG input cycle time (triggerable min imum) 1000 ns
tw(ADL) ADTRG input LOW pulse width 125 ns
Table 1.49: Serial I/O
Symbol Parameter Standard Unit
Min Max
tc(CK) CLKi input cycle time 200 ns
tw(CKH) CLKi input HIGH pulse width 100 ns
tw(CKL) CLKi input LOW pulse width 100 ns
td(C-Q) TxDi output delay time 80 ns
th(C-Q) TxDi hold time 0 ns
tsu(D-C) RxDi input se tup tim e 30 ns
th(C-D) RxDi input hold time 90 ns
Symbol Parameter Standard Unit
Min Max
tw(INH)INTi input HIGH pulse width 250 ns
tw(INL)INTi input LOW pulse width 250 ns
Timing Diagram
M30240 Group
Rev. H Sep 18, 2003 Page 130 of 139
1.4.3 Timing Diagram
Figure 1.115: Peripheral/interrupt timing diagram
TAiIN input
TAiOUT input
During event counter mode
t
c(TA)
t
w(TAH)
t
w(TAL)
t
c(UP)
t
w(UPH)
t
w(UPL)
t
h(T
IN
–UP)
t
su(UP–T
IN
)
TAi
IN
input
(When count on falling
edge is selected)
TAi
IN
input
(When count on rising
edge is selected)
TAi
OUT
input
(Up/down input)
t
su(D–C)
CLKi
TxDi
RxDi
t
c(AD)
t
w(ADL)
t
c(CK)
t
w(CKH)
t
w(CKL)
t
w(INL)
t
w(INH)
t
d(C–Q)
t
h(C–D)
t
h(C–Q)
INTi input
AD
TRG
input
Frequency Synthesizer
M30240 Group
Rev. H Sep 18, 2003 Page 131 of 139
1.5 Applications
1.5.1 Frequency Synthesizer
This section presents the recommended method of setting up and using the frequency synthesizer that
generat es the 4 8MHz c lock nee ded by the US B F CU a nd th e DC-DC c onver te r that pr ovi des pow er to
the D+/D- drivers.
1.5.1.1 Reset of USB-related registers
The special function registers (SFRs) that govern the operation of the frequency synthesizer, DC-DC
converter and USB FCU are affected by one or more reset events. The addresses of the special function
registers (SFRs) that are affected by Hardware Reset, USB Reset, or both are shown in Figure 1.116.
Figure 1.116: SFR Reset Venn Diagram
All resetable SFRs, including SFRs and other registers internal to the USB FCU, are affected by a
Hardware Reset, which occurs when the RESET pin is brought low or an undefined opcode is fetched.
See Section 2.4 for a complete listing of SFRs and their reset values.
Only registers internal to the USB FCU are reset when a USB Reset sent by the Host/Hub is detected.
These USB registers are reset to their default values except for bit 5 of USBIS2 (USB Reset Interrupt
Status Flag), which is set to a “1”. USB FCU registers are registers from address 030016to 033C16 and
all other registers within the USB FCU, man y of which the MCU doe s not hav e direct ac cess to (e.g.
FIFO address pointers). The USB FIFO registers are empty after USB reset because the FIFO ad-
dress pointers are reset. However, the physical contents of the FIFOs are not set to all ‘1‘s or all ‘0‘s.
Other SFRs such as USBC, FSC, and CM0, CM1 are not affected by a USB Reset.
Hardware Reset
USB Reset
SFR R egisters:
0004
16
to 005F
16
,
0378
16
to 03FF
16
000C (US BC),
03DC
16
(FSC)
SFR Registers:
0300
16
to 033C
16
(USB FCU registers)
Frequency Synthesizer
M30240 Group
Rev. H Sep 18, 2003 Page 132 of 139
1.5.1.2 Set up of Fre quency Synthesizer and DC-DC Converter
Figure 1.117: PLL, DC-DC Converter and USB Functional Block Diagram
A functi onal block dia gram of the USB system on the M 30240 which s hows how the co ntrol sign als
affect operation is given in Figure 1.117
1.5.1.3 Set up after Hardware Reset
A Hardware Reset occurs when either the RESET pin is brough t low fo r m ore tha n 2 µs or an inva lid
opcode is fetched by the CPU. The frequency synthesizer (PLL) and DC-DC converter should be set
up as follows in the Hardware Reset routine (see Figure 1.118),
• Power u p the M30 240 a nd o ther comp one nts on t he pe r iph eral d ev ice fo r l ess t han 1 00 m A o per a-
tion. The current limit only applies for bus powered devices.
• Configure the PLL for 48MHz f(VCO) operation.
• Enable the PLL by setting FSE (bit 0 of the Frequency Synthesizer Control Register (FSC)) to a “1”,
then wait for 2 ms.
• Check the lock status bit (LS, bit 7 of FSC).
• If the bit is a “1”, go on.
• If the bit is a “0”, wait 0.1 ms longer and then re -check the bit.
• Enable the DC-DC converter in high current mode by setting USBC4 (bit 4 of the USB Control Reg-
ister (US BC) ) to a “ 1” and ke epi ng USB C3 ( bi t 3 of US BC ) a “0” . Hi gh cur r ent mod e should alwa ys
be used du ring normal US B operatio n. Low current m ode should on ly be used dur ing a USB su s-
pend.
• Wait ( C + 1)ms (wher e C equal s the exte rnal capac itance conn ected to th e Ext Cap pin in µF) for
the voltage on Ext Cap to reach a steady state voltage of approximately 3.3V. (Since the D+ pullup
is con nected to the Ext Cap pin, the upstream h ub will dete ct that the p eripheral devi ce has bee n
plugged in once the voltage on D+ reaches approximately 2.0 V.)
•Example: A 2.2 µF cap acitor connec ted to Ext Cap require s 3.2 ms for the voltage on Ext C ap to be stable.
• Enable the USB clock by setting USBC5 (bit 5 of USBC) to a “1”. (If the USB clock and FCU are
enabled before the voltage on Ext Cap is stable, a phantom USB Reset may be detected, or the ac-
tual USB Reset may not be detected.)
• Wait at least 4 cycles of Φ, then enable the USB FCU by setting USBC7 (bit 7 of USBC) to a “1”.
• Enable other blocks as necessary.
27-33
Ω
27-33
Ω
D+
D-
USB FCU
2.2
µ
F0.1
µ
F
Ext Cap
Frequency
Synthesizer
f(Xin)
FSE LS
1.5 k
Ω
USB T ransceiver
DC-DC Converter
USBC3
USBC4
USBC7 USBC7
USBC5
USBCLK
(48MHz)
enable lock
enable
enable
(enable)
(enable)
enable current
mode
Frequency Synthesizer
M30240 Group
Rev. H Sep 18, 2003 Page 133 of 139
Figure 1.118: PLL and DC-DC Converter Set Up Timing after Hardware Reset
1.5.1.3.1 Precautions after Software Reset
A software reset occurs after writing a ‘1’ to bit ‘3’ of the processor mode register 0 (address 000416). Durin g
softwar e reset, the conten ts of the internal RAM are preserve d as well as all USB, DC- DC converter, and PLL
registers. If the PLL is used as the system clock source, it is important to note that after a software reset oc-
curs, any writes t o the freque ncy synt hesiz er regis ter will cau se it to free ze . This ca n cause errati c de vice be-
havior. In order to avoid this, it is recommended that the following procedure be used:
• Pri or to s oftware reset , sw it ch device clock so ur c e from ‘fs y n to f(Xi n)’. Plea se see the Fre que nc y Sy nth e-
sizer specification for more details.
• After s oftware reset us ing firmware, e valuate the condition of the synthesiz er control regi ster (FSC registe r,
address 03DC16, bit ‘0’). This bit is not effected by a software reset and can check to see if the PLL is still
enabled . If so, any setup routine that i nvolves writin g to the PLL registe rs should not be called. At this p oint,
the clock source can be changed back to fsyn.
1.5.1.4 Set up after USB Reset Signaling Detected
A USB Res et is dete cted b y the US B FCU when an SE0 is pres ent on D +/D- fo r at leas t 2.5 µs. De-
tection of a USB Rese t resu lts in bi t 5 of US B Inte rru pt Sta tus Register 2 (USBIS 2) bei ng set to a “1”
and the registers within the USB FCU being reset to their default values. Register USBC and the PLL
registers are not affected by a USB Reset. A USB Function Interrupt request is also generated when
the USB Reset is detected.
No modifi cations to the frequency synthesizer or DC-DC co nverter conf iguration shou ld be mad e in
the USB Function Interrupt routine. However, all USB FCU registers (addresses 30016 to 33C16) must
be reconfigured to their pre-enumeration state.
1.5.1.5 Set up after USB Suspend Detected
A USB Su spend occ urs if the US B FCU does not d etect any b us activity on D+/D- for a t least 3 ms.
Detection of a suspend results in bit 7 of USBIS2 and bit 0 of USBPM (SUSPEND) being set to a “1”.
This causes bit 3 of SUSPIC to be set to a “1”. Bit 7 of USBIS2 then needs to be cleared by writing a
“1” to the bit in order to allow a future suspend event.
The configuration of the frequency synthesizer and DC-DC converter should be changed as follows in
the USB Suspend Interrupt routine (if the device is bus powered):
RESET
FSE
LS
USBC4
USBC5
USBC7
Wait 2
m
s
Wait (C+1)
m
s
Enable PLL
Enable D C-DC converter
Enable USB Clock
Enabl e USB FCU
Wait at lea s t 4 cycles of
Φ
Frequency Synthesizer
M30240 Group
Rev. H Sep 18, 2003 Page 134 of 139
• Change the DC -DC converte r from high c urrent mod e to low curr ent mode by sett ing USBC 3 (bit 3
of the USBC) to a “1”
• Disabl e the USB clock by se tting US BC5 (b it 5 of USBC) to a “0”. Once the USB clock is dis able d,
registers internal to the USB FCU should not be written to. This includes all USB SFRs from address
030016 to 033C16. It does not include USBC or FSC.
• Perform other tasks to reduce total current to below 500µA.
• Disable the PLL by setting FSE (bit 0 of FSC) to a “0”.
• Make sure the I-FLAG is set to “1”.
• Stop the system clock by setting CM10 (bit 0 of CM1) to a “1”. Make sure to first enable writing to the
system clock control register by setting PRCO (bit 0 of PRCR) to “1’. Also, make sure to enable the
USB Resu me Interru pt (RSMIC regi ster) and c lear or execut e any pendi ng int errupts prior to s top-
ping the cloc k so the M CU can wake up onc e resu me si gnali ng is detec ted. If the c lock i s sto pped
using an interrupt routine, make sure to set the priority of the Resume Interrupt (RSMIC) higher than
the current interrupt.
• Note that no action may be necessary if the device is self powered.
1.5.1.6 Set up after USB Resume Signaling Detected
A resume occurs when the USB FCU is in the suspend state and detects a non-idle signaling on D+/
D-. Detection of a resume results in bit 6 of USBIS2 and bit 1 of USBPM (RESUME) being set to a “1”.
This causes bit 3 of RSMIC to also be set to “1”. If the MCU was in the stop state prior to the detection
of the resume, the USB Resume Interrupt request will cause the MCU to wake up from the stop state.
Bit 6 of USBIS2 needs to be cleared (by writing a “1” to the bit) in order to allow a future resume event.
See section 2.9 “Stop Mode” for details on waking up from the stop state.
The configuration of the frequency synthesizer and DC-DC converter should be changed as follows in
the USB Resume Interrupt routine (if the device is bus powered):
• Re-enable the PLL for 48MHz f(VCO) by setting FSE (bit 0 of the FSC) to a “1”, then wait for 2 ms.
• Wait for 2 ms.
• Check the lock status bit (LS, bit 7 of FSC).
• If the bit is a “1”, continue.
• If the bit is a “0”, wait 0.1 ms long er and then re-check the bit.
• Enable the USB clock by setting USBC5 (bit 5 of USBC) to a “1”.
• Wait for a minimum of 4 cycles.
• Change the DC-DC c onv erte r from l ow cur ren t m ode to hi gh c urr ent mo de by sett ing USBC 3 ( b it 3
of the USBC) to a “0”.
• Enable other blocks as necessary.
Registers internal to the USB FCU should not be written to until the USB clock is re-enabled. This in-
cludes all USB SFRs from address 030016 to 033C16. It does not include USBC or FSC.
Note th at the con figuration c hanges described above ma y not need to be mad e if the MC U was not
placed in a suspend state as described in section 5.1.2.3 Set up after USB Suspend Detected.
1.5.1.7 PLL Lock Bit
The PLL lock bit is used to indicate when the PLL is first locked. Accordingly, after the PLL is enabled
and it has been giv en 2.0 ms to stabiliz e, the loc k bit status should be checked . Once the lock bit is
HIGH, the USB c heck sho uld be e nabled. After th is stage, the loc k bit is no longer valid an d shoul d
not be monitored, unless the PLL is re-enabled.
Attach/Detach Function
M30240 Group
Rev. H Sep 18, 2003 Page 135 of 139
1.5.2 Attach/D etach Funct ion
The Attach/Detach Function can be used to attach or detach a USB function from the host without
disconnecting the cable. When attaching a USB function, the connect registers should be set to 0316 at
the same time on or before the DC-DC Converter is enabled. Similarly, when detaching the connect
register, it should be set to 0116 when powering down the DC-DC Converter.
If you do not set the connect (address 001F16) to HIGH, the system will default to its normal mode.
Note: If the D+ is connected to EXTCAP, this mode will not work.
D+ is connected to EXTCAP through a 1.5 K resistor in compliance with the USB specification. USB
Suspend/Resume Function
Hardware connections are shown below
1.5.3 Low Pass Filter Network
All passive components should be in close proximity to pin 78 (LPF), capacitors should be X7R di-
electric o r bett er. The r ecommended v alu es ar e li ste d in Table 1.5 1. See F ig ure 1.119 for sc hem ati c of
the LPF.
Analog V ss and Analog Vcc, pins 77 and 80 shoul d hav e isol ated conn ec tio ns to the digi tal V ss and Vcc
ground planes. Figure 1.120 shows the power supply isolation.
Table 1.51: Recommended values
Figure 1.119: LPF Filter Schematic Figure 1.120: Power Supply
R = 1000
Ω
10%
C2 = 680 pf 10%
C1 = 0.1 µf10%
Attach is connected to D+ through 1.5 K resistor.
ATTACH [P83] D+ (pin 9 M30240)
Atta ch/ Detach mode disabled
EXTCAP D+ (pin 9 M30240)
1.5 K
1.5 K
R
C1
C2
Pin 78
(LPF)
Pin 77 AVss
Digital
Vcc
(on card)
Digital
Vss
Analog
Vss (Pin
77)
Analog
Vcc
(Pin 80)
CC
Decoupling
Capacitors
Ferrite Beads
Figure 1 .119
Figure 1.120
USB Transceiver
M30240 Group
Rev. H Sep 18, 2003 Page 136 of 139
1.5.4 USB Transceiver
When using the on-chip voltage converter to supply the necessary 3.3V to the driver circuit, a capacitor
network m us t b e co nne cte d between E xt . Ca p (p in 6 ) and VSS (p in 13). T wo c apaci to r s are re q ui red
as show n in Fig ure 1.21. The h igh frequ ency 0.1
µ
F
capaci tor shou ld be
an X7R t ype or be tter. Th e
low freque ncy decoupl ing capaci tor of 2.2
µ
F
should be of tantalum di-electric or better.
The start-up
time for this value of the capacitor is 3.2 ms, approximately (1ms/
µ
F
) + 1 ms.
After enabling the on-chip voltage converter, a certain amount of time must pass before a wait or stop
clock ins tructio n is exe cuted . The amo unt of time i s given by (C+1) m s, whe n C is the v alue in
µ
F
of
the external capacitance connected to the Ext. Cap pin. For example, if the external capacitance is 2.2
µ
F
, at least 3.2 ms must elapse from the time that the on-chip voltage converter is enabled until a WAIT
instruction or STOP command (CM10 = 1) is executed.
In order to meet the impedance matching requirements of the USB Specification, a 27Ω-33Ω resistor
must be added to USB D+ (pin 9) and to USB D- (pin 10). In addition, capacitors connected between
USB D+ and USB D- or USB D+/D- and Vss may need to be added for rise/fall time matching and
edge control. These capacitors should be placed after the 33 Ω resistors. Their configuration and val-
ues will depend on the PCs layout. The placement of external components is illustrated in Figure .
Figure 1.121: Configuration of External USB components
27-33
Ω
27-33
Ω
+
_
D+
D-
XCV_Vm_in
XCV_Vp_in
XCV_Rxd
XCV_Vp_out
XCV_Suspend
XCV_Vm_out
XCV_Txen_n
Transceiver
USB_Vp_out
USB_Txen_n
USB_Vm_out
USB_Suspend
USB_Rxd
USB_Vp_in
USB_Vm_in
USB Block
Voltage Converter
2.2
µ
F0.1
µ
F 10%
EXTCAP
22 pF
22 pF
10%
33 p F
(Note)
Note: Capacitor and resistor values and configuration may depend on PCB layout.
Programming Notes
M30240 Group
Rev. H Sep 18, 2003 Page 137 of 139
1.5.5 Programming Notes
1.5.5.1 Accessing USB IN/OUT Control and Status Registers
Do not use r ead-modify- write instruct ion on these regi sters because they contain c ontrol and st atus
bits that can be changed by both hardware and software. There is a possibility that using a read-mod-
ify-writ e instructi on might cause i ncorrect data to be written ba ck to these regi sters. See T able 1.52
for a li st of bits that m ay have inc orrect data w ritten to them and the value y ou should writ e back in
order to prevent this from occurring.
The Endpoint 1-4 IN CSR’s (EPiICS, i = 1-4) have a bit IN_PKT_RDY (bit 0) that is set to a “1” by the
firmware after a packet of data is loaded to the respective endpoint’s FIFO. This signifies that a packet
is ready for transmission. If the firmware wants to send a NULL packet to the host, it can simply write
a “1” to the IN_PK T_RDY bit without lo ading da ta to the FIF O. This bit is cleare d by the har dware. If
the firmware manipulates (writes) the IN CSR for a purpose other than to signify to the hardware that
a data packet is ready for transmission (for instance, set/reset ISO bit, set/reset SEND_STALL bit), it
must make sure that a “0” is written back to the IN_PKT_RDY bit. Failure to do so could cause improp-
er operation of the device. Writing a “0” to the IN_PKT_RDY bit has no effect on its state.
The Endpoint 1-4 OUT CSRs (EPiICS, i = 1-4) have a bit OUT_PKT_RDY (bit 0) that is set to a “1” by
the hardwar e after a packe t of data is receiv ed from the host to the respec tive endp oint’s FIFO. This
signifi es that a packet i s ready for down load. This bit i s cleared by the fi rmware by writing a “0” t o it
after the data packet is unloaded from the FIFO. If the firmware manipulates (writes) the OUT CSR for
a purpo se other than to sign ify to the hardwar e that a dat a packet has been unl oaded (fo r instanc e,
set/reset ISO bit, set/reset SEND_STALL bit), it must make sure that a “1” is written back to the
OUT_PKT_RDY bit. Failure to do so could cause improper operation. Writing a “1” to the
OUT_PKT_RDY bit has no effect on its state.
Table 1.52: Bits that might have incorrect data
Register name Bit name Value to write for “No change”
EP0CS
IN_PKT_RDY (b1) “0”
DATA_END (b3) “0”
FORCE_STALL (b4) “1”
EPxICS (x = 1-4) IN_PKT_RDY (b0) “0”
UNDER_RUN (b1) “1”
EPxOCS (x = 1-4)
OUT_PKT_RDY (b0) “1”
OVER_RUN (b1) “1”
FORCE_STALL (b4) “1”
DATA-ERR (b5) “1”
Programming Notes
M30240 Group
Rev. H Sep 18, 2003 Page 138 of 139
Below is an example of how to set/reset the ISO bit of the IN CSR register (for initializing the respective
endpoint as an isochronous endpoint):
1.5.5.2 USB Consecutive Set Address
The USB Specification states that the host can send a SET_ADDRESS request for the following cas-
es:
1. During enumeration when the device is in default state. (The host assigns a non-zero address.)
2. When the device is in the address state. (The host can re-assign a new address.)
The device handles case #1 (when the device is in the default state) and case #2 (when the device is
in the add ress state) d iffer ently. The followi ng is a segment o f code to illust rate the program f low to
properly deal with these cases.
Note: wValue_lo = assigned address from the host in SET-ADDRESS request.
[R1L] = [EPiICS].B
OR.B #0AH, R1L ;set ISO bit = 1, write “1” back to UNDER_RUN bit
AND.B #0FEH, R1L ;write “0” back to IN_PKT_RDY bit
[EPiICS].B = [R1L]
[R1L] = [EPiICS].B
OR.B #02, R1L ;write “1” back to UNDER_RUN bit
AND.B #0F6H, R1L ;reset ISO bit = 0, write “0” back to IN_PKT_RDY bit
[EPiICS].B= [R1L]
DEFAULT_STATE:
If [USBA].B ==0
[USBA.].B = wValue _ lo ;If the device is in default state, update address before STATUS
completion
R1L = [EP0CS].B ;USB ENDPOINT 0 CSR
OR.B #58H, R1L ;Set serviced_out_pkt_rdy & data_end, write “1” back to FORCE_STALL bit
[EP0CS].B = R1L
wait for the completion of the status
JMP ADDR_END
else
ADDR_STATE
R1L [EP0CS].B ;USB ENDPOINT 0 CSR
OR.B #58H, R1L ;Set serviced_out_pkt_rdy & data_end, write “1” back to FORCE_STALL bit
[EP0CS].B = R1L
wait for the completion of the status
[USBA].B= wValue_lo ;If the device is in address state, update address before STATUS
completion
ADDR_END
endif
end of the set_address routine
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REVISION HISTORY M30240 Group Data Sheet
Rev. Date Description
Page Summary
G 10/23/2001 First Edition Issued
H 09/18/2003 -- Changed to new Renesas format
125 Table 1.38 : Removed reference to Table 2, added XIN and CNVSS to
VIH, VIL
126 Table 1.39: Removed Icc typical measurements
125-137 Tables 1.1 to 1.14 numbering changed to Tables 1.39 to 1.52
