Important notice
Dear Customer,
On 7 February 2017 the former NXP Standard Product business became a new company with the
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Replace the copyright notice at the bottom of each page or elsewhere in the document, depending on
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1. General description
The 74HC191 is an asynchronously presettable 4-bit binary up/down counter. It contains
four master/slave flip-flops with internal gatin g and steering log ic to provide a synchronou s
preset and synchronous count-up and count-down operation. Asynchronous parallel load
capability permits the counter to be preset to any desired value. Information present on
the parallel data input s (D0 to D3) is loaded into the counter and appears on the outputs
when the parallel load (PL) input is LOW. This operation overrides the counting function.
Counting is inhibited by a HIGH level on the count enable (CE) input. When CE is LOW
internal state changes are initiated synchronously by the LOW-to-HIGH transition of the
clock input. The up/down (U/D) input signal determines the direction of counting as
indicated in the function table. The CE input may go L OW when the clock is in either st ate,
however, the LOW-to-HIGH CE transition must occur only when the clock is HIGH. Also,
the U/D input should be changed only whe n either CE or CP is HIGH. Overflow/underflow
indications are provided by two types of outputs, the terminal count (TC) and ripple clock
(RC). The TC output is normally LOW and goes HIGH when a circuit reaches zero in the
count-down mode or reaches '15' in the count-up-mode. The TC output will remain HIGH
until a state change occurs, either by counting or prese ttin g , or un til U/D is changed. Do
not use the TC output as a clock signal because it is subject to decoding spikes. The TC
signal is used internally to enable the RC output. When TC is HIGH and CE is LOW, the
RC output follows the clock puls e (CP). This feature simplifies the design of multistage
counters as shown in Figure 5 and Figure 6. In Figure 5, each RC output is used as the
clock input to the next highe r st age. It is on ly necessary to inhibit the first st ag e to prevent
counting in all stages, since a HIGH on CE inhibits the RC output pulse . The timing skew
between state changes in the first and last stages is represented by the cumulative delay
of the clock as it ripples through the preceding stages. This can be a disad vantage of this
configuration in some applicatio ns. Figure 6 shows a method of causing state changes to
occur simultaneously in all stages. The RC outputs propagate the carr y/borrow signals in
ripple fashion and a ll clock inputs are driven in pa rallel. In this configuration the duration of
the clock LOW state must be lon g enough to allow the negative-going edge of the
carry/borrow signal to ripple through to the last stage before the clock goes HIGH. Since
the RC output of any package goes HIGH shortly af ter its CP input goes HIGH there is no
such restriction on the HIGH-state duration of the clock. In Figure 7, the configuration
shown avoids ripple delays and their associated restrictions. Combining the TC signals
from all the preceding stages forms the CE input for a given stage. An enable must be
included in each carry gate in order to inh ibit counting. The TC output of a given stage it
not affected by its own CE signal therefore th e simple inhibit scheme of Figure 5 and
Figure 6 does not apply. Inputs includ e cla mp diodes. This enables the use of current
limiting resistors to interface inputs to voltag es in excess of VCC.
74HC191
Presettable synchronous 4-bit binary up/down counter
Rev. 3 — 3 January 2017 Product data sheet
74HC191 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved.
Product data sheet Rev. 3 — 3 January 2017 2 of 22
NXP Semiconductors 74HC191
Presettable synchronous 4-bit binary up/down counter
2. Features and benefits
Complies with JEDEC standard no. 7A
Input levels:
For 74HC191: CMOS level
Synchronous reversible counting
Asynchronous parallel load
Count enable control for synchronous expansion
Single up/down control input
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 20 0 V
Multiple package options
Specified from 40 C to +85 C and 40 C to +125 C
3. Ordering information
4. Functional diagram
Table 1. Ordering information
Type number Package
Temperature range Name Description Version
74HC191D 40 C to +125 C SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1
74HC191DB 40 C to +125 C SSOP16 plastic shrink small outline package; 16 leads;
body width 5.3 mm SOT338-1
74HC191PW 40 C to +125 C TSSOP16 plastic thin shrink small outline package; 16 leads;
body width 4.4 mm SOT403-1
Fig 1. Functional di ag ram Fig 2. Logic symbol
DDD
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74HC191 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved.
Product data sheet Rev. 3 — 3 January 2017 3 of 22
NXP Semiconductors 74HC191
Presettable synchronous 4-bit binary up/down counter
5. Pinning information
5.1 Pinning
5.2 Pin description
Fig 3. Pin configuration SO16 Fig 4. Pin configuration TSSOP16 and SSOP16
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Table 2. Pin description
Symbol Pin Description
D0, D1, D2, D3 15, 1, 10, 9 data input
Q0, Q1, Q2, Q3 3, 2, 6, 7 flip-flop output
CE 4 count enable input (active LOW)
U/D 5 up/down input
GND 8 ground (0 V)
PL 11 parallel load input (active LOW)
TC 12 terminal count output
RC 13 ripple clock output (active LOW)
CP 14 clock input (LOW-to-HIGH, edge-triggered)
VCC 16 supply voltage
74HC191 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved.
Product data sheet Rev. 3 — 3 January 2017 4 of 22
NXP Semiconductors 74HC191
Presettable synchronous 4-bit binary up/down counter
6. Functional description
[1] H = HIGH voltage level
L = LOW voltage level
l = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition
X = don’t care
= LOW-to-HIGH clock transition
[1] H = HIGH voltage level
L = LOW voltage level
X = don’t care
= one LOW level pulse
= TC goes LOW on a LOW-to-HIGH clock transition
Table 3. Function table[1]
Operating mode Input Output
PL U/D CE CP Dn Qn
parallel load L X X X L L
LXXXHH
count up H L l X count up
count down H H l X count down
Hold (do nothing) H X H X X no change
Table 4. TC and RC Function t a ble[1]
Input Terminal co unt state Output
U/D CE CP Q0 Q1 Q2 Q3 TC RC
H HXHHHHLH
L HXHHHHHH
L L HHHH
L HXLLLLLH
H HXLLLLHH
H L LLLL
74HC191 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved.
Product data sheet Rev. 3 — 3 January 2017 5 of 22
NXP Semiconductors 74HC191
Presettable synchronous 4-bit binary up/down counter
Fig 5. N-st a ge ripple co unter using ripple clock
DDD
&3&/2&.
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Fig 6. Synchronous n-stage counter using ripple carry/borrow
DDD
&3
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Fig 7. Synchronous n-stage counter with parallel gated carry/borrow
DDD
&3
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&21752/
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8'
7& &3
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7&7&
74HC191 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved.
Product data sheet Rev. 3 — 3 January 2017 6 of 22
NXP Semiconductors 74HC191
Presettable synchronous 4-bit binary up/down counter
Fig 8. Logic diag ra m
DDD
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&3 &3
5' 5'
44444 444
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6' 6' 6'
7& 4 4 4 4
74HC191 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved.
Product data sheet Rev. 3 — 3 January 2017 7 of 22
NXP Semiconductors 74HC191
Presettable synchronous 4-bit binary up/down counter
7. Limiting values
[1] For SO16 packages: above 70 C the value of Ptot derates linearly at 8 mW/K.
For (T)SSOP16 packages: above 60 C the value of Ptot derates linearly at 5.5 mW/K.
Typical timing sequence: reset outputs to zero; preset to binary twelve; count to thirteen, fourteen, fifteen, zero, one and two;
inhibit.
Fig 9. Typical timing sequence
DDD
ORDG FRXQWXS
LQKLELW FRXQWGRZQ
3/
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Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
VCC supply voltage 0.5 +7.0 V
IIK input clamping current VI < 0.5 V or VI>V
CC + 0.5 V - 20 mA
IOK output clamping current VO < 0.5 V or VO > VCC + 0.5 V - 20 mA
IOoutput curren t VO= 0.5 V to VCC + 0.5 V - 25 mA
ICC supply current - 50 mA
IGND ground current 50 - mA
Tstg storage temperature 65 +150 C
Ptot total power dissipation SO16 package [1] - 500 mW
(T)SSOP16 package [1] - 500 mW
74HC191 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved.
Product data sheet Rev. 3 — 3 January 2017 8 of 22
NXP Semiconductors 74HC191
Presettable synchronous 4-bit binary up/down counter
8. Recommended operating conditions
9. Static characteristics
Table 6. Recommended operating con ditions
Voltages are referenced to GND (ground = 0 V)
Symbol Parameter Conditions Min Typ Max Unit
VCC supply voltage 2.0 5.0 6.0 V
VIinput voltage 0 - VCC V
VOoutput voltage 0 - VCC V
Tamb ambient temperature 40 +25 +125 C
t/V input transition rise and fall rate VCC = 2.0 V - - 625 ns/V
VCC = 4.5 V - 1.67 139 ns/V
VCC = 6.0 V - - 83 ns/V
Table 7. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 25 C40 C to +85 C40 C to +125 CUnit
Min Typ Max Min Max Min Max
VIH HIGH-level
input voltage VCC = 2.0 V 1.5 1.2 - 1.5 - 1.5 - V
VCC = 4.5 V 3.15 2.4 - 3.15 - 3.15 - V
VCC = 6.0 V 4.2 3.2 - 4.2 - 4.2 - V
VIL LOW-level
input voltage VCC = 2.0 V - 0.8 0.5 - 0.5 - 0.5 V
VCC = 4.5 V - 2.1 1.35 - 1.35 - 1.35 V
VCC = 6.0 V - 2.8 1.8 - 1.8 - 1.8 V
VOH HIGH-level
output voltage VI=V
IH or VIL
IO=20 A; VCC = 2.0 V 1.9 2.0 - 1.9 - 1.9 - V
IO=20 A; VCC = 4.5 V 4.4 4.5 - 4.4 - 4.4 - V
IO=20 A; VCC = 6.0 V 5.9 6.0 - 5.9 - 5.9 - V
IO=4.0; VCC = 4.5 V 3.98 4.32 - 3.84 - 3.7 - V
IO=5.2; VCC = 6.0 V 5.48 5.81 - 5.34 - 5.2 - V
VOL LOW-level
output voltage VI=V
IH or VIL
IO=20A; VCC = 2.0 V - 0 0.1 - 0.1 - 0.1 V
IO=20A; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V
IO=20A; VCC = 6.0 V - 0 0.1 - 0.1 - 0.1 V
IO=4.0mA; V
CC = 4.5 V - 0.15 0.26 - 0.33 - 0.4 V
IO=5.2mA; V
CC = 6.0 V - 0.16 0.26 - 0.33 - 0.4 V
IIinput leakage
current VI=V
CC or GND; VCC =6.0V - - 0.1 - 1.0 - 1.0 A
ICC supply current VI=V
CC or GND; IO=0A;
VCC =6.0V - - 8.0 - 80.0 - 160.0 A
CIinput
capacitance -3.5- - - - -pF
74HC191 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved.
Product data sheet Rev. 3 — 3 January 2017 9 of 22
NXP Semiconductors 74HC191
Presettable synchronous 4-bit binary up/down counter
10. Dynamic characteristics
Table 8. Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 18.
Symbol Parameter Conditions 25 C40 C to +85 C40 C to +125 CUnit
Min Typ Max Min Max Min Max
tpd propagation
delay CP to Qn; see Figure 10 [1]
VCC = 2.0 V - 72 220 - 275 - 330 ns
VCC = 4.5 V - 26 44 - 55 - 66 ns
VCC = 5.0 V; CL=15pF - 22 - - - - - ns
VCC = 6.0 V - 21 37 - 47 - 56 ns
CP to TC; see Figure 10
VCC = 2.0 V - 83 255 - 320 - 395 ns
VCC = 4.5 V - 30 51 - 64 - 77 ns
VCC = 6.0 V - 24 43 - 54 - 65 ns
CP to RC; see Figure 11
VCC = 2.0 V - 47 150 - 190 - 225 ns
VCC = 4.5 V - 17 30 - 38 - 45 ns
VCC = 6.0 V - 14 26 - 33 - 38 ns
CE to RC; see Figure 11
VCC = 2.0 V - 33 130 - 165 - 195 ns
VCC = 4.5 V - 12 26 - 33 - 39 ns
VCC = 6.0 V - 10 22 - 28 - 33 ns
Dn to Qn; see Figure 12
VCC = 2.0 V - 61 220 - 275 - 330 ns
VCC = 4.5 V - 22 44 - 55 - 66 ns
VCC = 6.0 V - 18 37 - 47 - 56 ns
PL to Qn; see Figure 13
VCC = 2.0 V - 61 220 - 275 - 330 ns
VCC = 4.5 V - 22 44 - 55 - 66 ns
VCC = 6.0 V - 18 37 - 47 - 56 ns
U/D to TC; see Figure 14
VCC = 2.0 V - 44 190 - 240 - 285 ns
VCC = 4.5 V - 16 38 - 48 - 57 ns
VCC = 6.0 V - 13 32 - 41 - 48 ns
U/D to RC; see Figure 14
VCC = 2.0 V - 50 210 - 265 - 315 ns
VCC = 4.5 V - 18 42 - 53 - 63 ns
VCC = 6.0 V - 14 36 - 45 - 54 ns
tttransition
time see Figure 15 [2]
VCC =2.0V - 19 75 - 95 - 110 ns
VCC =4.5V - 7 15 - 19 - 22 ns
VCC =6.0V - 6 13 - 16 - 19 ns
74HC191 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved.
Product data sheet Rev. 3 — 3 January 2017 10 of 22
NXP Semiconductors 74HC191
Presettable synchronous 4-bit binary up/down counter
tWpulse width CP; HIGH or LOW;
see Figure 10
VCC = 2.0 V 125 28 - 155 - 195 - ns
VCC =4.5V 25 10 - 31 - 39 - ns
VCC =6.0V 21 8 - 26 - 33 - ns
PL; LOW; see Figure 15
VCC = 2.0 V 100 22 - 125 - 150 - ns
VCC =4.5V 20 8 - 25 - 30 - ns
VCC =6.0V 17 6 - 21 - 26 - ns
trec recovery
time PL to CP; see Figure 15
VCC =2.0V 35 8 - 45 - 55 - ns
VCC =4.5V 7 3 - 9 - 11 - ns
VCC =6.0V 6 2 - 8 - 9 - ns
tsu set-up time U/D to CP; see Figure 17
VCC = 2.0 V 205 50 - 255 - 310 - ns
VCC =4.5V 41 18 - 51 - 62 - ns
VCC =6.0V 35 14 - 43 - 53 - ns
Dn to PL; see Figure 16
VCC = 2.0 V 100 19 - 125 - 150 - ns
VCC =4.5V 20 7 - 25 - 30 - ns
VCC =6.0V 17 6 - 21 - 26 - ns
CE to CP; see Figure 17
VCC = 2.0 V 140 44 - 175 - 210 - ns
VCC =4.5V 28 16 - 35 - 42 - ns
VCC =6.0V 24 13 - 30 - 36 - ns
thhold time U/D to CP; see Figure 17
VCC =2.0V 0 39 - 0 - 0 - ns
VCC =4.5V 0 14 - 0 - 0 - ns
VCC =6.0V 0 11 - 0 - 0 - ns
Dn to PL; see Figure 16
VCC =2.0V 0 11 - 0 - 0 - ns
VCC =4.5V 0 4- 0 - 0 -ns
VCC =6.0V 0 3- 0 - 0 -ns
CE to CP; see Figure 17
VCC =2.0V 0 28 - 0 - 0 - ns
VCC =4.5V 0 10 - 0 - 0 - ns
VCC =6.0V 0 8- 0 - 0 -ns
Table 8. Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 18.
Symbol Parameter Conditions 25 C40 C to +85 C40 C to +125 CUnit
Min Typ Max Min Max Min Max
74HC191 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved.
Product data sheet Rev. 3 — 3 January 2017 11 of 22
NXP Semiconductors 74HC191
Presettable synchronous 4-bit binary up/down counter
[1] tpd is the same as tPHL and tPLH.
[2] tt is the same as tTHL and tTLH.
[3] CPD is used to determine the dynamic power dissipation (PD in W):
PD=C
PD VCC2fiN+(CLVCC2fo) where:
fi= input frequency in MHz;
fo= output frequency in MHz;
CL= output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
(CLVCC2fo) = sum of outputs.
11. Waveforms
fmax maximum
frequency CP; see Figure 10
VCC = 2.0 V 4.0 11 - 3.2 - 2.6 - MHz
VCC =4.5V 20 33 - 16 - 13 - MHz
VCC = 5.0 V; CL=15pF - 36 - - - - - MHz
VCC =6.0V 24 39 - 19 - 15 - MHz
CPD power
dissipation
capacitance
VI = GND to VCC; VCC =5V;
fi=1MHz [3] -31- - - - -pF
Table 8. Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 18.
Symbol Parameter Conditions 25 C40 C to +85 C40 C to +125 CUnit
Min Typ Max Min Max Min Max
Measurement points are given in Table 9.
Logic levels VOL and VOH are typical output voltage levels that occur with the output load.
Fig 10. T he clock input (CP) to outp uts (Qn, TC) propagation delays, clock pulse width and maximum clock
frequency
DDD
9
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9
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9
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9
0
9
0
W
:
W
3/+
W
3+/
74HC191 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved.
Product data sheet Rev. 3 — 3 January 2017 12 of 22
NXP Semiconductors 74HC191
Presettable synchronous 4-bit binary up/down counter
Measurement points are given in Table 9.
Logic levels VOL and VOH are typical output voltage levels that occur with the output load.
Fig 11. The clock and count enable inputs (CP, CE) to ripple clock output (RC) prop agation delays
DDD
90
W3+/ W3/+
9
,
*1'
&3
&(LQSXW
92+
92/
90
5&RXWSXW
Measurement points are given in Table 9.
Logic levels VOL and VOH are typical output voltage levels that occur with the output load.
Fig 12. The input (Dn) to output (Qn) propagation delays
DDD
90
W3+/ W3/+
9
,
*1'
'QLQSXW
92+
92/
90
4QRXWSXW
Measurement points are given in Table 9.
Logic levels VOL and VOH are typical output voltage levels that occur with the output load.
Fig 13. The parallel load input (PL) to ou tpu t (Qn) propagation delays
DDD
9
0
9
0
9
O
9
O
*1'
'QLQSXW
3
/LQSXW
4QRXWSXW
*1'
9
2+
9
2/
W
3/+
W
3+/
74HC191 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved.
Product data sheet Rev. 3 — 3 January 2017 13 of 22
NXP Semiconductors 74HC191
Presettable synchronous 4-bit binary up/down counter
Measurement points are given in Table 9.
Logic levels VOL and VOH are typical output voltage levels that occur with the output load.
Fig 14. The up/down count input (U/D) to terminal count and ripple clock output (TC, RC) propagation delays
DDD
90
9
,
*1'
92+
92+
92/
92/
90
90
W3/+
W3+/ W3/+
W3+/
8'LQSXW
7&RXWSXW
5&RXWSXW
Measurement points are given in Table 9.
Logic levels VOL and VOH are typical output voltage levels that occur with the output load.
Fig 15. The parallel load input (PL) to clock (CP) recovery times, parallel load pulse width and output (Qn )
transition times
DDD
92+
92/
90
9,
9,
*1'
*1'
W7/+
W7+/
90
90
W:
WUHF
W3+/
4QRXWSXW
3/LQSXW
&3LQSXW
74HC191 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved.
Product data sheet Rev. 3 — 3 January 2017 14 of 22
NXP Semiconductors 74HC191
Presettable synchronous 4-bit binary up/down counter
The shaded areas indicate when the input is permitted to change for predictable output performance.
Measurement points are given in Table 9.
Fig 16. The parallel load input (PL) to data input (Dn) set-up and hold times
DDD
90
*1'
'QLQSXW
*1'
WK
3/LQSXW
90
WVX WVX
WK
9O
9O
The shaded areas indicate when the input is permitted to change for predictable output performance.
Measurement points are given in Table 9.
Fig 17. The count enabl e and up/down count inputs (CE, U/D) to clock input (CP) set-up and hold times
DDD
*1'
*1'
9O
90
&3LQSXW
*1'
90
90
&(8'LQSXW
&(8'LQSXW
9
O
9O
WVX
WK
WK
WVX
Table 9. Measurement points
Input Output
VMVIVM
0.5 VCC GND to VCC 0.5 VCC
74HC191 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved.
Product data sheet Rev. 3 — 3 January 2017 15 of 22
NXP Semiconductors 74HC191
Presettable synchronous 4-bit binary up/down counter
Test data is given in Table 10.
Test circuit definitions:
RT = Termination resistance should be equal to output impedance Zo of the pulse generator
CL = Load capacitance including jig and probe capacitance
RL = Load resistance.
S1 = Test selection switch
Fig 18. Test circuit for measuring switching times
9
0
9
0
W
:
W
:
9
9
,
9
,
QHJDWLYH
SXOVH
SRVLWLYH
SXOVH
9
9
0
9
0
W
I
W
U
W
U
W
I
DDG
'87
9
&&
9
&&
9,92
57
5/6
&/
RSHQ
*
Table 10. Test data
Input Load S1 position
VItr, tfCLRLtPHL, tPLH
VCC 6 ns 15 pF, 50 pF 1 kopen
74HC191 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved.
Product data sheet Rev. 3 — 3 January 2017 16 of 22
NXP Semiconductors 74HC191
Presettable synchronous 4-bit binary up/down counter
12. Package outline
Fig 19. Package outline SOT109-1 (SO16)
;
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Product data sheet Rev. 3 — 3 January 2017 17 of 22
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Product data sheet Rev. 3 — 3 January 2017 18 of 22
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74HC191 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved.
Product data sheet Rev. 3 — 3 January 2017 19 of 22
NXP Semiconductors 74HC191
Presettable synchronous 4-bit binary up/down counter
13. Abbreviations
14. Revision history
Table 11. Abbreviations
Acronym Description
CMOS Complementary Metal-Oxide Semiconductor
DUT Device Under Test
ESD ElectroStatic Discharge
HBM Human Body Model
MM Machine Model
Table 12. Revision history
Document ID Release date Data sheet status Change notice Supersedes
74HC191 v.3 20170103 Product data sheet - 74HC_HCT191 v.2
Modifications: •The format of this data sheet has been redesigned to comply with the new identity
guidelines of NXP Semiconductors.
•Legal texts have been adapted to the new company name where appropriate .
•Type numbers 74HCT191D, 74HCT191DB, 74HCT191PW removed.
74HC_HCT191_CNV v.2 19901201 Product specificatio n - -
74HC191 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved.
Product data sheet Rev. 3 — 3 January 2017 20 of 22
NXP Semiconductors 74HC191
Presettable synchronous 4-bit binary up/down counter
15. Legal information
15.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design .
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of device (s) descr ibed in this d ocument m ay have cha nged since thi s document w as publish ed and may dif fe r in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
15.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liab ility for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and tit le. A short data sh eet is intended
for quick reference only and shou ld not b e relied u pon to cont ain det ailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semicond uctors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall pre va il.
Product specificat io n — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to off er functions and qualities beyond those described in the
Product data sheet.
15.3 Disclaimers
Limited warr a nty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warrant ies, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Se miconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidenta l ,
punitive, special or consequ ential damages (including - wit hout limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulat ive liability toward s
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all informa tion supplied prior
to the publication hereof .
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expect ed
to result in perso nal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconducto rs products in such equipment or
applications and ther efore such inclu sion and/or use is at the cu stomer’s own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and ope ration of their applications
and products using NXP Semiconductors product s, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suit able and fit for t he customer’s applications and
products planned, as well as fo r the planned application and use of
customer’s third party customer(s). Custo mers should provide appropriate
design and operating safeguards to minimize the risks associate d with t heir
applications and products.
NXP Semiconductors does not accept any liabil ity related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party custo mer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by cust omer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individua l agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing i n this document may be interpreted or
construed as an of fer t o sell product s that is open for accept ance or the gr ant,
conveyance or implication of any license under any copyrights, patents or
other industrial or inte llectual property rights.
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specificat ion.
Product [short] data sheet Production This document contains the product specification.
74HC191 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved.
Product data sheet Rev. 3 — 3 January 2017 21 of 22
NXP Semiconductors 74HC191
Presettable synchronous 4-bit binary up/down counter
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It i s neit her qualif ied nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automot ive specifications and standards, custome r
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such au tomotive applications, use and specifi cations, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconduct ors for an y
liability, damages or failed product claims resulting from custome r design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specif ications.
Translations — A non-English (translated) versio n of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
15.4 Trademarks
Notice: All referenced b rands, produc t names, service names and trademarks
are the property of their respective ow ners.
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
NXP Semiconductors 74HC191
Presettable synchronous 4-bit binary up/down counter
© NXP Semiconductors N.V. 2017. A ll rights rese rved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 3 January 2017
Document identifi er: 74HC191
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
17. Contents
1 General description. . . . . . . . . . . . . . . . . . . . . . 1
2 Features and benefits . . . . . . . . . . . . . . . . . . . . 2
3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2
4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
5 Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
6 Functional description . . . . . . . . . . . . . . . . . . . 4
7 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 7
8 Recommended operating conditions. . . . . . . . 8
9 Static characteristics. . . . . . . . . . . . . . . . . . . . . 8
10 Dynamic characteristics . . . . . . . . . . . . . . . . . . 9
11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 16
13 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 19
14 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 19
15 Legal information. . . . . . . . . . . . . . . . . . . . . . . 20
15.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 20
15.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
15.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 20
15.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 21
16 Contact information. . . . . . . . . . . . . . . . . . . . . 21
17 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
