LM78L15ACMX NOPB - TEXAS INSTRUMENTS

August, 2009 − Rev. 18

1Publication Order Number:

CAT93C56/D

CAT93C56, CAT93C57

2-Kb Microwire Serial

CMOS EEPROM

Description

The CAT93C56/57 is a 2−kb CMOS Serial EEPROM device which

is organized as either 128 registers of 16 bits (ORG pin at VCC) or 256

registers of 8 bits (ORG pin at GND). Each register can be written (or

read) serially by using the DI (or DO) pin. The CAT93C56/57 features

sequential read and self−timed internal write with auto−clear. On−chip

Power−On Reset circuitry protects the internal logic against powering

up in the wrong state.

Features

•High Speed Operation: 2 MHz

•1.8 V to 5.5 V Supply Voltage Range

•Selectable x8 or x16 Memory Organization

•Sequential Read

•Software Write Protection

•Power−up Inadvertant Write Protection

•Low Power CMOS Technology

•1,000,000 Program/Erase Cycles

•100 Year Data Retention

•Industrial and Extended Temperature Ranges

•8−pin PDIP, SOIC, TSSOP and 8−pad TDFN Packages

•These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS

Compliant

ORG

CAT93C57

GND

VCC

CAT93C56

Figure 1. Functional Symbol

NOTE: When the ORG pin is connected to VCC, the x16 organization is selected.

When it is connected to ground, the x8 pin is selected. If the ORG pin is left

unconnected, then an internal pullup device will select the x16 organization.

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See detailed ordering and shipping information in the package

dimensions section on page 16 of this data sheet.

ORDERING INFORMATION

PIN CONFIGURATIONS

GND

VCC

CS 1

SOIC−8

V or W SUFFIX

CASE 751BD

TDFN−8

VP2 SUFFIX

CASE 511AK

ORG

PDIP (L), SOIC (V, X),

TSSOP (Y), TDFN (VP2, ZD4*)

PDIP−8

L SUFFIX

CASE 646AA

TSSOP−8

Y SUFFIX

CASE 948AL

Chip SelectCS

Clock InputSK

Serial Data InputDI

Serial Data OutputDO

Power SupplyVCC

GroundGND

FunctionPin Name

PIN FUNCTION

Memory OrganizationORG

No ConnectionNC

GND

ORG

VCC

SOIC (W*)

(Top Views)

SOIC−8 EIAJ

X SUFFIX

CASE 751BE

TDFN−8

ZD4 SUFFIX

CASE 511AL

* TDFN 3x3 mm (ZD4) and

SOIC (W) rotated pin−out

packages are available for

CAT93C57 and CAT93C56,

Rev. E only (not recommen-

ded for new designs of

CAT93C56)

CAT93C56, CAT93C57

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Table 1. ABSOLUTE MAXIMUM RATINGS

Parameters Ratings Units

Storage Temperature −65 to +150 °C

Voltage on Any Pin with Respect to Ground (Note 1) −0.5 to +6.5 V

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the

Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect

device reliability.

1. The DC input voltage on any pin should not be lower than −0.5 V or higher than VCC + 0.5 V. During transitions, the voltage on any pin may

undershoot to no less than −1.5 V or overshoot to no more than VCC + 1.5 V, for periods of less than 20 ns.

Table 2. RELIABILITY CHARACTERISTICS (Note 2)

Symbol Parameter Min Units

NEND (Note 3) Endurance 1,000,000 Program / Erase Cycles

TDR Data Retention 100 Years

2. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100

and JEDEC test methods.

3. Block Mode, VCC = 5 V, 25°C

Table 3. D.C. OPERATING CHARACTERISTICS, CAT93C56, Die Rev. G – New Product

(VCC = +1.8 V to +5.5 V, TA=−40°C to +125°C unless otherwise specified.)

Symbol Parameter Test Conditions Min Max Units

ICC1 Power Supply

Current (Write)

fSK = 1 MHz, VCC = 5.0 V 1 mA

ICC2 Power Supply

Current (Read)

fSK = 1 MHz, VCC = 5.0 V 500 mA

ISB1 Power Supply

Current (Standby)

(x8 Mode)

VIN = GND or VCC,

CS = GND ORG = GND

TA = −40°C to +85°C 2 mA

TA = −40°C to +125°C 4

ISB2 Power Supply

Current (Standby)

(x16 Mode)

VIN = GND or VCC, CS =

GND ORG = Float or VCC

TA = −40°C to +85°C 1 mA

TA = −40°C to +125°C 2

ILI Input Leakage

Current

VIN = GND to VCC TA = −40°C to +85°C 1 mA

TA = −40°C to +125°C 2

ILO Output Leakage

Current

VOUT = GND to VCC,

CS = GND

TA = −40°C to +85°C 1 mA

TA = −40°C to +125°C 2

VIL1 Input Low Voltage 4.5 V v VCC < 5.5 V −0.1 0.8 V

VIH1 Input High Voltage 4.5 V v VCC < 5.5 V 2 VCC + 1 V

VIL2 Input Low Voltage 1.8 V v VCC < 4.5 V 0 VCC x 0.2 V

VIH2 Input High Voltage 1.8 V v VCC < 4.5 V VCC x 0.7 VCC + 1 V

VOL1 Output Low Voltage 4.5 V v VCC < 5.5 V,

IOL = 2.1 mA

0.4 V

VOH1 Output High Voltage 4.5 V v VCC < 5.5 V,

IOH = −400 mA

2.4 V

VOL2 Output Low Voltage 1.8 V v VCC < 4.5 V,

IOL = 1 mA

0.2 V

VOH2 Output High Voltage 1.8 V v VCC < 4.5 V,

IOH = −100 mA

VCC − 0.2 V

CAT93C56, CAT93C57

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Table 4. D.C. OPERATING CHARACTERISTICS, CAT93C56/57, Die Rev. E – Mature Product (CAT93C56, Rev. E –

NOT RECOMMENDED FOR NEW DESIGNS) (VCC = +1.8 V to +5.5 V, TA=−40°C to +125°C unless otherwise specified.)

Symbol Parameter Test Conditions Min Max Units

ICC1 Power Supply Current (Write) fSK = 1 MHz, VCC = 5.0 V 3 mA

ICC2 Power Supply Current (Read) fSK = 1 MHz, VCC = 5.0 V 500 mA

ISB1 Power Supply Current (Standby)

(x8 Mode)

VIN = GND or VCC, CS = GND

ORG = GND

10 mA

ISB2 Power Supply Current (Standby)

(x16 Mode)

VIN = GND or VCC, CS = GND

ORG = Float or VCC

10 mA

ILI Input Leakage Current VIN = GND to VCC 1mA

ILO Output Leakage Current VOUT = GND to VCC, CS = GND 1mA

VIL1 Input Low Voltage 4.5 V v VCC < 5.5 V −0.1 0.8 V

VIH1 Input High Voltage 4.5 V v VCC < 5.5 V 2 VCC + 1 V

VIL2 Input Low Voltage 1.8 V v VCC < 4.5 V 0 VCC x 0.2 V

VIH2 Input High Voltage 1.8 V v VCC < 4.5 V VCC x 0.7 VCC + 1 V

VOL1 Output Low Voltage 4.5 V v VCC < 5.5 V, IOL = 2.1 mA 0.4 V

VOH1 Output High Voltage 4.5 V v VCC < 5.5 V, IOH = −400 mA2.4 V

VOL2 Output Low Voltage 1.8 V v VCC < 4.5 V, IOL = 1 mA 0.2 V

VOH2 Output High Voltage 1.8 V v VCC < 4.5 V, IOH = −100 mAVCC − 0.2 V

Table 5. PIN CAPACITANCE (TA = 25°C, f = 1 MHz, VCC = 5 V)

Symbol Test Conditions Min Typ Max Units

COUT (Note 4) Output Capacitance (DO) VOUT = 0 V 5 pF

CIN (Note 4) Input Capacitance (CS, SK, DI, ORG) VIN = 0 V 5 pF

4. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100

and JEDEC test methods.

CAT93C56, CAT93C57

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Table 6. A.C. CHARACTERISTICS (Note 5), CAT93C56, Die Rev. G – New Product

(VCC = +1.8V to +5.5V, TA = −40°C to +125°C, unless otherwise specified.)

Symbol Parameter

Limits

Units

Min Max

tCSS CS Setup Time 50 ns

tCSH CS Hold Time 0 ns

tDIS DI Setup Time 100 ns

tDIH DI Hold Time 100 ns

tPD1 Output Delay to 1 0.25 ms

tPD0 Output Delay to 0 0.25 ms

tHZ (Note 6) Output Delay to High−Z 100 ns

tEW Program/Erase Pulse Width 5 ms

tCSMIN Minimum CS Low Time 0.25 ms

tSKHI Minimum SK High Time 0.25 ms

tSKLOW Minimum SK Low Time 0.25 ms

tSV Output Delay to Status Valid 0.25 ms

SKMAX Maximum Clock Frequency DC 2000 kHz

Table 7. A.C. CHARACTERISTICS (Note 5), CAT93C56/57, Die Rev. E – Mature Product

(CAT93C56 Rev. E − NOT RECOMMENDED FOR NEW DESIGNS)

Symbol Parameter

Limits

Units

VCC = 1.8 V − 5.5 V VCC = 2.5 V − 5.5 V VCC = 4.5 V − 5.5 V

Min Max Min Max Min Max

tCSS CS Setup Time 200 100 50 ns

tCSH CS Hold Time 0 0 0 ns

tDIS DI Setup Time 400 200 100 ns

tDIH DI Hold Time 400 200 100 ns

tPD1 Output Delay to 1 1 0.5 0.25 ms

tPD0 Output Delay to 0 1 0.5 0.25 ms

tHZ

(Note 6)

Output Delay to High−Z 400 200 100 ns

tEW Program/Erase Pulse Width 10 10 10 ms

tCSMIN Minimum CS Low Time 1 0.5 0.25 ms

tSKHI Minimum SK High Time 1 0.5 0.25 ms

tSKLOW Minimum SK Low Time 1 0.5 0.25 ms

tSV Output Delay to Status Valid 1 0.5 0.25 ms

SKMAX Maximum Clock Frequency DC 250 DC 500 DC 1000 kHz

Table 8. POWER−UP TIMING (Notes 6 and 7)

Symbol Parameter Max Units

tPUR Power−up to Read Operation 1 ms

tPUW Power−up to Write Operation 1 ms

5. Test conditions according to “A.C. Test Conditions” table.

6. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate

AEC−Q100 and JEDEC test methods.

7. tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated.

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Table 9. A.C. TEST CONDITIONS

Input Rise and Fall Times ≤ 50 ns

Input Pulse Voltages 0.4 V to 2.4 V 4.5 V v VCC v 5.5 V

Timing Reference Voltages 0.8 V, 2.0 V 4.5 V v VCC v 5.5 V

Input Pulse Voltages 0.2 VCC to 0.7 VCC 1.8 V v VCC v 4.5 V

Timing Reference Voltages 0.5 VCC 1.8 V v VCC v 4.5 V

Output Load Current Source IOLmax/IOHmax; CL=100 pF

Device Operation

The CAT93C56/57 is a 2048−bit nonvolatile memory

intended for use with industry standard microprocessors.

The CAT93C56/57 can be organized as either registers of 16

bits or 8 bits. When organized as X16, seven 10−bit

instructions for 93C57 or seven 11−bit instructions for

93C56 control the reading, writing and erase operations of

the device. When organized as X8, seven 11−bit instructions

for 93C57 or seven 12−bit instructions for 93C56 control the

reading, writing and erase operations of the device. The

CAT93C56/57 operates on a single power supply and will

generate on chip, the high voltage required during any write

operation.

Instructions, addresses, and write data are clocked into the

DI pin on the rising edge of the clock (SK). The DO pin is

normally in a high impedance state except when reading data

from the device, or when checking the ready/busy status

after a write operation. The serial communication protocol

follows the timing shown in Figure 2.

The ready/busy status can be determined after the start of

internal write cycle by selecting the device (CS high) and

polling the DO pin; DO low indicates that the write

operation is not completed, while DO high indicates that the

device is ready for the next instruction. If necessary, the DO

pin may be placed back into a high impedance state during

chip select by shifting a dummy “1” into the DI pin. The DO

pin will enter the high impedance state on the rising edge of

the clock (SK). Placing the DO pin into the high impedance

state is recommended in applications where the DI pin and

the DO pin are to be tied together to form a common DI/O

pin.

VALID VALID

DATA VALID

Figure 2. Synchronous Data Timing

tCSS

tSKHI tSKLOW

tDIS

tDIH

tCSH

tCSMN

tPD0, tPD1

CAT93C56, CAT93C57

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The format for all instructions sent to the device is a

logical “1” start bit, a 2−bit (or 4−bit) opcode, 7−bit address

(CAT93C57) / 8−bit address (CAT93C56) (an additional bit

when organized X8) and for write operations a 16−bit data

field (8−bit for X8 organizations). The instruction format is

shown in Instruction Set table.

Table 10. INSTRUCTION SET

Instruction Device Type

Start

Bit Opcode

Address Data

Comments

x8 x16 x8 x16

READ 93C56 (Note 8) 1 10 A8−A0 A7−A0 Read Address

AN–A0

93C57 1 10 A7−A0 A6−A0

ERASE 93C56 (Note 8) 111 A8−A0 A7−A0 Clear Address

AN–A0

93C57 1 11 A7−A0 A6−A0

WRITE 93C56 (Note 8) 1 01 A8−A0 A7−A0 D7−D0 D15−D0 Write Address

AN–A0

93C57 1 01 A7−A0 A6−A0 D7−D0 D15−D0

EWEN 93C56 (Note 8) 1 00 11XXXXXXX 11XXXXXX Write Enable

93C57 1 00 11XXXXXX 11XXXXX

EWDS 93C56 (Note 8) 1 00 00XXXXXXX 00XXXXXX Write Disable

93C57 1 00 00XXXXXX 00XXXXX

ERAL 93C56 (Note 8) 1 00 10XXXXXXX 10XXXXXX Clear All

Addresses

93C57 1 00 10XXXXXX 10XXXXX

WRAL 93C56 (Note 8) 1 00 01XXXXXXX 01XXXXXX D7−D0 D15−D0 Write All

Addresses

93C57 1 00 01XXXXXX 01XXXXX D7−D0 D15−D0

8. Address bit A8 for 256x8 organization and A7 for 128x16 organization are “Don’t Care” bits, but must be kept at either a “1” or “0” for READ,

WRITE and ERASE commands.

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Read

Upon receiving a READ command and an address

(clocked into the DI pin), the DO pin of the CAT93C56/57

will come out of the high impedance state and, after sending

an initial dummy zero bit, will begin shifting out the data

addressed (MSB first). The output data bits will toggle on

the rising edge of the SK clock and are stable after the

specified time delay (tPD0 or tPD1).

For the CAT93C56/57, after the initial data word has been

shifted out and CS remains asserted with the SK clock

continuing to toggle, the device will automatically

increment to the next address and shift out the next data word

in a sequential READ mode. As long as CS is continuously

asserted and SK continues to toggle, the device will keep

incrementing to the next address automatically until it

reaches to the end of the address space, then loops back to

address 0. In the sequential READ mode, only the initial

data word is preceeded by a dummy zero bit. All subsequent

data words will follow without a dummy zero bit. The

READ instruction timing is illustrated in Figure 3.

Erase/Write Enable and Disable

The CAT93C56/57 powers up in the write disable state.

Any writing after power−up or after an EWDS (erase/write

disable) instruction must first be preceded by the EWEN

(erase/write enable) instruction. Once the write instruction

is enabled, it will remain enabled until power to the device

is removed, or the EWDS instruction is sent. The EWDS

instruction can be used to disable all CAT93C56/57 write

and erase instructions, and will prevent any accidental

writing or clearing of the device. Data can be read normally

from the device regardless of the write enable/disable status.

The EWEN and EWDS instructions timing is shown in

Figure 4.

DO HIGH−Z

11 0

Dummy 0 Address + 1 Address + 2 Address + n

Don’t Care

Figure 3. READ Instruction Timing

ANAN−1A0

tPD0

D15 . . .

D7 . . .

D15 . . . D0

D7 . . . D0

D15 . . . D0

D7 . . . D0

D15 . . . D0

D7 . . . D0

STANDBY

* ENABLE = 11

DISABLE = 00

Figure 4. EWEN/EWDS Instruction Timing

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Write

After receiving a WRITE command (Figure 5), address

and the data, the CS (Chip Select) pin must be deselected for

a minimum of tCSMIN. The falling edge of CS will start the

self clocking clear and data store cycle of the memory

location specified in the instruction. The clocking of the SK

pin is not necessary after the device has entered the self

clocking mode. The ready/busy status of the CAT93C56/57

can be determined by selecting the device and polling the

DO pin. Since this device features Auto−Clear before write,

it is NOT necessary to erase a memory location before it is

written into.

Erase

Upon receiving an ERASE command and address, the CS

(Chip Select) pin must be deasserted for a minimum of

tCSMIN (Figure 6). The falling edge of CS will start the self

clocking clear cycle of the selected memory location. The

clocking of the SaK pin is not necessary after the device has

entered the self clocking mode. The ready/busy status of the

CAT93C56/57 can be determined by selecting the device

and polling the DO pin. Once cleared, the content of a

cleared location returns to a logical “1” state.

STANDBY

HIGH−Z

101

BUSY

READY

STATUS

VERIFY

Figure 5. Write Instruction Timing

ANAN−1A0DND0

tCSMIN

tHZ

tSV

tEW

STANDBY

HIGH−Z

BUSY READY

STATUS VERIFY

Figure 6. Erase Instruction Timing

ANAN−1A0tCS

tSV tHZ

tEW

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Erase All

Upon receiving an ERAL command (Figure 7), the CS

(Chip Select) pin must be deselected for a minimum of

tCSMIN. The falling edge of CS will start the self clocking

clear cycle of all memory locations in the device. The

clocking of the SK pin is not necessary after the device has

entered the self clocking mode. The ready/busy status of the

CAT93C56/57 can be determined by selecting the device

and polling the DO pin. Once cleared, the contents of all

memory bits return to a logical “1” state.

Write All

Upon receiving a WRAL command and data, the CS

(Chip Select) pin must be deselected for a minimum of

tCSMIN (Figure 8). The falling edge of CS will start the self

clocking data write to all memory locations in the device.

The clocking of the SK pin is not necessary after the device

has entered the self clocking mode. The ready/busy status of

the CAT93C56/57 can be determined by selecting the device

and polling the DO pin. It is not necessary for all memory

locations to be cleared before the WRAL command is

executed.

STANDBY

HIGH−Z

10 1

BUSY READY

STATUS VERIFY

Figure 7. ERAL Instruction Timing

tCS

tHZ

tSV

tEW

STATUS VERIFY

STANDBY

HIGH−Z

10 1

BUSY READY

Figure 8. WRAL Instruction Timing

DND0

tCSMIN

tSV tHZ

tEW

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PACKAGE DIMENSIONS

PDIP−8, 300 mils

CASE 646AA−01

ISSUE A

TOP VIEW

SIDE VIEW END VIEW

PIN # 1

IDENTIFICATION

Notes:

(1) All dimensions are in millimeters.

(2) Complies with JEDEC MS-001.

SYMBOL MIN NOM MAX

0.38

2.92

0.36

6.10

1.14

0.20

9.02

2.54 BSC

3.30

5.33

4.95

0.56

7.11

1.78

0.36

10.16

eB 7.87 10.92

E 7.62 8.25

2.92 3.80

3.30

0.46

6.35

1.52

0.25

9.27

7.87

CAT93C56, CAT93C57

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PACKAGE DIMENSIONS

SOIC 8, 150 mils

CASE 751BD−01

ISSUE O

E1 E

PIN # 1

IDENTIFICATION

TOP VIEW

SIDE VIEW END VIEW

Notes:

(1) All dimensions are in millimeters. Angles in degrees.

(2) Complies with JEDEC MS-012.

SYMBOL MIN NOM MAX

0º 8º

0.10

0.33

0.19

0.25

4.80

5.80

3.80

1.27 BSC

1.75

0.25

0.51

0.25

0.50

5.00

6.20

4.00

L0.40 1.27

1.35

CAT93C56, CAT93C57

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PACKAGE DIMENSIONS

SOIC−8, 208 mils

CASE 751BE−01

ISSUE O

SIDE VIEW

TOP VIEW

PIN#1 IDENTIFICATION

END VIEW

Notes:

(1) All dimensions are in millimeters. Angles in degrees.

(2) Complies with EIAJ EDR-7320.

SYMBOL MIN NOM MAX

0º 8º

0.05

0.36

0.19

5.13

7.75

5.13

1.27 BSC

2.03

0.25

0.48

0.25

5.33

8.26

5.38

L0.51 0.76

CAT93C56, CAT93C57

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PACKAGE DIMENSIONS

TSSOP8, 4.4x3

CASE 948AL−01

ISSUE O

E1 E

TOP VIEW

SIDE VIEW END VIEW

L1 L

Notes:

(1) All dimensions are in millimeters. Angles in degrees.

(2) Complies with JEDEC MO-153.

SYMBOL

MIN NOM MAX

0º 8º

0.05

0.80

0.19

0.09

0.50

2.90

6.30

4.30

0.65 BSC

1.00 REF

1.20

0.15

1.05

0.30

0.20

0.75

3.10

6.50

4.50

0.90

0.60

3.00

6.40

4.40

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PACKAGE DIMENSIONS

TDFN8, 2x3

CASE 511AK−01

ISSUE A

PIN#1

IDENTIFICATION

ebD

TOP VIEW SIDE VIEW BOTTOM VIEW

PIN#1 INDEX AREA

FRONT VIEW

Notes:

(1) All dimensions are in millimeters.

(2) Complies with JEDEC MO-229.

SYMBOL MIN NOM MAX

A 0.70 0.75 0.80

A1 0.00 0.02 0.05

A3 0.20 REF

b 0.20 0.25 0.30

D 1.90 2.00 2.10

D2 1.30 1.40 1.50

E 3.00

E2 1.20 1.30 1.40

2.90

0.50 TYP

3.10

L 0.20 0.30 0.40

A2 0.45 0.55 0.65

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PACKAGE DIMENSIONS

TDFN8, 3x3

CASE 511AL−01

ISSUE A

SIDE VIEW BOTTOM VIEW

TOP VIEW

PIN#1 INDEX AREA

PIN#1 ID

FRONT VIEW

Notes:

(1) All dimensions are in millimeters.

(2) Complies with JEDEC MO-229.

SYMBOL MIN NOM MAX

A 0.70 0.75 0.80

A1 0.00 0.02 0.05

A3 0.20 REF

b 0.23 0.30 0.37

D 2.90 3.00 3.10

D2 2.20 −−− 2.50

E 3.00

E2 1.40 −−− 1.80

2.90

0.65 TYP

3.10

L 0.20 0.30 0.40

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Example of Ordering Information

CAT93C56, Die Rev. G, New Product

Prefix Device # Suffix

Company ID

CAT 93C56 V

Product Number

93C56

I− GT3

Package

I = Industrial (−40°C to +85°C)

E = Extended (−40°C to +125°C)

Temperature Range

L: PDIP

V: SOIC, JEDEC

X: SOIC, EIAJ (Note 14)

Y: TSSOP

VP2: TDFN (2 x 3 mm)

Lead Finish

G: NiPdAu

Blank: Matte−Tin

T: Tape & Reel

2: 2,000 Units / Reel (Note 14)

3: 3,000 Units / Reel

Tape & Reel (Note 16)

9. The device used in the above example is a CAT93C56VI−GT3 (SOIC, Industrial Temperature, NiPdAu, Tape & Reel).

CAT93C56/57, Die Rev. E, Mature Product

(CAT93C56, Rev. E − Not Recommended for New Designs)

Prefix Device # Suffix

Company ID

CAT 93C56 V

Product Number

93C56

I− G

Package

I = Industrial (−40°C to +85°C)

A = Automotive (−40°C to +105°C)

E = Extended (−40°C to +125°C)

Temperature Range

L: PDIP

V: SOIC, JEDEC

W: SOIC, JEDEC

X: SOIC, EIAJ (Note 14)

Y: TSSOP

ZD4: TDFN (3 x 3 mm)

Lead Finish

G: NiPdAu

Blank: Matte−Tin

Die Revision

93C56: E

93C57: E

93C57

−1.8

Operating Voltage

Blank: VCC = 2.5 V to 5.5 V

1.8: VCC = 1.8 V to 5.5 V

T: Tape & Reel

2: 2,000 Units / Reel (Note 14)

3: 3,000 Units / Reel

Rev E (Note 13)

Tape & Reel (Note 16)

10.All packages are RoHS−compliant (Lead−free, Halogen−free).

11. The standard lead finish is NiPdAu.

12.The device used in the above example is a CAT93C56VI−1.8−GT3 (SOIC green package, Industrial Temperature, 1.8 Volt to 5.5 Volt

Operating Voltage, NiPdAu finish, Tape & Reel).

13.Product die revision letter is marked on top of the package as a suffix to the production date code (e.g., AYWWE). For additional information,

please contact your ON Semiconductor sales office.

14.For SOIC, EIAJ (X) package the standard lead finish is Matte−Tin. This package is available in 2,000 pcs/reel, i.e. CAT93C56XI−T2.

15.For additional package and temperature options, please contact your nearest ON Semiconductor sales office.

16.For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

CAT93C56, CAT93C57

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CAT93C56/D

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