1. Product profile
1.1 General description
The BGA7351 MMIC is a dual independently digitally controlled IF Variable Gain
Amplifier (VGA) operating from 50 MHz to 500 MHz. Each IF VGA amplifies with a gain
range of 28 dB and at its maximum gain setting delivers 16.5 dBm output power at 1 dB
gain compressio n an d a su pe rio r line ar per fo rm a nc e.
The BGA7351 Dual IF VGA is optimized for a differential gain error of less than 0.1 dB
for accurate gain control and has a total integrated gain error of less than 0.3 dB.
Moreover it meets the demanding phase error requirements for GSM. BGA7351 has less
than 3.0 phase error over the full gain range of 28 dB.
The gain controls of each amplifier are separate digital gain-control word, which is
provided externally through two sets of 5 bits.
The BGA7351 is housed in a 32 pins 5 mm 5 mm leadless HVQFN32 package.
1.2 Features and benefits
Dual independent digitally controlled 28 dB gain range VGAs, with 5-bit control
interface
50 MHz to 500 MHz frequency operating range
Gain step size: 1 dB 0. 1 dB
22 dB power gain
Fast gain stage switching capability
16.5 dBm output po we r at 1 dB ga in comp r ess ion
46 dBm third orde r int er ce pt poin t
Constant third order intercept point over output power
85 dBc second harmonic level
Excellent noise figure of 6 dB
5 V single supply operation with power-down control
Logic-level shutdown control pin reduces supply current
Excellent ESD protectio n at all pins
Moisture sensitivity level 1
Unconditionally stable
Excellent differential integrated gain and phase error
Compliant to Directive 2002/95/EC, rega rd in g Re stri ctio n of Hazard ou s Sub stances
(RoHS)
BGA7351
50 MHz to 500 MHz high linearity Si variable gain amplifier;
28 dB gain range
Rev. 3 — 11 June 2014 Product data sheet
+94)1
BGA7351 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 3 — 11 June 2014 2 of 28
NXP Semiconductors BGA7351
50 MHz to 500 MHz high linearity Si variable gain amplifier
1.3 Applications
Compatible with GSM / W-CDMA / WiMAX / LTE base-station infrast ructure / multi
carrier systems
Multi channel receivers
General use for ADC driver applications
1.4 Quick reference data
[1] Maximum gain; gain code = 00000.
[2] Minimum gain; gain code = 11100.
[3] PL = 2 dBm per tone; spacing = 2 MHz (f1 = 171 MHz; f2 = 173 MHz)
[4] Gain code = 01110.
[5] Gain code = 00000, 00001, 00010, 00011, 00100.
[6] PL = 2 dBm one tone (f = 86 MHz; fmeas = 172 MHz)
Table 1. Quick reference data
A_EN = "1"; B_EN = "1" (VGA enabled). Typical values at VCC =5V; I
CC =280mA;
Tuned for fIF = 172 MHz; B = 60 MHz; Tcase =25
C; Differential input resistance matched to 150
;
Differential output resistance matched to 200
; unless otherwise specified; see Section 11
Application information.
Symbol Parameter Conditions Min Typ Max Unit
VCC supply voltage VCC(A) + VCC(B) 4.75 5 5.25 V
ICC supply current ICC(A) + ICC(B)
A_EN = "0"; B_EN = "0" - 3 5 mA
A_EN = "1"; B_EN = "1" - 280 300 mA
Gppower gain maximum gain [1] 21 22 23 dB
minimum gain [2] 765dB
Ri(dif) differential input
resistance 120 150 180
Ro(dif) diff erential output
resistance 140 180 220
NF noise figure maximum gain [1] -67dB
increased rate per gain step - 0.8 1 dB
IP3Ooutput third-order
intercept point gain step 14 [3][4] -46-dBm
PL(1dB) output power at 1 dB
gain compression upper 5 gain steps [1][5] -16.5-dBm
2H second harmonic level gain step 14 [4][6] -85 - dBc
EG(dif) differential gain error - 0.1 - dB
E(dif) differential phase error upper 12 dB gain range - 1.0 - deg
per gain step (for all
consecutive gain steps) -0.5-deg
BGA7351 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 3 — 11 June 2014 3 of 28
NXP Semiconductors BGA7351
50 MHz to 500 MHz high linearity Si variable gain amplifier
2. Pinning information
2.1 Pinning
2.2 Pin description
Fig 1. Pin configuration SOT 61 7 -1
aaa-001979
BGA7351
Transparent top view
B_OUT_P
B_D3
B_D2
B_OUT_N
B_D4 B_EN
n.c. GNDB
n.c. GNDA
A_D4 A_EN
A_D3 A_OUT_N
A_D2 A_OUT_P
B_D1
B_D0
B_IN_P
B_IN_N
GNDB
V
CCB
B_OUT_P
B_OUT_N
A_D1
A_D0
A_IN_P
A_IN_N
GNDA
V
CCA
A_OUT_P
A_OUT_N
817
718
619
520
421
322
223
124
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
terminal 1
index area
Table 2. Pin descripti on
Symbol Pin Description
A_D2 1 MSB 2 for gain control interface of channel A
A_D3 2 MSB 1 for gain control interface of channel A
A_D4 3 MSB for gain control interface of channel A
n.c. 4 not connected [1]
n.c. 5 not connected [1]
B_D4 6 MSB for gain control interface of channel B
B_D3 7 MSB 1 for gain control interface of channel B
B_D2 8 MSB 2 for gain control interface of channel B
B_D1 9 LSB + 1 for gain control interface of channel B
B_D0 10 LSB for gain control interface of channel B
B_IN_P 11 channel B positive input [2]
B_IN_N 12 channel B negative input [2]
GNDB 13, 20 ground for channel B
VCCB 14 supply voltage for channel B
B_OUT_P 15, 17 channel B positive output [2]
B_OUT_N 16, 18 channel B negative output [2]
B_EN 19 power enable pin for channel B
GNDA 21, 28 ground for channel A
BGA7351 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 3 — 11 June 2014 4 of 28
NXP Semiconductors BGA7351
50 MHz to 500 MHz high linearity Si variable gain amplifier
[1] Pin to be left open.
[2] Each channel should be independently enabled with logic HIGH and disabled with logic LOW.
[3] The center metal base of the SOT617-1 also functions as heatsink for the VGA.
3. Ordering information
A_EN 22 power enable pin for channel A
A_OUT_N 23, 25 channel A negative output [2]
A_OUT_P 24, 26 channel A positive output [2]
VCCA 27 supply voltage for channel A
A_IN_N 29 channel A negative input [2]
A_IN_P 30 channel A positive input [2]
A_D0 31 LSB for gain control interface of channel A
A_D1 32 LSB + 1 for gain control interface of channel A
GND GND paddle RF ground and DC ground [3]
Table 2. Pin descripti on …continued
Symbol Pin Description
Table 3. Ordering information
Type number Package
Name Description Version
BGA7351 HVQFN32 plastic thermal enhanced very thin quad flat package;
no leads; 32 terminals; body 5 50.85 mm SOT617-1
BGA7351 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 3 — 11 June 2014 5 of 28
NXP Semiconductors BGA7351
50 MHz to 500 MHz high linearity Si variable gain amplifier
4. Functional diagram
5. Enable control
Fig 2. Functional diagram
*$,1
&21752/
5(*8/$725
5(*8/$725
*$,1
&21752/
%*$
$B28
7B1
$B28
7B3
9&&$
*1'
$
$B,1
B1
$B,1
B3
$B'
$B'%B'
%B'
%B'
%B'
%B
9&20
$B
9&20
$B'
$B'
$B'
$B28
7B3
$B28
7B1
287
287
287
287
,1
&0
,1
,1
&0
,1
*$,1
&21752/
*$,1
&21752/
9&&
(1
(1
9&&
9'' 9''
$B(1
*1'
$
*1'
%
%B(1
%B28
7B1
%B28
7B3
%B'
%B,1B3
%B,1B1
*1'%
9&&%
%B287B3
%B287B1
9&&
9&&
9''
9''
9((
9((
9((
9((
DDD
Table 4. Enable / disable control settings
Mode Function description Mode description Enable VEN (V) IEN (A)
A_EN B_EN Min Max Min Max
A_EN, B_EN VGA function off disable "0" "0" 0 0.8 - 1
A_EN, B_EN VGA in operating mode enable "1" "1" 1.6 5.25 - 1
BGA7351 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 3 — 11 June 2014 6 of 28
NXP Semiconductors BGA7351
50 MHz to 500 MHz high linearity Si variable gain amplifier
6. Limiting values
[1] Caution: All digital pins may not exceed VCC as the internal ESD circuit can be damaged. To prevent this it
is recommended that VAEN and VBEN are limited to a maximum of 5 mA.
7. Thermal characteristics
Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
VCC(A) supply voltage (A) [1] -6V
VCC(B) supply voltage (B) [1] -6V
VAEN voltage on pin A_EN 0.6 +6 V
VBEN voltage on pin B_EN 0.6 +6 V
VAD0 voltage on pin A_D0 0.6 +6 V
VAD1 voltage on pin A_D1 0.6 +6 V
VAD2 voltage on pin A_D2 0.6 +6 V
VAD3 voltage on pin A_D3 0.6 +6 V
VAD4 voltage on pin A_D4 0.6 +6 V
VBD0 voltage on pin B_D0 0.6 +6 V
VBD1 voltage on pin B_D1 0.6 +6 V
VBD2 voltage on pin B_D2 0.6 +6 V
VBD3 voltage on pin B_D3 0.6 +6 V
VBD4 voltage on pin B_D4 0.6 +6 V
VAIN voltage on pin A_IN 0.6 +6 V
VBIN voltage on pin B_IN 0.6 +6 V
Pi(RF) RF input power - 20 dBm
Tcase case temperature 40 +85 C
Tjjunction temperature - 150 C
VESD electrostatic discharge
voltage Human Body Model (HBM);
According JEDEC standard 22-A114E - 4000 V
Charged Device Model (CDM);
According JEDEC standard 22-C101B - 2000 V
Machine Model (MM);
According JEDEC standard 22-A115 - 400 V
Table 6. Thermal characteristics
Symbol Parameter Conditions Typ Unit
Rth(j-case) thermal resistance from junction to case Tcase =85C; VCC =5V;
ICC = 280 mA 7K/W
BGA7351 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 3 — 11 June 2014 7 of 28
NXP Semiconductors BGA7351
50 MHz to 500 MHz high linearity Si variable gain amplifier
8. Static characteristics
[1] Voltage on the control pins.
9. Dynamic characteristics
Table 7. Characteristics
A_EN = "1"; B_EN = "1" (both channels enabled). Typical values at VCC =5V; T
case =25
C;
unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
VCC supply voltage VCC(A) + VCC(B) 4.75 5 5.25 V
ICC supply current ICC(A) + ICC(B)
A_EN = "0"; B_EN = "0" - 3 5 mA
A_EN = "1"; B_EN = "1" - 280 300 mA
VIH HIGH-level input voltage [1] 1.6 - 5.25 V
VIL LOW-level input voltage [1] --0.8V
P power dissipation - 1.4 1.6 W
Table 8. Characteristics
A_EN = "1"; B_EN = "1" (VGA enabled). Typical values at VCC =5V; I
CC =280mA;
Tuned for fIF = 172 MHz; B = 60 MHz; Tcase =25
C; Differential input resistance matched to 150
;
Differential output resistance matched to 200
; unless otherwise specified; see Section 11
Application information.
Symbol Parameter Conditions Min Typ Max Unit
Gppower gain maximum gain [1]
f = 50 MHz; B = 30 MHz - 22.5 - dB
f = 172 MHz; B = 60 MHz 21 22 23 dB
f = 250 MHz; B = 60 MHz - 21.5 - dB
f = 450 MHz; B = 100 MHz - 21.5 - dB
minimum gain [2]
f = 50 MHz; B = 30 MHz - 5.5 - dB
f = 172 MHz; B = 60 MHz 765dB
f = 250 MHz; B = 60 MHz - 6.5 - dB
f = 450 MHz; B = 100 MHz - 8-dB
Gadj gain adjustment range [1] -28- dB
Gstep gain step - 1 -
Gflat gain flatness [1] - 0.5 - dB
EG(dif) differential gain error - 0.1 - d B
EG(itg) integrated gain error upper 12 dB gain range - 0.2 - dB
full gain range - 0.3 - d B
E(dif) differential phase error upper 12 dB gain range - 1.0 - deg
per gain step (for all
consecutive gain steps) -0.5- deg
full gain range - 3.0 - deg
ts(step)G gain step settling time per 1.5 dB of steady state - 5 15 ns
per 0.1 dB of steady state - 20 40 ns
BGA7351 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 3 — 11 June 2014 8 of 28
NXP Semiconductors BGA7351
50 MHz to 500 MHz high linearity Si variable gain amplifier
td(grp) group delay time
variation B = 30 MHz - 86 - ps
tpu power-up ti me - - 1 s
Ri(dif) differential input
resistance 120 150 180
Ro(dif) dif ferential output
resistance 140 180 220
isol(ch-ch) isolation between
channels f 250 MHz 50 - - dB
250 MHz < f < 400 MHz 47 - - dB
400 MHz f 500 MHz 45 - - dB
CMRR common-mode
rejection ratio 40 - - dB
IP3Ooutput third-order
intercept point gain step 14 [3]
f=50MHz [4] -47- dBm
f = 172 MHz [5] -46- dBm
f = 250 MHz [6] -41- dBm
f = 450 MHz [7] -34- dBm
upper 5 gain steps [8]
f=50MHz [4] -48- dBm
f = 172 MHz [5] -44- dBm
f = 250 MHz [6] -41- dBm
f = 450 MHz [7] -33- dBm
IP2Ooutput second-order
intercept point upper 5 gain steps [8]
f=50MHz [9] -78- dBm
f = 172 MHz [10] -73- dBm
f = 250 MHz [11] -65- dBm
PL(1dB) output power at 1 dB
gain compression upper 5 gain steps [8]
f = 50 MHz - 16.8 - dBm
f = 172 MHz - 16.5 - dBm
f = 250 MHz - 15.8 - dBm
f = 450 MHz - 15.1 - dBm
Table 8. Characteristics …continued
A_EN = "1"; B_EN = "1" (VGA enabled). Typical values at VCC =5V; I
CC =280mA;
Tuned for fIF = 172 MHz; B = 60 MHz; Tcase =25
C; Differential input resistance matched to 150
;
Differential output resistance matched to 200
; unless otherwise specified; see Section 11
Application information.
Symbol Parameter Conditions Min Typ Max Unit
BGA7351 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 3 — 11 June 2014 9 of 28
NXP Semiconductors BGA7351
50 MHz to 500 MHz high linearity Si variable gain amplifier
[1] Maximum gain; gain code = 00000.
[2] Minimum gain; gain code = 11100.
[3] Gain code = 01110.
[4] PL = 2 dBm per tone; spacing = 2 MHz (f1 = 49 MHz; f2 = 51 MHz)
[5] PL = 2 dBm per tone; spacing = 2 MHz (f1 = 171 MHz; f2 = 173 MHz)
[6] PL = 2 dBm per tone; spacing = 2 MHz (f1 = 249 MHz; f2 = 251 MHz)
[7] PL = 2 dBm per tone; spacing = 2 MHz (f1 = 449 MHz; f2 = 451 MHz)
[8] Gain code = 00000, 00001, 00010, 00011, 00100.
[9] PL = 2 dBm per tone (f1 = 24 MHz; f2 = 74 MHz; fmeas = 50 MHz)
[10] PL = 2 dBm per tone (f1 = 82 MHz; f2 = 90 MHz; fmeas = 172 MHz)
[11] PL = 2 dBm per tone (f1 = 120 MHz; f2 = 130 MHz; fmeas = 250 MHz)
[12] PL = 2 dBm one tone (f = 86 MHz; fmeas = 172 MHz)
[13] PL = 5 dBm one tone (f = 86 MHz; fmeas = 172 MHz)
[14] PL = 2 dBm one tone (f = 225 MHz; fmeas = 450 MHz)
[15] PL = 5 dBm one tone (f = 225 MHz; fmeas = 450 MHz)
2H second harmonic level gain step 14 [3]
PL = 2 dBm, f = 172 MHz [12] -85 - dBc
PL = 5 dBm, f = 172 MHz [13] -82 - dBc
PL = 2 dBm, f = 450 MHz [14] -67 - dBc
PL = 5 dBm, f = 450 MHz [15] -64 - dBc
upper 5 gain steps [8]
PL = 2 dBm, f = 172 MHz [12] -83 - dBc
PL = 5 dBm, f = 172 MHz [13] -80 - dBc
PL = 2 dBm, f = 450 MHz [14] -59 - dBc
PL = 5 dBm, f = 450 MHz [15] -54 - dBc
NF noise figure maximum gain [1] -6 7dB
increase rate per gain step - 0.8 1 dB
Table 8. Characteristics …continued
A_EN = "1"; B_EN = "1" (VGA enabled). Typical values at VCC =5V; I
CC =280mA;
Tuned for fIF = 172 MHz; B = 60 MHz; Tcase =25
C; Differential input resistance matched to 150
;
Differential output resistance matched to 200
; unless otherwise specified; see Section 11
Application information.
Symbol Parameter Conditions Min Typ Max Unit
BGA7351 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 3 — 11 June 2014 10 of 28
NXP Semiconductors BGA7351
50 MHz to 500 MHz high linearity Si variable gain amplifier
10. Moisture sensitivity
Table 9. Gain control
gain step input to either A_D0 to A_D4 pins
or B_D0 to B_D4 pins nominal power gain (dB)
0 00000 22
1 00001 21
2 00010 20
3 00011 19
4 00100 18
5 00101 17
6 00110 16
7 00111 15
8 01000 14
9 01001 13
10 01010 12
11 01011 11
12 01100 10
13 01101 9
14 01110 8
15 01111 7
16 10000 6
17 10001 5
18 10010 4
19 10011 3
20 10100 2
21 10101 1
22 10110 0
23 10111 1
24 11000 2
25 11001 3
26 11010 4
27 11011 5
28 11100 6
- > 11100 6
Table 10. Moisture sensitivity leve l
Test methodology Class
JESD-22-A113 1
BGA7351 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 3 — 11 June 2014 11 of 28
NXP Semiconductors BGA7351
50 MHz to 500 MHz high linearity Si variable gain amplifier
11. Application information
(1) VO
(2) Ven
(1) VO
(2) Ven
Fig 3. Enable time response Fig 4. Gain step response from min. to max. gain
Tuned for fIF = 50 MHz; measured at gain step 0
(maximum gain). Tuned for fIF = 172 MHz; measured at gain step 0
(maximum gain).
Fig 5. S11 as a function of frequency Fig 6. S11 as a function of frequency
aaa-001981
t (ns)
0 1208040
-0.1
0.1
-0.3
0.3
0.5
Vo
(V)
-0.5
0.8
1.2
0.4
1.6
2.0
Ven
(V)
0
(2) (1)
aaa-001982
t (ns)
0 1208040
-0.1
0.1
-0.3
0.3
0.5
Vo
(V)
-0.5
0.8
1.2
0.4
1.6
2.0
Ven
(V)
0
(1)(2)
f (MHz)
20 806040
aaa-001986
0
mag S11
(dB)
phase S11
(deg)
-60
150
-30
0
30
60
90
120
-50
-40
-30
-20
-10
mag S11
phase S11
f (MHz)
100 240120 220140 160 200180
aaa-001987
0
mag S11
(dB)
phase S11
(deg)
-60
150
-30
0
30
60
90
120
-50
-40
-30
-20
-10
mag S11
phase S11
BGA7351 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 3 — 11 June 2014 12 of 28
NXP Semiconductors BGA7351
50 MHz to 500 MHz high linearity Si variable gain amplifier
Tuned for fIF = 50 MHz; PL = 5 dBm; step size 1 dB.
(1) gain step 0 (maximum gain)
(29) gain step 28 (minimum gain)
Tuned for fIF = 172 MHz; PL = 5 dBm; step size 1 dB.
(1) gain step 0 (maximum gain)
(29) gain step 28 (minimum gain)
Fig 7. Power gai n as a function of frequency Fig 8. Power gain as a function of frequency
Tuned for fIF = 250 MHz; PL = 5 dBm; step size 1 dB.
(1) gain step 0 (maximum gain)
(29) gain step 28 (minimum gain)
Tuned for fIF = 450 MHz; PL = 5 dBm; step size 1 dB.
(1) gain step 0 (maximum gain)
(29) gain step 28 (minimum gain)
Fig 9. Power gai n as a function of frequency Fig 10. Power gain as a function of frequency
f (MHz)
20 806040
aaa-001983
25
Gp
(dB)
-10
20
15
10
5
0
-5
(1)
(29)
f (MHz)
100 180 240160140 200120 220
aaa-001984
25
Gp
(dB)
-10
20
15
10
5
0
-5
(1)
(29)
f (MHz)
180 260 320240220 280200 300
aaa-001985
25
Gp
(dB)
-10
20
15
10
5
0
-5
(1)
(29)
DDD
     




I0+]
*S
*S
G%G%G%


BGA7351 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 3 — 11 June 2014 13 of 28
NXP Semiconductors BGA7351
50 MHz to 500 MHz high linearity Si variable gain amplifier
Tuned for fIF = 250 MHz; measured at gain step 0
(maximum gain). Tuned for fIF = 450 MHz; measured at gain step 0
(maximum gain).
Fig 11. S11 as a function of frequency Fig 12. S11 as a function of frequency
Tuned for fIF = 50 MHz; measured at gain step 0
(maximum gain). Tuned for fIF = 172 MHz; measured at gain step 0
(maximum gain).
Fig 13. S12 as a function of frequency Fig 14. S12 as a function of frequency
f (MHz)
180 320200 300220 240 280260
aaa-001990
0
mag S11
(dB)
phase S11
(deg)
-60
150
-30
0
30
60
90
120
-50
-40
-30
-20
-10
mag S11
phase S11
DDD
       
 
 
 
 
 

I0+]
PDJ6PDJ6
PDJ6
G%G%G%
SKDVH6SKDVH6
SKDVH6
GHJGHJGHJ
PDJ6PDJ6
PDJ6
SKDVH6SKDVH6
SKDVH6
f (MHz)
20 40 60 80
aaa-001991
0
mag S12
(dB)
-60
-10
-20
-30
-40
-50
f (MHz)
100 140 180 220 240200160120
aaa-001992
0
mag S12
(dB)
-60
-10
-20
-30
-40
-50
BGA7351 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 3 — 11 June 2014 14 of 28
NXP Semiconductors BGA7351
50 MHz to 500 MHz high linearity Si variable gain amplifier
Tuned for fIF = 250 MHz; measured at gain step 0
(maximum gain). Tuned for fIF = 450 MHz; measured at gain step 0
(maximum gain).
Fig 15. S12 as a function of frequency Fig 16. S12 as a function of frequency
Tuned for fIF = 50 MHz. Tuned for fIF = 172 MHz.
(1) Tamb = 40 C
(2) Tamb = +25 C
(3) Tamb = +85 C
Fig 17. Differential gain error as a function of
gain step Fig 18. Differential gain error as a function of
gain step
f (MHz)
180 220 260 300 320280240200
aaa-001993
0
mag S12
(dB)
-60
-10
-20
-30
-40
-50
DDD
       






I0+]
PDJ6PDJ6
PDJ6
G%G%G%
Gstep
0102030
aaa-001995
0.5
EG(dif)
(dB)
-0.5
0.3
0.1
-0.1
-0.3
Gstep
0102030
aaa-001996
0.5
EG(dif)
(dB)
-0.5
0.3
0.1
-0.1
-0.3
(1)
(2)
(3)
BGA7351 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 3 — 11 June 2014 15 of 28
NXP Semiconductors BGA7351
50 MHz to 500 MHz high linearity Si variable gain amplifier
Tuned for fIF = 250 MHz. Tuned for fIF = 450 MHz.
Fig 19. Differential gain error as a function of
gain step Fig 20. Differential gain error as a function of
gain step
Tuned for fIF = 50 MHz. Tuned for fIF = 172 MHz.
(1) Tamb = 40 C
(2) Tamb = +25 C
(3) Tamb = +85 C
Fig 21. output power at 1 dB gain compression as a
function of gain step Fig 22. output power at 1 dB gain compression as a
function of gain step
Gstep
0102030
aaa-001997
0.5
EG(dif)
(dB)
-0.5
0.3
0.1
-0.1
-0.3
DDD
    






*VWHS
(*GLI*GLI
(*GLI
G%G%G%
Gstep (dB)
054231
aaa-001998
17
18
16
19
20
PL(1dB)
(dBm)
15
Gstep (dB)
054231
aaa-001999
17
18
16
19
20
PL(1dB)
(dBm)
15
(1) (2) (3)
BGA7351 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 3 — 11 June 2014 16 of 28
NXP Semiconductors BGA7351
50 MHz to 500 MHz high linearity Si variable gain amplifier
Tuned for fIF = 250 MHz. Tuned for fIF = 450 MHz.
Fig 23. output power at 1 dB gain compression as a
function of gain step Fig 24. output power at 1 dB gain compression as a
function of gain step
Gstep (dB)
054231
aaa-002000
17
18
16
19
20
PL(1dB)
(dBm)
15
DDD






*VWHS
3/G%/G%
3/G%
G%PG%PG%P
Tuned for fIF = 172 MHz; measured at gain step 0 (maximum gain).
(1) Tamb = 40 C
(2) Tamb = +25 C
(3) Tamb = +85 C
Fig 25. Output third order intercept point as a func tion of output power per tone
PL (dBm) per tone
-2 3201-1
aaa-002001
55
50
45
40
IP3o
(dBm)
35
(1)
(2)
(3)
BGA7351 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 3 — 11 June 2014 17 of 28
NXP Semiconductors BGA7351
50 MHz to 500 MHz high linearity Si variable gain amplifier
Tuned for fIF = 50 MHz.
(1) gain step 0
(2) gain step 14
Tuned for fIF = 172 MHz.
(1) gain step 0
(2) gain step 14
Fig 26. Output third order intercept point as a f unction
of output power per tone Fig 27. Output third ord er intercept point as a function
of output power per tone
Tuned for fIF = 250 MHz.
(1) gain step 0
(2) gain step 14
Tuned for fIF = 450 MHz.
(1) gain step 0
(2) gain step 14
Fig 28. Output third order intercept point as a f unction
of output power per tone Fig 29. Output third ord er intercept point as a function
of output power per tone
PL (dBm) per tone
-4 6402-2
aaa-002002
55
45
35
25
IP3o
(dBm)
15
(2)
(1)
PL (dBm) per tone
-4 6402-2
aaa-002003
55
45
35
25
IP3o
(dBm)
15
(1)
(2)
PL (dBm) per tone
-4 6402-2
aaa-002004
55
45
35
25
IP3o
(dBm)
15
(2)
(1)
DDD
 





3/SHUWRQHG%P
,3,3R
,3R
G%PG%PG%P


BGA7351 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 3 — 11 June 2014 18 of 28
NXP Semiconductors BGA7351
50 MHz to 500 MHz high linearity Si variable gain amplifier
Tuned for fIF = 86 MHz; f2H = 172 MHz; f3H =258MHz.
(1) PL = 2 dBm
(2) PL = 5 dBm
Tuned for fIF = 225 MHz; f2H = 450 MHz; f3H = 675 MHz.
(1) PL = 2 dBm
(2) PL = 5 dBm
Fig 30. Second harmonic level as a fun ction of
gain step Fig 31. Se con d h armonic level as a function of
gain step
Tuned for fIF = 50 MHz; f2H = 100 MHz; f3H = 150 MHz;
Tamb = 25 C.
(1) gain step 0
(2) gain step 14
(3) gain step 24
Tuned for fIF = 86 MHz; f2H = 172 MHz; f3H = 258 MHz;
Tamb = 25 C.
(1) gain step 0
(2) gain step 14
(3) gain step 24
Fig 32. Second harmonic level and third harmonic
level as a function of output power Fig 33. Se con d h armonic level and third harmonic
level as a function of output power
Gstep
0102030
aaa-002005
-40
-50
-60
-70
-80
α2H
(dBc)
-90
(1)
(2)
DDD
    






*VWHS
Į++
Į+
G%FG%FG%F


PL (dBm)
-4 6420-2
aaa-002006
-70
-80
-90
-100
α2H
(dBc)
-110
-70
α3H
(dBc)
-110
-100
-90
-80
α2H
α3H
(1)
(3)
(1)
(2)
(2)
(3)
PL (dBm)
-4 6420-2
aaa-002007
-70
-80
-90
-100
α2H
(dBc)
-110
-70
α3H
(dBc)
-110
-100
-90
-80
α2H
α3H
(2)
(3)
(1)
(1)
(3)
(2)
BGA7351 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 3 — 11 June 2014 19 of 28
NXP Semiconductors BGA7351
50 MHz to 500 MHz high linearity Si variable gain amplifier
T uned for fIF = 172 MHz; f2H = 358 MHz; f3H = 530 MHz;
Tamb = 25 C.
(1) gain step 0
(2) gain step 14
(3) gain step 24
T uned for fIF = 250 MHz; f2H = 500 MHz; f3H = 750 MHz;
Tamb = 25 C.
(1) gain step 0
(2) gain step 14
(3) gain step 24
Fig 34. Second harmonic level and third harmonic
level as a function of output power Fig 35. Se con d h armonic level and third harmonic
level as a function of output power
Tuned for fIF = 450 MHz
(1) channel A at gain step 0 (maximum gain);
channel B at gain step 28 (minimum gain)
(2) channel A at gain step 0 (maximum gain);
channel B at gain step 0 (maximum gain)
Tuned for fIF = 450 MHz
(1) gain step 0
(2) gain step 1
(3) gain step 2
(4) gain step 3
(5) gain step 4
Fig 36. Isolation between channels as a function of
frequency Fig 37. Noise figure as a function of frequency
PL (dBm)
-4 6420-2
aaa-002008
-70
-80
-90
-100
α2H
(dBc)
-110
-70
α3H
(dBc)
-110
-100
-90
-80
α2H
α3H
(2)
(3)
(1)
(1)
(3)
(2)
PL (dBm)
-4 6420-2
aaa-002009
-50
-60
-70
-80
-90
-100
α2H
(dBc)
-110
-60
-70
-80
-90
-100
-110
-50
α3H
(dBc)
α2H
α3H
(1)
(3)
(2)
(1)
(3)
(2)
DDD
      






I0+]
ĮLVROFKFKLVROFKFK
ĮLVROFKFK
G%G%G%


DDD
     

I0+]
1)1)1)
G%G%G%





xxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx x xxxxxxxxxxxxxx xxxxxxxxxx xxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx
xxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx xxxxxxxxxxxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxx x x
BGA7351 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 3 — 11 June 2014 20 of 28
NXP Semiconductors BGA7351
50 MHz to 500 MHz high linearity Si variable gain amplifier
11.1 Application PCB
For a list of components see Table 11.
Fig 38. Schematic
aaa-002010
A_OUT_P
A_OUT_N
A_EN
GNDA
GNDB
B_EN
B_OUT_N
B_OUT_P
1
2
3
4
5
6
7
8
33
24
32 31 30 29 28 27 26 25
9 10111213141516
23
22
21
20
19
18
17
A_D2
A_D3
A_D4
n.c.
n.c.
B_D4
B_D3
B_D2
B_OUT_N
B_OUT_P
VCCB
GNDB
B_IN_N
B_IN_P
B_D0
B_D1
BGA7351
I1
A_OUT_N
A_OUT_P
VCCA
GNDA
A_IN_N
A_IN_P
A_D0
A_D1
JP5
VCCA
12
JP15
EN
R13
R12
0 Ω
R18
0 Ω
R19
0 Ω
R20
0 Ω
R23
n.m.
R21
ADT4-1T+
X5
SMA-142-0701-
851/861
R22
0 Ω
0 Ω
C11
n.m.
C12
n.m.
R24
0 Ω
R25
0 Ω
R10
10 Ω
JP16JP4
L2
180 nH
L1
180 nH
GND
GND
GND
C1
100 pF
C2
10 nF
C20
1 μF
10 Ω
VoutA
123
L4
180 nH
L3
180 nH
1
2
3
6
4
GND
C5
1 nF
C6
100 pF
C17 100 nF
C18 100 nF
C23
1 μF
GND
GND
GND
GND
GND
GND
JP10
TR2
TR3
VCMA
12
2
1
3
4
3
1
4
2219-02
S3
R26
n.m.
ADT4-1T+
X2
SMA-142-0701-
851/861
1
2
3
6
4GND
GND
GND
GND
GND
GND GND
JP11
JP3
VCMB
VoutB
VCCB
12
C7
1 nF
C3
100 pF
C4
10 nF
C21
1 μF
C8
100 pF
C22
1 μF
12312
GND
GND
GND
GND
GND
JP9 GND
VCMinB
1
2
GND
GND
GND
GND
GND
C16
100 nF
X3
TR4
SMA-142-0701-
851/861
ADT3-1T
123
64
GND
GND
GND
JP8 GND
GND
GND
GND
VCMinA
1
2C15
100 nF
X4
TR1
ADT3-1T
SMA-142-0701-
851/861
123
64
GND
GND
GND
1
4
GND
GND
GND GND
3
2
9
7
5
3
1
10
8
6
4
2
AG
JP1
JP7
JP2
9
7
5
3
1
10
8
6
4
2
3
1
4
2
VCM
BG
5
4
3
2
1
6
7
8
9
10
219-05
R4
10 kΩ
R3
10 kΩ
R2
10 kΩ
R1
10 kΩ
R15
10 kΩ
C19
1 μF
C9
100 pF
C10
100 nF
S1
5
4
3
2
1
6
7
8
9
10
lC1
PCF8575
24 VCC
SDA
SCL
A0
P17
P16
P15
P14
P13
P12
P11
P10
INT_B
A1
A2
P00
P01
P02
P03
P04
P05
P06
P07
GND
23
22
21
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
9
10
11
12
C14
n.m.
C13
n.m.
219-05
S2
R17
10 kΩ
R11
10 kΩ
R16
10 kΩ
R14
10 kΩ
X1
MKS1854-
6-0-404
4
3
2
1
R9
10 kΩ
R8
10 kΩ
R7
10 kΩ
R6
10 kΩ
R5
10 kΩ
JP6
VCCdig
12
GND
JP12
GND
GND
1 2
JP13
GND
GND
1 2
BGA7351 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 3 — 11 June 2014 21 of 28
NXP Semiconductors BGA7351
50 MHz to 500 MHz high linearity Si variable gain amplifier
For a list of components see Table 11.
Fig 39. Components top side
C8
123
12
LSB
MSB
MSB
LSB
A OUT
B OUT
VCC
GND
VCC I2C
A VDD25ext
B VDD25ext
VCM IN A
VCM IN B
GND
GND
GND
GND
GND
GND
GND
VCCA
GND
GND
GND
123
VCCB
C1
C2
C3
C4
JP15
C5
C6
C7
JP16
JP2
S2
L2
L1
L3
L4
R15
R1
R2
R3
R4
R5
R6
R7
R8
R9
JP1
S1
R13
R10
R11
JP3
S3
JPA
JP5
TR3
TR2
R14
X1
R16
JP6
C9
C10
JP7
C11
12
C12
C13
C14
R17
X3
X2
X5
X4
JP8
JP9
JP10
JP11
R21
R22
R23
R24
R25
R26
C19
JP12
JP13
TR1
TR4
+
+
+
+
I1
1234512345
aaa-001258
BGA7351 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 3 — 11 June 2014 22 of 28
NXP Semiconductors BGA7351
50 MHz to 500 MHz high linearity Si variable gain amplifier
For a list of components see Table 11.
Fig 40. Components bottom side
aaa-001259
C15
C16
C17
C18
R12
R18
R19
R20
C20
C21
C22
C23
Table 11. List of comp onents
See Figure 38, Figure 39 and Figure 40.
Component Description Conditions Value Size Remarks
C1, C3, C6, C8, C9 capacitor 100 pF 0603
C2, C4 capacitor 10 nF 0603
C5, C7 capacitor 1 nF 0603
C10, C15, C16, C17, C18 capacitor 100 nF 0603
C11 capacitor - 0603 not mounted
C12 capacitor - 0603 not mounted
C13 capacitor - 0603 not mounted
C14 capacitor - 0603 not mounted
C19, C20, C21, C22, C23 capacitor 1 F0603
I1 BGA7351 -
JP1 jumper - JP5 AG
JP2 jumper - JP5 BG
JP3 jumper - JP2 EN
JP4 jumper - JP2 VCCB
JP5 jumper - JP2 VCCA
JP6 jumper - JP2 VCCdig
JP7 jumper - JP2 VCM
JP8 jumper - JP2 VCMinA
BGA7351 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 3 — 11 June 2014 23 of 28
NXP Semiconductors BGA7351
50 MHz to 500 MHz high linearity Si variable gain amplifier
JP9 jumper - JP2 VCMinB
JP10 jumper - JP2 VCMA
JP11 jumper - JP2 VCMB
JP12 jumper - JP2 GND
JP13 jumper - JP2 GND
JP15 jumper - JP3 VoutA
JP16 jumper - JP3 VoutB
L1, L2, L3, L4 inductor fIF = 50 MHz 1200 nH 0603 dependent on PCB layout
fIF = 172 MHz 150 nH 06 03 dependent on PCB layout
fIF = 250 MHz 56 nH 0603 dependent on PCB layout
fIF = 450 MHz 27 nH 0603 dependent on PCB layout
R1, R2, R3, R4, R5, R6, R7, R8, R9, R11,
R14, R15, R16, R17 resistor 10 k0402
R10, R13 resistor 10 1206
R12, R18, R19, R20, R21, R22, R24, R25 resistor 0 0402
R23, R26 resistor - 0402 not mounted
S1, S2 DIP-switch - CTS-219-05
S3 DIP-switch - CTS-219-02
TR1 1:3 transformer - Mini Circuits ADT3-1T+
TR2 1:4 transformer - Mini Circuits ADT4-1T+
TR3 1:3 transformer - Mini Circuits ADT4-1T+
TR4 1:4 transformer - Mini Circuits ADT3-1T+
X1 - - not mounted
X2 SMA-connector - BOUT_P
X3 SMA-connector - BIN_P
X4 SMA-connector - AIN_P
X5 SMA-connector - AOUT_P
Table 11. List of comp onents
See Figure 38, Figure 39 and Figure 40.
Component Description Conditions Value Size Remarks
BGA7351 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 3 — 11 June 2014 24 of 28
NXP Semiconductors BGA7351
50 MHz to 500 MHz high linearity Si variable gain amplifier
12. Package outline
Fig 41. Package outline SOT617-1 (HVQFN32)

$ (K
E
81,7 \H

F
5()(5(1&(6
287/,1(
9(56,21
(8523($1
352-(&7,21 ,668('$7(
,(& -('(& -(,7$
PP 

'K


\




H

H




  
',0(16,216PPDUHWKHRULJLQDOGLPHQVLRQV
627 02 


/

Y

Z
  PP
VFDOH
627
+94)1SODVWLFWKHUPDOHQKDQFHGYHU\WKLQTXDGIODWSDFNDJHQROHDGV
WHUPLQDOVERG\[[PP
$
PD[
$
$
F
GHWDLO;
\
\ &
H
/
(K
'K
H
H
E
 
 




;
'
(
&
% $
H
WHUPLQDO
LQGH[DUHD
WHUPLQDO
LQGH[DUHD


H
H $&
&
%
Y 0
Z 0
(

1RWH
3ODVWLFRUPHWDOSURWUXVLRQVRIPPPD[LPXPSHUVLGHDUHQRWLQFOXGHG
'

BGA7351 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 3 — 11 June 2014 25 of 28
NXP Semiconductors BGA7351
50 MHz to 500 MHz high linearity Si variable gain amplifier
13. Abbreviations
14. Revision history
Table 12. Abbreviations
Acronym Description
ADC Ana log-to-Digital Converter
DIP Dual In-line Package
EMI ElectroMagnetic Interference
ESD ElectroStatic Discharge
GSM Global System for Mobile Communications
HTOL High Temperature Operating Life
HVQFN Heatsink Very-thin Quad Flat-pack No-leads
IF Intermediate Frequency
LSB Least Significant Bit
LTE Long Term Evolution
MMIC Monolithic Microwave Integrated Circuit
MSB Most Significant Bit
PCB Printed-Circuit Board
SMA SubMiniature version A
WiMAX Worldwide Interoperability for Microwave Access
W-CDMA Wideband Code Division Multiple Access
Table 13. Revision history
Document ID Release date Dat a sheet statu s Change notice Supersedes
BGA7351 v.3 20140611 Product data sheet - BGA7351 v.2
Modifications: Table 8 on page 7: some changes have been made
Section 11 on page 11: some graphs have been added.
Table 11 on page 22: the condition f = 450 MHz has been added for the row containing
the inductors
BGA7351 v.2 20121219 Product data sheet - BGA7351 v.1
BGA7351 v.1 20111228 Product data sheet - -
BGA7351 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 3 — 11 June 2014 26 of 28
NXP Semiconductors BGA7351
50 MHz to 500 MHz high linearity Si variable gain amplifier
15. Legal information
15.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of de vice(s) descr ibed in th is docume nt may have cha nged since this docume nt was publis hed and ma y dif fer in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
15.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liab ility for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and tit le. A short data sh eet is intended
for quick reference only and shou ld not be rel ied u pon to cont ain det ailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsisten cy or conf lict with the short data sheet, the
full data sheet shall pre vail.
Product specificat ion The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to off er functions and qualities beyond those described in the
Product data sheet.
15.3 Disclaimers
Limited warr a nty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Se miconductors takes no
responsibility for the content in this document if provided by an inf ormation
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidenta l ,
punitive, special or consequ ential damages (including - wit hout limitatio n - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconduct ors’ aggregate and cumulat ive liability toward s
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all informa tion supplied prior
to the publication hereof .
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in perso nal injury, death or severe prop erty or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconducto rs products in such equipment or
applications and ther efore such inclu sion and/or use is at the cu stomer’s own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty tha t such application s will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and ope ration of their applications
and products using NXP Semiconductors product s, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suit able and fit for the custome r’s applications and
products planned, as well as fo r the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associate d with their
applications and products.
NXP Semiconductors does not accept any liabil ity related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for th e customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress rating s only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanent ly and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individua l agreement. In case an individual
agreement is concluded only the ter ms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby exp ressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing i n this document may be interpreted or
construed as an of fer t o sell product s that is open for accept ance or t he grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specificat ion.
Product [short] dat a sheet Production This document contains the product specification.
BGA7351 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 3 — 11 June 2014 27 of 28
NXP Semiconductors BGA7351
50 MHz to 500 MHz high linearity Si variable gain amplifier
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characte ristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors prod uct is automotive qualified,
the product is not suitable for automotive use. It i s neit her qua lified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automot ive specifications and standard s, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed produ ct cl aims resulting from custome r design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
15.4 Trademarks
Notice: All referenced b rands, produc t names, service names and trademarks
are the property of their respect i ve ow ners.
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
NXP Semiconductors BGA7351
50 MHz to 500 MHz high linearity Si variable gain amplifier
© NXP Semiconductors N.V. 2014. All rights rese rved.
For more information, please visit: http://www.nxp.co m
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 11 June 2014
Document identifier: BGA7351
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
17. Contents
1 Product profile. . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 General description . . . . . . . . . . . . . . . . . . . . . 1
1.2 Features and benefits. . . . . . . . . . . . . . . . . . . . 1
1.3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.4 Quick reference data . . . . . . . . . . . . . . . . . . . . 2
2 Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
2.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
3 Ordering information. . . . . . . . . . . . . . . . . . . . . 4
4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 5
5 Enable control . . . . . . . . . . . . . . . . . . . . . . . . . . 5
6 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6
7 Thermal characteristics . . . . . . . . . . . . . . . . . . 6
8 Static characteristics. . . . . . . . . . . . . . . . . . . . . 7
9 Dynamic characteristics . . . . . . . . . . . . . . . . . . 7
10 Moisture sensitivity . . . . . . . . . . . . . . . . . . . . . 10
11 Application information. . . . . . . . . . . . . . . . . . 11
11 .1 Application PCB . . . . . . . . . . . . . . . . . . . . . . . 20
12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 24
13 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 25
14 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 25
15 Legal information . . . . . . . . . . . . . . . . . . . . . . . 26
15.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 26
15.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
15.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 26
15.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 27
16 Contact information. . . . . . . . . . . . . . . . . . . . . 27
17 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Mouser Electronics
Authorized Distributor
Click to View Pricing, Inventory, Delivery & Lifecycle Information:
NXP:
OM7924/BGA7351,598