IRFD120 Data Sheet January 2002 1.3A, 100V, 0.300 Ohm, N-Channel Power MOSFET Features * 1.3A, 100V This advanced power MOSFET is designed, tested, and guaranteed to withstand a specified level of energy in the breakdown avalanche mode of operation. These are N-Channel enhancement mode silicon gate power field effect transistors designed for applications such as switching regulators, switching convertors, motor drivers, relay drivers, and drivers for high power bipolar switching transistors requiring high speed and low gate drive power. They can be operated directly from integrated circuits. * rDS(ON) = 0.300 * Single Pulse Avalanche Energy Rated * SOA is Power Dissipation Limited * Nanosecond Switching Speeds * Linear Transfer Characteristics * High Input Impedance * Related Literature - TB334 "Guidelines for Soldering Surface Mount Components to PC Boards" Formerly developmental type TA17401. Ordering Information PART NUMBER IRFD120 PACKAGE HEXDIP Symbol BRAND D IRFD120 NOTE: When ordering, use the entire part number. G S Packaging HEXDIP DRAIN GATE SOURCE (c)2002 Fairchild Semiconductor Corporation IRFD120 Rev. B IRFD120 TC = 25oC, Unless Otherwise Specified Absolute Maximum Ratings Drain to Source Breakdown Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDS Drain to Gate Voltage (RGS = 20k) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .ID Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD Linear Derating Factor (See Figure 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Single Pulse Avalanche Energy Rating (Note 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg IRFD120 100 100 1.3 5.2 20 1.0 0.008 36 -55 to 150 UNITS V V A A V W W/oC mJ oC 300 260 oC oC CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. TJ = 25oC to 125oC. Electrical Specifications TC = 25oC, Unless Otherwise Specified MIN TYP MAX UNITS Drain to Source Breakdown Voltage PARAMETER BVDSS ID = 250A, VGS = 0V (Figure 9) 100 - - V Gate Threshold Voltage VGS(TH) VGS = VDS, ID = 250A 2.0 - 4.0 V - - 25 A - - 250 A 1.3 - - A Zero Gate Voltage Drain Current SYMBOL IDSS TEST CONDITIONS VDS = Rated BVDSS, VGS = 0V VDS = 0.8 x Rated BVDSS, VGS = 0V, TJ = 125oC On-State Drain Current (Note 2) Gate Source Leakage ID(ON) IGSS Drain Source On Resistance (Note 2) rDS(ON) Forward Transconductance (Note 2) gfs td(ON) Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Total Gate Charge (Gate to Source + Gate to Drain) Gate to Source Charge tr td(OFF) tf Qg(TOT) Qgs VDS > ID(ON) x rDS(ON) Max, VGS = 10V VGS = 20V - - 500 nA ID = 0.6A, VGS = 10V (Figures 7, 8) - 0.25 0.30 0.9 1.0 - S - 20 40 ns - 35 70 ns - 50 100 ns - 35 70 ns - 11 15 nC - 6.0 - nC VDS > ID(ON) x rDS(ON)MAX , ID = 0.6A (Figure 11) VDD = 0.5 x Rated BVDSS, ID 1.3A, VGS = 10V, RG = 9.1 RL = 38.5 for VDD = 50V MOSFET Switching Times are Essentially Independent of Operating Temperature VGS = 10V, ID = 1.3A, VDS = 0.8 x Rated BVDSS, Ig(REF) = 1.5mA (Figure 13) Gate Charge is Essentially Independent of Operating Temperature - 5.0 - nC - 450 - pF COSS - 200 - pF CRSS - 50 - pF - 4.0 - nH - 6.0 - nH - - 120 oC/W Gate to Drain "Miller" Charge Qgd Input Capacitance CISS Output Capacitance Reverse Transfer Capacitance VGS = 0V, VDS = 25V, f = 1MHz (Figure 10) Internal Drain Inductance LD Measured From the Drain Lead, 2mm (0.08in) from Package to Center of Die Internal Source Inductance LS Measured From the Source Lead, 2mm (0.08in) from Header to Source Bonding Pad Modified MOSFET Symbol Showing the Internal Device's Inductances D LD G LS S Thermal Resistance Junction to Ambient (c)2002 Fairchild Semiconductor Corporation RJA Free Air Operation IRFD120 Rev. B IRFD120 Source to Drain Diode Specifications PARAMETER SYMBOL Continuous Source to Drain Current Pulse Source to Drain Current ISD ISDM TEST CONDITIONS MIN TYP MAX UNITS - - 1.3 A - - 5.2 A TJ = 25oC, ISD = 1.3A, VGS = 0V (Figure 12) - - 2.5 V TJ = 150oC, ISD = 1.3A, dISD/dt = 100A/s TJ = 150oC, ISD = 1.3A, dISD/dt = 100A/s - 280 - ns - 1.6 - C Modified MOSFET Symbol Showing the Integral Reverse P-N Junction Diode D G S Source to Drain Diode Voltage (Note 2) Reverse Recovery Time Reverse Recovery Charge VSD trr QRR NOTES: 2. Pulse test: pulse width 300s, duty cycle 2%. 3. VDD = 25V, starting TJ = 25oC, L = 32mH, RG = 25, peak IAS = 1.3A. Typical Performance Curves Unless Otherwise Specified 1.5 POWER DISSIPATION MULTIPLIER 1.2 ID, DRAIN CURRENT (A) 1.0 0.8 0.6 0.4 0.2 0 1.2 0.9 0.6 0.3 0 0 25 125 50 75 100 TA , AMBIENT TEMPERATURE (oC) 150 25 50 75 FIGURE 1. NORMALIZED POWER DISSIPATION vs AMBIENT TEMPERATURE 150 20 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX 100s 1ms 1 10ms OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) 0.1 TJ = MAX RATED 0.1 1 10 VDS , DRAIN TO SOURCE VOLTAGE (V) 100ms VGS = 9V 16 VGS = 8V 12 VGS = 7V 8 VGS = 6V 4 VGS = 5V DC VGS = 4V 0 100 FIGURE 3. FORWARD BIAS SAFE OPERATING AREA (c)2002 Fairchild Semiconductor Corporation ID, DRAIN CURRENT (A) VGS = 10V ID, DRAIN CURRENT (A) 125 FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs AMBIENT TEMPERATURE 10 0.01 100 TA , AMBIENT TEMPERATURE (oC) 0 10 20 30 40 VDS, DRAIN TO SOURCE VOLTAGE (V) 50 FIGURE 4. OUTPUT CHARACTERISTICS IRFD120 Rev. B IRFD120 Typical Performance Curves PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX IDS(ON), DRAIN TO SOURCE CURRENT (A) ID, DRAIN CURRENT (A) 10 Unless Otherwise Specified (Continued) VGS = 8V VGS = 7V 8 VGS = 10V VGS = 9V VGS = 6V 6 4 VGS = 5V 2 VGS = 4V 0 0 1 2 3 4 VDS, DRAIN TO SOURCE VOLTAGE (V) 20 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VDS > ID(ON) x rDS(ON)MAX TJ = -55oC o TJ = 25 C TJ = 125oC 16 12 8 4 0 5 0 2 FIGURE 5. SATURATION CHARACTERISTICS 2.2 NORMALIZED DRAIN TO SOURCE ON RESISTANCE rDS(ON), DRAIN TO SOURCE ON RESISTANCE () 2s PULSE TEST VGS = 10V 0.4 VGS = 20V 0.2 0 NOTE: 8 10 1.8 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VGS = 10V, ID = 0.6A 1.4 1.0 0.6 0.2 10 0 20 30 ID, DRAIN CURRENT (A) -40 40 0 40 80 120 160 TJ , JUNCTION TEMPERATURE (oC) Heating effect of 2s pulse is minimal. FIGURE 7. DRAIN TO SOURCE ON RESISTANCE vs GATE VOLTAGE AND DRAIN CURRENT FIGURE 8. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE 1.25 1000 VGS = 0V, f = 1MHz CISS = CGS + CGD CRSS = CGD COSS CDS + CGD IDS = 250A 800 1.15 C, CAPACITANCE (pF) NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE 6 FIGURE 6. TRANSFER CHARACTERISTICS 0.8 0.6 4 VGS, GATE TO SOURCE VOLTAGE (V) 1.05 0.95 0.85 600 CISS 400 COSS 200 CRSS 0.75 -40 0 40 80 120 160 TJ , JUNCTION TEMPERATURE (oC) FIGURE 9. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE (c)2002 Fairchild Semiconductor Corporation 0 0 10 30 40 20 VDS, DRAIN TO SOURCE VOLTAGE (V) 50 FIGURE 10. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE IRFD120 Rev. B IRFD120 Typical Performance Curves PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX 2 TJ = -55oC ISD, SOURCE TO DRAIN CURRENT (A) gfs, TRANSCONDUCTANCE (S) 5 Unless Otherwise Specified (Continued) TJ = 25oC 4 TJ = 125oC 3 2 1 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX 102 5 2 10 TJ = 150oC 5 TJ = 25oC 2 0.1 0 0 4 8 12 ID , DRAIN CURRENT (A) 1 2 3 VSD, SOURCE TO DRAIN VOLTAGE (V) 0 20 16 FIGURE 11. TRANSCONDUCTANCE vs DRAIN CURRENT 4 FIGURE 12. SOURCE TO DRAIN DIODE VOLTAGE 20 VGS, GATE TO SOURCE (V) ID = 5.2A VDS = 20V 15 VDS = 50V VDS = 80V 10 5 0 2 0 4 6 QG, GATE CHARGE (nC) 8 10 FIGURE 13. GATE TO SOURCE VOLTAGE vs GATE CHARGE Test Circuits and Waveforms VDS BVDSS L VARY tP TO OBTAIN REQUIRED PEAK IAS tP IAS + RG - VGS VDS VDD VDD DUT 0V tP IAS 0 0.01 tAV FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT (c)2002 Fairchild Semiconductor Corporation FIGURE 15. UNCLAMPED ENERGY WAVEFORMS IRFD120 Rev. B IRFD120 Test Circuits and Waveforms (Continued) tON tOFF td(ON) td(OFF) tr RL VDS tf 90% 90% + RG - VDD 10% 10% 0 DUT 90% VGS VGS 0 FIGURE 16. SWITCHING TIME TEST CIRCUIT 0.2F 50% PULSE WIDTH 10% FIGURE 17. RESISTIVE SWITCHING WAVEFORMS VDS (ISOLATED SUPPLY) CURRENT REGULATOR 12V BATTERY 50% VDD Qg(TOT) SAME TYPE AS DUT 50k Qgd 0.3F VGS Qgs D VDS DUT G 0 Ig(REF) S 0 IG CURRENT SAMPLING RESISTOR VDS ID CURRENT SAMPLING RESISTOR FIGURE 18. GATE CHARGE TEST CIRCUIT (c)2002 Fairchild Semiconductor Corporation Ig(REF) 0 FIGURE 19. GATE CHARGE WAVEFORMS IRFD120 Rev. B TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. 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PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Product Status Definition Advance Information Formative or In Design This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. Preliminary First Production This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. No Identification Needed Full Production This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only. Rev. H4