©2002 Fairchild Semiconductor Corporation IRFD120 Rev. B
IRFD120
1.3A, 100V, 0.300 Ohm, N-Channel
Power MOSFET
This advanced power MOSFET is designed, tested, and
guaranteed to withstand a specified level of energy in the
breakdown avalanche mode of operation. These are
N-Channel enhancement mode silicon gate power field
effect transistors designed for applications such as switching
regulators, switching convertors, motor drivers, relay drivers,
and drivers for high power bipolar switching transistors
requiring high speed and low gate drive power. They can be
operated directly from integrated circuits.
Formerly developmental type TA17401.
Features
• 1.3A, 100V
•r
DS(ON)
= 0.300
Ω
• Single Pulse Avalanche Energy Rated
• SOA is Power Dissipation Limited
• Nanosecond Switching Speeds
• Linear Transfer Characteristics
• High Input Impedance
• Related Literature
- TB334 “Guidelines for Soldering Surface Mount
Components to PC Boards”
Symbol
Packaging
HEXDIP
Ordering Information
PART NUMBER PACKAGE BRAND
IRFD120 HEXDIP IRFD120
NOTE: When ordering, use the entire part number.
G
D
S
SOURCE
GATE
DRAIN
Data Sheet January 2002
©2002 Fairchild Semiconductor Corporation IRFD120 Rev. B
Absolute Maximum Ratings
T
C
= 25
o
C, Unless Otherwise Specified
IRFD120 UNITS
Drain to Source Breakdown Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
DS
100 V
Drain to Gate Voltage (R
GS
= 20k
Ω)
(Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
DGR
100 V
Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .I
D
1.3 A
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
DM
5.2 A
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V
GS
±
20 V
Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P
D
1.0 W
Linear Derating Factor (See Figure 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.008 W/
o
C
Single Pulse Avalanche Energy Rating (Note 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E
AS
36 mJ
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
J
, T
STG
-55 to 150
o
C
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
L
Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
pkg
300
260
o
C
o
C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. T
J
= 25
o
C to 125
o
C.
Electrical Specifications
T
C
= 25
o
C, Unless Otherwise Specified
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Drain to Source Breakdown Voltage BV
DSS
I
D
= 250
µ
A, V
GS
= 0V (Figure 9) 100 - - V
Gate Threshold Voltage V
GS(TH)
V
GS
= V
DS
, I
D
= 250
µ
A 2.0 - 4.0 V
Zero Gate Voltage Drain Current I
DSS
V
DS
= Rated BV
DSS
, V
GS
= 0V - - 25
µ
A
V
DS
= 0.8 x Rated BV
DSS
, V
GS
= 0V, T
J
= 125
o
C - - 250
µ
A
On-State Drain Current (Note 2) I
D(ON)
V
DS
> I
D(ON)
x r
DS(ON)
Max, V
GS
= 10V 1.3 - - A
Gate Source Leakage I
GSS
V
GS
=
±
20V - -
±
500 nA
Drain Source On Resistance (Note 2) r
DS(ON)
I
D
= 0.6A, V
GS
= 10V (Figures 7, 8) - 0.25 0.30
Ω
Forward Transconductance (Note 2) gfs V
DS
> I
D(ON)
x r
DS(ON)MAX
, I
D
= 0.6A (Figure 11) 0.9 1.0 - S
Turn-On Delay Time t
d(ON)
V
DD
= 0.5 x Rated BV
DSS
, I
D
≈
1.3A,
V
GS
= 10V, R
G
= 9.1
Ω
R
L
= 38.5
Ω
for V
DD
= 50V
MOSFET Switching Times are Essentially
Independent of Operating Temperature
-2040ns
Rise Time t
r
-3570ns
Turn-Off Delay Time t
d(OFF)
- 50 100 ns
Fall Time t
f
-3570ns
Total Gate Charge
(Gate to Source + Gate to Drain)
Q
g(TOT)
V
GS
= 10V, I
D
= 1.3A, V
DS
= 0.8 x Rated BV
DSS
,
I
g(REF)
= 1.5mA (Figure 13)
Gate Charge is Essentially Independent of Operating
Temperature
-1115nC
Gate to Source Charge Q
gs
- 6.0 - nC
Gate to Drain “Miller” Charge Q
gd
- 5.0 - nC
Input Capacitance C
ISS
V
GS
= 0V, V
DS
= 25V, f = 1MHz (Figure 10) - 450 - pF
Output Capacitance C
OSS
- 200 - pF
Reverse Transfer Capacitance C
RSS
-50- pF
Internal Drain Inductance L
D
Measured From the Drain
Lead, 2mm (0.08in) from
Package to Center of Die
Modified MOSFET
Symbol Showing the
Internal Device’s
Inductances
- 4.0 - nH
Internal Source Inductance L
S
Measured From the Source
Lead, 2mm (0.08in) from
Header to Source Bonding
Pad
- 6.0 - nH
Thermal Resistance Junction to Ambient R
θ
JA
Free Air Operation - - 120
o
C/W
LS
LD
G
D
S
IRFD120
©2002 Fairchild Semiconductor Corporation IRFD120 Rev. B
Source to Drain Diode Specifications
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Continuous Source to Drain Current I
SD
Modified MOSFET Symbol
Showing the Integral
Reverse P-N Junction
Diode
- - 1.3 A
Pulse Source to Drain Current I
SDM
- - 5.2 A
Source to Drain Diode Voltage (Note 2) V
SD
T
J
= 25
o
C, I
SD
= 1.3A, V
GS
= 0V (Figure 12) - - 2.5 V
Reverse Recovery Time t
rr
T
J
= 150
o
C, I
SD
= 1.3A, dI
SD
/dt = 100A/
µ
s - 280 - ns
Reverse Recovery Charge Q
RR
T
J
= 150
o
C, I
SD
= 1.3A, dI
SD
/dt = 100A/
µ
s - 1.6 -
µ
C
NOTES:
2. Pulse test: pulse width
≤
300
µ
s, duty cycle
≤
2%.
3. V
DD
= 25V, starting T
J
= 25
o
C, L = 32mH, R
G
= 25
Ω,
peak I
AS
= 1.3A.
Typical Performance Curves
Unless Otherwise Specified
FIGURE 1. NORMALIZED POWER DISSIPATION vs AMBIENT
TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
AMBIENT TEMPERATURE
FIGURE 3. FORWARD BIAS SAFE OPERATING AREA FIGURE 4. OUTPUT CHARACTERISTICS
G
D
S
TA, AMBIENT TEMPERATURE (oC)
POWER DISSIPATION MULTIPLIER
0
0 25 50 75 100 150
0.2
0.4
0.6
0.8
1.0
1.2
125
TA, AMBIENT TEMPERATURE (oC)
50 75 10025 150
1.5
1.2
0.9
0
0.6
ID, DRAIN CURRENT (A)
0.3
125
VDS, DRAIN TO SOURCE VOLTAGE (V)
1
ID, DRAIN CURRENT (A)
100
0.1
100.1
0.01
10
LIMITED BY rDS(ON)
AREA MAY BE
OPERATION IN THIS
TJ = MAX RATED
1ms
10ms
100ms
100µs
DC
1
ID, DRAIN CURRENT (A)
0 10203040
4
8
12
16
20
50
VDS, DRAIN TO SOURCE VOLTAGE (V)
0
VGS = 4V
VGS = 5V
VGS = 7V
PULSE DURATION = 80µs
VGS = 10V
VGS = 8V
VGS = 6V
VGS = 9V
DUTY CYCLE = 0.5% MAX
IRFD120
©2002 Fairchild Semiconductor Corporation IRFD120 Rev. B
FIGURE 5. SATURATION CHARACTERISTICS FIGURE 6. TRANSFER CHARACTERISTICS
NOTE: Heating effect of 2µs pulse is minimal.
FIGURE 7. DRAIN TO SOURCE ON RESISTANCE vs GATE
VOLTAGE AND DRAIN CURRENT
FIGURE 8. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
FIGURE 9. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
FIGURE 10. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
Typical Performance Curves Unless Otherwise Specified (Continued)
ID, DRAIN CURRENT (A)
01234
2
4
6
8
10
5
VDS, DRAIN TO SOURCE VOLTAGE (V)
0
VGS = 9V
VGS = 4V
VGS = 5V
VGS = 6V
VGS = 10V
VGS = 8V
VGS = 7V
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
20
IDS(ON), DRAIN TO SOURCE CURRENT (A)
VGS, GATE TO SOURCE VOLTAGE (V)
16
12
8
08642010
4
TJ = 25oC
TJ = 125oC
TJ = -55oC
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VDS > ID(ON) x rDS(ON)MAX
0
0.4
0.8
10 20 30
rDS(ON), DRAIN TO SOURCE
ID, DRAIN CURRENT (A)
400
0.2
0.6 VGS = 10V
VGS = 20V
ON RESISTANCE (Ω)
2µs PULSE TEST
NORMALIZED DRAIN TO SOURCE
2.2
1.4
1.0
0.6
0.2
40
TJ, JUNCTION TEMPERATURE (oC)
120 160
1.8
80
0-40
ON RESISTANCE
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VGS = 10V, ID = 0.6A
1.25
0.95
0.85
0.75
-40
TJ, JUNCTION TEMPERATURE (oC)
NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE
160
1.05
1.15
040
80 120
IDS = 250µA
1000
200
0020 50
C, CAPACITANCE (pF)
600
VDS, DRAIN TO SOURCE VOLTAGE (V)
800
400
10 30
CISS
COSS
CRSS
40
VGS = 0V, f = 1MHz
CISS = CGS + CGD
CRSS = CGD
COSS ≈ CDS + CGD
IRFD120
©2002 Fairchild Semiconductor Corporation IRFD120 Rev. B
FIGURE 11. TRANSCONDUCTANCE vs DRAIN CURRENT FIGURE 12. SOURCE TO DRAIN DIODE VOLTAGE
FIGURE 13. GATE TO SOURCE VOLTAGE vs GATE CHARGE
Test Circuits and Waveforms
FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 15. UNCLAMPED ENERGY WAVEFORMS
Typical Performance Curves Unless Otherwise Specified (Continued)
ID, DRAIN CURRENT (A)
gfs, TRANSCONDUCTANCE (S)
04 81216
1
2
3
4
5
20
0
TJ = -55oC
TJ = 25oC
TJ = 125oC
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
023
0.1
10
2
ISD, SOURCE TO DRAIN CURRENT (A)
VSD, SOURCE TO DRAIN VOLTAGE (V)
102
1
5
5
2
4
TJ = 25oC
TJ = 150oC
2PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
QG, GATE CHARGE (nC)
VGS, GATE TO SOURCE (V)
04610
5
15
20 ID = 5.2A
10
0
28
VDS = 80V
VDS = 50V
VDS = 20V
tP
VGS
0.01Ω
L
IAS
+
-
VDS
VDD
RG
DUT
VARY tP TO OBTAIN
REQUIRED PEAK IAS
0V
VDD
VDS
BVDSS
tP
IAS
tAV
0
IRFD120
©2002 Fairchild Semiconductor Corporation IRFD120 Rev. B
FIGURE 16. SWITCHING TIME TEST CIRCUIT FIGURE 17. RESISTIVE SWITCHING WAVEFORMS
FIGURE 18. GATE CHARGE TEST CIRCUIT FIGURE 19. GATE CHARGE WAVEFORMS
Test Circuits and Waveforms (Continued)
VGS
RL
RG
DUT
+
-
VDD
tON
td(ON)
tr
90%
10%
VDS 90%
10%
tf
td(OFF)
tOFF
90%
50%
50%
10% PULSE WIDTH
VGS
0
0
0.3µF
12V
BATTERY 50kΩ
VDS
S
DUT
D
G
Ig(REF)
0
(ISOLATED
VDS
0.2µF
CURRENT
REGULATOR
ID CURRENT
SAMPLING
IG CURRENT
SAMPLING
SUPPLY)
RESISTOR RESISTOR
SAME TYPE
AS DUT
Qg(TOT)
Qgd
Qgs
VDS
0
VGS
VDD
Ig(REF)
0
IRFD120
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER
NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD
DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT
OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT
RIGHTS, NOR THE RIGHTS OF OTHERS.
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not intended to be an exhaustive list of all such trademarks.
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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant into
the body, or (b) support or sustain life, or (c) whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
reasonably expected to result in significant injury to the
user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification Product Status Definition
Advance Information
Preliminary
No Identification Needed
Obsolete
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
Formative or
In Design
First Production
Full Production
Not In Production
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