JM38510/11201BDA - NATIONAL SEMICONDUCTOR

LM139JAN

LM139JAN Low Power Low Offset Voltage Quad Comparators

Literature Number: SNOSAJ7A

LM139JAN

October 26, 2010

Low Power Low Offset Voltage Quad Comparators

General Description

The LM139 consists of four independent precision voltage

comparators with an offset voltage specification as low as 2

mV max for all four comparators. These were designed

specifically to operate from a single power supply over a wide

range of voltages. Operation from split power supplies is also

possible and the low power supply current drain is indepen-

dent of the magnitude of the power supply voltage. These

comparators also have a unique characteristic in that the input

common-mode voltage range includes ground, even though

operated from a single power supply voltage.

Application areas include limit comparators, simple analog to

digital converters; pulse, squarewave and time delay gener-

ators; wide range VCO; MOS clock timers; multivibrators and

high voltage digital logic gates. The LM139 was designed to

directly interface with TTL and CMOS. When operated from

both plus and minus power supplies, they will directly inter-

face with MOS logic— where the low power drain of the

LM139 is a distinct advantage over standard comparators.

Features

■Wide supply voltage range 5V to 36 VDC

or ±2.5V to ±18 VDC

■Very low supply current drain (0.8 mA) - independent of

supply voltage

■Low input biasing current: 25 nA

■Low input offset current: ±5 nA

■Offset voltage: ±3 mV

■Input common-mode voltage range includes GND

■Differential input voltage range equal to the power supply

voltage

■Low output saturation voltage: 250 mV at 4 mA

■Output voltage compatible with TTL, DTL, ECL, MOS and

CMOS logic systems

Advantages

■High precision comparators

■Reduced VOS drift over temperature

■Eliminates need for dual supplies

■Allows sensing near GND

■Compatible with all forms of logic

■Power drain suitable for battery operation

Ordering Information

NS Part Number JAN Part Number NS Package Number Package Description

JL139BDA JM38510/11201BDA W14B 14LD CERPACK

LM139JAN Low Power Low Offset Voltage Quad Comparators

Connection Diagrams

20129527

See NS Package Number W14B

Schematic Diagram

20129501

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LM139JAN

Absolute Maximum Ratings (Note 1)

Supply Voltage, V+36 VDC or ±18 VDC

Differential Input Voltage (Note 7) 36 VDC

Output Voltage 36 VDC

Input Voltage −0.3 VDC to +36 VDC

Input Current (VIN < −0.3 VDC) (Note 3) 50 mA

Power Dissipation (Note 4, Note 12)

CERPACK 350 mW @ TA = 125°C

Output Short-Circuit to GND, (Note 2) Continuous

Storage Temperature Range −65°C ≤ TA ≤ +150°C

Maximum Junction Temperature (TJ) +175°C

Lead Temperature (Soldering, 10 seconds) 260°C

Operating Temperature Range −55°C ≤ TA ≤ +125°C

Thermal Resistance

θJA

CERPACK (Still Air) 183°C/W

CERPACK (500LF / Min Air flow) 120°C/W

θJC

CERPACK 23°C/W

Package Weight (typical)

CERPACK 460mg

ESD rating (Note 11) 600V

Quality Conformance Inspection

Mil-Std-883, Method 5005 - Group A

Subgroup Description Temp (°C)

1 Static tests at +25

2 Static tests at +125

3 Static tests at -55

4 Dynamic tests at +25

5 Dynamic tests at +125

6 Dynamic tests at -55

7 Functional tests at +25

8A Functional tests at +125

8B Functional tests at -55

9 Switching tests at +25

10 Switching tests at +125

11 Switching tests at -55

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LM139JAN

LM139 JAN Electrical Characteristics

DC Parameters

The following conditions apply, unless otherwise specified. −VCC = 0V

Symbol Parameters Conditions Notes Min Max Unit Sub-

groups

VIO Input Offset Voltage +VCC = 30V, VO = 15V -5.0 5.0 mV 1

-7.0 7.0 mV 2, 3

+VCC = 2V, -VCC = -28V,

VO = -13V

-5.0 5.0 mV 1

-7.0 7.0 mV 2, 3

+VCC = 5V, VO = 1.4V -5.0 5.0 mV 1

-7.0 7.0 mV 2, 3

+VCC = 2V, -VCC = -3V,

VO = -1.6V

-5.0 5.0 mV 1

-7.0 7.0 mV 2, 3

IIO Input Offset Current +VCC = 30V, RS = 20KΩ,

VO = 15V

(Note 8) -25 25 nA 1, 2

(Note 8) -75 75 nA 3

+VCC = 2V, -VCC = -28V,

RS = 20KΩ, VO = -13V

(Note 8) -25 25 nA 1, 2

(Note 8) -75 75 nA 3

+VCC = 5V, RS = 20KΩ,

VO = 1.4V

(Note 8) -25 25 nA 1, 2

(Note 8) -75 75 nA 3

+VCC = 2V, -VCC = -3V,

RS = 20KΩ, VO = -1.6V

(Note 8) -25 25 nA 1, 2

(Note 8) -75 75 nA 3

±IIB Input Bias Current +VCC = 30V, RS = 20KΩ,

VO = 15V

(Note 8) -100 +0.1 nA 1, 2

(Note 8) -200 +0.1 nA 3

+VCC = 2V, -VCC = -28V,

RS = 20KΩ, VO = -13V

(Note 8) -100 +0.1 nA 1, 2

(Note 8) -200 +0.1 nA 3

+VCC = 5V, RS = 20KΩ,

VO = 1.4V

(Note 8) -100 +0.1 nA 1, 2

(Note 8) -200 +0.1 nA 3

+VCC = 2V, -VCC = -3V,

RS = 20KΩ, VO = -1.6V

(Note 8) -100 +0.1 nA 1, 2

(Note 8) -200 +0.1 nA 3

CMRR Input Voltage Common Mode

Rejection

+VCC = 30V 76 dB 1, 2, 3

+VCC = 5V 70 dB 1, 2, 3

ICEX Output Leakage +VCC = 30V, VO = +30V 1.0 µA 1, 2, 3

+IIL Input Leakage Current +VCC = 36V, V + i = 34V,

V − i = 0V -500 500 nA 1, 2, 3

-IIL Input Leakage Current +VCC = 36V, V + i = 0V,

V − i = 34V -500 500 nA 1, 2, 3

VOL Logical "0" Output Voltage +VCC = 4.5V, IO = 4mA 0.4 V 1

0.7 V 2, 3

+VCC = 4.5V, IO = 8mA 1.5 V 1

2.0 V 2, 3

ICC Power Supply Current +VCC = 5V, VID = 15mV 2.0 mA 1, 2

3.0 mA 3

+VCC = 30V, VID = 15mV 3.0 mA 1, 2

4.0 mA 3

ΔVIO /ΔTTemperature Coefficient of Input

Offset Voltage

25°C ≤ TA ≤ 125°C (Note 9) -25 25 µV/°C 2

-55°C ≤ TA ≤ 25°C (Note 9) -25 25 µV/°C 3

ΔIIO /ΔTTemperature Coefficient of Input

Offset Current

25°C ≤ TA ≤ 125°C (Note 9) -300 300 pA/°C 2

-55°C ≤ TA ≤ 25°C (Note 9) -400 400 pA/°C 3

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LM139JAN

Symbol Parameters Conditions Notes Min Max Unit Sub-

groups

AVS Open Loop Voltage Gain +VCC = 15V, RL=15KΩ,

1V ≤ VO ≤ 11V

(Note 10) 50 V/mV 4

(Note 10) 25 V/mV 5, 6

VIO Tempco Screen 4.0 mV

CMRR Tempco Screen 70 dB

IIO Tempco Screen 13 nA

IIB Tempco Screen 12 nA

AC Parameters

Symbol Parameters Conditions Notes Min Max Unit Sub-

groups

tRLH Response Time: Low-to-High +VCC = 5V, VI = 100mV,

RL = 5.1KΩ, VOD = 5mV

5.0 µS 7, 8B

7.0 µS 8A

+VCC = 5V, VI = 100mV,

RL = 5.1KΩ, VOD = 50mV

0.8 µS 7, 8B

1.2 µS 8A

tRHL Response Time: High-to-Low +VCC = 5V, VI = 100mV,

RL = 5.1KΩ, VOD = 5mV

2.5 µS 7, 8B

3.0 µS 8A

+VCC = 5V, VI = 100mV,

RL = 5.1KΩ, VOD = 50mV

0.8 µS 7, 8B

1.0 µS 8A

CSChannel Separation +VCC = 20V, -VCC = -10V,

A to B 80 dB 7

+VCC = 20V, -VCC = -10V,

A to C 80 dB 7

+VCC = 20V, -VCC = -10V,

A to D 80 dB 7

+VCC = 20V, -VCC = -10V,

B to A 80 dB 7

+VCC = 20V, -VCC = -10V,

B to C 80 dB 7

+VCC = 20V, -VCC = -10V,

B to D 80 dB 7

+VCC = 20V, -VCC = -10V,

C to A 80 dB 7

+VCC = 20V, -VCC = -10V,

C to B 80 dB 7

+VCC = 20V, -VCC = -10V,

C to D 80 dB 7

+VCC = 20V, -VCC = -10V,

D to A 80 dB 7

+VCC = 20V, -VCC = -10V,

D to B 80 dB 7

+VCC = 20V, -VCC = -10V,

D to C 80 dB 7

VLAT Voltage Latch (Logical "1" Input) +VCC = 5V, VI = 10V,

IO = 4mA 0.4 V 9

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LM139JAN

DC Parameters Drift Values

The following conditions apply, unless otherwise specified. −VCC = 0V

Delta calculations performed on JAN S product at Group B, Subgroup 5.

Symbol Parameters Conditions Notes Min Max Unit Sub-

groups

VIO Input Offset Voltage VCC = 30V,VO = 15V -1.0 1.0 mV 1

±IBias Input Bias Current VCC = 30V,RS = 20KΩ,

VO = 15V -15 15 nA 1

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is

functional, but do not guaranteed specific performance limits. For guaranteed specifications and test conditions, see, the Electrical Characteristics. The guaranteed

specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test

conditions.

Note 2: Short circuits from the output to V+ can cause excessive heating and eventual destruction. When considering short circuits to ground, the maximum output

current is approximately 20 mA independent of the magnitude of V+.

Note 3: This input current will only exist when the voltage at any of the input leads is driven negative. It is due to the collector-base junction of the input PNP

transistors becoming forward biased and thereby acting as input diode clamps. In addition to this diode action, there is also lateral NPN parasitic transistor action

on the IC chip. This transistor action can cause the output voltages of the comparators to go to the V+ voltage level (or to ground for a large overdrive) for the

time duration that an input is driven negative. This is not destructive and normal output states will re-establish when the input voltage, which was negative, again

returns to a value greater than −0.3 VDC (at 25°)C.

Note 4: The low bias dissipation and the ON-OFF characteristics of the outputs keeps the chip dissipation very small (PD ≤ 100mW), provided the output transistors

are allowed to saturate.

Note 5: The direction of the input current is out of the IC due to the PNP input stage. This current is essentially constant, independent of the state of the output

so no loading change exists on the reference or input lines.

Note 6: Short circuits from the output to V+ can cause excessive heating and eventual destruction. When considering short circuits to ground, the maximum output

current is approximately 20mA independent of the magnitude of V+

Note 7: Positive excursions of input voltage may exceed the power supply level. As long as the other voltage remains within the common-mode range, the

comparator will provide a proper output state. The low input voltage state must not be less than −0.3 VDC (or 0.3 VDCbelow the magnitude of the negative power

supply, if used) (at 25°C).

Note 8: S/S RS = 20KΩ, tested at RS = 10KΩ as equivalent test.

Note 9: Calculated parameter; for Delta VIO / Delta T use VIO test at +VCC = 30V, −VCC = 0V, VO = 15V; and for Delta IIO / Delta T use IIB test at +VCC = 30V,

−VCC = 0V, VO = 15V

Note 10: Datalog of K = V/mV.

Note 11: Human Body model, 1.5 KΩ in series with 100 pF

Note 12: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJmax (maximum junction temperature), θJA (Package

junction to ambient thermal resistance), and TA (ambient temperature). The maximum allowable power dissipation at any temperature is PDmax = (TJmax — TA) /

θJA or the number given in the Absolute Maximum Ratings, whichever is lower.

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LM139JAN

Typical Performance Characteristics

Supply Current

20129534

Input Current

20129535

Output Saturation Voltage

20129536

Response Time for Various Input Overdrives

—Negative Transition

20129537

Response Time for Various Input Overdrives

—Positive Transition

20129538

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LM139JAN

Application Hints

The LM139 is a high gain, wide bandwidth device which, like

most comparators, can easily oscillate if the output lead is

inadvertently allowed to capacitively couple to the inputs via

stray capacitance. This shows up only during the output volt-

age transition intervals as the comparator changes states.

Power supply bypassing is not required to solve this problem.

Standard PC board layout is helpful as it reduces stray input-

output coupling. Reducing the input resistors to < 10 kΩ

reduces the feedback signal levels and finally, adding even a

small amount (1 to 10 mV) of positive feedback (hysteresis)

causes such a rapid transition that oscillations due to stray

feedback are not possible. Simply socketing the IC and at-

taching resistors to the pins will cause input-output oscilla-

tions during the small transition intervals unless hysteresis is

used. If the input signal is a pulse waveform, with relatively

fast rise and fall times, hysteresis is not required.

All pins of any unused comparators should be tied to the neg-

ative supply.

The bias network of the LM139 establishes a drain current

which is independent of the magnitude of the power supply

voltage over the range of from 5 VDC to 30 VDC.

It is usually unnecessary to use a bypass capacitor across the

power supply line.

The differential input voltage may be larger than V+ without

damaging the device. Protection should be provided to pre-

vent the input voltages from going negative more than −0.3

VDC (at 25°C). An input clamp diode can be used as shown

in the applications section.

The output of the LM139 is the uncommitted collector of a

grounded-emitter NPN output transistor. Many collectors can

be tied together to provide an output OR'ing function. An out-

put pull-up resistor can be connected to any available power

supply voltage within the permitted supply voltage range and

there is no restriction on this voltage due to the magnitude of

the voltage which is applied to the V+ terminal of the LM139

package. The output can also be used as a simple SPST

switch to ground (when a pull-up resistor is not used). The

amount of current which the output device can sink is limited

by the drive available (which is independent of V+) and the β

of this device. When the maximum current limit is reached

(approximately 16 mA), the output transistor will come out of

saturation and the output voltage will rise very rapidly. The

output saturation voltage is limited by the approximately

60Ω RSAT of the output transistor. The low offset voltage of

the output transistor (1 mV) allows the output to clamp es-

sentially to ground level for small load currents.

Typical Applications

(V+ = 5.0 VDC)

Basic Comparator

20129503

Driving CMOS

20129504

Driving TTL

20129505

AND Gate

20129508

OR Gate

20129509

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LM139JAN

Typical Applications

(V+= 15 VDC)

One-Shot Multivibrator

20129510

Bi-Stable Multivibrator

20129511

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LM139JAN

One-Shot Multivibrator with Input Lock Out

20129512

Pulse Generator

20129517

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LM139JAN

Large Fan-In AND Gate

20129513

ORing the Outputs

20129515

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LM139JAN

Time Delay Generator

20129514

Non-Inverting Comparator with Hysteresis

20129518

Inverting Comparator with Hysteresis

20129519

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LM139JAN

Squarewave Oscillator

20129516

Basic Comparator

20129521

Limit Comparator

20129524

Comparing Input Voltages

of Opposite Polarity

20129520

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LM139JAN

Output Strobing

20129522

* Or open-collector logic gate without pull-up resistor

Crystal Controlled Oscillator

20129525

Transducer Amplifier

20129528

Zero Crossing Detector (Single Power Supply)

20129530

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LM139JAN

Two-Decade High-Frequency VCO

20129523

V+ = +30 VDC

250 mVDC ≤ VC ≤ +50 VDC

700 Hz ≤ fO ≤ 100 kHz

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LM139JAN

Split-Supply Applications

(V+ = +15 VDC and V− = −15 VDC)

MOS Clock Driver

20129531

Zero Crossing Detector

20129532

Comparator With a Negative Reference

20129533

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LM139JAN

Revision History

Date Released Revision Section Changes

02/15/05 A New Release to corporate format 1 MDS datasheet converted into Corp. datasheet

format. MJLM139-X rev 0D0. MDS datasheet will be

archived.

10/26/2010 B Order Information, Connection Diagrams,

Absolute Ratings, Physical Dimensions

drawings,

Update with current device information and format.

Deleted J and WG pkg references. Revision A will be

Archived

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LM139JAN

Physical Dimensions inches (millimeters) unless otherwise noted

Ceramic Flat Package (W)

NS Package Number W14B

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LM139JAN

Notes

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LM139JAN

Notes

LM139JAN Low Power Low Offset Voltage Quad Comparators

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