PD - 95103 Advanced Process Technology Ultra Low On-Resistance l Dynamic dv/dt Rating l 175C Operating Temperature l Fast Switching l Fully Avalanche Rated l Lead-Free Description IRF1010NSPbF IRF1010NLPbF l HEXFET(R) Power MOSFET l D VDSS = 55V RDS(on) = 11m G Advanced HEXFET (R) Power MOSFETs from International Rectifier utilize advanced processing techniques to achieve extremely low on-resistance per silicon area. This benefit, combined with the fast switching speed and ruggedized device design that HEXFET power MOSFETs are well known for, provides the designer with an extremely efficient and reliable device for use in a wide variety of applications. ID = 85A S The D2Pak is a surface mount power package capable of accommodating die sizes up to HEX-4. It provides the highest power capability and the lowest possible onresistance in any existing surface mount package. The D2Pak is suitable for high current applications because of its low internal connection resistance and can dissipate up to 2.0W in a typical surface mount application. The through-hole version (IRF1010NL) is available for lowprofile applications. D 2 Pak TO-262 IRF1010NSPbF IRF1010NLPbF Absolute Maximum Ratings Parameter ID @ TC = 25C ID @ TC = 100C IDM PD @TC = 25C VGS IAR EAR dv/dt TJ TSTG Continuous Drain Current, VGS @ 10V Continuous Drain Current, VGS @ 10V Pulsed Drain Current Power Dissipation Linear Derating Factor Gate-to-Source Voltage Avalanche Current Repetitive Avalanche Energy Peak Diode Recovery dv/dt Operating Junction and Storage Temperature Range Soldering Temperature, for 10 seconds Mounting torque, 6-32 or M3 srew Max. 85 Units 60 290 180 1.2 20 43 18 3.6 -55 to + 175 A W W/C V A mJ V/ns C 300 (1.6mm from case ) 10 lbf*in (1.1N*m) Thermal Resistance Parameter RJC RJA www.irf.com Junction-to-Case Junction-to-Ambient ( PCB Mounted,steady-state)** Typ. Max. Units --- --- 0.85 40 C/W 1 03/11/04 IRF1010NS/LPbF Electrical Characteristics @ TJ = 25C (unless otherwise specified) RDS(on) VGS(th) gfs Parameter Drain-to-Source Breakdown Voltage Breakdown Voltage Temp. Coefficient Static Drain-to-Source On-Resistance Gate Threshold Voltage Forward Transconductance Qg Qgs Qgd td(on) tr td(off) tf Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage Total Gate Charge Gate-to-Source Charge Gate-to-Drain ("Miller") Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Min. 55 --- --- 2.0 32 --- --- --- --- --- --- --- --- --- --- --- Typ. --- 0.058 --- --- --- --- --- --- --- --- --- --- 13 76 39 48 IDSS Drain-to-Source Leakage Current LD Internal Drain Inductance --- 4.5 LS Internal Source Inductance --- 7.5 Ciss Coss Crss EAS Input Capacitance Output Capacitance Reverse Transfer Capacitance Single Pulse Avalanche Energy --- 3210 --- 690 --- 140 --- 1030 V(BR)DSS V(BR)DSS/TJ IGSS Max. Units Conditions --- V VGS = 0V, ID = 250A --- V/C Reference to 25C, ID = 1mA 11 m VGS = 10V, ID = 43A 4.0 V VDS = VGS, ID = 250A --- S VDS = 25V, ID = 43A 25 VDS = 55V, VGS = 0V A 250 VDS = 44V, VGS = 0V, TJ = 150C 100 VGS = 20V nA -100 VGS = -20V 120 ID = 43A 19 nC VDS = 44V 41 VGS = 10V, See Fig. 6 and 13 --- VDD = 28V --- ID = 43A ns --- RG = 3.6 --- VGS = 10V, See Fig. 10 D Between lead, --- 6mm (0.25in.) nH G from package --- and center of die contact S --- VGS = 0V --- VDS = 25V --- pF = 1.0MHz, See Fig. 5 250 mJ IAS = 4.3A, L = 270H Source-Drain Ratings and Characteristics IS ISM VSD trr Qrr ton Parameter Continuous Source Current (Body Diode) Pulsed Source Current (Body Diode) Diode Forward Voltage Reverse Recovery Time Reverse Recovery Charge Forward Turn-On Time Min. Typ. Max. Units Conditions D MOSFET symbol --- --- 85 showing the A G integral reverse --- --- 290 S p-n junction diode. --- --- 1.3 V TJ = 25C, IS = 43A, VGS = 0V --- 69 100 ns TJ = 25C, IF = 43A --- 220 230 nC di/dt = 100A/s Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD) Notes: Repetitive rating; pulse width limited by max. junction temperature. ( See fig. 11 ) Starting TJ = 25C, L = 270H RG = 25, IAS = 43A, VGS=10V (See Figure 12) ISD 43A, di/dt 210A/s, VDD V(BR)DSS, TJ 175C Pulse width 400s; duty cycle 2%. This is a typical value at device destruction and represents operation outside rated limits. 2 This is a calculated value limited to TJ = 175C . Calculated continuous current based on maximum allowable junction temperature. Package limitation current is 75A. Uses IRF1010N data and test conditions. ** When mounted on 1" square PCB ( FR-4 or G-10 Material ). For recommended footprint and soldering techniques refer to application note #AN-994. www.irf.com IRF1010NS/LPbF 1000 1000 VGS 15V 10V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.5V VGS 15V 10V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.5V 100 TOP I D , Drain-to-Source Current (A) I D , Drain-to-Source Current (A) TOP 100 4.5V 10 20s PULSE WIDTH TJ = 25 C 1 0.1 1 10 4.5V 10 1 0.1 100 Fig 1. Typical Output Characteristics RDS(on) , Drain-to-Source On Resistance (Normalized) I D , Drain-to-Source Current (A) 2.5 TJ = 25 C TJ = 175 C 10 V DS = 25V 20s PULSE WIDTH 6 8 10 VGS , Gate-to-Source Voltage (V) Fig 3. Typical Transfer Characteristics www.irf.com 10 100 Fig 2. Typical Output Characteristics 100 4 1 VDS , Drain-to-Source Voltage (V) VDS , Drain-to-Source Voltage (V) 1 20s PULSE WIDTH TJ = 175 C 12 ID = 85A 2.0 1.5 1.0 0.5 0.0 -60 -40 -20 0 VGS = 10V 20 40 60 80 100 120 140 160 180 TJ , Junction Temperature ( C) Fig 4. Normalized On-Resistance Vs. Temperature 3 IRF1010NS/LPbF 20 6000 5000 VGS , Gate-to-Source Voltage (V) VGS = 0V, f = 1 MHZ Ciss = Cgs + Cgd, Cds SHORTED Crss = Cgd C, Capacitance(pF) Coss = Cds + Cgd Ciss 4000 3000 Coss 2000 Crss 1000 10 12 8 4 0 100 1000 20 1000 ID, Drain-to-Source Current (A) ISD , Reverse Drain Current (A) 0 100 TJ = 175 C TJ = 25 C V GS = 0 V 0.6 60 80 100 120 OPERATION IN THIS AREA LIMITED BY R DS(on) 100 10 1 40 Fig 6. Typical Gate Charge Vs. Gate-to-Source Voltage Fig 5. Typical Capacitance Vs. Drain-to-Source Voltage 1.2 1.8 VSD ,Source-to-Drain Voltage (V) Fig 7. Typical Source-Drain Diode Forward Voltage 4 FOR TEST CIRCUIT SEE FIGURE 13 QG , Total Gate Charge (nC) VDS, Drain-to-Source Voltage (V) 0.1 0.0 VDS = 44V VDS = 27V VDS = 11V 16 0 1 ID = 43A 2.4 100sec 1msec 10 Tc = 25C Tj = 175C Single Pulse 1 1 10msec 10 100 1000 VDS , Drain-toSource Voltage (V) Fig 8. Maximum Safe Operating Area www.irf.com IRF1010NS/LPbF 100 VDS LIMITED BY PACKAGE VGS 80 D.U.T. ID , Drain Current (A) RG 60 RD + -VDD V GS Pulse Width 1 s Duty Factor 0.1 % 40 Fig 10a. Switching Time Test Circuit 20 VDS 90% 0 25 50 75 100 125 150 175 TC , Case Temperature ( C) 10% VGS Fig 9. Maximum Drain Current Vs. Case Temperature td(on) tr t d(off) tf Fig 10b. Switching Time Waveforms Thermal Response (Z thJC ) 1 D = 0.50 0.20 0.10 0.1 0.05 0.02 0.01 0.01 0.00001 PDM SINGLE PULSE (THERMAL RESPONSE) t1 t2 Notes: 1. Duty factor D = t 1 / t 2 2. Peak T J = P DM x Z thJC + TC 0.0001 0.001 0.01 0.1 t1 , Rectangular Pulse Duration (sec) Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case www.irf.com 5 15V L VDS D.U.T RG VGS 20V IAS tp DRIVER + V - DD A 0.01 Fig 12a. Unclamped Inductive Test Circuit V(BR)DSS tp EAS , Single Pulse Avalanche Energy (mJ) IRF1010NS/LPbF 500 ID 18A 30A 43A TOP 400 BOTTOM 300 200 100 0 25 50 75 100 125 150 175 Starting TJ , Junction Temperature ( C) Fig 12c. Maximum Avalanche Energy Vs. Drain Current I AS Fig 12b. Unclamped Inductive Waveforms Current Regulator Same Type as D.U.T. 50K QG 12V .2F .3F VGS QGS D.U.T. QGD + V - DS VGS VG 3mA Charge Fig 13a. Basic Gate Charge Waveform 6 IG ID Current Sampling Resistors Fig 13b. Gate Charge Test Circuit www.irf.com IRF1010NS/LPbF Peak Diode Recovery dv/dt Test Circuit + D.U.T* Circuit Layout Considerations * Low Stray Inductance * Ground Plane * Low Leakage Inductance Current Transformer + - - + RG * dv/dt controlled by RG * ISD controlled by Duty Factor "D" * D.U.T. - Device Under Test VGS * + - VDD Reverse Polarity of D.U.T for P-Channel Driver Gate Drive P.W. Period D= P.W. Period [VGS=10V ] *** D.U.T. ISD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt Re-Applied Voltage Body Diode [VDD] Forward Drop Inductor Curent Ripple 5% [ISD ] *** VGS = 5.0V for Logic Level and 3V Drive Devices Fig 14. For N-channel HEXFET(R) power MOSFETs www.irf.com 7 IRF1010NS/LPbF D2Pak Package Outline Dimensions are shown in millimeters (inches) D2Pak Part Marking Information (Lead-Free) T H IS IS AN IR F 5 3 0 S W IT H L OT CODE 80 2 4 AS S E M B L E D ON W W 0 2, 20 00 IN T H E AS S E M B L Y L IN E "L " IN T E R N AT IO N AL R E C T IF IE R L OGO N ote: "P " in as s em bly lin e po s itio n in dicates "L ead-F r ee" P AR T N U M B E R F 5 30 S AS S E M B L Y L O T CO D E D AT E C O D E Y E AR 0 = 2 0 0 0 W E E K 02 L IN E L OR IN T E R N AT IO N AL R E C T IF IE R L OGO AS S E M B L Y L OT COD E 8 P AR T N U M B E R F 530S D AT E CO D E P = D E S IG N AT E S L E AD -F R E E P R O D U C T (O P T IO N AL ) Y E AR 0 = 2 0 0 0 W E E K 02 A = AS S E M B L Y S IT E CO D E www.irf.com IRF1010NS/LPbF TO-262 Package Outline IGBT 1- GATE 2- COLLECTOR 3- EMITTER TO-262 Part Marking Information EXAMPLE: T HIS IS AN IRL3103L LOT CODE 1789 AS SEMBLED ON WW 19, 1997 IN T HE ASS EMBLY LINE "C" Note: "P" in as s embly line pos ition indicates "Lead-Free" INT ERNAT IONAL RECT IFIER LOGO ASS EMBLY LOT CODE PART NUMBER DAT E CODE YEAR 7 = 1997 WEEK 19 LINE C OR INT ERNAT IONAL RECT IFIER LOGO AS S EMBLY LOT CODE www.irf.com PART NUMBER DAT E CODE P = DES IGNAT ES LEAD-FREE PRODUCT (OPTIONAL) YEAR 7 = 1997 WEEK 19 A = AS S EMBLY S ITE CODE 9 IRF1010NS/LPbF D2Pak Tape & Reel Infomation Dimensions are shown in millimeters (inches) TRR 1.60 (.063) 1.50 (.059) 4.10 (.161) 3.90 (.153) FEED DIRECTION 1.85 (.073) 1.65 (.065) 1.60 (.063) 1.50 (.059) 11.60 (.457) 11.40 (.449) 0.368 (.0145) 0.342 (.0135) 15.42 (.609) 15.22 (.601) 24.30 (.957) 23.90 (.941) TRL 10.90 (.429) 10.70 (.421) 1.75 (.069) 1.25 (.049) 4.72 (.136) 4.52 (.178) 16.10 (.634) 15.90 (.626) FEED DIRECTION 13.50 (.532) 12.80 (.504) 27.40 (1.079) 23.90 (.941) 4 330.00 (14.173) MAX. NOTES : 1. COMFORMS TO EIA-418. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION MEASURED @ HUB. 4. INCLUDES FLANGE DISTORTION @ OUTER EDGE. 60.00 (2.362) MIN. 26.40 (1.039) 24.40 (.961) 3 30.40 (1.197) MAX. 4 Data and specifications subject to change without notice. This product has been designed and qualified for the Industrial market. Qualification Standards can be found on IR's Web site. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information. 03/04 10 www.irf.com Note: For the most current drawings please refer to the IR website at: http://www.irf.com/package/