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General Description
The MAX1652–MAX1655 are high-efficiency, pulse-
width-modulated (PWM), step-down DC-DC controllers
in small QSOP packages. The MAX1653/MAX1655 also
come in 16-pin narrow SO packages that are pin-
compatible upgrades to the popular MAX797. Improve-
ments include higher duty-cycle operation for better
dropout, lower quiescent supply currents for better
light-load efficiency, and an output voltage down to 1V
(MAX1655).
The MAX1652–MAX1655 achieve up to 96% efficiency
and deliver up to 10A using a unique Idle Mode™ syn-
chronous-rectified PWM control scheme. These devices
automatically switch between PWM operation at heavy
loads and pulse-frequency-modulated (PFM) operation
at light loads to optimize efficiency over the entire out-
put current range. The MAX1653/MAX1655 also feature
logic-controlled, forced PWM operation for noise-sensi-
tive applications.
All devices operate with a selectable 150kHz/300kHz
switching frequency, which can also be synchronized
to an external clock signal. Both external power switch-
es are inexpensive N-channel MOSFETs, which provide
low resistance while saving space and reducing cost.
The MAX1652 and MAX1654 have an additional feed-
back pin that permits regulation of a low-cost second
output tapped from a transformer winding. The
MAX1652 provides an additional positive output. The
MAX1654 provides an additional negative output.
The MAX1652–MAX1655 have a 4.5V to 30V input volt-
age range. The MAX1652/MAX1653/MAX1654’s output
range is 2.5V to 5.5V while the MAX1655’s output range
extends down to 1V. An evaluation kit (MAX1653EVKIT)
is available to speed designs.
Applications
Notebook Computers
PDAs
Cellular Phones
Hand-Held Computers
Handy-Terminals
Mobile Communicators
Distributed Power
____________________________Features
♦96% Efficiency
♦Small, 16-Pin QSOP Package
(half the size of a 16-pin narrow SO)
♦Pin-Compatible with MAX797 (MAX1653/MAX1655)
♦Output Voltage Down to 1V (MAX1655)
♦4.5V to 30V Input Range
♦99% Duty Cycle for Lower Dropout
♦170µA Quiescent Supply Current
♦3µA Logic-Controlled Shutdown
♦Dual, N-Channel, Synchronous-Rectified Control
♦Fixed 150kHz/300kHz PWM Switching,
or Synchronized from 190kHz to 340kHz
♦Programmable Soft Start
♦Low-Cost Secondary Outputs (MAX1652/MAX1654)
MAX1652–MAX1655
High-Efficiency, PWM, Step-Down
DC-DC Controllers in 16-Pin QSOP
________________________________________________________________
Maxim Integrated Products
1
19-1357; Rev 1; 7/98
EVALUATION KIT
AVAILABLE
Ordering Information
Selection Guide
Pin Configurations appear at end of data sheet.
Idle Mode is a trademark of Maxim Integrated Products.
PART FEEDBACK
VOLTAGE (V) SPECIAL
FEATURE COMPATIBILITY
MAX1652 2.5
Regulates positive
secondary voltage
(such as +12V)
Same pin order
as MAX796, but
smaller package
MAX1653 2.5 Logic-controlled,
low-noise mode Pin-compatible
with MAX797
MAX1654 2.5
Regulates negative
secondary voltage
(such as -5V)
Same pin order
as MAX799, but
smaller package
MAX1655 1
Low output volt-
ages (1V to 5.5V);
logic-controlled,
low-noise mode
Pin compatible
with MAX797
(except for feed-
back voltage)
PART
MAX1652EEE -40°C to +85°C
TEMP. RANGE PIN-PACKAGE
16 QSOP
MAX1653EEE -40°C to +85°C 16 QSOP
MAX1654EEE -40°C to +85°C 16 QSOP
MAX1653ESE -40°C to +85°C 16 Narrow SO
MAX1655ESE -40°C to +85°C 16 Narrow SO
MAX1655EEE -40°C to +85°C 16 QSOP
MAX1652–MAX1655
High-Efficiency, PWM, Step-Down
DC-DC Controllers in 16-Pin QSOP
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(V+ = +15V, GND = PGND = 0V, SYNC = REF, IVL = IREF = 0A, TA= 0°C to +85°C, unless otherwise noted.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
V+ to GND..............................................................-0.3V to +36V
GND to PGND .......................................................-0.3V to +0.3V
VL to GND ................................................................-0.3V to +6V
BST to GND............................................................-0.3V to +36V
DH to LX.....................................................-0.3V to (BST + 0.3V)
LX to BST..................................................................-6V to +0.3V
SHDN to GND...............................................-0.3V to (V+ + 0.3V)
SYNC, SS, REF, SECFB, SKIP, FB to GND...-0.3V to (VL + 0.3V)
DL to PGND..................................................-0.3V to (VL + 0.3V)
CSH, CSL to GND ....................................................-0.3V to +6V
VL Short Circuit to GND..............................................Momentary
REF Short Circuit to GND...........................................Continuous
VL Output Current...............................................+50mA to -1mA
REF Output Current...............................................+5mA to -1mA
Continuous Power Dissipation (TA= +70°C)
SO (derate 8.70mW/°C above +70°C) .......................696mW
QSOP (derate 8.3mW/°C above +70°C) ....................667mW
Operating Temperature Range
MAX165_E_E ..................................................-40°C to +85°C
Storage Temperature Range.............................-65°C to +160°C
Lead Temperature (soldering, 10sec).............................+300°C
Rising edge, falling edge hysteresis = 60mV
Rising edge, falling edge hysteresis = 50mV
SHDN = 2V, 0 < IVL < 25mA, 5.5V < V+ < 30V
Rising edge, falling edge, hysteresis = 22mV (MAX1654)
CSH - CSL, negative
CSH - CSL, positive
Falling edge, rising edge, hysteresis = 22mV (MAX1652)
6V < V+ < 30V
25mV < (CSH - CSL) < 80mV
0 < (CSH - CSL) < 80mV, FB = VL, 6V < V+ < 30V,
includes line and load regulation
External resistor divider
VSS = 4V
0 < (CSH - CSL) < 80mV
VSS = 0V
CONDITIONS
V4.2 4.5 4.7VL/CSL Switchover Voltage V3.8 3.9 4.0VL Fault Lockout Voltage V4.7 5.0 5.3VL Output Voltage
-0.05 0 0.05 V
2.45 2.50 2.55
SECFB Regulation Setpoint
mA2.0SS Fault Sink Current µA2.5 4.0 6.5SS Source Current
V4.5 30Input Supply Range
-50 -100 -160 mV
80 100 120
Current-Limit Voltage
%/V0.03 0.06Line Regulation 1.2
V4.85 5.06 5.255V Output Voltage (CSL)
V
1 5.5
Nominal Adjustable Output
Voltage Range
%
2
Load Regulation
UNITSMIN TYP MAXPARAMETER
0 < (CSH - CSL) < 80mV, FB = 0V, 4.5V < V+ < 30V,
includes line and load regulation V3.20 3.34 3.463.3V Output Voltage (CSL)
2.5 5.5
MAX1655
MAX1652/MAX1653/
MAX1654
2.43 2.50 2.57
MAX1652/MAX1653/
MAX1654
CSH - CSL = 0V, CSL = FB,
SKIP = 0V, 4.5V < V+ < 30V
MAX1655 V
0.97 1.00 1.03
Feedback Voltage
3.3V AND 5V STEP-DOWN CONTROLLERS
FLYBACK/PWM CONTROLLER
INTERNAL REGULATOR AND REFERENCE
MAX1652–MAX1655
High-Efficiency, PWM, Step-Down
DC-DC Controllers in 16-Pin QSOP
_______________________________________________________________________________________ 3
Note 1: Since the reference uses VL as its supply, V+ line-regulation error is insignificant.
Note 2: At very low input voltages, quiescent supply current may increase due to excessive PNP base current in the VL linear
regulator. This occurs if V+ falls below the preset VL regulation point (5V nominal).
ELECTRICAL CHARACTERISTICS (continued)
(V+ = +15V, GND = PGND = 0V, SYNC = REF, IVL = IREF = 0A, TA= 0°C to +85°C, unless otherwise noted.)
SECFB, 0 or 4V
SHDN, 0 or 30V
SHDN, SKIP
SYNC
SYNC = 0 or 5V
SYNC = REF
Guaranteed by design, not tested
CSH = CSL = 5.5V
V+ = 4.5V, CSH = CSL = 4.0V (Note 2)
SYNC = 0 or 5V
Falling edge
0 < IREF < 100µA
SYNC = REF
SHDN = 0V, CSL = 5.5V, CSH = 5.5V, V+ = 0 or 30V,
VL = 0V
CONDITIONS
0.1 µA
3.0
No external load (Note 1)
Input Current
2.0 V
VL - 0.5
Input High Voltage
%
98 99
97 98
Dropout-Mode Maximum Duty
Cycle
kHz190 340Oscillator Sync Range ns200SYNC Rise/Fall Time ns200SYNC Low Pulse Width ns200SYNC High Pulse Width 125 150 175 kHz
270 300 330
Oscillator Frequency
2.46 2.50 2.54
1 2Quiescent Power Consumption 1 8Dropout Power Consumption
515
V+ Shutdown Current
V2.0 2.4Reference Fault Lockout Voltage mV15Reference Load Regulation
µA0.1 1
CSL, CSH Shutdown Leakage
Current
UNITSMIN TYP MAXPARAMETER
SHDN = 0V, V+ = 30V, CSL = 0 or 5.5V
FB = CSH = CSL = 5.5V, VL switched over to CSLV+ Off-State Leakage Current
DL forced to 2V
FB, FB = REF
CSH, CSL, CSH = CSL ≤4V
SYNC, SKIP
A1DL Sink/Source Current ±0.1
70
1.0
SHDN, SKIP
SYNC 0.5 V
0.8
Input Low Voltage
DH forced to 2V, BST - LX = 4.5V A1DH Sink/Source Current
High or low, BST - LX = 4.5V
High or low Ω1.5 5DH On-Resistance Ω1.5 5DL On-Resistance
Reference Output Voltage V
OSCILLATOR AND INPUTS/OUTPUTS
3 7
515 µA
µA
mW
mW
V
MAX1652–MAX1655
High-Efficiency, PWM, Step-Down
DC-DC Controllers in 16-Pin QSOP
4 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(V+ = +15V, GND = PGND = 0V, SYNC = REF, IVL = IREF = 0A, TA= -40°C to +85°C, unless otherwise noted.) (Note 3)
Note 3: Specifications from 0°C to -40°C are guaranteed by design, not production tested.
0 < (CSH - CSL) < 70mV, FB = VL, 4.5V < V+ < 30V,
includes line and load regulation
0 < (CSH - CSL) < 70mV, FB = VL, 6V < V+ < 30V,
includes line and load regulation
CONDITIONS
V3.16 3.503.3V Output Voltage (CSL)
V4.5 30Input Supply Range
V4.80 5.305V Output Voltage (CSL)
UNITSMIN TYP MAXPARAMETER
CSH - CSL, negative
CSH - CSL, positive -40 -160
Current-Limit Voltage
V
0.96 1.04
Feedback Voltage 2.40 2.60
mV
70 130
FB = CSH = CSL = 5.5V, VL switched over to CSL
SHDN = 0V, V+ = 30V, CSL = 0 or 5.5V
Rising edge, hysteresis = 60mV
No external load (Note 1)
0 < IREF < 100µA
µA15V+ Off-State Leakage Current µA10V+ Shutdown Current
V
Rising edge, hysteresis = 50mV
SHDN = 2V, 0 < IVL < 25mA, 5.5V < V+ < 30V
4.2 4.7VL/CSL Switchover Voltage V2.43 2.57Reference Output Voltage
Falling edge, hysteresis = 22mV (MAX1652)
Falling edge, hysteresis = 22mV (MAX1654)
mV15Reference Load Regulation
V3.75 4.05VL Fault Lockout Voltage V4.7 5.3VL Output Voltage
2.40 2.60 V
-0.08 0.08
SECFB Regulation Setpoint
SYNC = REF
SYNC = 0 or 5V
97 kHz210 320Oscillator Sync Range
kHz
SYNC = REF 120 180
Oscillator Frequency
ns250SYNC High Pulse Width ns250SYNC Low Pulse Width
250 350
mW2Quiescent Power Consumption
High or low, BST - LX = 4.5V
High or low
SYNC = 0 or 5V
Ω5DH On-Resistance Ω5DL On-Resistance
%
98
Maximum Duty Cycle
CSH - CSL = 0V, 5V < V+ < 30V,
CSL = FB, SKIP = 0V
6V < V+ < 30V %/V0.06Line Regulation
3.3V and 5V STEP-DOWN CONTROLLERS
FLYBACK/PWM CONTROLLER
INTERNAL REGULATOR AND REFERENCE
OSCILLATOR AND INPUTS/OUTPUTS
MAX1652/MAX1653/
MAX1654
MAX1655
MAX1652–MAX1655
High-Efficiency, PWM, Step-Down
DC-DC Controllers in 16-Pin QSOP
_______________________________________________________________________________________ 5
SHDN
DH
+12V
OUTPUT
+5V
OUTPUT
INPUT
6V TO 30V
BST
LX
DL
PGND
CSH
CSL
SS
REF
SYNC
GND
V+
VL
FB
SECFB
MAX1652
MAX1653
MAX1655
SHDN
DH
+3.3V
OUTPUT
INPUT
4.5V TO 30V
BST
LX
DL
PGND
CSH
CSL
SS
REF
SYNC
GND
SKIP FB
V+ VL
Typical Operating Circuits
__________________________________________Typical Operating Characteristics
(Circuit of Figure 1, SKIP = GND, TA = +25°C, unless otherwise noted.)
100
500.001 0.1 10.01 10
EFFICIENCY vs.
LOAD CURRENT (3.3V/1A CIRCUIT)
60
MAX1652 toc01
LOAD CURRENT (A)
EFFICIENCY (%)
70
80
90 V+ = 6V
MAX1653
f = 300kHz
V+ = 28V
V+ = 12V
100
500.001 0.1 10.01 10
EFFICIENCY vs.
LOAD CURRENT (3.3V/2A CIRCUIT)
60
MAX1652 toc02
LOAD CURRENT (A)
EFFICIENCY (%)
70
80
90 V+ = 6V
V+ = 28V
V+ = 12V
MAX1653
f = 300kHz
100
500.001 0.1 10.01 10
EFFICIENCY vs.
LOAD CURRENT (3.3V/3A CIRCUIT)
60
MAX1652 toc03
LOAD CURRENT (A)
EFFICIENCY (%)
70
80
90 V+ = 6V
V+ = 28V
V+ = 12V
MAX1653
f = 300kHz
MAX1652–MAX1655
High-Efficiency, PWM, Step-Down
DC-DC Controllers in 16-Pin QSOP
6 _______________________________________________________________________________________
MAX1654
SHDN
DH
-5V
OUTPUT
+5V
OUTPUT
INPUT
6V TO 30V
BST
LX
DL
PGND
CSH
CSL
SS
REF
FROM
REF
SYNC
GND
V+
VL
FB
SECFB
Typical Operating Circuits (continued)
MAX1652–MAX1655
High-Efficiency, PWM, Step-Down
DC-DC Controllers in 16-Pin QSOP
_______________________________________________________________________________________
7
100
500.001 0.1 10.01 10
EFFICIENCY vs.
LOAD CURRENT (5V/3A CIRCUIT)
60
MAX1652 toc04a
LOAD CURRENT (A)
EFFICIENCY (%)
70
80
90
V+ = 28V
V+ = 6V
V+ = 12V
MAX1653
f = 300kHz
____________________________________Typical Operating Characteristics (continued)
(Circuit of Figure 1, SKIP = GND, TA = +25°C, unless otherwise noted.)
100
500.001 0.1 10.01 10
EFFICIENCY vs.
LOAD CURRENT (3.3V/5A CIRCUIT)
60
MAX1652 toc04
LOAD CURRENT (A)
EFFICIENCY (%)
70
80
90 V+ = 6V
V+ = 28V
V+ = 12V MAX1653
f = 300kHz
0
10
5
20
15
25
30
0 10 155 20 25 30
PWM-MODE SUPPLY CURRENT vs.
INPUT VOLTAGE (3.3V/3A CIRCUIT)
MAX1652 toc07
INPUT VOLTAGE (V)
SUPPLY CURRENT (mA)
MAX1653
SKIP = VL
f = 300kHz
NO LOAD
100
500.001 0.1 10.01 10
EFFICIENCY vs.
LOAD CURRENT (1.8V/2.5A CIRCUIT)
60
MAX1652 toc05
LOAD CURRENT (A)
EFFICIENCY (%)
70
80
90 V+ = 6V
V+ = 24V
V+ = 12V
MAX1655
f = 300kHz
0
4
2
6
8
10
0 10 155 20 25 30
SHUTDOWN SUPPLY CURRENT
vs. INPUT VOLTAGE
MAX1652 toc08
INPUT VOLTAGE (V)
SUPPLY CURRENT (µA)
SHDN = 0V
0
10
5
20
15
25
30
0 100 15050 200 250 300 350 400
REF LOAD-REGULATION ERROR
vs. REF LOAD CURRENT
MAX1652 toc010
LOAD CURRENT (µA)
LOAD REGULATION ∆V (mV)
0
300
900
600
1200
1500
0 10 155 20 25 30
MAX1652 MAXIMUM SECONDARY OUTPUT
CURRENT vs. SUPPLY VOLTAGE
MAX1652 toc12
SUPPLY VOLTAGE (V)
MAXIMUM SECONDARY CURRENT (mA)
VSEC > 12.75V,
+5V OUTPUT > 4.75V,
CIRCUIT OF FIGURE 9
+5V LOAD = 0A
+5V LOAD = 3A
OUTPUT
VOLTAGE
LOAD
CURRENT
100mV/div,
AC
2A/div
TIME (10µs)
VIN = 15V, 3.3V/3A CIRCUIT
LOAD-TRANSIENT RESPONSE
MAX1652-16
OUTPUT
VOLTAGE
LX
VOLTAGE
10mV/div,
AC
5V/div
TIME (5µs)
VIN = 5.1V, NO LOAD, 3.3V/3A CIRCUIT,
SET TO 5V OUTPUT (FB = VL)
DROPOUT WAVEFORMS
MAX1652-15
MAX1652–MAX1655
High-Efficiency, PWM, Step-Down
DC-DC Controllers in 16-Pin QSOP
8 _______________________________________________________________________________________
OUTPUT
VOLTAGE
LX
VOLTAGE
10mV/div,
AC
5V/div
TIME (1µs)
VIN = 6V, 3.3V/3A CIRCUIT
PULSE-WIDTH-MODULATION
MODE WAVEFORMS
MAX1652-13
OUTPUT
VOLTAGE
LX
VOLTAGE
50mV/div,
AC
5V/div
TIME (2.5µs)
ILOAD = 300mA, VIN = 10V, 3.3V/3A CIRCUIT
IDLE-MODE WAVEFORMS
MAX1652-14
Typical Operating Characteristics (continued)
(Circuit of Figure 1, SKIP = GND, TA = +25°C, unless otherwise noted.)
00.01 1010.1
DROPOUT VOLTAGE vs.
LOAD CURRENT (3.3V/3A CIRCUIT)
100
300
400
200
500
MAX1652 toc09
LOAD CURRENT (A)
DROPOUT VOLTAGE (mV)
OUTPUT SET FOR 5V (FB = VL)
VOUT > 4.85V
f = 150kHz
f = 300kHz
MAX1652–MAX1655
High-Efficiency, PWM, Step-Down
DC-DC Controllers in 16-Pin QSOP
_______________________________________________________________________________________ 9
Pin Description
Dual Mode is a trademark of Maxim Integrated Products.
SKIP
(MAX1653/
MAX1655)
Disables pulse-skipping mode when high. Connect to GND for normal use. Don’t leave SKIP unconnected.
With SKIP grounded, the device will
automatically
change from pulse-skipping operation to full PWM opera-
tion when the load current exceeds approximately 30% of maximum (Table 3).
16 DH High-Side Gate-Drive Output. Normally drives the main buck switch. DH is a floating driver output that swings
from LX to BST, riding on the LX switching-node voltage.
15 LX Switching Node (inductor) Connection. Can swing 2V below ground without hazard.
14 BST Boost Capacitor Connection for High-Side Gate Drive (0.1µF)
13 DL Low-Side Gate-Drive Output. Normally drives the synchronous-rectifier MOSFET. Swings from 0V to VL.
NAME FUNCTION
1SS Soft-Start Timing Capacitor Connection. Ramp time to full current limit is approximately 1ms/nF.
2
SECFB
(MAX1652/
MAX1654)
Secondary Winding Feedback Input. Normally connected to a resistor divider from an auxiliary output.
Don’t leave SECFB unconnected.
•MAX1652: SECFB regulates at VSECFB = 2.50V. Tie to VL if not used.
•MAX1654: SECFB regulates at VSECFB = 0V. Tie to a negative voltage through a high-value current-
limiting resistor (IMAX = 100µA) if not used.
PIN
3 REF Reference Voltage Output. Bypass to GND with 0.33µF minimum.
7 FB
Feedback Input. Regulates at the feedback voltage in adjustable mode. FB is a Dual ModeTM input that also
selects the fixed output voltage settings as follows:
•Connect to GND for 3.3V operation.
•Connect to VL for 5V operation.
•Connect FB to a resistor divider for adjustable mode. FB can be driven with +5V CMOS logic in order to
change the output voltage under system control.
6 SHDN Shutdown Control Input, active low. Logic threshold is set at approximately 1V (VTH of an internal N-channel
MOSFET). Tie SHDN to V+ for automatic start-up.
5 SYNC Oscillator Synchronization and Frequency Select. Tie to GND or VL for 150kHz operation; tie to REF for
300kHz operation. A high-to-low transition begins a new cycle. Drive SYNC with 0 to 5V logic levels (see the
Electrical Characteristics
table for VIH and VIL specifications). SYNC capture range is 190kHz to 340kHz.
4 GND Low-Noise Analog Ground and Feedback Reference Point
12 PGND Power Ground
11 VL 5V Internal Linear-Regulator Output. VL is also the supply voltage rail for the chip. VL is switched to the out-
put voltage via CSL (VCSL > 4.5V) for automatic bootstrapping. Bypass to GND with 4.7µF. VL can supply up
to 5mA for external loads.
10 V+ Battery Voltage Input (4.5V to 30V). Bypass V+ to PGND close to the IC with a 0.1µF capacitor. Connects to a
linear regulator that powers VL.
9 CSL Current-Sense Input, low side. Also serves as the feedback input in fixed-output modes.
8 CSH Current-Sense Input, high side. Current-limit level is 100mV referred to CSL.
MAX1652–MAX1655
High-Efficiency, PWM, Step-Down
DC-DC Controllers in 16-Pin QSOP
10 ______________________________________________________________________________________
Standard Application Circuits
It’s easy to adapt the basic MAX1653 single-output 3.3V
buck converter (Figure 1) to meet a wide range of appli-
cations with inputs up to 30V (limited by choice of exter-
nal MOSFET). Simply substitute the appropriate
components from Table 1 (candidate suppliers are pro-
vided in Table 2). These circuits represent a good set of
trade-offs among cost, size, and efficiency while staying
within the worst-case specification limits for stress-relat-
ed parameters such as capacitor ripple current.
Don’t change the frequency of these circuits without
first recalculating component values (particularly induc-
tance value at maximum battery voltage).
For a discussion of dual-output circuits using the
MAX1652 and MAX1654, see Figure 9 and the
Secondary Feedback-Regulation Loop
section.
Detailed Description
The MAX1652 family are BiCMOS, switch-mode power-
supply controllers designed primarily for buck-topology
regulators in battery-powered applications where high
efficiency and low quiescent supply current are critical.
The parts also work well in other topologies such as
boost, inverting, and Cuk due to the flexibility of their
floating high-speed gate driver. Light-load efficiency is
enhanced by automatic idle-mode operation—a vari-
able-frequency pulse-skipping mode that reduces
losses due to MOSFET gate charge. The step-down
power-switching circuit consists of two N-channel
MOSFETs, a rectifier, and an LC output filter. The out-
put voltage is the average of the AC voltage at the
switching node, which is adjusted and regulated by
changing the duty cycle of the MOSFET switches. The
gate-drive signal to the N-channel high-side MOSFET
must exceed the battery voltage and is provided by a
flying capacitor boost circuit that uses a 100nF capaci-
tor connected to BST.
MAX1653
CSL
CSH
VL
SYNC
FB
V+
10 11
57
14 Q1
Q2
16
15
13
D2
CMPSH-3
J1
150kHz/300kHz
JUMPER
NOTE: KEEP CURRENT-SENSE
LINES SHORT AND CLOSE
TOGETHER. SEE FIGURE 8.
D1
12
8
9
REF 3
GND 4
+5V AT
5mA
+3.3V
OUTPUT
GND
OUT
BST
DH
LX
DL
2
1
LOW-NOISE
CONTROL
PGND
SKIP
SS
6
ON/OFF
CONTROL SHDN
INPUT
REF OUTPUT
+2.5V AT 100µA
C5
0.33µF
C4
4.7µF
C7
0.1µF
C6
0.01µF
(OPTIONAL)
C1
C2
C3
0.1µF
R1
L1
Figure 1. Standard 3.3V Application Circuit (see Table 1 for Component Values)
MAX1652–MAX1655
High-Efficiency, PWM, Step-Down
DC-DC Controllers in 16-Pin QSOP
______________________________________________________________________________________ 11
Table 1. Component Selection for Standard Applications
COMPONENT 3.3V at 1A 3.3V at 2A 5V/3.3V at 3A 3.3V at 5A 1.8V at 2.5A
Frequency 300kHz 300kHz 300kHz 300kHz 150kHz
Q1 High-Side
MOSFET International Rectifier
1/2 IRF7101
International Rectifier
1/2 IRF7303 or
Fairchild
Semiconductor
1/2 NDS8936
International Rectifier
IRF7403 or
Fairchild
Semiconductor
NDS 8410A
Fairchild
Semiconductor
FDS6680
International Rectifier
1/2 IRF7303 or
Fairchild
Semiconductor
1/2 NDS8936
Q2 Low-Side
MOSFET International Rectifier
1/2 IRF7101
International Rectifier
1/2 IRF7303 or
Fairchild
Semiconductor
1/2 NDS8936
International Rectifier
IRF7403 or
Fairchild
Semiconductor
NDS 8410A
Fairchild
Semiconductor
FDS6680
International Rectifier
1/2 IRF7303 or
Fairchild
Semiconductor
1/2 NDS8936
C1 Input
Capacitor
10µF, 35V
AVX
TPSD106M035R0300
22µF, 35V
AVX
TPSE226M035R0300
(2) 22µF, 35V
AVX
TPSE226M035R0300
(3) 22µF, 35V
AVX
TPSE226M035R0300
10µF, 25V ceramic
Taiyo Yuden
TMK325F106Z
C2 Output
Capacitor 100µF, 6.3V
AVX TPSC107M006R
220µF, 10V
AVX
TPSE227M010R0100
or Sprague
594D227X001002T
470µF, 6V (for 3.3V)
Kemet
T510X477M006AS
or
(2) 220µF, 10V (for 5V)
AVX
TPSE227M010R011
(3) 330µF, 10V
Sprague
594D337X0010R2T
or
(2) 470µF, 6V
Kemet
T510X477M006AS
470µF, 4V
Sprague
594D477X0004R2T
or
470µF, 6V
Kemet
T510X477M006AS
D1 Rectifier 1N5819 or Motorola
MBR0520L 1N5819 or Motorola
MBRS130LT3 1N5819 or Motorola
MBRS130LT3 1N5821 or Motorola
MBRS340T3 1N5817 or Motorola
MBRS130LT3
R1 Sense
Resistor
70mΩ
Dale WSL-1206-R070F
or IRC LR2010-01-R070
33mΩ
Dale WSL-2010-R033F
or IRC LR2010-01-R033
25mΩ
Dale WSL-2010-R025F
or IRC LR2010-01-R025
12mΩ
Dale WSL-2512-R012F
30mΩ
Dale WSL-2010-R030F
or IRC LR2010-01-R030
L1 Inductor 33µH
Sumida CDR74B-330 15µH
Sumida CDR105B-150 10µH
Sumida CDRH125-100 4.7µH
Sumida CDRH127-4R7 15µH
Sumida CDRH125-150
Table 2. Component Suppliers
*
Distributor
[1] 602-994-6430602-303-5454Motorola
[1] 408-986-1442408-986-0424Kemet [1] 512-992-3377512-992-7900IRC
[1] 408-721-1635408-822-2181Fairchild [1] 605-665-1627605-668-4131Dale [1] 561-241-9339561-241-7876Coiltronics [1] 847-639-1469847-639-6400Coilcraft [1] 516-435-1824516-435-1110Central Semiconductor [1] 803-626-3123803-946-0690AVX
FACTORY FAX
[Country Code]
USA PHONEMANUFACTURER
Input Range 4.75V to 28V 4.75V to 28V 4.75V to 28V 4.75V to 28V 4.75V to 22V
[1] 408-573-4159408-573-4150Taiyo Yuden [81] 3-3607-5144847-956-0666Sumida [1] 603-224-1430603-224-1961Sprague
[1] 408-970-3950
408-988-8000
800-554-5565
Siliconix
[81] 7-2070-1174619-661-6835Sanyo [81] 3-3494-7414805-867-2555*NIEC
[1] 814-238-0490
814-237-1431
800-831-9172
Murata
FACTORY FAX
[Country Code]
USA PHONEMANUFACTURER
[1] 702-831-3521702-831-0140Transpower Technologies
[1] 714-960-6492714-969-2491Matsuo
[1] 310-322-3332310-322-3331International Rectifier
[1] 847-390-4405847-390-4461TDK
MAX1652–MAX1655
High-Efficiency, PWM, Step-Down
DC-DC Controllers in 16-Pin QSOP
12 ______________________________________________________________________________________
The MAX1652–MAX1655 contain nine major circuit
blocks, which are shown in Figure 2:
PWM Controller Blocks:
•Multi-Input PWM Comparator
•Current-Sense Circuit
•PWM Logic Block
•Dual-Mode Internal Feedback Mux
•Gate-Driver Outputs
•Secondary Feedback Comparator
Bias Generator Blocks:
•+5V Linear Regulator
•Automatic Bootstrap Switchover Circuit
•+2.50V Reference
These internal IC blocks aren’t powered directly from
the battery. Instead, a +5V linear regulator steps down
the battery voltage to supply both the IC internal rail (VL
pin) as well as the gate drivers. The synchronous-
switch gate driver is directly powered from +5V VL,
while the high-side-switch gate driver is indirectly pow-
ered from VL via an external diode-capacitor boost cir-
cuit. An automatic bootstrap circuit turns off the +5V
linear regulator and powers the IC from its output volt-
age if the output is above 4.5V.
PWM Controller Block
The heart of the current-mode PWM controller is a
multi-input open-loop comparator that sums three sig-
nals: output voltage error signal with respect to the ref-
erence voltage, current-sense signal, and slope
compensation ramp (Figure 3). The PWM controller is a
direct summing type, lacking a traditional error amplifi-
er and the phase shift associated with it. This direct-
summing configuration approaches the ideal of
cycle-by-cycle control over the output voltage.
Under heavy loads, the controller operates in full PWM
mode. Each pulse from the oscillator sets the main
PWM latch that turns on the high-side switch for a peri-
od determined by the duty factor (approximately
VOUT/VIN). As the high-side switch turns off, the syn-
chronous rectifier latch is set. 60ns later the low-side
switch turns on, and stays on until the beginning of the
next clock cycle (in continuous mode) or until the
inductor current crosses zero (in discontinuous mode).
Under fault conditions where the inductor current
exceeds the 100mV current-limit threshold, the high-
side latch resets and the high-side switch turns off.
If the load is light in Idle Mode (SKIP = low), the induc-
tor current does not exceed the 25mV threshold set by
the Idle Mode comparator. When this occurs, the con-
troller skips most of the oscillator pulses in order to
reduce the switching frequency and cut back gate-
charge losses. The oscillator is effectively gated off at
light loads because the Idle Mode comparator immedi-
ately resets the high-side latch at the beginning of each
cycle, unless the feedback signal falls below the refer-
ence voltage level.
When in PWM mode, the controller operates as a fixed-
frequency current-mode controller where the duty ratio
is set by the input/output voltage ratio. The current-
mode feedback system regulates the peak inductor
current as a function of the output voltage error signal.
Since the average inductor current is nearly the same
as the peak current, the circuit acts as a switch-mode
transconductance amplifier and pushes the second out-
put LC filter pole, normally found in a duty-factor-
controlled (voltage-mode) PWM, to a higher frequency.
To preserve inner-loop stability and eliminate regenera-
tive inductor current “staircasing,” a slope-compensa-
tion ramp is summed into the main PWM comparator to
reduce the apparent duty factor to less than 50%.
The relative gains of the voltage- and current-sense
inputs are weighted by the values of current sources
that bias three differential input stages in the main PWM
comparator (Figure 4). The relative gain of the voltage
comparator to the current comparator is internally fixed
at K = 2:1. The resulting loop gain (which is relatively
low) determines the 2% typical load regulation error.
The low loop-gain value helps reduce output filter
capacitor size and cost by shifting the unity-gain
crossover to a lower frequency.
The output filter capacitor C2 sets a dominant pole in
the feedback loop. This pole must roll off the loop gain
to unity before the zero introduced by the output
capacitor’s parasitic resistance (ESR) is encountered
(see
Design Procedure
section). A 12kHz pole-zero
cancellation filter provides additional rolloff above the
unity-gain crossover. This internal 12kHz lowpass com-
pensation filter cancels the zero due to the filter capaci-
tor’s ESR. The 12kHz filter is included in the loop in
both fixed- and adjustable-output modes.
Synchronous-Rectifier Driver (DL Pin)
Synchronous rectification reduces conduction losses in
the rectifier by shunting the normal Schottky diode with
a low-resistance MOSFET switch. The synchronous rec-
tifier also ensures proper start-up of the boost-gate driv-
er circuit. If you must omit the synchronous power
MOSFET for cost or other reasons, replace it with a
small-signal MOSFET such as a 2N7002.
If the circuit is operating in continuous-conduction mode,
the DL drive waveform is simply the complement of the
DH high-side drive waveform (with controlled dead
time to prevent cross-conduction or “shoot-through”).
MAX1652–MAX1655
High-Efficiency, PWM, Step-Down
DC-DC Controllers in 16-Pin QSOP
______________________________________________________________________________________ 13
MAX1652
MAX1653
MAX1654
MAX1655
1V
CSL
CSH
REF
GND
4V
FB
ADJ FB
5V FB
3.3V FB
SYNC
LPF
12kHz
PWM
COMPARATOR
OUT
V+
BATTERY VOLTAGE
4.5V VL
TO
CSL
+5V AT 5mA
BST
DH
LX
DL
PGND
SECFB
MAIN
OUTPUT
AUXILIARY
OUTPUT
SHDN
PWM
LOGIC
SHDN
SS
ON/OFF
+2.50V
AT 100µA
+5V LINEAR
REGULATOR
+2.50V
REF
Figure 2. MAX1652–MAX1655 Functional Diagram
MAX1652–MAX1655
High-Efficiency, PWM, Step-Down
DC-DC Controllers in 16-Pin QSOP
14 ______________________________________________________________________________________
SHOOT-
THROUGH
CONTROL
RQ
25mV
RQLEVEL
SHIFT
1µs
SINGLE-SHOT
MAIN PWM
COMPARATOR
OSC
LEVEL
SHIFT
CURRENT
LIMIT
VL
24R
1R
2.5V
4µA
SYNCHRONOUS-
RECTIFIER CONTROL
2.5V (1V, MAX1655)
SS
SHDN
-100mV
(NOTE 1)
COMPARATOR
CSH
CSL
FROM
FEEDBACK
DIVIDER
BST
DH
LX
VL
DL
PGND
S
S
SLOPE COMP
IDLE MODE
COMPARATOR
N
SKIP
(MAX1653/
MAX1655
ONLY)
REF (MAX1652)
GND (MAX1654)
MAX1652, MAX1654 ONLY
SECFB
NOTE 1: COMPARATOR INPUT POLARITIES
ARE REVERSED FOR THE MAX1654.
Figure 3. PWM Controller Detailed Block Diagram
MAX1652–MAX1655
High-Efficiency, PWM, Step-Down
DC-DC Controllers in 16-Pin QSOP
______________________________________________________________________________________ 15
In discontinuous (light-load) mode, the synchronous
switch is turned off as the inductor current falls through
zero. The synchronous rectifier works under all operat-
ing conditions, including idle mode. The synchronous-
switch timing is further controlled by the secondary
feedback (SECFB) signal in order to improve multiple-
output cross-regulation (see
Secondary Feedback-
Regulation Loop
section).
Internal VL and REF Supplies
An internal regulator produces the 5V supply (VL) that
powers the PWM controller, logic, reference, and other
blocks. This +5V low-dropout linear regulator can sup-
ply up to 5mA for external loads, with a reserve of
20mA for gate-drive power. Bypass VL to GND with
4.7µF. Important: VL must not be allowed to exceed
5.5V. Measure VL with the main output fully loaded. If
VL is being pumped up above 5.5V, the probable
cause is either excessive boost-diode capacitance or
excessive ripple at V+. Use only small-signal diodes for
D2 (10mA to 100mA Schottky or 1N4148 are preferred)
and bypass V+ to PGND with 0.1µF directly at the
package pins.
The 2.5V reference (REF) is accurate to ±1.6% over
temperature, making REF useful as a precision system
reference. Bypass REF to GND with 0.33µF minimum.
REF can supply up to 1mA for external loads. However,
if tight-accuracy specs for either VOUT or REF are
essential, avoid loading REF with more than 100µA.
Loading REF reduces the main output voltage slightly,
according to the reference-voltage load regulation
error. In MAX1654 applications, ensure that the SECFB
divider doesn’t load REF heavily.
When the main output voltage is above 4.5V, an internal
P-channel MOSFET switch connects CSL to VL while
simultaneously shutting down the VL linear regulator.
This action bootstraps the IC, powering the internal cir-
cuitry from the output voltage, rather than through a lin-
ear regulator from the battery. Bootstrapping reduces
power dissipation caused by gate-charge and quies-
cent losses by providing that power from a 90%-effi-
cient switch-mode source, rather than from a less
efficient linear regulator.
It’s often possible to achieve a bootstrap-like effect,
even for circuits that are set to VOUT < 4.5V, by power-
ing VL from an external-system +5V supply. To achieve
this pseudo-bootstrap, add a Schottky diode between
the external +5V source and VL, with the cathode to the
VL side. This circuit provides a 1% to 2% efficiency
boost and also extends the minimum battery input to
less than 4V. The external source must be in the range
of 4.8V to 5.5V.
Boost High-Side
Gate-Driver Supply (BST Pin)
Gate-drive voltage for the high-side N-channel switch is
generated by a flying-capacitor boost circuit as shown
in Figure 5. The capacitor is alternately charged from
the VL supply and placed in parallel with the high-side
MOSFET’s gate-source terminals.
On start-up, the synchronous rectifier (low-side MOS-
FET) forces LX to 0V and charges the BST capacitor to
5V. On the second half-cycle, the PWM turns on the
high-side MOSFET by closing an internal switch
between BST and DH. This provides the necessary
enhancement voltage to turn on the high-side switch,
FB
REF
CSH
CSL
SLOPE COMPENSATION
VL
I1
R1 R2
TO PWM
LOGIC
OUTPUT DRIVER
UNCOMPENSATED
HIGH-SPEED
LEVEL TRANSLATOR
AND BUFFER
I2 I3
Figure 4. Main PWM Comparator Block Diagram
MAX1652–MAX1655
High-Efficiency, PWM, Step-Down
DC-DC Controllers in 16-Pin QSOP
16 ______________________________________________________________________________________
an action that “boosts” the 5V gate-drive signal above
the battery voltage.
Ringing seen at the high-side MOSFET gate (DH) in
discontinuous-conduction mode (light loads) is a natur-
al operating condition caused by the residual energy in
the tank circuit formed by the inductor and stray capac-
itance at the switching node LX. The gate-driver nega-
tive rail is referred to LX, so any ringing there is directly
coupled to the gate-drive output.
Current-Limiting and
Current-Sense Inputs (CSH and CSL)
The current-limit circuit resets the main PWM latch and
turns off the high-side MOSFET switch whenever the
voltage difference between CSH and CSL exceeds
100mV. This limiting is effective for both current flow
directions, putting the threshold limit at ±100mV. The
tolerance on the positive current limit is ±20%, so the
external low-value sense resistor must be sized for
80mV/R1 to guarantee enough load capability, while
components must be designed to withstand continuous
current stresses of 120mV/R1.
For breadboarding purposes or very-high-current appli-
cations, it may be useful to wire the current-sense inputs
with a twisted pair rather than PC traces.
Oscillator Frequency and
Synchronization (SYNC Pin)
The SYNC input controls the oscillator frequency.
Connecting SYNC to GND or to VL selects 150kHz
operation; connecting SYNC to REF selects 300kHz.
SYNC can also be used to synchronize with an external
5V CMOS clock generator. SYNC has a guaranteed
190kHz to 340kHz capture range.
300kHz operation optimizes the application circuit for
component size and cost. 150kHz operation provides
increased efficiency and improved low-duty factor
operation (see
Dropout Operation
section).
Dropout Operation
Dropout (low input-output differential operation) is en-
hanced by stretching the clock pulse width to increase
the maximum duty factor. The algorithm follows: if the out-
put voltage (VOUT) drops out of regulation without the
current limit having been reached, the controller skips an
off-time period (extending the on-time). At the end of the
cycle, if the output is still out of regulation, another off-time
period is skipped. This action can continue until three off-
time periods are skipped, effectively dividing the clock
frequency by as much as four.
The typical PWM minimum off-time is 300ns, regardless
of the operating frequency. Lowering the operating fre-
quency raises the maximum duty factor above 98%.
Low-Noise Mode (SKIP Pin)
The low-noise mode (SKIP = high) is useful for minimiz-
ing RF and audio interference in noise-sensitive appli-
cations such as audio-equipped systems, cellular
phones, RF communicating computers, and electro-
magnetic pen-entry systems. See the summary of oper-
ating modes in Table 3. SKIP can be driven from an
external logic signal.
The MAX1653 and MAX1655 can reduce interference
due to switching noise by ensuring a constant switch-
ing frequency regardless of load and line conditions,
thus concentrating the emissions at a known frequency
outside the system audio or IF bands. Choose an oscil-
lator frequency where harmonics of the switching fre-
quency don’t overlap a sensitive frequency band. If
necessary, synchronize the oscillator to a tight-toler-
ance external clock generator.
The low-noise mode (SKIP = high) forces two changes
upon the PWM controller. First, it ensures fixed-frequen-
cy operation by disabling the minimum-current com-
parator and ensuring that the PWM latch is set at the
beginning of each cycle, even if the output is in regula-
tion. Second, it ensures continuous inductor current
MAX1652
MAX1653
MAX1654
MAX1655
BST
VL
+5V
VL SUPPLY BATTERY
INPUT
VL
VL
DH
LX
DL
PWM
LEVEL
TRANSLATOR
Figure 5. Boost Supply for Gate Drivers
MAX1652–MAX1655
High-Efficiency, PWM, Step-Down
DC-DC Controllers in 16-Pin QSOP
______________________________________________________________________________________ 17
flow, and thereby suppresses discontinuous-mode
inductor ringing by changing the reverse current-limit
detection threshold from 0 to -100mV, allowing the
inductor current to reverse at very light loads.
In most applications, SKIP should be tied to GND in
order to minimize quiescent supply current. Supply cur-
rent with SKIP high is typically 10mA to 20mA, depend-
ing on external MOSFET gate capacitance and
switching losses.
Forced continuous conduction via SKIP can improve
cross regulation of transformer-coupled multiple-output
supplies. This second function of the SKIP pin produces
a result that is similar to the method of adding sec-
ondary regulation via the SECFB feedback pin, but with
much higher quiescent supply current. Still, improving
cross regulation by enabling SKIP instead of building in
SECFB feedback can be useful in noise-sensitive appli-
cations, since SECFB and SKIP are mutually exclusive
pins/functions in the MAX1652 family.
Adjustable-Output Feedback
(Dual-Mode FB Pin)
The MAX1652–MAX1655 family has both fixed and
adjustable output voltage modes. For fixed mode, con-
nect FB to GND for a 3.3V output and to VLfor a 5V out-
put. Adjusting the main output voltage with external
resistors is easy for any of the devices in this family, via
the circuit of Figure 6. The feedback voltage is nominal-
ly 2.5 for all family members except the MAX1655,
which has a nominal FB voltage of 1V. The output volt-
age (given by the formula in Figure 6) should be set
approximately 2% high in order to make up for the
MAX1652’s load-regulation error. For example, if
designing for a 3.0V output, use a resistor ratio that
results in a nominal output voltage of 3.06V. This slight
offsetting gives the best possible accuracy.
Recommended normal values for R5 range from 5kΩto
100kΩ.
Remote sensing of the output voltage, while not possi-
ble in fixed-output mode due to the combined nature of
the voltage- and current-sense input (CSL), is easy to
achieve in adjustable mode by using the top of the
external resistor divider as the remote sense point.
Duty-Factor Limitations for
Low V
OUT
/V
IN
Ratios
The MAX1652/MAX1653/MAX1654’s output voltage is
adjustable down to 2.5V and the MAX1655’s output is
adjustable as low as 1V. However, the minimum duty
factor may limit the choice of operating frequency, high
input voltage, and low output voltage.
MAX1652
MAX1653
MAX1654
MAX1655
CSL
CSH
GND FB
R4
R5
MAIN
OUTPUT
REMOTE
SENSE
LINES
DH
DL
VOUT
WHERE VREF (NOMINAL) = 2.5V (MAX1652–MAX1654)
= 1.0V (MAX1655)
= VREF (1 + –––)
R4
R5
V+
Figure 6. Adjusting the Main Output Voltage
SHDN SKIP LOAD
CURRENT MODE
NAME DESCRIPTION
Low X X Shutdown All circuit blocks
turned off; supply
current = 3µA typ
High Low Low,
<10% Idle
Pulse-skipping;
supply current =
300µA typ at VIN =
10V; discontinuous
inductor current
High Low Medium,
<30% Idle Pulse-skipping;
continuous inductor
current
High Low High,
>30% PWM Constant-frequency
PWM; continuous
inductor current
High High X Low Noise*
(PWM)
Constant-frequency
PWM regardless of
load; continuous
inductor current
even at no load
Table 3. Operating-Mode Truth Table
*
MAX1652/MAX1654 have no SKIP pin and therefore can’t go
into low-noise mode.
X = Don’t care
MAX1652–MAX1655
High-Efficiency, PWM, Step-Down
DC-DC Controllers in 16-Pin QSOP
18 ______________________________________________________________________________________
With high input voltages, the required duty factor is
approximately (VOUT + VQ2)/ VIN, where VQ2 is the volt-
age drop across the synchronous rectifier. The
MAX1652’s minimum duty factor is determined by
delays through the feedback network, error comparator,
internal logic gate drivers, and the external MOSFETs,
which typically total 400ns. This delay is about 12% of
the switching period at 300kHz and 6% at 150kHz, limit-
ing the typical minimum duty factor to these values.
Even if the circuit can not attain the required duty factor
dictated by the input and output voltages, the output
voltage will remain in regulation. However, there may be
intermittent or continuous half-frequency operation. This
can cause a factor-of-two increase in output voltage rip-
ple and current ripple, which will increase noise and
reduce efficiency. Choose 150kHz operation for high-
input-voltage/low-output-voltage circuits.
Secondary Feedback-Regulation Loop
(SECFB Pin)
A flyback winding control loop regulates a secondary
winding output (MAX1652/MAX1654 only), improving
cross-regulation when the primary is lightly loaded
or when there is a low input-output differential voltage.
If SECFB crosses its regulation threshold, a 1µs one-
shot is triggered that extends the low-side switch’s
on-time beyond the point where the inductor current
crosses zero (in discontinuous mode). This causes the
inductor (primary) current to reverse, which in turn pulls
current out of the output filter capacitor and causes the
flyback transformer to operate in the forward mode. The
low impedance presented by the transformer secondary
in the forward mode dumps current into the secondary
output, charging up the secondary capacitor and bring-
ing SECFB back into regulation. The SECFB feedback
loop does not improve secondary output accuracy in
normal flyback mode, where the main (primary) output is
heavily loaded. In this mode, secondary output accura-
cy is determined (as usual) by the secondary rectifier
drop, turns ratio, and accuracy of the main output volt-
age. Hence, a linear post-regulator may still be needed
in order to meet tight output accuracy specifications.
The secondary output voltage-regulation point is deter-
mined by an external resistor-divider at SECFB. For neg-
ative output voltages, the SECFB comparator is
referenced to GND (MAX1654); for positive output volt-
ages, SECFB regulates at the 2.50V reference
(MAX1652). As a result, output resistor-divider connec-
tions and design equations for the two device types dif-
fer slightly (Figure 7). Ordinarily, the secondary
regulation point is set 5% to 10% below the voltage nor-
mally produced by the flyback effect. For example, if the
MAX1654
NEGATIVE
SECONDARY
OUTPUT
MAIN
OUTPUT
DH
V+
SECFB R3
R2
1-SHOT
TRIG
DL
0.33µF
REF
MAX1652
POSITIVE
SECONDARY
OUTPUT
MAIN
OUTPUT
DH
V+
SECFB
2.5V REF
R3
R2
1-SHOT
TRIG
DL
+VTRIP WHERE VREF (NOMINAL) = 2.5V= VREF (1 + –––)
R2
R3 -VTRIP R3 = 100kΩ (RECOMMENDED)= -VREF (–––)
R2
R3
Figure 7. Secondary-Output Feedback Dividers
MAX1652–MAX1655
High-Efficiency, PWM, Step-Down
DC-DC Controllers in 16-Pin QSOP
______________________________________________________________________________________ 19
output voltage as determined by the turns ratio is +15V,
the feedback resistor ratio should be set to produce
about +13.5V; otherwise, the SECFB one-shot might be
triggered unintentionally, causing an unnecessary
increase in supply current and output noise. In negative-
output (MAX1654) applications, the resistor-divider acts
as a load on the internal reference, which in turn can
cause errors at the main output. Avoid overloading REF
(see the Reference Load-Regulation Error vs. Load
Current graph in the
Typical Operating Characteristics
).
100kΩis a good value for R3 in MAX1654 circuits.
Output current on secondary winding applications is
limited at low input voltages. See the MAX1652
Maximum Secondary Output Current vs. Supply Voltage
graph in the Typical Operating Characteristics for data
from the application circuit of Figure 8.
Soft-Start Circuit (SS)
Soft-start allows a gradual increase of the internal cur-
rent-limit level at start-up for the purpose of reducing
input surge currents, and perhaps for power-supply
sequencing. In shutdown mode, the soft-start circuit
holds the SS capacitor discharged to ground. When
SHDN goes high, a 4µA current source charges the SS
capacitor up to 3.2V. The resulting linear ramp wave-
form causes the internal current-limit level to increase
proportionally from 0 to 100mV. The main output capaci-
tor thus charges up relatively slowly, depending on the
SS capacitor value. The exact time of the output rise
depends on output capacitance and load current and is
typically 1ms per nanofarad of soft-start capacitance.
With no SS capacitor connected, maximum current limit
is reached within 10µs.
Shutdown
Shutdown mode (SHDN = 0V) reduces the V+ supply
current to typically 3µA. In this mode, the reference and
VL are inactive. SHDN is a logic-level input, but it can
be safely driven to the full V+ range. Connect SHDN to
V+ for automatic start-up. Do not allow slow transitions
(slower than 0.02V/µs) on SHDN.
MAX1652
FB
GND
REF
SYNC
SECFB VL 10
211
7
35
14
Si9410
Si9410 D2
EC11FS1
T1 = TRANSPOWER TTI5870
* = OPTIONAL, MAY NOT BE NEEDED
16
15
13
D1
CMPSH
-3A
1N5819
12
8
9
VIN (6.5V TO 18V)
+15V AT
250mA
+5V
AT 3A
6
ON/OFF
1
CSL
CSH
BST
V+
DH
LX
DL
PGND
SHDN
SS
0.33µF
C2
4.7µFC3
15µF
2.5V
220µF
10V 220µF
10V
0.1µF
22µF, 35V
22µF, 35V
0.01µF
20mΩ
22Ω*
4700pF*
T1
15µH
2.2:1
49.9k, 1%
210k, 1%
0.01µF
(OPTIONAL)
18V
1/4 W
C2
4.7µF
4
Figure 8. 5V/15V Dual-Output Application Circuit (MAX1652)
MAX1652–MAX1655
High-Efficiency, PWM, Step-Down
DC-DC Controllers in 16-Pin QSOP
20 ______________________________________________________________________________________
__________________Design Procedure
The predesigned standard application circuits (Figure
1 and Table 1) contain ready-to-use solutions for com-
mon applications. Use the following design procedure
to optimize the basic schematic for different voltage or
current requirements. Before beginning a design, firmly
establish the following:
VIN(MAX), the maximum input (battery) voltage. This
value should include the worst-case conditions, such
as no-load operation when a battery charger or AC
adapter is connected but no battery is installed.
VIN(MAX) must not exceed 30V. This 30V upper limit is
determined by the breakdown voltage of the BST float-
ing gate driver to GND (36V absolute maximum).
VIN(MIN), the minimum input (battery) voltage. This
should be at full-load under the lowest battery condi-
tions. If VIN(MIN) is less than 4.5V, a special circuit must
be used to externally hold up VL above 4.8V. If the min-
imum input-output difference is less than 1V, the filter
capacitance required to maintain good AC load regula-
tion increases.
Inductor Value
The exact inductor value isn’t critical and can be
adjusted freely in order to make trade-offs among size,
cost, and efficiency. Although lower inductor values will
minimize size and cost, they will also reduce efficiency
due to higher peak currents. To permit use of the physi-
cally smallest inductor, lower the inductance until the
circuit is operating at the border between continuous
and discontinuous modes. Reducing the inductor value
even further, below this crossover point, results in dis-
continuous-conduction operation even at full load. This
helps reduce output filter capacitance requirements but
causes the core energy storage requirements to
increase again. On the other hand, higher inductor val-
ues will increase efficiency, but at some point resistive
losses due to extra turns of wire will exceed the benefit
gained from lower AC current levels. Also, high induc-
tor values affect load-transient response; see the VSAG
equation in the
Low-Voltage Operation
section.
The following equations are given for continuous-conduc-
tion operation since the MAX1652 family is mainly intend-
ed for high-efficiency, battery-powered applications. See
Appendix A in Maxim’s
Battery Management and DC-DC
Converter Circuit Collection
for crossover point and dis-
continuous-mode equations. Discontinuous conduction
doesn’t affect normal Idle Mode operation.
Three key inductor parameters must be specified:
inductance value (L), peak current (IPEAK), and DC
resistance (RDC). The following equation includes a
constant LIR, which is the ratio of inductor peak-to-peak
AC current to DC load current. A higher value of LIR
allows smaller inductance, but results in higher losses
and ripple. A good compromise between size and loss-
es is found at a 30% ripple current to load current ratio
(LIR = 0.3), which corresponds to a peak inductor cur-
rent 1.15 times higher than the DC load current.
VOUT (VIN(MAX) - VOUT)
L = ———————————
VIN(MAX) x f x IOUT x LIR
where: f =switching frequency, normally 150kHz or
300kHz
IOUT =maximum DC load current
LIR =ratio of AC to DC inductor current,
typically 0.3
The peak inductor current at full load is 1.15 x IOUT if
the above equation is used; otherwise, the peak current
can be calculated by:
The inductor’s DC resistance is a key parameter for effi-
ciency performance and must be ruthlessly minimized,
preferably to less than 25mΩat IOUT = 3A. If a stan-
dard off-the-shelf inductor is not available, choose a
core with an LI2rating greater than L x IPEAK2and wind
it with the largest diameter wire that fits the winding
area. For 300kHz applications, ferrite core material is
strongly preferred; for 150kHz applications, Kool-mu
(aluminum alloy) and even powdered iron can be
acceptable. If light-load efficiency is unimportant (in
desktop 5V-to-3V applications, for example) then low-
permeability iron-powder cores may be acceptable,
even at 300kHz. For high-current applications, shielded
core geometries (such as toroidal or pot core) help
keep noise, EMI, and switching-waveform jitter low.
Current-Sense Resistor Value
The current-sense resistor value is calculated accord-
ing to the worst-case, low-current-limit threshold voltage
(from the
Electrical Characteristics
table) and the peak
inductor current. The continuous-mode peak inductor-
current calculations that follow are also useful for sizing
the switches and specifying the inductor-current satu-
ration ratings. In order to simplify the calculation, ILOAD
may be used in place of IPEAK if the inductor value has
been set for LIR = 0.3 or less (high inductor values)
and 300kHz operation is selected. Low-inductance
resistors, such as surface-mount metal-film resistors,
are preferred. 80mV
RSENSE = ————
IPEAK
I I x f x L x V
PEAK LOAD IN MAX
= +
( )
V (V - V )
OUT IN(MAX) OUT
2
MAX1652–MAX1655
High-Efficiency, PWM, Step-Down
DC-DC Controllers in 16-Pin QSOP
______________________________________________________________________________________ 21
Input Capacitor Value
Place a small ceramic capacitor (0.1µF) between V+ and
GND, close to the device. Also, connect a low-ESR bulk
capacitor directly to the drain of the high-side MOSFET.
Select the bulk input filter capacitor according to input
ripple-current requirements and voltage rating, rather
than capacitor value. Electrolytic capacitors that have
low enough effective series resistance (ESR) to meet the
ripple-current requirement invariably have more than
adequate capacitance values. Ceramic capacitors or
low-ESR aluminum-electrolytic capacitors such as Sanyo
OS-CON or Nichicon PL are preferred. Tantalum types
are also acceptable but may be less tolerant of high
input surge currents. RMS input ripple current is deter-
mined by the input voltage and load current, with the
worst possible case occurring at VIN = 2 x VOUT:
Output Filter Capacitor Value
The output filter capacitor values are determined by the
ESR, capacitance, and voltage rating requirements.
Electrolytic and tantalum capacitors are generally cho-
sen by voltage rating and ESR specifications, as they
will generally have more output capacitance than is
required for AC stability. Use only specialized low-ESR
capacitors intended for switching-regulator applications,
such as AVX TPS, Sprague 595D, Sanyo OS-CON, or
Nichicon PL series. To ensure stability, the capacitor
must meet
both
minimum capacitance and maximum
ESR values as given in the following equations:
VREF (1 + VOUT / VIN(MIN))
COUT > ––––––––––––––––———–––
VOUT x RSENSE x f
RSENSE x VOUT
RESR < ————————
VREF
(can be multiplied by 1.5, see note below)
These equations are “worst-case” with 45 degrees of
phase margin to ensure jitter-free fixed-frequency opera-
tion and provide a nicely damped output response for
zero to full-load step changes. Some cost-conscious
designers may wish to bend these rules by using less
expensive (lower quality) capacitors, particularly if the
load lacks large step changes. This practice is tolerable if
some bench testing over temperature is done to verify
acceptable noise and transient response.
There is no well-defined boundary between stable and
unstable operation. As phase margin is reduced, the
first symptom is a bit of timing jitter, which shows up as
blurred edges in the switching waveforms where the
scope won’t quite sync up. Technically speaking, this
(usually) harmless jitter is unstable operation, since the
switching frequency is now nonconstant. As the capac-
itor quality is reduced, the jitter becomes more pro-
nounced and the load-transient output voltage
waveform starts looking ragged at the edges.
Eventually, the load-transient waveform has enough
ringing on it that the peak noise levels exceed the
allowable output voltage tolerance. Note that even with
zero phase margin and gross instability present, the
output voltage noise never gets much worse than IPEAK
x RESR (under constant loads, at least).
Note: Designers of RF communicators or other noise-
sensitive analog equipment should be conservative
and stick to the ESR guidelines. Designers of notebook
computers and similar commercial-temperature-range
digital systems can multiply the RESR value by a factor
of 1.5 without hurting stability or transient response.
The output voltage ripple is usually dominated by the
ESR of the filter capacitor and can be approximated as
IRIPPLE x RESR. There is also a capacitive term, so the
full equation for ripple in the continuous mode is
VNOISE(p-p) = IRIPPLE x [RESR + 1 / (8 x f x COUT)]. In
Idle Mode, the inductor current becomes discontinuous
with high peaks and widely spaced pulses, so the noise
can actually be higher at light load compared to full load.
In Idle Mode, the output ripple can be calculated as:
0.025 x RESR
VNOISE(p-p) = —————— +
RSENSE
(0.025)2x L x [1 / VOUT + 1 / (VIN - VOUT)]
———————————————————
(RSENSE)2x COUT
Transformer Design
(MAX1652/MAX1654 Only)
Buck-plus-flyback applications, sometimes called “cou-
pled-inductor” topologies, use a transformer to generate
multiple output voltages. The basic electrical design is a
simple task of calculating turns ratios and adding the
power delivered to the secondary in order to calculate the
current-sense resistor and primary inductance. However,
extremes of low input-output differentials, widely different
output loading levels, and high turns ratios can compli-
cate the design due to parasitic transformer parameters
such as interwinding capacitance, secondary resistance,
and leakage inductance. For examples of what is possi-
ble with real-world transformers, see the graphs of
Maximum Secondary Current vs. Input Voltage in the
Typical Operating Characteristics.
I I x VV
I I when V is x V
RMS LOAD OUT VIN VOUT
IN
RMS LOAD IN OUT
/
( )
=
=
−
2 2
MAX1652–MAX1655
High-Efficiency, PWM, Step-Down
DC-DC Controllers in 16-Pin QSOP
22 ______________________________________________________________________________________
Power from the main and secondary outputs is lumped
together to obtain an equivalent current referred to the
main output voltage (see
Inductor Value
section for def-
initions of parameters). Set the value of the current-
sense resistor at 80mV / ITOTAL.
PTOTAL =the sum of the output power from
all outputs
ITOTAL =PTOTAL / VOUT = the equivalent output
current referred to VOUT
VOUT (VIN(MAX) - VOUT)
L(primary) = —————————————
VIN(MAX) x f x ITOTAL x LIR
VSEC + VFWD
Turns Ratio N = ——————————————
VOUT(MIN) + VRECT + VSENSE
where: VSEC is the minimum required rectified
secondary-output voltage
VFWD is the forward drop across the
secondary rectifier
VOUT(MIN) is the
minimum
value of the main
output voltage (from the
Electrical
Characteristics
)
VRECT is the on-state voltage drop across the
synchronous-rectifier MOSFET
VSENSE is the voltage drop across the sense
resistor
In positive-output (MAX1652) applications, the trans-
former secondary return is often referred to the main
output voltage rather than to ground in order to reduce
the needed turns ratio. In this case, the main output
voltage must first be subtracted from the secondary
voltage to obtain VSEC.
______Selecting Other Components
MOSFET Switches
The two high-current N-channel MOSFETs must be
logic-level types with guaranteed on-resistance specifi-
cations at VGS = 4.5V. Lower gate threshold specs are
better (i.e., 2V max rather than 3V max). Drain-source
breakdown voltage ratings must at least equal the max-
imum input voltage, preferably with a 20% derating
factor. The best MOSFETs will have the lowest on-resis-
tance per nanocoulomb of gate charge. Multiplying
RDS(ON) x QGprovides a meaningful figure by which to
compare various MOSFETs. Newer MOSFET process
technologies with dense cell structures generally give
the best performance. The internal gate drivers can tol-
erate more than 100nC total gate charge, but 70nC is a
more practical upper limit to maintain best switching
times.
In high-current applications, MOSFET package power
dissipation often becomes a dominant design factor.
I2R losses are distributed between Q1 and Q2 accord-
ing to duty factor (see the equations below). Switching
losses affect the upper MOSFET only, since the
Schottky rectifier clamps the switching node before the
synchronous rectifier turns on. Gate-charge losses are
dissipated by the driver and don’t heat the MOSFET.
Ensure that both MOSFETs are within their maximum
junction temperature at high ambient temperature by
calculating the temperature rise according to package
thermal-resistance specifications. The worst-case dissi-
pation for the high-side MOSFET occurs at the minimum
battery voltage, and the worst-case for the low-side
MOSFET occurs at the maximum battery voltage.
PD (upper FET) = ILOAD2x RDS(ON) x DUTY
VIN x CRSS
+ VIN x ILOAD x f x
(
––––––––––– +20ns
)
IGATE
PD (lower FET) = ILOAD2x RDS(ON) x (1 - DUTY)
DUTY = (VOUT + VQ2) / (VIN - VQ1 + VQ2)
where the on-state voltage drop VQ_ = ILOAD x RDS(ON)
CRSS =MOSFET reverse transfer capacitance
IGATE =DH driver peak output current capability
(1A typically)
20ns =DH driver inherent rise/fall time
Under output short circuit, the synchronous-rectifier
MOSFET suffers extra stress and may need to be over-
sized if a continuous DC short circuit must be tolerated.
During short circuit, Q2’s duty factor can increase to
greater than 0.9 according to:
Q2 DUTY (short circuit) = 1 - [VQ2 / (VIN(MAX) - VQ1 + VQ2)]
where the on-state voltage drop VQ= (120mV / RSENSE)
x RDS(ON).
Rectifier Diode D1
Rectifier D1 is a clamp that catches the negative induc-
tor swing during the 60ns dead time between turning
off the high-side MOSFET and turning on the low-side.
D1 must be a Schottky type in order to prevent the
lossy parasitic MOSFET body diode from conducting. It
is acceptable to omit D1 and let the body diode clamp
the negative inductor swing, but efficiency will drop one
or two percent as a result. Use an MBR0530 (500mA
rated) type for loads up to 1.5A, a 1N5819 type for
loads up to 3A, or a 1N5822 type for loads up to 10A.
D1’s rated reverse breakdown voltage must be at least
equal to the maximum input voltage, preferably with a
20% derating factor.
MAX1652–MAX1655
High-Efficiency, PWM, Step-Down
DC-DC Controllers in 16-Pin QSOP
______________________________________________________________________________________ 23
Boost-Supply Diode D2
A 10mA to 100mA Schottky diode or signal diode such
as a 1N4148 works well for D2 in most applications. If
the input voltage can go below 6V, use a Schottky
diode for slightly improved efficiency and dropout char-
acteristics. Don’t use large power diodes such as
1N5817 or 1N4001, since high junction capacitance
can cause VL to be pumped up to excessive voltages.
Rectifier Diode D3
(Transformer Secondary Diode)
The secondary diode in coupled-inductor applications
must withstand high flyback voltages greater than 60V,
which usually rules out most Schottky rectifiers.
Common silicon rectifiers such as the 1N4001 are also
prohibited, as they are far too slow. This often makes
fast silicon rectifiers such as the MURS120 the only
choice. The flyback voltage across the rectifier is relat-
ed to the VIN-VOUT difference according to the trans-
former turns ratio:
VFLYBACK = VSEC + (VIN - VOUT) x N
where: N is the transformer turns ratio SEC/PRI
VSEC is the maximum secondary DC output voltage
VOUT is the primary (main) output voltage
Subtract the main output voltage (VOUT) from VFLYBACK
in this equation if the secondary winding is returned to
VOUT and not to ground. The diode reverse breakdown
rating must also accommodate any ringing due to leak-
age inductance. D3’s current rating should be at least
twice the DC load current on the secondary output.
_____________Low-Voltage Operation
Low input voltages and low input-output differential volt-
ages each require some extra care in the design. Low
absolute input voltages can cause the VL linear regula-
tor to enter dropout, and eventually shut itself off. Low
input voltages relative to the output (low VIN-VOUT differ-
ential) can cause bad load regulation in multi-output fly-
back applications. See
Transformer Design
section.
Finally, low VIN-VOUT differentials can also cause the
output voltage to sag when the load current changes
abruptly. The amplitude of the sag is a function of induc-
tor value and maximum duty factor (DMAX an
Electrical
Characteristics
parameter, 98% guaranteed over tem-
perature at f = 150kHz) as follows:
(ISTEP)2x L
VSAG = ———————————————
2 x COUT x (VIN(MIN) x DMAX - VOUT)
The cure for low-voltage sag is to increase the value of
the output capacitor. For example, at VIN = 5.5V, VOUT
= 5V, L = 10µH, f = 150kHz, a total capacitance of
660µF will prevent excessive sag. Note that only the
capacitance requirement is increased and the ESR
requirements don’t change. Therefore, the added
capacitance can be supplied by a low-cost bulk
capacitor in parallel with the normal low-ESR capacitor.
Table 4 summarizes low-voltage operational issues.
Table 4. Low-Voltage Troubleshooting
Supply VL from an external source other
than VBATT, such as the system 5V supply.
VL output is so low that it hits the
VL UVLO threshold at 4.2V max.
Low input voltage, <4.5V
Won’t start under load or
quits before battery is
completely dead
Use a small 20mA Schottky diode for
boost diode D2. Supply VL from an
external source.
VL linear regulator is going into
dropout and isn’t providing
good gate-drive levels.
Low input voltage, <5V
High supply current,
poor efficiency
Reduce f to 150kHz. Reduce secondary
impedances—use Schottky if possible.
Stack secondary winding on main output.
Not enough duty cycle left to
initiate forward-mode operation.
Small AC current in primary can’t
store energy for flyback operation.
Low VIN-VOUT differential,
VIN < 1.3 x VOUT(main)
Secondary output won’t
support a load
Increase the minimum input voltage or
ignore.
Normal function of internal low-
dropout circuitry.
Low VIN-VOUT differential,
<0.5V
Unstable—jitters between
two distinct duty factors
Reduce f to 150kHz. Reduce MOSFET
on-resistance and coil DCR.
Maximum duty-cycle limits
exceeded.
Low VIN-VOUT differential,
<0.5V
Dropout voltage is too
high (VOUT follows VIN as
VIN decreases)
Increase bulk output capacitance per
formula above. Reduce inductor value.
Limited inductor-current slew
rate per cycle.
Low VIN-VOUT differential,
<1V
Sag or droop in VOUT
under step load change
SOLUTION
ROOT CAUSECONDITIONSYMPTOM
__________Applications Information
Heavy-Load Efficiency Considerations
The major efficiency loss mechanisms under loads (in
the usual order of importance) are:
•P(I2R), I2R losses
•P(gate), gate-charge losses
•P(diode), diode-conduction losses
•P(tran), transition losses
•P(cap), capacitor ESR losses
•P(IC), losses due to the operating supply current
of the IC
Inductor-core losses are fairly low at heavy loads
because the inductor’s AC current component is small.
Therefore, they aren’t accounted for in this analysis.
Ferrite cores are preferred, especially at 300kHz, but
powdered cores such as Kool-mu can work well.
Efficiency = POUT / PIN x 100%
= POUT / (POUT + PTOTAL) x 100%
PTOTAL = P(I2R) + P(gate) + P(diode) + P(tran) +
P(cap) + P(IC)
P(I2R) = (ILOAD)2x (RDC + RDS(ON) + RSENSE)
where RDC is the DC resistance of the coil, RDS(ON) is
the MOSFET on-resistance, and RSENSE is the current-
sense resistor value. The RDS(ON) term assumes identi-
cal MOSFETs for the high- and low-side switches
because they time-share the inductor current. If the
MOSFETs aren’t identical, their losses can be estimat-
ed by averaging the losses according to duty factor.
P(gate) = gate-driver loss = qG x f x VL
where VL is the MAX1652 internal logic supply voltage
(5V), and qG is the sum of the gate-charge values for
low- and high-side switches. For matched MOSFETs,
qG is twice the data sheet value of an individual
MOSFET. If VOUT is set to less than 4.5V, replace VL in
this equation with VBATT. In this case, efficiency can be
improved by connecting VL to an efficient 5V source,
such as the system +5V supply.
P(diode) =diode conduction losses
=ILOAD x VFWD x tDx f
where tDis the diode conduction time (120ns typ) and
VFWD is the forward voltage of the Schottky.
PD(tran) = transition loss = VBATT x CRSS
VBATT x ILOAD x f x
(
——————— + 20ns
)
IGATE
where CRSS is the reverse transfer capacitance of the
high-side MOSFET (a data sheet parameter), IGATE is
the DH gate-driver peak output current (1A typ), and
20ns is the rise/fall time of the DH driver.
P(cap) = input capacitor ESR loss = (IRMS)2x RESR
where IRMS is the input ripple current as calculated in the
Input Capacitor Value
section of the
Design Procedure.
Light-Load Efficiency Considerations
Under light loads, the PWM operates in discontinuous
mode, where the inductor current discharges to zero at
some point during the switching cycle. This causes the
AC component of the inductor current to be high com-
pared to the load current, which increases core losses
and I2R losses in the output filter capacitors. Obtain best
light-load efficiency by using MOSFETs with moderate
gate-charge levels and by using ferrite, MPP, or other
low-loss core material. Avoid powdered iron cores; even
Kool-mu (aluminum alloy) is not as good as ferrite.
__PC Board Layout Considerations
Good PC board layout is
required
to achieve specified
noise, efficiency, and stability performance. The PC
board layout artist must be provided with explicit
instructions, preferably a pencil sketch of the place-
ment of power switching components and high-current
routing. See the evaluation kit PC board layouts in the
MAX1653, MAX796, and MAX797 EV kit manuals for
examples. A ground plane is essential for optimum per-
formance. In most applications, the circuit will be locat-
ed on a multilayer board, and full use of the four or
more copper layers is recommended. Use the top layer
for high-current connections, the bottom layer for quiet
connections (REF, SS, GND), and the inner layers for
an uninterrupted ground plane. Use the following step-
by-step guide.
1) Place the high-power components (C1, C2, Q1, Q2,
D1, L1, and R1) first, with their grounds adjacent.
Priority 1: Minimize current-sense resistor trace
lengths (see Figure 9).
Priority 2: Minimize ground trace lengths in the
high-current paths (discussed below).
Priority 3: Minimize other trace lengths in the high-
current paths. Use >5mm wide traces.
C1 to Q1: 10mm max length. D1 anode to
Q2: 5mm max length LX node (Q1
source, Q2 drain, D1 cathode, inductor):
15mm max length
Ideally, surface-mount power components are
butted up to one another with their ground terminals
almost touching. These high-current grounds (C1-,
C2-, source of Q2, anode of D1, and PGND) are
then connected to each other with a wide filled zone
MAX1652–MAX1655
High-Efficiency, PWM, Step-Down
DC-DC Controllers in 16-Pin QSOP
24 ______________________________________________________________________________________
of top-layer copper, so that they don’t go through
vias. The resulting top-layer “sub-ground-plane” is
connected to the normal inner-layer ground plane at
the output ground terminals. This ensures that the
analog GND of the IC is sensing at the output termi-
nals of the supply, without interference from IR
drops and ground noise. Other high-current paths
should also be minimized, but focusing ruthlessly
on short ground and current-sense connections
eliminates about 90% of all PC board layout diffi-
culties. See the evaluation kit PC board layouts for
examples.
2) Place the IC and signal components. Keep the main
switching node (LX node) away from sensitive ana-
log components (current-sense traces and REF and
SS capacitors). Placing the IC and analog compo-
nents on the opposite side of the board from the
power-switching node is desirable. Important: the
IC must be no farther than 10mm from the current-
sense resistor. Keep the gate-drive traces (DH, DL,
and BST) shorter than 20mm and route them away
from CSH, CSL, REF, and SS.
3) Employ a single-point star ground where the input
ground trace, power ground (subground plane),
and normal ground plane all meet at the output
ground terminal of the supply.
MAX1652–MAX1655
High-Efficiency, PWM, Step-Down
DC-DC Controllers in 16-Pin QSOP
______________________________________________________________________________________ 25
MAX1652
MAX1653
MAX1654
MAX1655
SENSE RESISTOR
MAIN CURRENT PATH
FAT, HIGH-CURRENT TRACES
Figure 9. Kelvin Connections for the Current-Sense Resistor
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
DH
LX
BST
DL
GND
REF
(SECFB) SKIP
SS
TOP VIEW
MAX1652
MAX1653
MAX1654
MAX1655
PGND
VL
V+
CSL
( ) ARE FOR MAX1652/ MAX1654.
CSH
FB
SHDN
SYNC
QSOP
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
DH
LX
BST
DL
GND
REF
SKIP
SS
MAX1653
MAX1655
PGND
VL
V+
CSL
CSH
FB
SHDN
SYNC
Narrow SO
Pin Configurations
MAX1652–MAX1655
High-Efficiency, PWM, Step-Down
DC-DC Controllers in 16-Pin QSOP
26 ______________________________________________________________________________________
TRANSISTOR COUNT: 1990
___________________Chip Information
________________________________________________________Package Information
QSOP.EPS
MAX1652–MAX1655
High-Efficiency, PWM, Step-Down
DC-DC Controllers in 16-Pin QSOP
______________________________________________________________________________________ 27
___________________________________________Package Information (continued)
SOICN.EPS
MAX1652–MAX1655
High-Efficiency, PWM, Step-Down
DC-DC Controllers in 16-Pin QSOP
28 ______________________________________________________________________________________
NOTES
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MAX1653EEE+T MAX1653ESE+T MAX1654EEE+ MAX1654EEE+T MAX1655EEE+T MAX1655ESE+T
MAX1653ESE-T MAX1654EEE-T MAX1655ESE-T MAX1653ESE MAX1654EEE MAX1655EEE MAX1655ESE
MAX1653EEE MAX1653EEE-T MAX1655EEE-T