LM1815
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SNOSBU8F –SEPTEMBER 2000–REVISED MARCH 2013
LM1815 Adaptive Variable Reluctance Sensor Amplifier
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1FEATURES DESCRIPTION
The LM1815 is an adaptive sense amplifier and
2• Adaptive Hysteresis default gating circuit for motor control applications.
• Single Supply Operation The sense amplifier provides a one-shot pulse output
• Ground Referenced Input whose leading edge coincides with the negative-
going zero crossing of a ground referenced input
• True Zero Crossing Timing Reference signal such as from a variable reluctance magnetic
• Operates from 2V to 12V Supply Voltage pick-up coil.
• Handles Inputs from 100 mVP-P to over 120VP-P In normal operation, this timing reference signal is
with External Resistor processed (delayed) externally and returned to the
• CMOS Compatible Logic LM1815. A Logic input is then able to select either
the timing reference or the processed signal for
APPLICATIONS transmission to the output driver stage.
• Position Sensing with Notched Wheels The adaptive sense amplifier operates with a positive-
going threshold which is derived by peak detecting
• Zero Crossing Switch the incoming signal and dividing this down. Thus the
• Motor Speed Control input hysteresis varies with input signal amplitude.
• Tachometer This enables the circuit to sense in situations where
• Engine Testing the high speed noise is greater than the low speed
signal amplitude. Minimum input signal is 150mVP-P.
Connection Diagram
Figure 1. Top View
14-Lead SOIC or PDIP
See D or NFF0014A Package
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2000–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
LM1815
SNOSBU8F –SEPTEMBER 2000–REVISED MARCH 2013
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Absolute Maximum Ratings(1)(2)
Supply Voltage 12V
Power Dissipation(3) 1250 mW
Operating Temperature Range −40°C ≤TA≤+125°C
Storage Temperature Range −65°C ≤TJ≤+150°C
Junction Temperature +150°C
Input Current ±30 mA
Lead Temperature (Soldering, 10 sec.) 260°C
(1) “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be ensured. They are not meant to imply
that the devices should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
(3) For operation at elevated temperatures, the device must be derated based on a 150°C maximum junction temperature and a thermal
resistance of 80°C/W (DIP), 120°C/W (SO-14) junction to ambient.
Electrical Characteristics
(TA= 25°C, VCC = 10V, unless otherwise specified, see Figure 17)
Parameter Conditions Min Typ Max Units
Operating Supply Voltage 2.5 10 12 V
Supply Current Pin 3 = -0.1V, Pin 9 = 2V, Pin 11 = 0.8V 3.6 6 mA
Reference Pulse Width fIN = 1Hz to 2kHz, R = 150kΩ, C = 0.001µF 70 100 130 µs
Logic Input Bias Current VIN = 2V, (Pin 9 and Pin 11) 5 µA
Signal Input Bias Current VIN = 0V dc, (Pin 3) -200 nA
Logic Threshold (Pin 9 and Pin 11) 0.8 1.1 2.0 V
VOUT High RL= 1kΩ, (Pin 10) 7.5 8.6 V
VOUT Low ISINK = 0.1mA, (Pin 10) 0.3 0.4 V
Output Leakage Pin 12 V12 = 11V 0.01 10 µA
Saturation Voltage P12 I12 = 2mA 0.2 0.4 V
Input Zero Crossing Threshold All Modes, VSIGNAL = 1V pk-pk -25 0 25 mV(1)
Mode 1, Pin 5 = Open 30 45 60 mV(1)
Minimum Input Arming Threshold Mode 2, Pin 5 = VCC 200 300 450 mV(1)
Mode 3, Pin 5 = Gnd -25 0 25 mV(1)
Mode 1, Pin 5 = Open 40 80 90 %(1)
VSIGNAL ≥230mV pk-pk(2)
Mode 2, Pin 5 = VCC
Adaptive Input Arming Threshold 80 %(1)
VSIGNAL ≥1.0V pk-pk(2)
Mode 3, Pin 5 = Gnd 80 %(1)
VSIGNAL ≥150mV pk-pk(2)
(1) The Min/Typ Max limits are relative to the positive voltage peak seen at VIN Pin 3.
(2) Tested per Figure 17, VSIGNAL is a Sine Wave; FSIGNAL is 1000Hz.
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Typical Performance Characteristics
Mode 1 Minimum Arming Threshold Mode 2 Minimum Arming Threshold
vs Temperature vs Temperature
Figure 2. Figure 3.
Mode 3 Minimum Arming Threshold
vs Temperature Mode 1 Minimum Arming Threshold vs VCC
Figure 4. Figure 5.
Mode 2 Minimum Arming Threshold vs VCC Pin 3 VIN vs VSIGNAL
Figure 6. Figure 7.
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Typical Performance Characteristics (continued)
Pin 3 VIN vs VSIGNAL, RIN = 10kΩPin 3 VIN vs VSIGNAL, RIN = 20kΩ
Figure 8. Figure 9.
Pin 3 VIN vs VSIGNAL, RIN = 50kΩPin 3 Bias Current vs Temperature
Figure 10. Figure 11.
Peak Detector Charge Current
vs Temperature Peak Detector Charge Current vs VCC
Figure 12. Figure 13.
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Typical Performance Characteristics (continued)
Peak Detector Voltage Peak Detector Voltage
vs Pin 3 VIN, Mode 1 vs Pin 3 VIN, Mode 2
Figure 14. Figure 15.
Peak Detector Voltage
vs Pin 3 VIN, Mode 3
Figure 16.
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TRUTH TABLE
Signal Input RC Timing Input Select Timing Input Gated Output
Pin 3 Pin 14 Pin 11 Pin 9 Pin 10
± Pulses RC L X Pulses = RC
X X H H H
X X H L L
± Pulses L L L Zero Crossing
Figure 17. LM1815 Adaptive Sense Amplifier
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APPLICATION HINTS
Figure 18. LM1815 Oscillograms
INPUT VOLTAGE CLAMP
The signal input voltage at pin 3 is internally clamped. Current limit for the Input pin is provided by an external
resistor which should be selected to allow a peak current of ±3 mA in normal operation. Positive inputs are
clamped by a 1kΩresistor and series diode (see R4 and Q12 in the internal schematic diagram), while an active
clamp limits pin 3 to typically 350mV below Ground for negative inputs (see R2, R3, Q10, and Q11 in the internal
schematic diagram). Thus for input signal transitions that are more than 350mV below Ground, the input pin
current (up to 3mA) will be pulled from the V+ supply. If the V+ pin is not adequately bypassed the resulting
voltage ripple at the V+ pin will disrupt normal device operation. Likewise, for input signal transitions that are
more than 500mV above Ground, the input pin current will be dumped to Ground through device pin 2. Slight
shifts in the Ground potential at device pin 2, due to poor grounding techniques relative to the input signal
ground, can cause unreliable operation. As always, adequate device grounding, and V+ bypassing, needs to be
considered across the entire input voltage and frequency range for the intended application.
INPUT CURRENT LIMITING
As stated earlier, current limiting for the Input pin is provided by a user supplied external resistor. For purposes of
selecting the appropriate resistor value the Input pin should be considered to be a zero ohm connection to
ground. For applications where the input voltage signal is not symmetrical with relationship to Ground the worst
case voltage peak should be used.
Minimum Rext = [(Vin peak)/3mA]
In the application example shown in Figure 17 (Rext = 18kΩ) the recommended maximum input signal voltage is
±54V (i.e. 108Vp-p).
OPERATION OF ZERO CROSSING DETECTOR
The LM1815 is designed to operate as a zero crossing detector, triggering an internal one shot on the negative-
going edge of the input signal. Unlike other zero crossing detectors, the LM1815 cannot be triggered until the
input signal has crossed an "arming" threshold on the positive-going portion of the waveform. The arming circuit
is reset when the chip is triggered, and subsequent zero crossings are ignored until the arming threshold is
exceeded again. This threshold varies depending on the connection at pin 5. Three different modes of operation
are possible:
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MODE 1, PIN 5 OPEN
The adaptive mode is selected by leaving device pin 5 open circuit. For input signals of less than ±135mV (i.e.
270 mVp-p) and greater than typically ±75mV (i.e. 150mVp-p), the input arming threshold is typically at 45mV.
Under these conditions the input signal must first cross the 45mV threshold in the positive direction to arm the
zero crossing detector, and then cross zero in the negative direction to trigger it.
If the signal is less than 30mV peak (minimum rating in Electrical Characteristics), the one shot is ensured to not
trigger.
Input signals of greater than ±230mV (i.e. 460 mVp-p) will cause the arming threshold to track at 80% of the
peak input voltage. A peak detector capacitor at device pin 7 stores a value relative to the positive input peaks to
establish the arming threshold. Input signals must exceed this threshold in the positive direction to arm the zero
crossing detector, which can then be triggered by a negative-going zero crossing.
The peak detector tracks rapidly as the input signal amplitude increases, and decays by virtue of the resistor
connected externally at pin 7 track decreases in the input signal.
If the input signal amplitude falls faster than the voltage stored on the peak detector capacitor there may be a
loss of output signal until the capacitor voltage has decayed to an appropriate level.
Note that since the input voltage is clamped, the waveform observed at pin 3 is not identical to the waveform
observed at the variable reluctance sensor. Similarly, the voltage stored at pin 7 is not identical to the peak
voltage appearing at pin 3.
MODE 2, PIN 5 CONNECTED TO V+
The input arming threshold is fixed at 200mV minimum when device pin 5 is connected to the positive supply.
The chip has no output for signals of less than ±200 mV (i.e. 400mVp-p) and triggers on the next negative-going
zero crossing when the arming threshold is has been exceeded.
MODE 3, PIN 5 GROUNDED
With pin 5 grounded, the input arming threshold is set to 0V, ±25mV maximum. Positive-going zero crossings
arm the chip, and the next negative-going zero crossing triggers it. This is the very basic form of zero-crossing
detection.
ONE SHOT TIMING
The one shot timing is set by a resistor and capacitor connected to pin 14. The recommended maximum resistor
value is 150kohms. The capacitor value can be changed as needed, as long as the capacitor type does not
present any signfigant leakage that would adversely affect the RC time constant.
The output pulse width is:
pulse width = 0.673 x R x C (1)
For a given One Shot pulse width, the recommended maximum input signal frequency is:
Fin(max) = 1/(1.346 x R x C) (2)
In the application example shown in Figure 17 (R=150kohms, C=0.001µF) the recommended maximum input
frequency will typically be 5kHz. Operating with input frequencies above the recommended Fin (max) value may
result in unreliable performance of the One Shot circuitry. For those applications where the One Shot circuit is
not required, device pin 14 can be tied directly to Ground.
LOGIC INPUTS
In some systems it is necessary to externally generate pulses, such as during stall conditions when the variable
reluctance sensor has no output. External pulse inputs at pin 9 are gated through to pin 10 when Input Select
(pin 11) is pulled high. Pin 12 is a direct output for the one shot and is unaffected by the status of pin 11.
Input/output pins 9, 11, 10, and 12 are all CMOS logic compatible. In addition, pins 9, 11, and 12 are TTL
compatible. Pin 10 is not ensured to drive a TTL load.
Pins 1, 4, 6 and 13 have no internal connections and can be grounded.
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REVISION HISTORY
Changes from Revision E (March 2013) to Revision F Page
• Changed layout of National Data Sheet to TI format ............................................................................................................ 9
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PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
LM1815M/NOPB ACTIVE SOIC D 14 55 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 LM1815M
LM1815MX/NOPB ACTIVE SOIC D 14 2500 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 LM1815M
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
Addendum-Page 2
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
LM1815MX/NOPB SOIC D 14 2500 330.0 16.4 6.5 9.35 2.3 8.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 16-Jun-2018
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LM1815MX/NOPB SOIC D 14 2500 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 16-Jun-2018
Pack Materials-Page 2
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