© Semiconductor Components Industries, LLC, 2015
May, 2019 − Rev. P3
1Publication Order Number:
NTMFD5C650NL/D
NTMFD5C650NL
MOSFET – Power, Dual,
N-Channel
60 V, 4.2 mW, 111 A
Features
•Small Footprint (5x6 mm) for Compact Design
•Low RDS(on) to Minimize Conduction Losses
•Low QG and Capacitance to Minimize Driver Losses
•These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Parameter Symbol Value Unit
Drain−to−Source Voltage VDSS 60 V
Gate−to−Source Voltage VGS ±20 V
Continuous Drain
Current RqJC
(Notes 1, 2, 3) Steady
State
TC = 25°CID111 A
TC = 100°C 88
Power Dissipation
RqJC (Notes 1, 2)
TC = 25°CPD125 W
TC = 100°C 62
Continuous Drain
Current RqJA
(Notes 1, 2, 3) Steady
State
TA = 25°CID21 A
TA = 100°C 15
Power Dissipation
RqJA (Notes 1 & 2)
TA = 25°CPD3.5 W
TA = 100°C 1.8
Pulsed Drain Current TA = 25°C, tp = 10 msIDM 502 A
Operating Junction and Storage Temperature TJ, Tstg −55 to
+ 175
°C
Source Current (Body Diode) IS91 A
Single Pulse Drain−to−Source Avalanche
Energy (IL(pk) = 6 A)
EAS 186 mJ
Lead Temperature for Soldering Purposes
(1/8″ from case for 10 s)
TL260 °C
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
THERMAL RESISTANCE MAXIMUM RATINGS
Parameter Symbol Value Unit
Junction−to−Case − Steady State RqJC 1.37 °C/W
Junction−to−Ambient − Steady State (Note 2) RqJA 46.9
1. The entire application environment impacts the thermal resistance values shown,
they are not constants and are only valid for the particular conditions noted.
2. Surface−mounted on FR4 board using a 650 mm2, 2 oz. Cu pad.
3. Maximum current for pulses as long as 1 second is higher but is dependent
on pulse duration and duty cycle.
MARKING
DIAGRAM
www.onsemi.com
A = Assembly Location
Y = Year
W = Work Week
ZZ = Lot Traceability
V(BR)DSS RDS(ON) MAX ID MAX
60 V 4.2 mW @ 10 V
111 A
5.8 mW @ 4.5 V
See detailed ordering, marking and shipping information in the
package dimensions section on page 5 of this data sheet.
ORDERING INFORMATION
D1
D1
D2
D2
S1
G1
S2
G2
Dual N−Channel
D1
S1
G1
XXXXXX
AYWZZ
D2
D1
D2
S2
G2
D2
D1
DFN8 5x6
(SO8FL)
CASE 506BT
1
NTMFD5C650NL
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2
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise specified)
Parameter Symbol Test Condition Min Typ Max Unit
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage V(BR)DSS VGS = 0 V, ID = 250 mA60 V
Drain−to−Source Breakdown Voltage
Temperature Coefficient
V(BR)DSS/
TJ
27.1 mV/°C
Zero Gate Voltage Drain Current IDSS VGS = 0 V,
VDS = 60 V
TJ = 25°C 10
mA
TJ = 125°C 100
Gate−to−Source Leakage Current IGSS VDS = 0 V, VGS = 20 V 100 nA
ON CHARACTERISTICS (Note 4)
Gate Threshold Voltage VGS(TH) VGS = VDS, ID = 98 mA1.2 2.2 V
Negative Threshold Temperature Coefficient VGS(TH)/TJ−5.0 mV/°C
Drain−to−Source On Resistance RDS(on) VGS = 10 V ID = 20 A 3.5 4.2
mW
VGS = 4.5 V ID = 20 A 4.6 5.8
Forward Transconductance gFS VDS = 15 V, ID = 50 A 120 S
CHARGES, CAPACITANCES & GATE RESISTANCE
Input Capacitance CISS
VGS = 0 V, f = 1 MHz, VDS = 25 V
2546
pF
Output Capacitance COSS 1258
Reverse Transfer Capacitance CRSS 17
Total Gate Charge QG(TOT) VGS = 4.5 V, VDS = 48 V; ID = 50 A 16
nC
Total Gate Charge QG(TOT) VGS = 10 V, VDS = 48 V; ID = 50 A 37
Threshold Gate Charge QG(TH)
VGS = 4.5 V, VDS = 48 V; ID = 50 A
4.3
Gate−to−Source Charge QGS 8.3
Gate−to−Drain Charge QGD 3.1
Plateau Voltage VGP 3.3 V
SWITCHING CHARACTERISTICS (Note 5)
Turn−On Delay Time td(ON)
VGS = 4.5 V, VDS = 48 V,
ID = 5 A, RG = 1.0 W
13
ns
Rise Time tr24
Turn−Off Delay Time td(OFF) 37
Fall Time tf13
DRAIN−SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage VSD VGS = 0 V,
IS = 20 A
TJ = 25°C 0.9 1.2
V
TJ = 125°C 0.8
Reverse Recovery Time tRR
VGS = 0 V, dIS/dt = 50 A/ms,
IS = 50 A
44
ns
Charge Time ta22
Discharge Time tb22
Reverse Recovery Charge QRR 35 nC
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
4. Pulse Test: pulse width v 300 ms, duty cycle v 2%.
5. Switching characteristics are independent of operating junction temperatures.
NTMFD5C650NL
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3
TYPICAL CHARACTERISTICS
0
20
40
60
80
140
0 0.5 1.0 2.0 4.0
Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics
VDS, DRAIN−TO−SOURCE VOLTAGE (V) VGS, GATE−TO−SOURCE VOLTAGE (V)
Figure 3. On−Resistance vs. Gate−to−Source
Voltage
Figure 4. On−Resistance vs. Drain Current and
Gate Voltage
VGS, GATE−TO−SOURCE VOLTAGE (V) ID, DRAIN CURRENT (A)
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−to−Source Leakage Current
vs. Voltage
TJ, JUNCTION TEMPERATURE (°C) VDS, DRAIN−TO−SOURCE VOLTAGE (V)
ID, DRAIN CURRENT (A)
ID, DRAIN CURRENT (A)
RDS(on), DRAIN−TO−SOURCE RESISTANCE (mW)
RDS(on), DRAIN−TO−SOURCE RESISTANCE (mW)
RDS(on), NORMALIZED DRAIN−TO−
SOURCE RESISTANCE
IDSS, LEAKAGE (nA)
2.6 V
3.0 V
TJ = 125°C
TJ = 25°C
TJ = −55°C
TJ = 25°C
ID = 20 A
TJ = 25°C
VGS = 10 V
VGS = 10 V
ID = 20 A
TJ = 125°C
TJ = 85°C
3.4 V
VDS = 10 V
TJ = 150°C
VGS = 4.5 V to 10 V
2.8 V
3.2 V
0
20
40
60
80
140
0 0.5 1.0 1.5 2.0
3.6 V
4
5
7
8
10
34 5 6 7 8 910
8
10 20 60 70 100
6
3
2
40
0.6
0.8
1.0
1.4
1.6
1.8
2.0
−50 −25 0 25 50 75 100 125 150 175
100
1K
10K
100K
515
5
1.2
4535
TJ = 25°C
10
1
2.5
30 50 80 90
25 55
TJ = 175°C
100
120
1.5 2.5 3.0 3.5
100
120
VGS = 4.5 V
4
7
6
9
NTMFD5C650NL
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4
TYPICAL CHARACTERISTICS
Figure 7. Capacitance Variation Figure 8. Gate−to−Source vs. Total Charge
VDS, DRAIN−TO−SOURCE VOLTAGE (V) QG, TOTAL GATE CHARGE (nC)
Figure 9. Resistive Switching Time Variation
vs. Gate Resistance
Figure 10. Diode Forward Voltage vs. Current
RG, GATE RESISTANCE (W)VSD, SOURCE−TO−DRAIN VOLTAGE (V)
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
Figure 12. IPEAK vs. Time in Avalanche
VDS, DRAIN−TO−SOURCE VOLTAGE (V) TIME IN AVALANCHE (s)
C, CAPACITANCE (pF)
VGS, GATE−TO−SOURCE VOLTAGE (V)
t, TIME (ns)
IS, SOURCE CURRENT (A)
ID, DRAIN CURRENT (A)
IPEAK, (A)
VGS = 0 V
TJ = 25°C
f = 1 MHz
CISS
COSS
CRSS VDS = 48 V
TJ = 25°C
ID = 50 A
QGS QGD
VGS = 4.5 V
VDS = 48 V
ID = 50 A td(off)
td(on)
tf
tr
TJ = 125°C TJ = 25°C TJ = −55°C
RDS(on) Limit
Thermal Limit
Package Limit
1 ms
10 ms
TC = 25°C
VGS ≤ 10 V
Single Pulse
1
100
1K
10K
0102030
0
2
4
6
8
10
05 20
10
100
1K
1 10 100
0.1
0.3 0.4 0.5 0.6
1K
1 10 1000.1
100
10
1
0.1 0.1
10
100
0.00001 0.001 0.010.0001
40 60 25 40
0.7 0.8 0.9
1K
10 ms
0.5 ms
VGS = 0 V
50 15 30
1
3
5
7
9
10
10
1
10 35
TJ (initial) = 100°C
TJ (initial) = 25°C
1
1
NTMFD5C650NL
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5
TYPICAL CHARACTERISTICS
0.01
0.1
1
100
0.000001 0.00001 0.0001 0.001 0.01 0.1 1 10 100
Figure 13. Thermal Characteristics
PULSE TIME (sec)
R(t) (°C/W)
1000
10
Single Pulse
50% Duty Cycle
20%
10%
5%
2%
1%
NVMFD5C650NL 5x6 SOFL DS PCB Cu Area 650 mm2 PCB Cu thk 2oz
DEVICE ORDERING INFORMATION
Device Marking Package Shipping†
NTMFD5C650NLT1G 5C650L DFN8
(Pb−Free)
1500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
M3.25
h−−−
3.50
−−−
DFN8 5x6, 1.27P Dual Flag (SO8FL−Dual)
CASE 506BT
ISSUE E
DATE 26 FEB 2013
SCALE 2:1
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED
BETWEEN 0.15 AND 0.30 MM FROM THE TERMINAL TIP.
4. PROFILE TOLERANCE APPLIES TO THE EXPOSED PAD AS WELL
AS THE TERMINALS.
5. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD FLASH,
PROTRUSIONS, OR GATE BURRS.
6. SEATING PLANE IS DEFINED BY THE TERMINALS. A1 IS DEFINED
AS THE DISTANCE FROM THE SEATING PLANE TO THE LOWEST
POINT ON THE PACKAGE BODY.
7. A VISUAL INDICATOR FOR PIN 1 MUST BE LOCATED IN THIS AREA.
XXXXXX= Specific Device Code
A = Assembly Location
Y = Year
W = Work Week
ZZ = Lot Traceability
1234
56
TOP VIEW
SIDE VIEW
BOTTOM VIEW
D1
E1
h
D
E
B
A
0.20 C
0.20 C
2X
2X
DIM MIN
MILLIMETERS
A0.90
A1 −−−
b0.33
c0.20
D5.15 BSC
D1 4.70
D2 3.90
E6.15 BSC
E1 5.70
E2 3.90
e1.27 BSC
G0.45
K0.51
L0.48
A
0.10 C
0.10 C
14
8
e
8X
D2
b1 E2
b
A0.10 B
C
0.05 C
L
DETAIL A
A1
c
4X
GENERIC
MARKING DIAGRAM*
*This information is generic. Please refer
to device data sheet for actual part
marking.
1
XXXXXX
AYWZZ
1
5
MAX
−−−
−−−
0.42
−−−
4.90
4.10
5.90
4.15
0.55
−−−
0.61
M
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
1.27
0.75
1.40
3.70
4.56
8X
N1.80 2.00
78
N
PITCH
6.59
4.84
1.00
DIMENSION: MILLIMETERS
PIN ONE
IDENTIFIER
NOTE 7
NOTE 4 CSEATING
PLANE
DETAIL A NOTE 6
4X
K
NOTE 3
2.30
4X
0.70
5.55
4X
0.56
2X
D3 1.50 1.70
b1 0.33 0.42
ÉÉ
ÉÉ
4X
D3
G
4X
DETAIL B
DETAIL B
ALTERNATE
CONSTRUCTION
2.08
2X
K1 0.56 −−−
K1
3.75
12
_
MAX
1.10
0.05
0.51
0.33
5.10
4.30
6.10
4.40
0.65
−−−
0.71
2.20
1.90
0.51
−−−
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
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DFN8 5X6, 1.27P DUAL FLAG (SO8FL−DUAL)
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