Single Port, PLC Differential Line Driver ISL15100 Features The ISL15100 is a single port differential line driver developed for Power Line Communication (PLC) applications. The device is designed to drive heavy line loads while maintaining the high level of linearity required in OFDM PLC modem links. With 15.5dBm of total transmit signal power into 100 line load, the driver achieves -43dB average MTPR distortion across the output spectrum up to 86MHz. * Single differential driver The ISL15100 has two bias current control pins (C0, C1) to allow for four power settings (disable, low, medium, high). In disable mode, the line driver outputs maintain a high impedance in the presence of high receive signal amplitude, so it doesn't affect TDM receive signal integrity. The ISL15100 is available in the thermally-enhanced 16 Ld QFN and is specified for operation over the full -40C to +85C ambient temperature range. * 100MHz Broadband PLC G.hn, EOC, HomePlug AV2 * Control pins for enable/disable and supply current selection * High output impedance when disabled for TDM operation * -43dBc average MTPR distortion at full line power * Single +12V or bipolar 6V nominal supplies * High surge current handling capability Applications * Power Line Communication differential driver * Pin compatible upgrade to ISL1571IRZ Related Literature * AN1325 "Choosing and Using Bypass Capacitors" TABLE 1. ALTERNATE SOLUTIONS PART # NOMINAL VS (V) BANDWIDTH (MHz) APPLICATIONS ISL1571 6, +12 200 HomePlug AV1 +12V 100n + SUPPLY DECOUPLING NOT SHOW N 500 1/2 ISL15100 -30 3.9 -40 Rf 1k Vcm -60 Rg 133 100 NOMINAL LINE Rf 1k 2.2n 1/2 ISL15100 500 3.9 + POWER (dBM) AFE -50 1:2 -70 -80 -90 -100 -110 -120 100n -130 TYPICAL DIFFERENTIAL I/O LINE DRIVER FIGURE 1. TYPICAL APPLICATION CIRCUIT September 19, 2013 FN8577.0 1 2 7 12 17 22 27 32 37 42 47 FREQUENCY (MHz) FIGURE 2. 50MHz PLC SPECTRUM CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2013. All Rights Reserved Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners. ISL15100 Connection Diagram +12V + + PLINE = 16dBm CF = 15.4dB Av = 1 + 2 x 1000 = 16(V/V) 133 140 DIFFERENTIAL RECEIVER PATH LOAD AT TXMN INPUT INA+ + OUTA 1/2 ISL15100 3.9 500 - 1k 1:2 INA- 500mVp +6V 133 11.8Vp INTO PLINE 100 8.0Vp INB- 1/2 ISL15100 500 INB+ Txmn 1k OUTB 3.9 + BIAS CURRENT CONTROL C0 C1 FIGURE 3. TYPICAL DIFFERENTIAL AMPLIFIER I/O Ordering Information PART NUMBER (Notes 2, 3) PART MARKING TEMP RANGE (C) PACKAGE (Pb-free) PKG. DWG. # ISL15100IRZ 151 00IRZ -40 to +85 16 Ld QFN L16.4x4H ISL15100IRZ-T7 (Note 1) 151 00IRZ -40 to +85 16 Ld QFN L16.4x4H ISL15100IRZ-T13 (Note 1) 151 00IRZ -40 to +85 16 Ld QFN L16.4x4H ISL15100EVAL1Z Evaluation Board NOTES: 1. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. For Moisture Sensitivity Level (MSL), please see device information page for ISL15100. For more information on MSL please see tech brief TB363. 2 FN8577.0 September 19, 2013 ISL15100 Pin Configuration OUTA NC VS+ OUTB ISL15100 (16 LD QFN) TOP VIEW 16 15 14 13 NC 1 12 NC INA- 2 11 INBEP* 5 6 7 8 C0 9 VS- GND 4 NC 10 INB+ NC INA+ 3 C1 *EXPOSED THERMAL PAD CONNECTS TO MOST NEGATIVE SUPPLY Pin Descriptions PIN NUMBER PIN NAME EP THERMAL PAD 1 NC No Internal Connection 2 INA- Amplifier A Inverting Input 3 INA+ Amplifier A Non-Inverting Input 4 GND 5 NC No Internal Connection 6 NC No Internal Connection 7 VS- Negative Supply Voltage (-6V for split supplies, GND for single supply operation) 8 C0 Digital Control Pin 9 C1 Digital Control Pin 10 INB+ Amplifier B Non-Inverting Input 11 INB- Amplifier B Inverting Input 12 NC 13 OUTB FUNCTION Connect to the Most Negative Supply Ground No Internal Connection Amplifier B Output 14 VS+ Positive Supply Voltage (+6V for split supplies, +12V for single supply operation) 15 NC No Internal Connection 16 OUTA Amplifier A Output C0, C1 Truth Table C1 C0 0 0 High Bias Setting 0 1 Medium Bias Setting 1 0 Low Bias Setting 1 1 Outputs Disabled (Power Down) 3 FUNCTION FN8577.0 September 19, 2013 ISL15100 Absolute Maximum Ratings (TA = +25C) Thermal Information VS+ Voltage to VS- or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +13.3V INA+, INB+ Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND to VS+ C0, C1 Voltage to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VS+ Current into any Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8mA Continuous Output Current for Long Term Reliability. . . . . . . . . . . . . . . . 50mA Latch-up (Tested per JESD78D, Class II) . . . . . . . . . . . . . . . . . . . . . . 100mA ESD Rating Human Body Model (Tested per JESD22-A114F). . . . . . . . . . . . . . . . . . 4kV Charge Device Model (Tested per JESD22-C101E). . . . . . . . . . . . . 1.5kV Machine Model (Tested per JESD22-A115C) . . . . . . . . . . . . . . . . . 300V Thermal Resistance (Typical) JA (C/W) JC (C/W) 16 Ld QFN Package (Notes 4, 5) . . . . . . . . 53 16.5 Maximum Junction Temperature (Plastic Package) . . . . . . . . . . . +150C Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . -40C to +150C Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Operating Conditions Ambient Temperature Range . . . . . . . . . . . . . . . . . . . . . . . -40C to +85C Junction Temperature Range . . . . . . . . . . . . . . . . . . . . . . - 40C to +150C CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 4. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with "direct attach" features. See Tech Brief TB379. 5. For JC, the "case temp" location is the center of the exposed metal pad on the package underside. Electrical Specifications VS+ = +12V, VS- = GND = 0V, see Figure 3, Full Bias (C0 = C1 = 0V), TA = +25C, unless otherwise specified. PARAMETER DESCRIPTION CONDITIONS MIN (Note 6) TYP MAX (Note 6) UNIT DYNAMIC PERFORMANCE -3dB Bandwidth BW Figure 3, 2VP-P differential output at pins 180 MHz Slew Rate SR Differential VOUT (VOUTA - VOUTB) from -5V to +5V (10VP-P) 1200 V/s Total Harmonic Distortion THD, Low Frequency, 200kHz, differential 12VP-P, across 350 Light Load differential load -88 -67 dBc THD, Low Frequency, 200kHz, differential 12VP-P, across 29 differential load Heavy Load -72 -68 dBc THD, High Frequency, 4MHz, differential 12VP-P, across 350 Light Load differential load -64 -58 dBc THD, High Frequency, 4MHz, differential 12VP-P, across 29 Heavy Load differential load -51 -48 dBc Avg. Multi-Tone Power Ratio MTPR 2MHz to 50MHz, 25kHz tone spacing, PLINE = 15.5dBm, CF = 15dB -43 dBc Off State Multi-Tone Power Ratio MTPR-OFF 2MHz to 50MHz, 25kHz tone spacing, PLINE = 15.5dBm, CF = 15dB -55 dBc Non-inverting Input Spot Voltage Noise Eni F > 1MHz, spot noise voltage on INA+ and INB+ inputs separately 6 nV/Hz Non-inverting Input Spot Current Noise Ini+ F > 1MHz, spot noise current on INA+ and INB+ inputs separately 13 pA/Hz Inverting Input Spot Current Noise Ini- F > 1MHz, spot noise current on INA- and INB- inputs separately 50 pA/Hz Non-Inverting Input Bias Current IB+ Non-inverting inputs, INA+ and INB+, at mid-supply voltage (Note 7) -7 2 7 A Non-Inverting Input Bias Current Mismatch IB+DM Difference between the INA+ and INB+ bias currents -0.5 0 0.5 A Inverting Input Bias Current IB- Inverting inputs, INA- and INB-, at mid supply voltage (Note 7) -90 -30 55 A DC AND INPUT CHARACTERISTICS 4 FN8577.0 September 19, 2013 ISL15100 Electrical Specifications VS+ = +12V, VS- = GND = 0V, see Figure 3, Full Bias (C0 = C1 = 0V), TA = +25C, unless otherwise specified. PARAMETER DESCRIPTION CONDITIONS MIN (Note 6) TYP MAX (Note 6) UNIT Inverting Input Bias Current Mismatch IB-DM Difference between the INA- and INB- input bias currents -35 0 35 A Inverting Input Bias Current Common Mode IB-CM Average inverting input bias currents (Note 7) -90 -30 55 A Input Offset Voltage VIOA, VIOB Voltage difference from INA+ to INA- and from INB+ to INB- -85 0 85 mV Input Offset Voltage Mismatch VIODM VIOA - VIOB -5 0 5 mV Input Offset Voltage Common Mode VIOCM Average offset voltage across the two inputs -80 20 80 mV Differential Mode Output Offset Voltage VOSDM Output referred total effect of all differential DC error terms -7.8 0 7.8 mV Common Mode Output Offset Voltage VOSCM Output referred total effect of all common mode DC errors -105 40 145 mV Input Headroom to Positive Supply (VS+) - VIN(MAX) INA+ and INB+ required margin to VS+ supply 3 V Input Headroom to Negative Supply VIN(MIN) - (VS-) INA+ and INB+ required margin to VSsupply 3 V VO-OPEN VS = 6V, Differential RLOAD 1k, each output pin voltage range 5.0 V VO-LOADED VS = 6V, VO in linear region, Differential RLOAD = 29, each output pin voltage range. 4.6 V OUTPUT CHARACTERISTICS Output Swing 4.85 VS = 6V, VO driven into the rail, differential RLOAD = 29, each output pin voltage range. 4.2 4.7 V IO Linear output current (not short circuit) 300 400 mA Bipolar Supply Range VS Symmetric supply, pin 4 at GND for logic reference 4 6 6.6 V Single Supply Range VS+ Single supply with VS- and pin 4 at GND 8 12 13.2 V Positive Supply Currents IS+ (Full bias) VO(DIFF) = 0V, C0 = C1 = 0V 27 32 37 mA IS+ (Medium bias) VO(DIFF) = 0V, C0 = 3.3V, C1 = 0V 19 23 26 mA IS+ (Low bias) VO(DIFF) = 0V, C0 = 0V, C1 = 3.3V 12 15 18 mA IS+ (Power down) C0 = C1 = 3.3V 5.5 7 8.5 mA C0, C1 Input High Current IINH, C0 or C1 C0 = C1 = 3.3V (Note 7) -150 -90 -30 A C0, C1 Input Low Current IINL, C0 or C1 C0 = C1 = 0V (Note 7) -1.5 1 1.5 A C0, C1 Logic High Voltage VINH Pin 4 at GND, logic reference pin 2 3.3 5.5 V C0, C1 Logic Low Voltage VINL Pin 4 at GND, logic reference pin -0.3 0 0.8 V Output Current POWER SUPPLY NOTES: 6. Compliance to data sheet limits is assured by one or more methods: production test, characterization and/or design. 7. Positive currents flow out of the pin. 5 FN8577.0 September 19, 2013 ISL15100 Applications Information Multi-Tone Power Ratio (MTPR) Product Description G.hn PLC uses OFDM modulation to digitally encode data for communication. A carrier spacing of 24.41kHz is used in power lines, and 48.82kHz is used in phone lines. Feedback Resistor Values The ISL15100 has been designed and specified with RF = 1k for AV = +16. As is the case with all current feedback amplifiers, wider bandwidth at the expense of slight peaking, can be obtained by reducing the value of the feedback resistor. Inversely, larger values of the feedback resistor will cause rolloff to occur at a lower frequency. Quiescent Current vs Temperature The ISL15100 was designed to have the quiescent current increase with temperature, which maintains good distortion performance at high temperatures. Supply Voltage Range The ISL15100 operates with bipolar supply voltages from 4.0V to 6.6V (6.65V maximum). Optimum bandwidth, slew rate, and video characteristics are obtained at higher supply voltages. Single Supply Operation If a single supply is desired, values from +8.0V to +13.2V (+13.3V maximum) can be used as long as the input common mode range is not exceeded. When using a single supply, be sure to either: 1. DC bias the inputs at an appropriate common mode voltage and AC-couple the signal. 2. Ensure the driving signal is within the common mode range of the ISL15100. In multi-tone signaling, linearity is shown in the MTPR measurement. MTPR measures the difference in power of a carrier tone vs. a missing tone. -30 -40 TONE POWER (dBm) The ISL15100 is a differential operational amplifier designed for line driving in power line communications (PLC). It is a low distortion, current mode feedback amplifier that draws moderately low supply current. Due to the current feedback architecture, the ISL15100 closed-loop -3dB bandwidth is dependent on the value of the feedback resistor. The desired bandwidth is selected by choosing the feedback resistor, RF, and then the gain is set by picking the gain resistor, RG. -50 -60 MTPR -70 -80 -90 -100 1.50 1.52 1.54 1.56 FREQUENCY (MHz) 1.58 1.60 FIGURE 4. PLC SIGNAL TONES WITH 25kHz SPACING Figure 4 shows ISL15100's MTPR performance for a narrow frequency span. Disable Linearity Unlike DSL, communication in PLC systems is half duplex meaning only one device can transmit at a time. When the line driver is not transmitting, it is disabled and the receiver is enabled. Figure 5 shows the shared transmit and receive signal path of two ends. When Txa is transmitting, optimal MTPR is achieved if Txb is removed. Since Txb cannot be removed, the best MTPR occurs if the line driver is a very high impedance when disabled. RBM are resistors to limit fault currents, and to provide a driving impedance to the transformer, thus setting its frequency span. RBM is typically low in value (<10). FIGURE 5. Tx AND Rx SIGNAL PATH. CASE1:[Txa: ON, Rxa: OFF, Txb: OFF, Rxb: ON]. CASE2:[Txa: OFF, Rxa: ON, Txb: ON, Rxb: OFF] 6 FN8577.0 September 19, 2013 ISL15100 PC Board Design Recommendation Thermal Resistance and Power Dissipation To minimize parasitic capacitance in the ISL15100 design, consider laying out short output traces. Also, select low capacitance protection devices, and use line transformers with low interwinding capacitance in the signal path. Thermal resistance for junction to ambient, TJA, is +53C/W. The power dissipation at 12V supply is 600mW. The ambient temperature allowed given the maximum junction temperature of +150C is: The supply decoupling capacitors must be close to the supply pins to minimize parasitic inductance in the supply paths. High frequency load currents are pulled through these capacitors, so placement of the 0.1F capacitors close to the supply pin(s) improves dynamic performance. The higher value 4.7F capacitors provide low frequency decoupling, so they can be placed farther from the supply pins. (EQ. 1) T A = T J - JA x Pd T A = +150C - 53 ( C W ) 600mW = +118C The ISL15100's thermal pad (EP) should be connected to VS(ground in single supply applications). For good thermal control, include a thermal pad in the layout footprint, as shown in the "Typical Recommended Land Pattern" on the "Package Outline Drawing" page. Adding vias to this thermal pad helps dissipate heat away from the package. The ISL15100 evaluation board uses four 10mil (hole size) vias with 20mil diameter pads. R4 0 OUTA R3 0 Rext4 OUTB 56.2 Rext2 243 Rext1 243 Rext3 22 2W TP1 D2 OPEN D1 OPEN TP2 D4 OPEN D3 OPEN VS- VS+ VS+ C3 3 VS+ TP5 GND 13 14 VS+ 15 16 + 12 11 + C1 9 VS+ R11 10K C2 TP14 GND 0.1uf J2 GND + TP13 VS- L2 C1 4.7uF 1 2 VS- VS- INB RSB 49.9 C0 VS- GND R10 100 R2 0 10 ISL15100IRZ 4 TP10 INB RGB OPEN 8 J1 VS+ J3 VS- U1 5 TP12 VS+ TP4 GND _ NC RSA 49.9 _ 7 R1 0 1k NC NC R9 100 NC 6 INA 2 RLB 3.9 1/4 W RFB 0.1uf NC 1 RGA OPEN L1 C4 RFA TP9 INA VS+ 4.7uF RLA 3.9 1/4 W 1k + SW1:1 4 SW1:2 3 D5 4.3V ZENER DIODE 2.9V@ 300 uA S/N=CMHZ5229B RCG 133 FIGURE 6. ISL15100 EVALUATION BOARD 7 FN8577.0 September 19, 2013 ISL15100 Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have the latest revision. DATE REVISION September 19 2013 FN8577.0 CHANGE Initial Release. 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No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 8 FN8577.0 September 19, 2013 ISL15100 Package Outline Drawing L16.4x4H 16 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 0, 1/12 2.40 4X 1.95 4.00 12X 0.65 A B 13 6 PIN 1 INDEX AREA 6 PIN #1 INDEX AREA 16 1 4.00 12 2.40 9 4 (4X) 0.15 5 8 0.10 M C A B 16x 0.5500.05 TOP VIEW BOTTOM VIEW 4 0.30 0.05 SEE DETAIL "X" 0.900.10 0.10 C C BASE PLANE SEATING PLANE ( 3 . 6 TYP ) SIDE VIEW ( (12x0.65) 2.40) (16x0.30) C 0 . 20 REF 5 (16x0.75) +0.03/-0.02 TYPICAL RECOMMENDED LAND PATTERN DETAIL "X" NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to ASME Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal 0.05 4. Dimension applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 5. Tiebar shown (if present) is a non-functional feature. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 9 FN8577.0 September 19, 2013