M68CBL05C - Motorola / Freescale Semiconductor

WWW.MOTOROLA.COM/SEMICONDUCTORS

M68HC08

Microcontrollers

MC68HC908GR8/D

Rev. 4, 6/2002

MC68HC908GR8

Technical Data

MC68HC908GR4

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MC68HC908G R8 — Rev 4.0 Technical Data

MOTOROLA 3

MC68HC908GR8

MC68HC908GR4

Technical Data — Rev 4.0

Motorola reserves the right to make changes without further notice to any products

herein. Motorola makes no warranty, representation or guarantee regarding the

suitability of its products for any particular purpose, nor does Motorola assume any

liability arising out of the application or use of any product or circuit, and specifically

disclaims any and all liability, including without limitation consequential or incidental

damages. "Typical" parameters which may be provided in Motorola data sheets and/or

specifications can and do vary in different applications and actual performance may

vary over time. All operating parameters, including "Typicals" must be validated for

each customer application by customer’s technical experts. Motorola does not convey

any licen se under its patent rights n or the rights of others. Moto rola prod ucts are not

designed, intended, or authorized for use as components in systems intended for

surgical implant into the body, or other applications intended to support or sustain life,

or for any oth er appl icat ion in whic h the fail ure of the Motor ola produ ct cou ld create a

situation where personal injury or death may occur. Should Buyer purchase or use

Motorola products for any such unintended or unauthorized application, Buyer shall

indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and

distributors harmless against all claims, costs, damages, and expenses, and

reasonable attorney fees arising out of, directly or indirectly, any claim of personal

injury or death associated with such unintended or unauthorized use, even if such claim

alleges that Motorola was negligent regarding the design or manufacture of the part.

Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.

Motorola and are registered trademarks of Motorola, Inc.

DigitalDNA is a trademark of Motorola, Inc. © Motorola, Inc., 2002

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Technical Data MC68HC908GR8 — Rev 4.0

4MOTOROLA

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MC68HC908GR8 — Rev 4.0 Technical Data

MOTOROLA List of Paragraphs 5

Technical Data — MC68HC908GR8

List of Paragraphs

List of Paragraphs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

List of Tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

Section 1. General Description . . . . . . . . . . . . . . . . . . . .25

Section 2. Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . .35

Section 3. Low Power Modes. . . . . . . . . . . . . . . . . . . . . .49

Section 4. Resets and Interrupts. . . . . . . . . . . . . . . . . . .61

Section 5. Analog-to-Digital Converter (ADC) . . . . . . . .79

Section 6. Break Module (BRK) . . . . . . . . . . . . . . . . . . . .91

Section 7. Clock Generator Module (CGMC) . . . . . . . . .99

Section 8. Configuration Register (CONFI G) . . . . . . . .129

Section 9. Computer Oper ating Properly (COP) . . . . .133

Section 10. Central Processing Unit (CPU) . . . . . . . . .139

Section 11. Flash Memory . . . . . . . . . . . . . . . . . . . . . . .157

Section 12. External Interrupt (IRQ) . . . . . . . . . . . . . . .167

Section 13. Keyboard Interrupt (KBI) . . . . . . . . . . . . . .175

Section 14. Low-Voltage Inhibit (LVI) . . . . . . . . . . . . . .183

Section 15. Monitor ROM (MON) . . . . . . . . . . . . . . . . . .189

Section 16. Input/Output Ports (I/O) . . . . . . . . . . . . . . .205

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List of Paragraphs

Technical Data MC68HC908GR8 — Rev 4.0

6 List of Paragraphs MOTOROLA

Section 17. RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .229

Section 18. Serial Communications Interface (SCI). . .231

Section 19. System Integration Modu le (SIM) . . . . . . .271

Section 20. Serial Peripheral Interface (SPI). . . . . . . . .297

Section 21. Timebase Module (TBM). . . . . . . . . . . . . . .329

Section 22. Timer Int erface Module (TIM) . . . . . . . . . . .335

Section 23. Electrical Specifications. . . . . . . . . . . . . . .361

Section 24. Mechanical Specifications . . . . . . . . . . . . .387

Section 25. Ordering Informatio n . . . . . . . . . . . . . . . . .391

Glossary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .395

Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .405

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MC68HC908GR8 — Rev 4.0 Technical Data
MOTOROLA Table of Contents 7
 
Technical Data — MC68HC908GR8
Table of Contents
List of Paragraphs
Table of Contents
List of Tables
List of Figures
Section 1. General Description
1.1 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
1.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
1.4 MCU Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
1.5 Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
1.6 Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Section 2. Memory Map
2.1 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
2.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
2.3 Unimplemented Memory Locations  . . . . . . . . . . . . . . . . . . . . . .35
2.4 Reserved Memory Locations . . . . . . . . . . . . . . . . . . . . . . . . . .36
2.5 Input/Output (I/O) Section. . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
    
  
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Table of Contents
Technical Data MC68HC908GR8 — Rev 4.0
8 Table of Conten ts MOTOROLA
Section 3. Low Power Modes
3.1 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
3.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
3.3 Analog-to-Digital Converter (ADC) . . . . . . . . . . . . . . . . . . . . . .50
3.4 Break Modu le (BRK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
3.5 Central Processor Unit (CPU). . . . . . . . . . . . . . . . . . . . . . . . . .51
3.6 Clock Generator Module (CGM). . . . . . . . . . . . . . . . . . . . . . . .52
3.7 Computer Operating Properly Module (COP). . . . . . . . . . . . . .52
3.8 External Interrupt Module (IRQ) . . . . . . . . . . . . . . . . . . . . . . . .53
3.9 Keyboard Interrupt Modul e (KBI) . . . . . . . . . . . . . . . . . . . . . . .53
3.10 Low-Voltage Inhibit Module (LVI) . . . . . . . . . . . . . . . . . . . . . . .54
3.11 Serial Communications Interface Module (SCI) . . . . . . . . . . . .54
3.12 Serial Peripheral Interface Module (SPI) . . . . . . . . . . . . . . . . .55
3.13 Timer Interface Module (TIM1 and TIM2). . . . . . . . . . . . . . . . .55
3.14 Timebase Module (TBM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
3.15 Exiting Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
3.16 Exiting Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
Section 4. Resets and Interrupts
4.1 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
4.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
4.3 Resets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
4.4 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
Section 5. Analog-to-Digital Converter (ADC)
5.1 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
5.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
    
  
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Table of Contents
MC68HC908GR8 — Rev 4.0 Technical Data
MOTOROLA Table of Contents 9
 
5.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
5.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
5.5 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
5.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
5.7 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
5.8 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
Section 6. Break Module (BRK)
6.1 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
6.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
6.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
6.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
6.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
6.6 Break Modu le Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
Section 7. Clock Generator Module (CGMC)
7.1 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
7.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
7.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100
7.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100
7.5 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112
7.6 CGMC Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114
7.7 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123
7.8 Special Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123
7.9 Acquisition/Lock Time Specifications . . . . . . . . . . . . . . . . . . .125
    
  
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Table of Contents
Technical Data MC68HC908GR8 — Rev 4.0
10 Table of Contents MOTOROLA
Section 8. Configuration Register (CONFIG)
8.1 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129
8.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129
8.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129
Section 9. C omputer Operating Pr operly (COP)
9.1 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133
9.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133
9.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133
9.4 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135
9.5 COP Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 36
9.6 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136
9.7 Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137
9.8 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 37
9.9 COP Module During Break Mode. . . . . . . . . . . . . . . . . . . . . .137
Section 10. Central Processi ng Unit (CPU)
10.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139
10.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139
10.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 39
10.4 CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140
10.5 Arithmetic/logic unit (ALU) . . . . . . . . . . . . . . . . . . . . . . . . . . .145
10.6 Low-power modes  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145
10.7 CPU during break interrupts. . . . . . . . . . . . . . . . . . . . . . . . . .146
10.8 Instruction Set Summary  . . . . . . . . . . . . . . . . . . . . . . . . . . . .147
10.9 Opcode Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 54
    
  
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Table of Contents
MC68HC908GR8 — Rev 4.0 Technical Data
MOTOROLA Table of Contents 1 1
 
Section 11. Flash Memory
11.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .157
11.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .157
11.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 57
11.4 FLASH Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . .159
11.5 FLASH Page Erase Operation . . . . . . . . . . . . . . . . . . . . . . . .160
11.6 FLASH Mass Erase Operation . . . . . . . . . . . . . . . . . . . . . . . .161
11.7 FLASH Program/Read Operation. . . . . . . . . . . . . . . . . . . . . .162
11.8 FLASH Block Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . .163
11.9 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .166
11.10 STOP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .166
Section 12. External Interrupt (IRQ)
12.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .167
12.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .167
12.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 67
12.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 68
12.5 IRQ1 Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .170
12.6 IRQ Module During Break Interrupts  . . . . . . . . . . . . . . . . . . .171
12.7 IRQ Status and Control Register . . . . . . . . . . . . . . . . . . . . . .172
Section 13. Keyboard Interrupt (KBI)
13.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175
13.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175
13.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 75
13.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 76
13.5 Keyboard Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .179
    
  
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Table of Contents
Technical Data MC68HC908GR8 — Rev 4.0
12 Table of Contents MOTOROLA
13.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .180
13.7 Keyboard Module During Break Interrupts . . . . . . . . . . . . . . .180
13.8 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 81
Section 14. Low-Volt age Inhibit (LVI)
14.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .183
14.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .183
14.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 83
14.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 84
14.5 LVI Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .187
14.6 LVI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .188
14.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .188
Section 15. Mon itor ROM (MON)
15.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .189
15.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .189
15.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 89
15.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 90
15.5 Security. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .202
Section 16. Input/Output Ports (I/O)
16.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .205
16.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .205
16.3 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .209
16.4 Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .213
16.5 Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 16
16.6 Port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 20
    
  
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Table of Contents
MC68HC908GR8 — Rev 4.0 Technical Data
MOTOROLA Table of Contents 1 3
 
16.7 Port E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .225
Section 17. RAM
17.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .229
17.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .229
17.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 29
Section 18. Ser ial Communicatio ns Interf ace (SCI)
18.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .231
18.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .231
18.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 32
18.4 Pin Name Conventions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .233
18.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 33
18.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .250
18.7 SCI During Break Module Interrupts. . . . . . . . . . . . . . . . . . . .2 51
18.8 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .251
18.9 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 52
Section 19. System Integration Module (SIM)
19.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .271
19.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .271
19.3 SIM Bus Cl ock Control and Generation . . . . . . . . . . . . . . . . .275
19.4 Reset and System Initialization. . . . . . . . . . . . . . . . . . . . . . . .276
19.5 SIM Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .281
19.6 Exception Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .282
19.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .290
19.8 SIM Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .293
    
  
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Table of Contents
Technical Data MC68HC908GR8 — Rev 4.0
14 Table of Contents MOTOROLA
Section 20. Ser ial Peripheral Interface (SPI)
20.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .297
20.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .297
20.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 98
20.4 Pin Name Conven tions and I/O Register Addresses . . . . . . .298
20.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 99
20.6 Transmission Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .303
20.7 Queuing Transmission Data. . . . . . . . . . . . . . . . . . . . . . . . . .309
20.8 Error Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .310
20.9 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .314
20.10 Resetting the SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 16
20.11 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 17
20.12 SPI During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . .318
20.13 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .318
20.14 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .322
Section 21. Timebase Module (TBM)
21.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .329
21.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .329
21.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 29
21.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 30
21.5 Timebase Register Description. . . . . . . . . . . . . . . . . . . . . . . .3 31
21.6 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .332
21.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .333
Section 22. Timer Interface Module (TIM)
22.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .335
    
  
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Table of Contents
MC68HC908GR8 — Rev 4.0 Technical Data
MOTOROLA Table of Contents 1 5
 
2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .335
3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 36
4 Pin Name Conventions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .336
5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 37
6 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .346
7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .347
8 TIM During Break Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . .348
9 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .348
10 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .349
Section 23. Electr ical Specifications
1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .361
2 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . .362
3 Functional Operating Range. . . . . . . . . . . . . . . . . . . . . . . . . .363
4 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .363
5 5.0 V DC Electrical Characteristics. . . . . . . . . . . . . . . . . . . . .364
6 3.0 V DC Electrical Characteristics. . . . . . . . . . . . . . . . . . . . .366
7 5.0 V Control Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .368
8 3.0 V Control Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .369
9 Output High-Voltage Characteristics  . . . . . . . . . . . . . . . . . . .370
10 Output Lo w-Voltage Characteristics. . . . . . . . . . . . . . . . . . . .373
11 Typical Supply Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . .376
12 ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .378
13 5.0 V SPI Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 79
14 3.0 V SPI Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 80
15 Timer Interface Module Characteristics . . . . . . . . . . . . . . . . .3 83
    
  
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Table of Contents
Technical Data MC68HC908GR8 — Rev 4.0
16 Table of Contents MOTOROLA
23.16 Clock Generation Module Characteristics  . . . . . . . . . . . . . . .383
23.17 Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .385
Section 24. Mechanical Specifications
24.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .387
24.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .387
24.3 32-Pin LQFP (Case #873A) . . . . . . . . . . . . . . . . . . . . . . . . . .3 88
24.4 28-Pin PDIP (Case #710). . . . . . . . . . . . . . . . . . . . . . . . . . . .389
24.5 28-Pin SOIC (Case #751F). . . . . . . . . . . . . . . . . . . . . . . . . . .390
Section 25. Ordering Information
25.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .391
25.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .391
25.3 MC Order Numbers  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .392
25.4 Development Tools. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .393
Glossary
Revision History
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .405
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .405
Changes from Rev 3.0 published in Febru ary 2002 to Rev 4.0 
published i n June 2002. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 05
Changes f rom Rev 2.0 published in January 2002 to Rev 3.0 pub-
lished in February 2002 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .406
Changes fr om Rev 1.0 published in April 2001 to Rev 2.0 pub-
lished in December 2001 . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 06
    
  
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MC68HC908GR8 — Rev 4.0 Technical Data
MOTOROLA List of Tables 17
 
Technical Data — MC68HC908GR8
List of Tab les
Table Title Page
2-1 Vector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
4-1 Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
4-2 Interrupt Source Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
5-1 Mux Channel Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
5-2 ADC Clock Divide Ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
7-1 Numeric Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
7-2 PRE 1 and PRE0 Programming . . . . . . . . . . . . . . . . . . . . . . .117
7-3 VPR1 and VPR0 Programming  . . . . . . . . . . . . . . . . . . . . . . .117
10-1 Instruction Se t Summary  . . . . . . . . . . . . . . . . . . . . . . . . . . . .147
10-2 Opcode Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155
11-1 Examples of protect start address:. . . . . . . . . . . . . . . . . . . . .166
14-1 LVIOUT Bit Indication. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .187
15-1 Monitor Mode Signal Requirements and Option s. . . . . . . . . .193
15-2 Mode Differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .196
15-3 Monitor Baud Rate Selection . . . . . . . . . . . . . . . . . . . . . . . . .197
15-4 READ (Read Memory) Command . . . . . . . . . . . . . . . . . . . . .199
15-5 WRITE (Write Memory) Command. . . . . . . . . . . . . . . . . . . . .199
15-6 IREAD (Indexed Read) Command . . . . . . . . . . . . . . . . . . . . .200
15-7 IWRITE (Indexed Write) Command . . . . . . . . . . . . . . . . . . . .200
15-8 READSP (Read Stack Pointer) Command. . . . . . . . . . . . . . .201
15-9 RUN (Run User Program) Command. . . . . . . . . . . . . . . . . . .201
16-1 Port Control Register Bits Summary. . . . . . . . . . . . . . . . . . . .208
16-2 Port A Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .211
16-3 Port B Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .215
16-4 Port C Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .218
16-5 Port D Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .223
16-6 Port E Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .227
18-1 Pin Name Conventions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .233
18-2 Start Bit Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .244
    
  
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List of Tab les
Technical Data MC68HC908GR8 — Rev 4.0
18 List of Tables MOTOROLA
18-3 Data Bit Recovery. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .244
18-4 Stop Bit Recovery. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .245
18-5 Character Format Selection . . . . . . . . . . . . . . . . . . . . . . . . . .255
18-6 SCI Baud Rate Prescal ing . . . . . . . . . . . . . . . . . . . . . . . . . . .266
18-7 SCI Baud Rate Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . .266
18-8 SCI Baud Rate Selection Examples. . . . . . . . . . . . . . . . . . . .268
19-1 Signal Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . .273
19-2 PIN Bit Set Timing  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .277
19-3 Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .286
19-4 SIM Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .293
20-1 Pin Name Conventions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .299
20-2 SPI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .314
20-3 SPI Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .321
20-4 SPI Master Baud Rate Selection . . . . . . . . . . . . . . . . . . . . . .327
21-1 Timebase Rate Selection for OSC1 = 32 .768 kHz . . . . . . . . .331
22-1 Pin Name Conventions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .336
22-2 Prescaler Selecti on. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .351
22-3 Mode, Edge , and Level Selection. . . . . . . . . . . . . . . . . . . . . .358
23-1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . .362
23-2 Functional Operation Range. . . . . . . . . . . . . . . . . . . . . . . . . .363
23-3 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .363
23-4 5.0V DC Electrical C haracteristics . . . . . . . . . . . . . . . . . . . . .364
23-5 3.0 V DC Electrical Characteristics. . . . . . . . . . . . . . . . . . . . .366
23-6 5.0 V Control Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .368
23-7 3.0 V Control Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .369
23-8 Timer Interface Module Characteristics . . . . . . . . . . . . . . . . .383
23-9 CGM Component Specifications. . . . . . . . . . . . . . . . . . . . . . .383
25-1 MC Order Number s  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .392
25-2 Development Tool Kits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .393
25-3 Development Tool Components. . . . . . . . . . . . . . . . . . . . . . .393
    
  
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MC68HC908GR8 — Rev 4.0 Technical Data
MOTOROLA List of Figures 19
 
Technical Data — MC68HC908GR8
List of Figures
Figure Title Page
1-1 MCU Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
1-2 QFP Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
1-3 DIP And SOIC Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . .31
1-4 Power Supply Bypassing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
2-1 Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
2-2 Control, Status, and Data Registers. . . . . . . . . . . . . . . . . . . . .39
4-1 Internal Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
4-2 Power-On Reset Recovery. . . . . . . . . . . . . . . . . . . . . . . . . . . .63
4-3 SIM Reset Status Register (SRSR) . . . . . . . . . . . . . . . . . . . . .65
4-4 Interrupt Stacking Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
4-5 Interrupt Recognition Example . . . . . . . . . . . . . . . . . . . . . . . . .68
4-6 Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
4-7 Interrupt Status Register 1 (INT1). . . . . . . . . . . . . . . . . . . . . . .76
4-8 Interrupt Status Register 2 (INT2). . . . . . . . . . . . . . . . . . . . . . .76
4-9 Interrupt Status Register 3 (INT3). . . . . . . . . . . . . . . . . . . . . . .77
5-1 ADC Block Diagr am . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
5-2 ADC Status and Control Register (ADSCR). . . . . . . . . . . . . . .85
5-3 ADC Data Register (ADR ) . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
5-4 ADC Clock Register (ADCLK)  . . . . . . . . . . . . . . . . . . . . . . . . .88
6-1 Break Modu le Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . .92
6-2 I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
6-3 Break Status and Control Register (BRKSCR). . . . . . . . . . . . .95
6-4 Break Ad dress Register High (BRKH) . . . . . . . . . . . . . . . . . . .96
6-5 Break Ad dress Register Low (BRKL) . . . . . . . . . . . . . . . . . . . .96
6-6 SIM Break Status Register (SBSR) . . . . . . . . . . . . . . . . . . . . .96
6-7 SIM Break Flag Control Register (SBFCR)  . . . . . . . . . . . . . . .98
7-1 CGMC Block Diagram  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101
7-2 CGMC External Connections . . . . . . . . . . . . . . . . . . . . . . . . .111
7-3 CGMC I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . .114
    
  
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List of Figures
Technical Data MC68HC908GR8 — Rev 4.0
20 List of Figures MOTOROLA
7-4 PLL Control Register (PCTL) . . . . . . . . . . . . . . . . . . . . . . . . .115
7-5 PLL Band width Control Register (PBWC)  . . . . . . . . . . . . . . .118
7-6 PLL Multiplier Select Register High (PMSH)  . . . . . . . . . . . . .119
7-7 PLL Multiplier Select Register Low (PMSL) . . . . . . . . . . . . . .120
7-8 PLL VCO Range Select Register (PMRS) . . . . . . . . . . . . . . .121
7-9 PLL Reference Divider Select Register (PMDS)  . . . . . . . . . .1 22
7-10 PLL Filter  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127
8-1 Configuration Register 2 (CONFIG2) . . . . . . . . . . . . . . . . . . .130
8-2 Configuration Register 1 (CONFIG1) . . . . . . . . . . . . . . . . . . .130
9-1 COP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134
9-2 COP Control Register (COPCTL). . . . . . . . . . . . . . . . . . . . . .136
10-1 CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140
10-2 Accumulator (A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141
10-3 Index register (H:X). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 41
10-4 Stack pointer (SP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .142
10-5 Program counter (PC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143
10-6 Condition  code register (CCR) . . . . . . . . . . . . . . . . . . . . . . . .143
11-1 FLASH Control Register  (FLCR)  . . . . . . . . . . . . . . . . . . . . . .159
11-2 FLASH Programming Flowchart. . . . . . . . . . . . . . . . . . . . . . .164
11-3 FLASH Block Protect Register (FLBPR). . . . . . . . . . . . . . . . .165
11-4 FLASH Block Protect Start Address. . . . . . . . . . . . . . . . . . . .165
12-1 IRQ Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . .169
12-2 IRQ I/O Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . .1 69
12-3 IRQ Status and Control Register (INTSCR) . . . . . . . . . . . . . .172
13-1 Keyboard Module Block Diagram. . . . . . . . . . . . . . . . . . . . . .177
13-2 I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .177
13-3 Keyboard Status and Control Registe r (INTKBSCR) . . . . . . .181
13-4 Keyboard Interrupt Enable Register (INTKBIER) . . . . . . . . . .1 82
14-1 LVI Module Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . .185
14-2 LVI I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . .186
14-3 LVI Status Register (LVISR). . . . . . . . . . . . . . . . . . . . . . . . . .1 87
15-1 Monitor Mode Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .191
15-2 Low-Voltage Monitor Mode Entry Flowchart. . . . . . . . . . . . . .195
15-3 Monitor Data Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .196
15-4 Break Transacti on. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .196
15-5 Read Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .198
15-6 Write Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .198
15-7 Stack Pointe r at Monitor Mode Entry . . . . . . . . . . . . . . . . . . .202
    
  
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List of Figures
MC68HC908GR8 — Rev 4.0 Technical Data
MOTOROLA List of Figures 21
 
15-8 Monitor Mode En try Timing. . . . . . . . . . . . . . . . . . . . . . . . . . .203
16-1 I/O Port Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . .206
16-2 Port A Data Register (PTA)  . . . . . . . . . . . . . . . . . . . . . . . . . .209
16-3 Data Direction Register A (DDRA) . . . . . . . . . . . . . . . . . . . . .210
16-4 Port A I/O C ircuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .211
16-5 Port A Inpu t Pullup Enable Register (PTAPUE) . . . . . . . . . . .212
16-6 Port B Data Register (PTB)  . . . . . . . . . . . . . . . . . . . . . . . . . .213
16-7 Data Direction Register B (DDRB) . . . . . . . . . . . . . . . . . . . . .214
16-8 Port B I/O C ircuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .215
16-9 Port C Data Register (PTC) . . . . . . . . . . . . . . . . . . . . . . . . . .216
16-10 Data Direction Register C (DDRC). . . . . . . . . . . . . . . . . . . . .217
16-11 Port C I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .218
16-12 Port C Input Pullup Enable Register (PTCPUE). . . . . . . . . . .219
16-13 Port D Data Register (PTD) . . . . . . . . . . . . . . . . . . . . . . . . . .220
16-14 Data Direction Register D (DDRD). . . . . . . . . . . . . . . . . . . . .222
16-15 Port D I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .223
16-16 Port D Input Pullup Enable Register (PTDPUE). . . . . . . . . . .224
16-17 Port E Data Register (PTE)  . . . . . . . . . . . . . . . . . . . . . . . . . .2 25
16-18 Data Direction Register E (DDRE) . . . . . . . . . . . . . . . . . . . . .226
16-19 Port E I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .227
18-1 SCI Module Bl ock Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . .234
18-2 SCI I/O Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . .235
18-3 SCI Data Formats. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .236
18-4 SCI Transmitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .237
18-5 SCI Receiver Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . .242
18-6 Receiver Data Sa mpling. . . . . . . . . . . . . . . . . . . . . . . . . . . . .243
18-7 Slow Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 46
18-8 Fast Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .247
18-9 SCI Control Register 1 (SCC1). . . . . . . . . . . . . . . . . . . . . . . .2 53
18-10 SCI Control Register 2 (SCC2). . . . . . . . . . . . . . . . . . . . . . . .2 56
18-11 SCI Control Register 3 (SCC3). . . . . . . . . . . . . . . . . . . . . . . .2 58
18-12 SCI Status R egister 1 (SCS1)  . . . . . . . . . . . . . . . . . . . . . . . .260
18-13 Flag Clearing Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 63
18-14 SCI Status R egister 2 (SCS2)  . . . . . . . . . . . . . . . . . . . . . . . .264
18-15 SCI Data Register (SCDR). . . . . . . . . . . . . . . . . . . . . . . . . . .265
18-16 SCI Baud Rate Register (SCBR) . . . . . . . . . . . . . . . . . . . . . .265
19-1 SIM Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 72
19-2 SIM I/O Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . .274
    
  
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List of Figures
Technical Data MC68HC908GR8 — Rev 4.0
22 List of Figures MOTOROLA
19-3 CGM Clock Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 75
19-4 External Reset Timing  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .277
19-5 Internal Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .278
19-6 Sources of Internal Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . .278
19-7 POR Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .279
19-8 Interrupt Entry Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .283
19-9 Interrupt Recovery Timing  . . . . . . . . . . . . . . . . . . . . . . . . . . .283
19-10 Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .284
19-11 Interrupt Recognition Example. . . . . . . . . . . . . . . . . . . . . . . .285
19-12 Interrupt Status Register 1 (INT1). . . . . . . . . . . . . . . . . . . . . .288
19-13 Interrupt Status Register 2 (INT2). . . . . . . . . . . . . . . . . . . . . .288
19-14 Interrupt Status Register 3 (INT3). . . . . . . . . . . . . . . . . . . . . .289
19-15 Wait Mode Entry Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .291
19-16 Wait Recovery from Interrupt or Break. . . . . . . . . . . . . . . . . .291
19-17 Wait Recovery from Internal Reset. . . . . . . . . . . . . . . . . . . . .292
19-18 Stop Mode Entry Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . .293
19-19 Stop Mode Recovery from Interrupt or Break. . . . . . . . . . . . .293
19-20 SIM Break Status Register (SBSR) . . . . . . . . . . . . . . . . . . . .294
19-21 SIM Reset Status Register (SRSR) . . . . . . . . . . . . . . . . . . . .295
19-22 SIM Break Flag Control Register (SBFCR)  . . . . . . . . . . . . . .296
20-1 SPI I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . .299
20-2 SPI Module Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . .300
20-3 Full-Duplex Master-Slave Connections  . . . . . . . . . . . . . . . . .301
20-4 Transmission Format (CPHA = 0)  . . . . . . . . . . . . . . . . . . . . .305
20-5 CPHA/SS Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 05
20-6 Transmission Format (CPHA = 1)  . . . . . . . . . . . . . . . . . . . . .306
20-7 Transmission Start Delay (Master). . . . . . . . . . . . . . . . . . . . .308
20-8 .SPRF/SPTE CPU Interrupt Timing . . . . . . . . . . . . . . . . . . . .309
20-9 Missed Read of Over flow Condition . . . . . . . . . . . . . . . . . . . .311
20-10 Clearing SPRF When OVRF Interrupt Is Not Enabled . . . . . .3 12
20-11 SPI Interrupt Request Generation  . . . . . . . . . . . . . . . . . . . . .315
20-12 CPHA/SS Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .320
20-13 SPI Control Register (SPCR) . . . . . . . . . . . . . . . . . . . . . . . . .322
20-14 SPI Status and Control Register (SPSCR). . . . . . . . . . . . . . .325
20-15 SPI Data Register (SPDR) . . . . . . . . . . . . . . . . . . . . . . . . . . .328
21-1 Timebase Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .330
21-2 Timebase Control Register (TBCR) . . . . . . . . . . . . . . . . . . . .331
22-1 TIM Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .338
    
  
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List of Figures
MC68HC908GR8 — Rev 4.0 Technical Data
MOTOROLA List of Figures 23
 
22-2 TIM I/O Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . .339
22-3 PWM Period and Pulse Width  . . . . . . . . . . . . . . . . . . . . . . . .343
22-4 TIM Status and Control Register (T SC) . . . . . . . . . . . . . . . . .3 49
22-5 TIM Counter Registers High (T CNTH) . . . . . . . . . . . . . . . . . .352
22-6 TIM Counter Registers Low (TCNTL). . . . . . . . . . . . . . . . . . .352
22-7 TIM Counter Modulo Register High (TMODH) . . . . . . . . . . . .353
22-8 TIM Counter Modulo Register Low (TMODL). . . . . . . . . . . . .353
22-9 TIM Counter Register High (TCNTH) . . . . . . . . . . . . . . . . . . .354
22-10 TIM Counter Register Low (TCNTL). . . . . . . . . . . . . . . . . . . .354
22-11 TIM Channel 0 Status and Control Register (TSC0)  . . . . . . .355
22-12 TIM Channel 1 Status and Control Register (TSC1)  . . . . . . .355
22-13 CHxMAX La tency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .359
22-14 TIM Channel 0 Register High (TCH0H) . . . . . . . . . . . . . . . . .360
22-15 TIM Channel 0 Register Low (TCH0L) . . . . . . . . . . . . . . . . . .360
22-16 TIM Channel 1 Register High (TCH1H) . . . . . . . . . . . . . . . . .360
22-17 TIM Channel 1 Register Low (TCH1L) . . . . . . . . . . . . . . . . . .360
23-1 Typical High-Side Driver Characteristics –
Port PTA3–PTA0 (VDD = 4.5 Vdc) . . . . . . . . . . . . . . . . . . . . .370
23-2 Typical High-Side Driver Characteristics –
Port PTA3–PTA0 (VDD = 2.7 Vdc) . . . . . . . . . . . . . . . . . . . . .370
23-3 Typical High-Side Driver Characteristics –
Port P T C1–PTC0 (VDD = 4.5 Vdc) . . . . . . . . . . . . . . . . . . . . .371
23-4 Typical High-Side Driver Characteristics –
Port P T C1–PTC0 (VDD = 2.7 Vdc) . . . . . . . . . . . . . . . . . . . . .371
23-5 Typical High-Side Driver Characteristics – Ports PTB5–PTB0, 
PTD6–PTD0, and PTE1–PTE0 (VDD = 5.5 Vdc) . . . . . . . . . .372
23-6 Typical High-Side Driver Characteristics – Ports PTB5–PTB0, 
PTD6–PTD0, and PTE1–PTE0 (VDD = 2.7 Vdc) . . . . . . . . . .372
23-7 Typical Low-Side Driver Ch aracteristics –
Port PTA3–PTA0 (VDD = 5.5 Vdc) . . . . . . . . . . . . . . . . . . . . .373
23-8 Typical Low-Side Driver Ch aracteristics –
Port PTA3–PTA0 (VDD = 2.7 Vdc) . . . . . . . . . . . . . . . . . . . . .373
23-9 Typical Low-Side Driver Ch aracteristics –
Port P T C1–PTC0 (VDD = 4.5 Vdc) . . . . . . . . . . . . . . . . . . . . .374
23-10 Typic al Low-Side Driver Chara c teristics –
Port P T C1–PTC0 (VDD = 2.7 Vdc) . . . . . . . . . . . . . . . . . . . . .374
23-11 Typic al Low-Side Driver Chara c teristics – Ports PTB5–PTB0, 
PTD6–PTD0, and PTE1–PTE0 (VDD = 5.5 Vdc) . . . . . . . . . .375
    
  
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List of Figures

Technical Data MC68HC908GR8 — Rev 4.0

24 List of Figures MOTOROLA

23-12 Typic al Low-Side Driver Chara c teristics – Ports PTB5–PTB0,

PTD6–PTD0, and PTE1–PTE0 (VDD = 2.7 Vdc) . . . . . . . . . .375

23-13 Typical Operating IDD, with All Modules Turned On

(–40 °C to 125 °C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 76

23-14 Typical Wait Mode ID D, with all Modules Disabled

(–40 °C to 125 °C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 76

23-15 Typical Stop Mode IDD, with all Modules Disabled

(–40 °C to 125 °C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 77

23-16 SPI Master Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .381

23-17 SPI Slave Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .382

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MC68HC908GR8 — Rev 4.0 Technical Data
MOTOROLA General Description 25
 
Technical Data — MC68HC908GR8
Section 1. General Descriptio n
1.1  Contents
1.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
1.4 MCU Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
1.5 Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
1.6 Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
1.2  Introduction
The MC68HC908GR8 is a member of the low-cost, high-performance 
M68H C08 Fa mily  of 8- bit  micro cont rol ler uni ts  (MCU s).  All M CUs  in th e 
family use the enhanced M68HC08 central processor unit (CPU08) and 
are available with a variety of modules, memory sizes and types, and 
package type s.
This document also describes the MC68HC908GR4. The 
MC68HC908GR4 is a device identical to the MC68HC908GR8 except 
that it ha s less Flash memo ry. Only when there ar e differences fr om the 
MC68HC908GR8 is the MC68HC908GR4 specifically mentioned in the 
text.
    
  
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General Description

Technical Data MC68HC908GR8 — Rev 4.0

26 General Description MOTOROLA

1.3 Features

For co nven ience, features have been or ganize d to ref lect:

•Standard features of the MC68HC908GR8

•Features of the CPU08

1.3.1 Standard Features of the MC68HC908GR8

•High-performance M68HC08 architecture optimized for C-

compilers

•Fully up wa r d- com pa ti ble object cod e wi th M 680 5, M 14 68 05, and

M68HC05 Families

•8-MHz internal bus frequency

•FLASH program memory security(1)

•On-chip programming firmware for use with host personal

computer which does not require high voltage for entry

•In-system programming

•Syst em protection features:

–Optional computer operating pr operly (COP) reset

–Low-voltage detection with optional reset and selectable trip

points for 3.0 V and 5.0 V operation

–Illegal opcode detection with reset

–Illegal address detection with reset

•Low-power design; fully static with stop and wait modes

•Standard low-power modes of operation:

–Wait mode

–Stop mode

•Master reset pin and power-on reset (P OR)

1. No security feature is absolutely se cure . Howe ve r, Moto rola ’s strategy is to make reading or

copying the FLASH difficult for unauthoriz ed users.

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General Description

Features

MC68HC908GR8 — Rev 4.0 Technical Data

MOTOROLA General Description 27

•7680 bytes of on-chip FLASH memo ry on the MC68HC908GR8

and 4096 bytes of on-chip FLASH memory on the

MC68HC908GR4 with in-circuit programmi ng capabilities of

FLASH program memory

•384 bytes of on-chip random-access memory (RAM)

•Serial peripheral in terfac e module (SPI)

•Serial communicatio ns interface module (SCI)

•One 16-b it, 2-channel timer (TIM1) and one 16-bit, 1-channel

timer (TIM2) interface modules wi th selectable input capture,

output comp are, and PWM capability on each channel

•6-channel, 8-bit successive approximation analog-to-digital

converter (ADC)

•BREAK module (BRK) to allow single breakpoint setting during in-

circuit debugging

•Internal pullups on IRQ and RST to reduce customer system cost

•Clock generator mo dule with on-chip 32-kHz crystal compatible

PLL (pha se- l ock loop)

•Up to 21 general-purpose input/output (I/O) pins, including:

–19 shared-function I/O pins

–Up to two dedicated I/O pins, depending on package choice

•Selectable pullups on inputs only on ports A, C, and D. Selection

is on an individual port bit basis. During output mode, pullups are

disengaged.

•High current 10-mA sink/10-mA source capability on all port pins

•Higher c urrent 15-mA sink/source ca pability on PTC0–PTC1

•Timebase module with clock prescaler circuitry for eight user

selecta bl e peri od ic re al- ti m e inter r upt s with opti o na l active clock

source du ring stop mode for periodic wakeup from stop using an

external 32- kHz crystal

•Oscillator stop mode enable bit (OSCSTOPENB) in the CONFIG

disabled du ring stop mode

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General Description

Technical Data MC68HC908GR8 — Rev 4.0

28 General Description MOTOROLA

•4-bit keyboard wakeup port

•32-pin quad fl at pack (QFP) or 28- pin pla stic dual -in-lin e package

(DIP) or 28-pin small o utline integrated circ uit (SO IC)

•Specific features of the MC68HC908GR8 in 28-pin DIP and 28-pin

SOIC are:

–Por t B is on ly 4 bits: PTB0–PTB3; 4-channel ADC module

–No Port C bits

1.3.2 Features of the CPU08

Features of the CPU08 include:

•Enhanced HC05 programming model

•Exte nsiv e loop control functions

•16 addressing modes (eig ht more than the HC05)

•16-bit index register and stack pointer

•Memory-to-memory data transfers

•Fast 8 × 8 multiply instruction

•Fast 16/8 divide instruction

•Binary-coded decimal (BCD) instructions

•Optimization for controller applications

•Efficient C language support

1.4 MCU Block Diagram

Figure 1-1 shows the s tructure of the MC68HC908 GR8.

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General Description

MCU Block Diagram

MC68HC908GR8 — Rev 4.0 Technical Data

MOTOROLA General Description 29

Figure 1-1. MCU Bloc k Diagram

SINGLE BRKPT BREAK

MODULE

CLOCK GENERATOR MODULE

24 INTR SYSTEM INTEGRATION

MODULE

PROGR. TIMEBASE

MODULE

MONITO R MO DULE

SERIAL PE RIP H ER AL

1-CHANNEL TIMER INTERFACE

MODULE 2

DUAL V. LOW-V OL TAG E INHIBIT

MODULE

4-BIT KEYBOARD

ARITHMETIC/LOGIC

UNIT (ALU)

CPU

REGISTERS

M68HC08 CPU

CONTROL AND STATUS REGISTERS — 64 BYTES

MC68HC908GR8 USER FLASH — 7680 BYTES

USER RAM — 384 BYTES

MONITOR ROM — 310 BYTES

USER FLASH VECTOR SPACE — 36 BYTES

SINGLE EXTERNAL IRQ

MODULE

PORTA

DDRA

DDRD

PORTD

DDRE

PORTE

INTERNAL BUS

OSC1

OSC2

CGMXFC

* RST

* IRQ

INTERFACE MODULE

INTERRUPT MODULE

COMPUTER OPERATING

PROPERLY MODULE

PTA3/KBD3–PTA0/KBD0 †

DDAD /

REFH

8-BIT ANALO G-TO-DIG ITA L

CONVERTER MODULE

PTD6/T2CH0 †

PTD5/T1CH1 †

PTD4/T1CH0 †

PTD3/SPSCK †

PTD2/MOSI †

PTD1/MISO †

PTD0/SS †

PTE1/RxD

PTE0/TxD

SSAD

/ V

REFL

2-CHANNEL TIMER INTERFACE

MODULE 1

32-kHz OSCILLATOR

PHASE-LOCKED LOOP

SERIAL COMMUNICATIONS

INTERFACE MODULE

DATA BUS SWITCH

MODULE

MEMORY MAP

MODULE

MASK OPTION REGISTER1

MODULE

SECURITY

MODULE

POWER

SSA

DDA

† Ports are software configurable with pullup device if input port .

‡ Higher current drive port pins

* Pin contains integrated pullup device

MONITOR MODE ENTRY

MODULE

PORTB

DDRB

PTB5/AD5–PTB0/AD0

PORTC

DDRC

PTC1–PTC0 † ‡

POWER-ON RESET

MODULE

FLASH PROGRAMMING (BURN-IN) ROM — 544 BYTES

MASK OPTION REGISTER2

MODULE

MC68H C908GR4 US ER FLA SH — 4096BYTES

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General Description

Technical Data MC68HC908GR8 — Rev 4.0

30 General Description MOTOROLA

1.5 Pi n Assignments

Figure 1-2. QFP Pin Assignments

NOTE: Ports PTB4, PTB5, PTC0, and PTC1 are avail abl e only with the QFP.

PTD3/SPSCK

PTA3/KBD3

PTD2/MOSI

PTD1/MISO

PTD0/SS

IRQ

PTE1/RxD

PTE0/TxD

RST PTA2/KBD2

PTA1/KBD1

PTA0/KBD0

VSSAD/VREFL

VDDAD/VREFH

PTB5/AD5

PTB4/AD4

PTB3/AD3

OSC1

OSC2

CGMXFC

SSA

DDA

PTC1

PTC0

PTB2/AD2

PTD4/T1CH0

PTD5/T1CH1

PTD6/T2CH0

PTB0/AD0

PTB1/AD1

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General Description

Pin Functions

MC68HC908GR8 — Rev 4.0 Technical Data

MOTOROLA General Description 31

Figure 1-3. DIP And SOIC Pin Assignments

1.6 Pin Functions

Descri pt io ns of t he pin func tions are provide d her e .

1.6.1 Power Supply Pins (VDD and VSS)

VDD and VSS are the po wer supply and ground pins. The MCU operates

from a single power supply.

Fast signal transitions on MCU pins place high, short-duration current

demands on the power supply. To prevent noise problems, take special

care to provide power supply bypassing at the MCU as Figure 1-4

shows. P lace the C 1 bypass capacitor as close to the MC U as possible.

Use a high-frequency-response ceramic capacitor for C1. C2 is an

optional bulk current bypass capacitor for use in applications that require

the port pins to source high current levels.

CGMXFC

OSC2

OSC1

RST

PTE0/TxD

PTE1/RxD

IRQ

PTD0/SS

PTD1/MISO

PTD2/MOSI

PTD3/SPSCK

VSS

VDD

PTD4/T1CH0

VSSA

VDDA

PTA3/KBD3

PTA2/KBD2

PTA1/KBD1

PTA0/KBD0

VSSAD/VREFL

VDDAD/VREFH

PTB3/AD3

PTB2/AD2

PTB1/AD1

PTB0/AD0

PTD6/T2CH0

PTD5/T1CH1

NOTE: Ports PTB4, PTB5, PTC0, and PTC1 are available only with the QFP.

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General Description

Technical Data MC68HC908GR8 — Rev 4.0

32 General Description MOTOROLA

Figure 1-4. Power Supply Bypassing

1.6.2 Oscillator Pins (OSC1 and OSC2)

The OSC1 and OSC2 pins are the connections fo r the on-chip oscillator

circuit. See Clock Generator Module (CGMC).

1.6.3 External Reset Pin (RST )

A logic 0 on the RST pin forces the MCU to a known startup state. RST

is bidirectional, allowing a reset of the entire system. It is driven low when

any internal reset source is asserted. This pin contains an internal pullup

resistor that is always activated, even when the reset pin is pulled low.

See Resets and Interrupts.

1.6.4 External Inte rrupt Pin (IRQ)

IRQ is an asynchronous external interrupt pin. This pin contains an

interna l pullup resistor that is always activa ted, even when the reset pin

is pulled low. See External Interrupt (IRQ).

1.6.5 CGM Power Supply Pins (VDDA and VSSA)

VDDA and VSSA are the power supply pins for the an alog portion o f the

clock generator module (CGM). Decoupling of these pins should be as

per the digital supply. See Clock Generator Modu le (CGMC).

MCU

VDD

0.1 µF

VSS

VDD

NOTE: Component values shown represent typical applications.

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General Description

Pin Functions

MC68HC908GR8 — Rev 4.0 Technical Data

MOTOROLA General Description 33

1.6.6 External Filter Capaci tor Pin (CGMX FC)

CGMXFC is an external filter capacitor connection for the CGM. See

Clock Generator Module (CGMC).

1.6.7 Analog Power Supply/Reference Pins (VDDAD/VREFH and VSSAD/VREFL)

VDDAD and VSSAD are the power supply pins for the analog-to-digital

converte r . D eco up ling of these pi ns sh ou ld be as per the digital supp l y .

NOTE: VREFH is the high reference supply for the ADC. The VREFH signal is

internally connected with VDDAD and have the sa me pote ntial a s VDDAD.

VDDAD should be tied to the same potential as VDD via separate traces.

VREFL is the low reference supply for the ADC. The VREFL pin is

inter na lly conn ecte d wi th VSSAD and has the same potential as VSSAD.

VSSAD should be tied to the same potential as VSS via separate traces.

See Analog-to-Digital Converter (ADC).

1.6.8 Port A Input/Output (I/O) Pins (PTA3/KBD3–PTA0/KBD0)

PTA3–PTA0 are special-function, bidirectional I/O port pins. Any or all of

the por t A pins can be pro grammed to serve as keybo ard inter rupt pins.

See Inp ut/ Outp ut Ports (I /O) and External Interrupt (IRQ).

These port pins also ha ve selectable pu llups when configured for input

mode. The pullups are disengaged when configured for output mode.

The pullu ps are selectable on an individual port bit basis.

When the port pins are configured for special-function mode (KBI),

pullups will be automatically engaged. As long as the port pins are in

special-func tion mode, the pullups will always be on.

1.6.9 Port B I/O Pins (PTB5/AD5–PTB0/AD0)

PTB5–PTB0 are special-function, bidirectional I/O port pins that can also

be use d for analog-t o-digital converter (ADC) inputs. See Input/Output

Ports (I/O) and Analog-to-Digital Converter (ADC).

There are no pullups a ssociated with this port.

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General Description
Technical Data MC68HC908GR8 — Rev 4.0
34 General Description MOTOROLA
1.6.10  Port C I/O Pins (PTC1–PTC0)
PTC1–PTC0 are general-purpose, bidirectional I/O port pins. See 
Input/Output Ports (I/O). PTC0 and PTC1 are on l y availa ble on 32-pin 
QFP package s. 
These port pins also ha ve selectable pu llups when configured for input 
mode. The pullups are disengaged when configured for output mode. 
The pullu ps are selectable on an individual  port bit basis.
1.6.11  Port D I/O Pins (PTD6/T2CH0–PTD0/SS)
PTD6–PTD0 are special-function, bidirectional I/O port pins. 
PTD3–PTD0 can b e pr ogra mme d to b e ser ial p eriph eral  in terfa ce (SP I) 
pins, while PTD6–PTD4 can be individually programmed to be timer 
interface module (TIM1 and TIM2) pins. See Timer Interface Modu le 
(TIM), Serial Peripheral Interface (SPI),  and Input/Output Ports (I/O).
These port pins also ha ve selectable pu llups when configured for input 
mode. The pullups are disengaged when configured for output mode. 
The pullu ps are selectable on an individual  port bit basis.
When the port pins are configured for special-function mode (SPI, TIM1, 
TIM2), pullups can be selectable on an individual port pin basis.
1.6.12  Port E I/O Pins (PTE1/Rx D –PTE0/TxD)
PTE1–PTE0 are spe cial-functi on, bidirectio nal I/O port pi ns. These pins 
can also be programme d to be serial comm unications int erface  (SCI) 
pins. See Serial Communications Interface (SCI) and Input/Output Ports 
(I/O).
NOTE: Any unused i nputs and I/O ports should be tied to an appropriate logic 
level (either VDD or VSS). Although the I/O ports of the MC68HC908GR8 
do not require termination, termination is recommended to reduce the 
possibility of electro-static discharge damag e.
    
  
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MC68HC908GR8 — Rev 4.0 Technical Data
MOTOROLA Memory Map 35
 
Technical Data — MC68HC908GR8
Section 2. Memory Map
2.1  Contents
2.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
2.3 Unimplemented Memory Locations  . . . . . . . . . . . . . . . . . . . . . .35
2.4 Reserved Memory Locations . . . . . . . . . . . . . . . . . . . . . . . . . .36
2.5 Input/Output (I/O) Section. . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
2.2  Introduction
The CPU08 can address 64K bytes of memory space. The memory 
map, shown in Figure 2-1, includes:
•8K bytes of FLASH  memor y, 7680 byte s of u ser space on  the 
MC68HC 908GR8 or
4K bytes of FLASH  memor y, 4096 byte s of u ser space on  the 
MC68HC908GR4
•384 bytes of rando m-access memory (RAM)
•36 bytes of us er-defined vec tors
•310 bytes of monitor routines in read-only memory (ROM)
•544 bytes of  integr ated FLASH burn-i n  rout ines in ROM
2.3  Unimplemented Memory Locations
Accessing an unimplemented location can cause an illegal address 
reset if illegal address resets are enabled. In the memory map (Figure 2-
1) and in register figures in this document, unimplemented locations are 
shaded.
    
  
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Memory Map

Technical Data MC68HC908GR8 — Rev 4.0

36 Memory Map MOTOROLA

2.4 Reserved Memory Locations

Accessing a r eserved location can have unpredictable effects on MCU

operation. In the Figure 2-1 and in register figures in this document,

reser ved location s are marke d with t he word R eserved or w ith the l etter

2.5 Inp ut/Output (I/O) Section

Most of the control, status, and data registers are in the zero page area

of $0000–$003F. Additional I/O registers have these addresses:

•$FE00; SIM break status register, SBSR

•$FE01; SIM rese t status register, SRSR

•$FE03; SIM break flag control register, SBFCR

•$FE09; interrupt st atus register 1, INT1

•$FE0A; interrupt status register 2, INT2

•$FE0B; interrupt status register 3, INT3

•$FE07; reserved FLASH test co ntrol register, FLTCR

•$FE08; FLASH control regist er, FLCR

•$FE09; break address register high, BRKH

•$FE0A; break address register low, BRKL

•$FE0B; break status and control register, BRKSCR

•$FE0C; LVI status register, LVISR

•$FF7 E; FLAS H block prote ct reg i ster , FL BP R

Data registers are shown in Figure 2-2, and Table 2-1 is a list of vector

locations.

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Memory Map

Input/Output (I/O) Section

MC68HC908GR8 — Rev 4.0 Technical Data

MOTOROLA Memory Map 37

$0000 I/O Registers

64 Bytes

↓

$003F

$0040 RAM

384 Bytes

↓

$01BF

$01C0 Unimplemented

6720 Bytes

↓

$1BFF

$1C00 Reserved for Integrated FLASH Burn-in Routines

544 Bytes

↓

$1E1F

$1E20 Unimplemented

49,632 Bytes

↓

$DFFF

$E000

MC68HC908GR8

FLASH Memory

7680 Bytes

MC68HC908GR4

Unimplemented

3584 Bytes

↓

$EDFF

$EE00 MC68HC908GR4

FLASH Memory

4096 Bytes

↓

$FDFF

$FE00 SIM Break Status Register (SBSR)

$FE01 SIM Reset Status Register (SRSR)

$FE02 Reserved

$FE03 SIM Break Flag Control Register (SBFCR)

$FE09 Interrupt Status Register 1 (INT1)

$FE0A Interrupt Status Register 2 (INT2)

$FE0B Interrupt Status Register 3 (INT3)

$FE07 Reserved for FLASH Test Control Register (FLTCR)

Figure 2-1. Memory Map

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Memory Map

Technical Data MC68HC908GR8 — Rev 4.0

38 Memory Map MOTOROLA

$FE08 FLASH Control Register (FLCR)

$FE09 Break Address Register High (BRKH)

$FE0A Break Address Register Low (BRKL)

$FE0B Break Status and Control Register (BRKSCR)

$FE0C LVI Status Register (LVISR)

$FE0D Reserved

3 Bytes

↓

$FE0F

$FE10 Unimplemented

16 Bytes

Reserved for Compatibility wi th Monitor Code

for A-Family Parts

↓

$FE1F

$FE20 Monitor ROM

310 Bytes

↓

$FF55

$FF56 Unimplemented

40 Bytes

↓

$FF7D

$FF7E FLASH Block Protect Register (FLBPR)

$FF7F Unimplemented

93 Bytes

↓

$FFDB

Note: $FFF6–$FFFD

contains

8 security bytes

$FFDC FLASH Vectors

(36 Bytes inluding $FFFF)

↓

$FFFE

$FFFF Low byte of reset vector when read

COP Control Register (COPCTL)

Figure 2-1. Memory Map (Continued)

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Memory Map

Input/Output (I/O) Section

MC68HC908GR8 — Rev 4.0 Technical Data

MOTOROLA Memory Map 39

Addr.Register Name Bit 7654321Bit 0

$0000 Port A Data Register

(PTA)

PTA3 PTA2 PTA1 PTA0

Write:

Reset: Unaffected by reset

$0001 Port B Data Register

(PTB)

Read: 0 0 PTB5 PTB4 PTB3 PTB2 PTB1 PTB0

Write:

Reset: Unaffected by reset

$0002 Port C Data Register

(PTC)

PTC1 PTC0

Write:

Reset: Unaffected by reset

$0003 Port D Data Register

(PTD)

Read: 0 PTD6 PTD5 PTD4 PTD3 PTD2 PTD1 PTD0

Write:

Reset: Unaffected by reset

$0004 Data Direction Register A

(DDRA)

DDRA3 DDRA2 DDRA1 DDRA0

Write:

Reset:00000000

$0005 Data Direction Register B

(DDRB)

Read: 0 0 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0

Write:

Reset:00000000

$0006 Data Direction Register C

(DDRC)

DDRC1 DDRC0

Write:

Reset:00000000

$0007 Data Direction Register D

(DDRD)

Read: 0 DDRD6 DDRD5 DDRD4 DDRD3 DDRD2 DDRD1 DDRD0

Write:

Reset:00000000

$0008 Port E Data Register

(PTE)

PTE1 PTE0

Write:

Reset: Unaffected by reset

$0009 Unimplemented

Read:

Write:

Reset:00000000

= Unimplemented R = Reserved U = Unaffected

Figure 2-2. Control, Status, and Data Registers (Sheet 1 of 8)

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Memory Map

Technical Data MC68HC908GR8 — Rev 4.0

40 Memory Map MOTOROLA

$000A Unimplemented

Read:

Write:

Reset:00000000

$000B Unimplemented

Read:

Write:

Reset:00000000

$000C Data Direction Register E

(DDRE)

DDRE1 DDRE0

Write:

Reset:00000000

$000D Port A Input Pullup Enable

PTAPUE3 PTAPUE2 PTAPUE1 PTAPUE0

Write:

Reset:00000000

$000E Port C Input Pullup Enable

PTCPUE1 PTCPUE0

Write:

Reset:00000000

$000F Port D Input Pullup Enable

Read: 0 PTDPUE6 PTDPUE5 PTDPUE4 PTDPUE3 PTDPUE2 PTDPUE1 PTDPUE0

Write:

Reset:00000000

$0010 SPI Control Register

(SPCR)

Read: SPRIE DMAS SPMSTR CPOL CPHA SPWOM SPE SPTIE

Write:

Reset:00101000

$0011 SPI Status and Control

Read: SPRF ERRIE OVRF MODF SPTE MODFEN SPR1 SPR0

Write:

Reset:00001000

$0012 SPI Data Register

(SPDR)

Read: R7 R6 R5 R4 R3 R2 R1 R0

Write: T7 T6 T5 T4 T3 T2 T1 T0

Reset: Unaffected by reset

$0013 SCI Control Register 1

(SCC1)

Read: LOOPS ENSCI TXINV M WAKE ILTY PEN PTY

Write:

Reset:00000000

Addr.Register Name Bit 7654321Bit 0

= Unimplemented R = Reserved U = Unaffected

Figure 2-2. Control, Status, and Data Registers (Sheet 2 of 8)

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Memory Map

Input/Output (I/O) Section

MC68HC908GR8 — Rev 4.0 Technical Data

MOTOROLA Memory Map 41

$0014 SCI Control Register 2

(SCC2)

Read: SCTIE TCIE SCRIE ILIE TE RE RWU SBK

Write:

Reset:00000000

$0015 SCI Control Register 3

(SCC3)

Read: R8 T8 DMARE DMATE ORIE NEIE FEIE PEIE

Write:

Reset:UU000000

$0016 SCI Status Register 1

(SCS1)

Read: SCTE TC SCRF IDLE OR NF FE PE

Write:

Reset:11000000

$0017 SCI Status Register 2

(SCS2)

Read: BKF RPF

Write:

Reset:00000000

$0018 SCI Data Register

(SCDR)

Read: R7 R6 R5 R4 R3 R2 R1 R0

Write: T7 T6 T5 T4 T3 T2 T1 T0

Reset: Unaffected by reset

$0019 SCI Baud Rate Register

(SCBR)

Read: SCP1 SCP0 R SCR2 SCR1 SCR0

Write:

Reset:00000000

$001A Keyboard Status

and Control Register

(INTKBSCR)

Read: 0000KEYF0

IMASKK MODEK

Write: ACKK

Reset:00000000

$001B Keyboard Interrupt Enable

Read: KBIE3 KBIE2 KBIE1 KBIE0

Write:

Reset: 0000

$001C Time Base Module Control

Read: TBIF TBR2 TBR1 TBR0 0TBIE TBON R

Write: TACK

Reset:00000000

$001D IRQ Status and Control

Read: 0000IRQF10

IMASK1 MODE1

Write: ACK1

Reset:00000000

Addr.Register Name Bit 7654321Bit 0

= Unimplemented R = Reserved U = Unaffected

Figure 2-2. Control, Status, and Data Registers (Sheet 3 of 8)

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Memory Map

Technical Data MC68HC908GR8 — Rev 4.0

42 Memory Map MOTOROLA

$001E Configuration Register 2

(CONFIG2)†

OSC-

STOPENB SCIBD-

SRC

Write:

Reset:00000000

$001F Configuration Register 1

(CONFIG1)†

Read: COPRS LVISTOP LVIRSTD LVIPWRD LVI5OR3†SSREC STOP COPD

Write:

Reset:00000000

$0020 Timer 1 Status and Control

Read: TOF TOIE TSTOP 00

PS2 PS1 PS0

Write: 0 TRST

Reset:00100000

$0021 Timer 1 Counter Register

High (T1CNTH)

Read: Bit 15 14 13 12 11 10 9 Bit 8

Write:

Reset:00000000

$0022 Timer 1 Counter Register

Low (T1CNTL)

Read: Bit 7 654321Bit 0

Write:

Reset:00000000

$0023 Timer 1 Counter Modulo

Read: Bit 15 14 13 12 11 10 9 Bit 8

Write:

Reset:11111111

$0024 Timer 1 Counter Modulo

Read: Bit 7654321Bit 0

Write:

Reset:11111111

$0025 Timer 1 Channel 0 Status

and Control Register

(T1SC0)

Read: CH0F CH0IE MS0B MS0A ELS0B ELS0A TOV0 CH0MAX

Write: 0

Reset:00000000

$0026 Timer 1 Channel 0

Read: Bit 15 14 13 12 11 10 9 Bit 8

Write:

Reset: Indeterminate after reset

$0027 Timer 1 Channel 0

Read: Bit 7654321Bit 0

Write:

Reset: Indeterminate after reset

† One-time writeable register after each reset, except LVI5OR3 bit. LVI5OR3 bit is only reset via POR (power-on reset).

Addr.Register Name Bit 7654321Bit 0

= Unimplemented R = Reserved U = Unaffected

Figure 2-2. Control, Status, and Data Registers (Sheet 4 of 8)

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Memory Map

Input/Output (I/O) Section

MC68HC908GR8 — Rev 4.0 Technical Data

MOTOROLA Memory Map 43

$0028 Timer 1 Channel 1 Status

and Control Register

(T1SC1)

Read: CH1F CH1IE 0MS1A ELS1B ELS1A TOV1 CH1MAX

Write: 0

Reset:00000000

$0029 Timer 1 Channel 1

Read: Bit 15 14 13 12 11 10 9 Bit 8

Write:

Reset: Indeterminate after reset

$002A Timer 1 Channel 1

Read: Bit 7654321Bit 0

Write:

Reset: Indeterminate after reset

$002B Timer 2 Status and Control

Read: TOF TOIE TSTOP 00

PS2 PS1 PS0

Write: 0 TRST

Reset:00100000

$002C Timer 2 Counter Register

High (T2CNTH)

Read: Bit 15 14 13 12 11 10 9 Bit 8

Write:

Reset:00000000

$002D Timer 2 Counter Register

Low (T2CNTL)

Read: Bit 7 654321Bit 0

Write:

Reset:00000000

$002E Timer 2 Counter Modulo

Read: Bit 15 14 13 12 11 10 9 Bit 8

Write:

Reset:11111111

$002F Timer 2 Counter Modulo

Read: Bit 7654321Bit 0

Write:

Reset:11111111

$0030 Timer 2 Channel 0 Status

and Control Register

(T2SC0)

Read: CH0F CH0IE MS0B MS0A ELS0B ELS0A TOV0 CH0MAX

Write: 0

Reset:00000000

$0031 Timer 2 Channel 0

Read: Bit 15 14 13 12 11 10 9 Bit 8

Write:

Reset: Indeterminate after reset

Addr.Register Name Bit 7654321Bit 0

= Unimplemented R = Reserved U = Unaffected

Figure 2-2. Control, Status, and Data Registers (Sheet 5 of 8)

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Memory Map

Technical Data MC68HC908GR8 — Rev 4.0

44 Memory Map MOTOROLA

$0032 Timer 2 Channel 0

Read: Bit 7654321Bit 0

Write:

Reset: Indeterminate after reset

$0033 Unimplemented Read:

Write:

Reset:00000000

$0034 Unimplemented

Read:

Write:

Reset: Indeterminate after reset

$0035 Unimplemented

Read:

Write:

Reset: Indeterminate after reset

$0036 PLL Control Register

(PCTL)

Read: PLLIE PLLF PLLON BCS PRE1 PRE0 VPR1 VPR0

Write:

Reset:00100000

$0037 PLL Bandwidth Control

Read: AUTO LOCK ACQ 0000R

Write:

Reset:00000000

$0038 PLL Multiplier Select High

MUL11 MUL10 MUL9 MUL8

Write:

Reset:00000000

$0039 PLL Multiplier Select Low

Read: MUL7 MUL6 MUL5 MUL4 MUL3 MUL2 MUL1 MUL0

Write:

Reset:01000000

$003A PLL VCO Select Range

Read: VRS7 VRS6 VRS5 VRS4 VRS3 VRS2 VRS1 VRS0

Write:

Reset:01000000

$003B PLL Reference Divider

Select Register (PMDS)

RDS3 RDS2 RDS1 RDS0

Write:

Reset:00000001

Addr.Register Name Bit 7654321Bit 0

= Unimplemented R = Reserved U = Unaffected

Figure 2-2. Control, Status, and Data Registers (Sheet 6 of 8)

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Memory Map

Input/Output (I/O) Section

MC68HC908GR8 — Rev 4.0 Technical Data

MOTOROLA Memory Map 45

$003C Analog-to-Digital Status

and Control Register

(ADSCR)

Read: COCO AIEN ADCO ADCH4 ADCH3 ADCH2 ADCH1 ADCH0

Write: R

Reset:00011111

$003D Analog-to-Digital Data

Read: AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0

Write:RRRRRRRR

Reset: Indeterminate after reset

$003E Analog-to-Digital Input

Clock Register (ADCLK)

Read: ADIV2 ADIV1 ADIV0 ADICLK 0000

Write: RRRR

Reset:00000000

$003F Unimplemented

Read:

Write:

Reset:

$FE00 SIM Break Status Register

(SBSR)

Read: RRRRRR

SBSW R

Write: NOTE

Reset:00000000

Note: Writing a logic 0 clears SBSW.

$FE01 SIM Reset Status Register

(SRSR)

Read: POR PIN COP ILOP ILAD MODRST LVI 0

Write:

POR:10000000

$FE02 Unimplemented

Read:

Write:

Reset:

$FE03 SIM Break Flag Control

Read: BCFERRRRRRR

Write:

Reset: 0

$FE09 Interrupt Status Register 1

(INT1)

Read: IF6 IF5 IF4 IF3 IF2 IF1 0 0

Write:RRRRRRRR

Reset:00000000

$FE0A Interrupt Status Register 2

(INT2)

Read: IF14 IF13 IF12 IF11 IF10 IF9 IF8 IF7

Write:RRRRRRRR

Reset:00000000

Addr.Register Name Bit 7654321Bit 0

= Unimplemented R = Reserved U = Unaffected

Figure 2-2. Control, Status, and Data Registers (Sheet 7 of 8)

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Memory Map

Technical Data MC68HC908GR8 — Rev 4.0

46 Memory Map MOTOROLA

$FE0B Interrupt Status Register 3

(INT3)

Read: 000000IF16IF15

Write:RRRRRRRR

Reset:00000000

$FE07 FLASH Test Control

Read: RRRRRRRR

Write:

Reset:00000000

$FE08 FLASH Control Register

(FLCR)

HVEN MASS ERASE PGM

Write:

Reset:00000000

$FE09 Break Address Register

High (BRKH)

Read: Bit 15 14 13 12 11 10 9 Bit 8

Write:

Reset:00000000

$FE0A Break Address Register

Low (BRKL)

Read: Bit 7654321Bit 0

Write:

Reset:00000000

$FE0B Break Status and Control

Read: BRKE BRKA 000000

Write:

Reset:00000000

$FE0C LVI Status Register

(LVISR)

Read: LVIOUT 0000000

Write:

Reset:00000000

$FF7E FLASH Block Protect

Read: BPR7 BPR6 BPR5 BPR4 BPR3 BPR2 BPR1 BPR0

Write:

Reset:UUUUUUUU

$FFFF COP Control Register

(COPCTL)

Read: Low byte of reset vector

Write: Writing clears COP counter (any value)

Reset: Unaffected by reset

† Non-volatile FLASH register

Addr.Register Name Bit 7654321Bit 0

= Unimplemented R = Reserved U = Unaffected

Figure 2-2. Control, Status, and Data Registers (Sheet 8 of 8)

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Memory Map

Input/Output (I/O) Section

MC68HC908GR8 — Rev 4.0 Technical Data

MOTOROLA Memory Map 47

Table 2-1. Vector Addresses

Vector Priority Vector Address Vector

Lowest IF16 $FFDC Timebase V ector (High)

$FFDD Timebase Vector (Low)

IF15 $FFDE ADC Conversion Complete Vector (High)

$FFDF ADC Conversion Complete Vector (Low)

IF14 $FFE0 Keyboard Vector (High)

$FFE1 Keyboard Vector (Low)

IF13 $FFE2 SCI Tran smit Vect or (High )

$FFE3 SCI Transm it Vector (Low)

IF12 $FFE4 SCI Receive Vector (Hig h)

$FFE5 SCI Receive Vector (Low)

IF11 $FFE6 SCI Error Vector (High)

$FFE7 SCI Error Vector (Low)

IF10 $FFE8 SPI Transmit Vector (High)

$FFE9 SPI Transmit Vector (Low)

IF9 $FFEA SPI Receive Vector (High)

$FFEB SPI Receive Vector (Low)

IF8 $FFEC TIM2 Overflow Vector (High)

$FFED TIM2 Overflow Vector (Low)

IF7 $FFEE Reserved

$FFEF Reserved

IF6 $FFF0 TIM2 Channel 0 Vector (High)

$FFF1 TIM2 Channel 0 Vector (Low)

IF5 $FFF2 TIM1 Overflow Vector (High)

$FFF3 TIM1 Overflow Vector (Low)

IF4 $FFF4 TIM1 Channel 1 Vector (High)

$FFF5 TIM1 Channel 1 Vector (Low)

IF3 $FFF6 TIM1 Channel 0 Vector (High)

$FFF7 TIM1 Channel 0 Vector (Low)

IF2 $FFF8 PLL Vector (High)

$FFF9 PLL Vector (Low)

IF1 $FFFA IRQ Vector (High)

$FFFB IRQ Vector (Low)

—$FFFC SWI Vector (High)

$FFFD SWI Vector (Low)

—$FFFE Reset Vector (High)

Highest $FFFF Reset Vector (Low)

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Memory Map

Technical Data MC68HC908GR8 — Rev 4.0

48 Memory Map MOTOROLA

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MC68HC908GR8 — Rev 4.0 Technical Data
MOTOROLA Low Power Modes 49
 
Technical Data — MC68HC908GR8
Section 3. Low Power Modes
3.1  Contents
3.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
3.3 Analog-to-Digital Converter (ADC) . . . . . . . . . . . . . . . . . . . . . .50
3.4 Break Modu le (BRK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
3.5 Central Processor Unit (CPU). . . . . . . . . . . . . . . . . . . . . . . . . .51
3.6 Clock Generator Module (CGM). . . . . . . . . . . . . . . . . . . . . . . .52
3.7 Computer Operating Properly Module (COP). . . . . . . . . . . . . .52
3.8 External Interrupt Module (IRQ) . . . . . . . . . . . . . . . . . . . . . . . .53
3.9 Keyboard Interrupt Modul e (KBI) . . . . . . . . . . . . . . . . . . . . . . .53
3.10 Low-Voltage Inhibit Module (LVI) . . . . . . . . . . . . . . . . . . . . . . .54
3.11 Serial Communications Interface Module (SCI) . . . . . . . . . . . .54
3.12 Serial Peripheral Interface Module (SPI) . . . . . . . . . . . . . . . . .55
3.13 Timer Interface Module (TIM1 and TIM2). . . . . . . . . . . . . . . . .55
3.14 Timebase Module (TBM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
3.15 Exiting Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
3.16 Exiting Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
3.2  Introduction
The MCU may enter two low-power modes: wait mode and stop mode. 
They are common to all HC08 MCUs and are entered through instruction 
execution. This section describes how each module acts in the low-
power mo des.
    
  
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Low Power Modes

Technical Data MC68HC908GR8 — Rev 4.0

50 Low Power Modes MOTOROLA

3.2.1 Wait Mode

The WAIT instruction puts the MCU in a low-power standby mode in

which the CPU clock is disabled but the bus clock continues to run.

Power co nsumption can be furt her reduced by disabling th e LVI mo dule

and/or the timebase module through bits in the CONFIG register. (See

Config uration Register (CONFIG).)

3.2.2 Stop Mode

Stop mode is entered when a STOP instruction is executed. The CPU

clock is disabled and the bus clock is disabled if the OSCSTOPENB bit

in the CONFIG register is at a logic 0. (See Configuration Register

(CONFIG).)

3.3 Analog-to-Digital Converter (ADC)

3.3.1 Wait Mode

The ADC continues normal operation during wait mode. Any enabled

CPU interrupt request from the ADC can bring the MCU out of wait

mode. If the ADC is not required to bring the MCU out of wait mode,

power down the ADC by setting ADCH4–ADCH0 bits in the ADC status

and control register before executing the WAIT instruction.

3.3.2 Stop Mode

The AD C module is inactiv e after the ex ecution of a STOP instruction.

Any pending conversion is aborted. ADC conversions resume when the

MCU exits stop mode after an external interrupt. A llow one conversi on

cycle to stabilize the analog circuitry.

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Low Power Modes

Break Module (BRK)

MC68HC908GR8 — Rev 4.0 Technical Data

MOTOROLA Low Power Modes 51

3.4 Break Module (BRK)

3.4.1 Wait Mode

If enabled, the break module is active in wait mode. In the break routine,

the user can subtract one from the return address on the stack if the BW

bit in the break status register is set.

3.4.2 Stop Mode

The break module is inactive in stop mode. A break interrupt causes exit

from stop mode and sets the BW bit in the break status register. The

STOP instruction does not affect break module register states.

3.5 Centra l Processor Unit (C PU)

3.5.1 Wait Mode

The WAIT instruction:

•Clears the interrupt mask (I bit) in the condition code regi ster,

enabling int errupts. After exit from wait mode by inte rrupt, the I bit

remains clear. After exit by reset, the I bit is set.

•Disables the CPU clock

3.5.2 Stop Mode

The STOP instruction:

•Clears the interrupt mask (I bit) in the condition code regi ster,

enabling external interrupts. After exit from stop mode by external

interrupt, the I bit remains clear. After exit by reset, the I bit is set.

•Disables the CPU clock

After exiting stop mode, the CPU clock begins running after the oscillator

stabilization delay.

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Low Power Modes

Technical Data MC68HC908GR8 — Rev 4.0

52 Low Power Modes MOTOROLA

3.6 Clo ck Generator Module (CGM)

3.6.1 Wait Mode

The CGM remains active in wait mode. Before entering wait mode,

software can disengage and turn off the PLL by clearing the BCS and

PLLON bits in the PLL control register (PCTL). Less power-sensitive

applications can disengage the PLL without turning it off. Applications

that require the PLL to wake the MCU from wait mode also can deselect

the PLL output without turni ng off the PLL.

3.6.2 Stop Mode

If the OSCSTOPEN bit in the CONFIG register is cleared (default), then

the STOP instruction disables the CGM (oscillator and phase-lo cked

loop) and holds low all CGM outputs (CGMXCLK, CGMOUT, and

CGMINT).

If the STOP instruction is executed with the VCO clock, CGMVCLK,

divided by two driving C GM OU T, th e P LL automatica lly clears the B CS

bit in the PLL control register (PCTL), thereby selecting the crystal clock,

CGMXCL K, d ivid ed by two as the source of CGM OUT . W he n t he MC U

recovers from STOP, the crystal clock divided by two drives CGMOUT

and BCS remains clear.

If the OSCSTOPEN bit in the CONFIG register is set, then the phase

locked loop is shut off, but the oscillator will continue to operate in stop

mode.

3.7 Computer Operating Properly Modul e (COP)

3.7.1 Wait Mode

The COP remains active in wait mode. To prevent a COP reset during

wait mode, periodically clear the COP counter in a CPU interrupt routine

or a DMA servic e routin e.

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Low Power Modes

External Interrupt Module (IRQ)

MC68HC908GR8 — Rev 4.0 Technical Data

MOTOROLA Low Power Modes 53

3.7.2 Stop Mode

Stop mode turns off the CGMXCLK input to the COP and clears the COP

prescaler . Ser v ic e the C OP i mmed i ate ly be for e en ter i ng or a fte r exi ti ng

stop m ode to ensure a full CO P timeout period afte r entering or exiting

stop mode.

The STO P bit in the configura tion registe r (CONFIG) enables the STO P

instruction. To prevent inadvertently turning off the COP with a STOP

instructio n, disable the STOP instruction by clearing the STOP bit.

3.8 External Interrupt Module (IRQ)

3.8.1 Wait Mode

The IRQ module remains active in wait mode. Clearing the IMASK1 bit

in the IRQ status and control register enables IRQ CPU interrupt

requests to bring the MCU out of wait mode.

3.8.2 Stop Mode

The IRQ modu le rema ins active in stop mode. Clearing the IMAS K1 bit

in the IRQ status and control register enables IRQ CPU interrupt

requests to bring the MCU out of stop mode.

3.9 Keyboard Interrupt Module (KBI)

3.9.1 Wait Mode

The keyboard module remains active in wait mode. Cle aring the

IMASKK bit in the keyboard status and control register enables keyboard

inter r upt requ ests to br ing the MCU out of wait mod e.

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Low Power Modes

Technical Data MC68HC908GR8 — Rev 4.0

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3.9.2 Stop Mode

The keyboard module remains active in stop mode. Clearing the

IMASKK bit in the keyboard status and control register enables keyboard

interrupt requests to bring the MCU out of stop mode.

3.10 Low-Voltage Inhibit Module (LVI)

3.10.1 Wait Mode

If enabl ed, the LVI modu le remains active i n wait mode. If enabled to

generate resets, the LVI module can generate a reset and bring the MCU

out of wait mode.

3.10.2 Stop Mode

If ena bled, the LVI module remain s activ e in stop mode. If enabled to

generate resets, the LVI module can generate a reset and bring the MCU

out of stop mode.

3.11 Serial Communications Interface Module (SC I)

3.11.1 Wait Mode

The SCI module remains active in wait mode. Any enabled CPU

interrupt request from the SCI module can bring the MCU out of wait

mode.

If SCI module functions are not required during wait mode, reduce power

consumption by disabling the module before executing the WAIT

instruction.

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Low Power Modes

Serial Peripheral Interface Module (SPI)

MC68HC908GR8 — Rev 4.0 Technical Data

MOTOROLA Low Power Modes 55

3.11.2 Stop Mode

The SCI module is inactive in stop mode. The STOP instruction does not

affect SCI register states. SCI module operation resumes after the MCU

exits stop mode.

Beca use the internal clock is inactive during st op mode , ente ring stop

mode during an SCI transmission or reception results in invalid data.

3.12 Serial Peripheral Interface Module (SPI)

3.12.1 Wait Mode

The SPI module remains active in wait mode. Any enabled CPU interrupt

request from the SPI module can bring the MCU out of wait mode.

If SPI module functions are not required during wait mode, reduce power

consumption by disabling the SPI module before executing the WAIT

instruction.

3.12.2 Stop Mode

The SPI module is inactive in stop mode. The STOP instruction does not

affect SPI register states. SPI operation resumes after an external

interrupt. If stop mode is exited by reset, any transfer in progress is

aborte d, an d the SPI is re set.

3.13 Timer Interface Module (TIM1 and TIM2)

3.13.1 Wait Mode

The TIM remains active in wait mode. Any enabled CPU interrupt

request from the TIM can bring the MCU out of wait mode.

If TIM functions are not required during wait mode, reduce power

consumption by stopping the TIM before executing the WAIT instruction.

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Low Power Modes

Technical Data MC68HC908GR8 — Rev 4.0

56 Low Power Modes MOTOROLA

3.13.2 Stop Mode

The TIM is i nac ti ve in stop mode. The STOP i n structi o n do es n ot a ffe ct

when the MCU exits stop mode after an external interrupt.

3.14 Timebase Module (TBM)

3.14.1 Wait Mode

The timebase module remains active after execution of the WAIT

instruction. In wait mode, the timebase register is not accessible by the

CPU.

If the timebase functions are not required during wait mode, reduce the

power consumption by stopping the time base before enabling the WAIT

instruction.

3.14.2 Stop Mode

The timeba se module may remain active after execution of the STOP

instruction if the oscillator has been enabled to operate during stop mode

through the OSCSTOPEN bit in the CONFIG register. T he timebase

module can be used in this mode to generate a periodic wakeup from

stop mode.

If the oscillator has not been enabled to operate in st op mode, the

timebase module will not be active during stop mode. In stop mode, the

timebase register is not accessible by the CPU.

If the ti meba se funct ions ar e not req uired duri ng sto p mode, r educe the

power consumption by stopping the timebase before enabling the STOP

instruction.

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Low Power Modes

Exiting Wait Mode

MC68HC908GR8 — Rev 4.0 Technical Data

MOTOROLA Low Power Modes 57

3.15 Exiting Wait Mode

These events restart the CPU clock and load the program counter with

the reset vector or with an interrupt vector:

•External reset — A logic 0 on the RST pin resets the MCU and

loads the program counter with the contents of locations $FFFE

and $FFFF.

•External interrupt — A high-to- low transition on an external

interrupt pin (IRQ pin) loads the program counter with the contents

of locations: $FFFA and $FFFB; IRQ pin.

•Break interrupt — A break interrupt loads the program counter

with the contents of $FFFC and $FFFD.

•Computer operating properly module (COP) reset — A timeout of

the COP cou nte r r eset s the MC U and lo ads th e pr og ra m counter

with the contents of $FFFE and $FFFF.

•Low-voltage inhibit module (LVI) reset — A power supply voltage

below the Vtripf voltage resets the MCU and loads the program

counter with the contents of locations $FFFE and $FFFF.

•Clock generator modu le (CGM) interrupt — A CPU interrupt

request from the phase-locked loop (PLL) loads the program

counter with the contents of $FFF8 and $FFF9.

•Keyboard module (KBI) interrupt — A CPU interrupt request from

the KBI module loads the program counter with the contents of

$FFDE and $FFDF.

•Timer 1 interface module (TIM1) interrupt — A CPU interrupt

request from the TIM1 loads the program counter with the

contents of:

–$FFF2 and $FFF3; TIM1 overflow

–$FFF4 and $FFF5; TIM1 channel 1

–$FFF6 and $FFF7; TIM1 channel 0

•Timer 2 interface module (TIM2) interrupt — A CPU interrupt

request from the TIM2 loads the program counter with the

contents of:

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–$FFEC and $FFED; TIM2 overflow

–$FFF0 and $FFF1; TIM2 channel 0

•Serial peripheral interface module (SPI) interrupt — A CPU

interrupt request from the SPI loads the program counter with the

contents of:

–$FFE8 and $FFE9; SPI transmitter

–$FFEA and $FFEB; SPI re ceiver

•Serial communications interface module (SCI) interrupt — A CPU

interrupt request from the SCI loads the program counter with the

contents of:

–$FFE2 and $FFE3; SCI transmitter

–$FFE4 and $FFE5 ; SCI rec eiver

–$FFE6 and $FFE7; SCI receiver error

•Analog -to-digital converter module (ADC) interrupt — A CPU

interrupt request from the ADC loads the program counter with the

contents of: $FFDE and $FFDF; ADC conversion co mplete .

•Timebase module (TBM) interrupt — A CPU interrupt request from

the TBM loads the program counter with the contents of: $FFDC

and $FFDD; TBM interrupt.

3.16 Exiting Stop Mode

These even ts restart the system clocks and load the program counter

with the reset vector or with an interrupt vector:

•External reset — A logic 0 on the RST pin resets the MCU and

loads the program counter with the contents of locations $FFFE

and $FFFF.

•External interrupt — A high-to- low transition on an external

interrupt pin loa ds the program counter with th e contents of

locations:

–$FFFA and $FFFB; IRQ pin

–$FFDE and $FFDF; keyboard interrupt pins

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Low Power Modes

Technical Data MC68HC908GR8 — Rev 4.0

59 Low Power Modes MOTOROLA

•Low- vol tag e in hi bi t (L VI) res et — A power supp ly voltage below

the LVItripf voltage resets the MCU and loads the program counter

with the contents of locations $FFFE and $FFFF.

•Break interrupt — A break interrupt loads the program counter

with the contents of locations $FFFC and $FFFD.

•Timebase module (TBM) interrupt — A TBM interrupt loads the

program counter with the contents of locations $FFDC and $FFDD

when the timebase counter has rolled over. This allows the TBM

to generate a periodic wakeup from stop mode.

Upon exit from stop mode, the system clocks begin running after an

oscillator stab ilization delay. A 12-bit stop recovery coun ter inhibits the

system clocks for 4096 CGMXCLK cycles after the reset or external

interrupt.

The short stop recovery bit, SSREC, in the configuration register

controls the o scillator stabilization delay during stop recovery. Setting

SSREC reduces stop recovery time from 4096 CGMXCLK cycles to 32

CGMXCLK cycles.

NOTE: Use the full stop re cove ry ti me ( SSR E C = 0 ) in applicatio ns that use an

external crystal.

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MC68HC908GR8 — Rev 4.0 Technical Data

MOTOROLA Resets and Interrupts 61

Technical Data — MC68HC908GR8

Section 4. Resets and Interrupts

4.1 Contents

4.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61

4.3 Resets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61

4.4 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66

4.2 Introduction

Resets and interrup ts are responses to exceptional ev ents during

program execution. A reset re-initializes the MCU to its startup condition.

An interrup t vect ors the program counte r to a service routine.

4.3 Resets

A reset immediately returns the MCU to a known startup condition and

begins program execution from a user-defined memory location.

4.3.1 Effects

A reset:

•Immediately stops the operation of the instruction being executed

•Initializes certain control and status bits

•Loads the program counter with a user-defined reset vector

address from locations $FFFE and $FFFF

•Selects CGMXCLK divided by four as the bus clock

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Resets and Interrupts

Technical Data MC68HC908GR8 — Rev 4.0

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4.3.2 External Reset

A logic 0 applied to the RST pin for a time, tIRL, generates an extern al

reset. An external reset sets the PIN bit in the SIM reset status register.

4.3.3 Internal Reset

Sources:

•Power - on reset (POR)

•Computer operating properly (COP)

•Low-power reset circuits

•Illegal op code

•Illegal address

All internal reset sour ces pull the RST pin low for 32 CGMXCLK cycles

to allow resetting of external devices. The MCU is held in reset for an

additional 32 CGMXCLK cycles after releasing the RST pin.

Figure 4-1. Internal Reset Timing

4.3.3.1 Power-On Reset

A power-on reset is an internal reset caused by a positive transition on

the VDD pin. VDD at the POR must go completely to 0 V to reset the MCU.

This distinguishes between a reset and a POR. The POR is not a brown-

out detector, low-voltage detector, or glitch detector.

RST PIN

PULLED LOW BY MCU

INTERNAL

32 CY CLES 32 CYCLES

CGMXCLK

RESET

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Resets and Interrupts

Resets

MC68HC908GR8 — Rev 4.0 Technical Data

MOTOROLA Resets and Interrupts 63

A power-on reset:

•Holds the clocks to the CPU and modules inactive for an oscillator

stabilization delay of 4096 CGMXCLK cycles

•Drives the R ST pin low during the oscillator stabil ization delay

•Releases the RST pin 32 CGMXCLK cycles after the oscillator

stabilization delay

•Releases the CPU to begin the reset vector sequence 64

CGMXCLK cycles after the oscillator stabilization delay

•Sets the POR bit in the SIM reset status register and clears all

other bits in the register

Figure 4-2. Power-On Reset Recovery

4.3.3.2 COP Reset

A COP reset is an internal reset caused by an overflow of the COP

counter. A CO P reset sets the COP bit in the syste m integration module

(SIM) reset status register.

To clear the COP counter and prevent a COP reset, write any value to

the COP control register at location $FFFF.

PORRST(1)

OSC1

CGMXCLK

CGMOUT

RST PIN

INTERNAL

4096

CYCLES 32

CYCLES

1. PORRST is an internally generated power-on reset pulse.

RESET

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Technical Data MC68HC908GR8 — Rev 4.0

64 Resets and Interrupts MOTOROLA

4.3.3.3 Low-Voltage Inhibit Reset

A low-vol ta ge inhi bi t (L VI) re set is an i nte rnal r eset cause d by a dr op in

the power supply voltage to the LVI trip voltage, VTRIPF.

An LVI reset:

•Holds the clocks to the CPU and modules inactive for an oscillator

stabilization delay of 4096 CGMXCLK cycles after the power

supply voltage rises to VTRIPF

•Drives the R ST pin low for as long as VDD is below VTRIPF and

during the oscillator stabilization delay

•Releases the RST pin 32 CGMXCLK cycles after the oscillator

stabilization delay

•Releases the CPU to begin the reset vector sequence

64 CGMXCLK cycles after the oscillator stabilization delay

•Sets the LVI bit in the SIM reset status register

4.3.3.4 Illegal Opcode Reset

An illeg al op code re set i s an inte rnal reset caused by an op cod e tha t is

not in the instruction set. An illegal opcode reset sets the ILOP bit in the

SIM reset status register.

If the stop enabl e bit, STO P, in t he mas k opt ion regi ster is a l ogic 0, the

STOP instruction causes an illegal opcode reset.

4.3.3.5 Illegal Address Reset

An illegal address reset is an internal reset caused by opcode fetch from

an unmapped address. An illegal address reset sets the ILAD bit in the

SIM reset status register.

A data fetch from an un mapped address does not generate a reset.

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Resets

MC68HC908GR8 — Rev 4.0 Technical Data

MOTOROLA Resets and Interrupts 65

4.3.4 SIM Reset Status Register

This re ad-only re gister contai ns flags to sho w reset sources. All flag bit s

are aut omatica lly clea re d follo wing a r ead of th e regi ster. Reset servi ce

can read the SIM reset status register to clear the register after power-

on reset and to determine the sourc e of any s ubse quent reset.

The reg ister is initia lized on p owerup as sho wn wi th the POR bit set and

all ot her bits cl eared. Du ring a P OR or any oth er inte rnal rese t, the RST

pin is pulle d low. After the pin is relea s ed, it will be sampled 32 XCLK

cycles later. If the pin is not above a VIH at that time, then the PIN bit in

the SRSR may be set in addition to whatever other bits are set.

NOTE: Only a read of the SIM reset status register clears all reset flags. After

multiple resets from different sources without reading the register,

multiple flags remain set.

POR — Power-On Reset Flag

1 = Power-on reset since last read of SRSR

0 = Read of SRSR since last power-on reset

PIN — E xternal Reset Fl ag

1 = External reset via RST pin since last r ead of SR SR

0 = POR or read of SRSR since last external reset

COP — Computer Operating Properly Reset Bit

1 = Last reset caused by timeout of COP counter

0 = POR or read of SRSR

Address: $FE01

Bit 7654321Bit 0

Read: POR PIN COP ILOP ILAD 0 LVI 0

Write:

POR:10000000

= Unimplemented

Figure 4-3. SIM Reset Status Register (SRSR)

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66 Resets and Interrupts MOTOROLA

ILOP — Illegal Opcode Reset Bit

1 = Last reset caused by an illegal opcode

0 = POR or read of SRSR

ILAD — Illegal Address Reset Bit

1 = Last reset caused by an opcode fetch from an illegal address

0 = POR or read of SRSR

LVI — Low-Voltage Inhibit Reset Bit

1 = Last reset caused by low-power supply voltage

0 = POR or read of SRSR

4.4 Interrupts

An interrupt temporarily changes the sequence of program execution to

respond to a particular event. An interrupt does not stop the operation of

the instruction being executed, but begins when the current instruction

completes its operation.

4.4.1 Effects

An interrupt:

•Saves the CPU registe rs on the stack. At the end of th e interrup t,

the RTI instruction recovers the CPU registers from the stack so

that normal processi ng can resume.

•Sets the i nterrupt mask (I bit) to prevent additional interrupts.

Once an i nterrupt is latched, no other interrupt can take

precedence, regardless of its priority.

•Loads the program counter with a user-defined vector address

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MC68HC908GR8 — Rev 4.0 Technical Data

MOTOROLA Resets and Interrupts 67

Figure 4-4. Interrupt Stacking Order

After eve ry instr u ction, the CPU chec ks all pe nd in g i nte rr u pts if the I bit

is not set. If more than one interrupt is pending when an instruction is

done, the highest priority interrupt is serviced first. In the example shown

in Figure 4-5, if an interrup t is pending upon exit from the interrupt

service routine, the pending interrupt is serviced before the LDA

instruction is executed.

CONDITION CODE REGISTER

ACCUMULATOR

INDEX REGISTER (LOW BYTE)*

PROGRAM COUNTER (HIGH BYTE )

PROGRAM COU NTER (LOW BYTE)

•

STACKING

ORDER

*High byte of index register is not stacked.

$00FF DEFAULT ADDRESS ON RESET

UNSTACKING

ORDER

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Technical Data MC68HC908GR8 — Rev 4.0

68 Resets and Interrupts MOTOROLA

Figure 4-5. Interrupt Recognition Example

The LDA opcode is prefetched by both the INT1 and INT2 RTI

instructions. However, in the case of the INT1 RTI prefetch, this is a

redundant operation.

NOTE: To maintain compatibility with the M6805 Family, the H register is not

pushed on the stack during interrupt entry. If the interrupt service routine

modifi es the H reg ister or uses the inde xed addressing mode , save the

H register and then restore it prior to exiting the routine.

CLI

LDA

INT1

PULH

RTI

INT2

BACKGROUND

#$FF

PSHH

INT1 INTERRUPT SERVICE ROUTINE

PULH

RTI

PSHH

INT2 INTERRUPT SERVICE ROUTINE

ROUTINE

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MC68HC908GR8 — Rev 4.0 Technical Data

MOTOROLA Resets and Interrupts 69

Figure 4-6. Interrupt Processing

YES

FROM RESET

BREAK

I BIT SET?

IRQ

INTERRUPT

CGM

INTERRUPT

FETCH NEXT

INSTRUCTION

UNSTACK CPU REGISTERS

STACK CPU REGISTERS

SET I BIT

LOAD PC WITH INTERRUPT VECTOR

EXECUTE INSTRUCTION

YES

I BIT SET?

INTERRUPT

YES

OTHER

INTERRUPTS

SWI

INSTRUCTION

RTI

INSTRUCTION

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4.4.2 Sources

The sources in Table 4-1 can generate CPU interrupt requests.

Table 4-1. Interrupt Sources

Source Flag Mask(1) INT Register

Flag Priority(2) Vector

Address

Reset None None None 0 $FFFE–$FFFF

SWI instruction None None None 0 $FFFC–$FFFD

IRQ pin IRQF IMASK1 IF1 1 $FFFA–$FFFB

CGM (PLL) PLLF PLLIE IF2 2 $FFF8–$FFF9

TIM1 channel 0 CH0F CH0IE IF3 3 $FFF6–$FFF7

TIM1 channel 1 CH1F CH1IE IF4 4 $FFF4–$FFF5

TIM1 overflow TOF TOIE IF5 5 $FFF2–$FFF3

TIM2 channel 0 CH0F CH0IE IF6 6 $FFF0–$FFF1

TIM2 overflow TOF TOIE IF8 8 $FFEC–$FFED

SPI receiver full SPRF SPRIE

IF9 9 $FFEA–$FFEBSPI overflow OVRF ERRIE

SPI mode fault MODF ERRIE

SPI transmitter empty SPTE SPTIE IF10 10 $FFE8–$FFE9

SCI receiver overrun OR ORIE

IF11 11 $FFE6–$FFE7

SCI noise fag NF NEIE

SCI framing error FE FEIE

SCI parity error PE PEIE

SCI receiver full SCRF SCRIE IF12 12 $FFE4–$FFE5

SCI input idle IDLE ILIE

SCI transmitter empty SCTE SCTIE IF13 13 $FFE2–$FFE3

SCI transmission complete TC TCIE

Keyboa rd pin KEYF IMASKK IF14 14 $FFDE –$FFDF

ADC conversion complete COCO AIEN IF15 15 $FFDE–$FFDF

Timebase TBIF TBIE IF16 16 $FFDC–$FFDD

Note:

1. The I bit in the condition code register is a global mask for all interrupt sources except the SWI instruction.

2. 0 = highest priority

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MC68HC908GR8 — Rev 4.0 Technical Data

MOTOROLA Resets and Interrupts 71

4.4.2.1 SWI Instruction

The software interrupt instruction (SWI) causes a non-maskable

interrupt.

NOTE: A software interrupt pushes PC onto the stack. An SWI does not push

PC – 1, as a hardware in terrup t does.

4.4.2.2 Break Interrupt

The br eak module ca uses the CPU to execute an SWI instruction at a

softw are-programmable brea k point.

4.4.2.3 IRQ Pin

A logic 0 on the IRQ1 pin latches an external interrupt re quest.

4.4.2.4 CGM

The CGM can generate a CPU interrupt request every time the phase-

locked loop circuit (PLL) enters or leaves the locked state. When the

LOCK bit changes state, the PLL flag (PLLF) i s set. The PLL in terrupt

enable bit (PLLIE) enables PLLF CPU interrupt requests. LOCK is in the

PLL bandwidth control register. PLLF is in the PLL control register.

4.4.2.5 TIM1

TIM1 CPU interrupt sources:

•TIM1 overflow flag (TOF) — The TOF bit is set when the TIM1

counter value rolls over to $0000 after matching the valu e in the

TIM1 counter modulo registers. The TIM1 overflow interrupt

enable bit, TOIE , enables TIM1 ove rf low CPU interrup t re qu ests.

TOF and TOIE are in the TIM1 status and control register.

•TIM1 channel flags (CH1F–CH0F) — The CHxF bit is set when an

input capture or output compare occurs on channel x. The channel

x interrupt enable bit, CHxIE, enables channel x TIM1 CPU

interrup t requests. CHxF and CHxIE are in the TIM1 channel x

status and contro l register.

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72 Resets and Interrupts MOTOROLA

4.4.2.6 TIM2

TIM2 CPU interrupt sources:

•TIM2 overflow flag (TOF) — The TOF bit is set when the TIM2

counter value rolls over to $0000 after matching the valu e in the

TIM2 counter modulo registers. The TIM2 overflow interrupt

enable bit, TOIE , enables TIM2 ove rf low CPU interrup t re qu ests.

TOF and TOIE are in the TIM2 status and control register.

•TIM2 channel flag (CH0F) — The CH0F bit is set wh en an input

capture or output compare occurs on channel 0. The channel 0

interrupt enable bit, CH0IE, enables channel 0 TIM2 CPU interrupt

reque sts. CH0F and CH 0IE ar e in the TIM2 chan nel 0 stat us and

control register.

4.4.2.7 SPI

SPI CPU interrupt sources:

•SPI receiver full bit (SPRF) — The SPRF bit is set every time a

byte transfers from the shift register to the receive data register.

The SPI receiver interrupt enable bit, SPRIE, enables SPRF CPU

interr upt requests. SPRF is in the SPI status and control register

and SPRIE is in the SPI c ontro l register.

•SPI tran smitter empty (SPTE) — The SPTE bit i s set every time a

byte transfers from the transmit data register to the shi ft register.

The SPI transmit in terrupt en able bi t, SPTIE, en ables SPTE CPU

interrupt requests. SPTE is in the S PI status and control register

and SPTIE is in the SPI control register.

•Mode fault bit (MODF) — The MODF bit is set in a slave SPI if the

SS pin goes high during a transmission with the mode fault enable

bit (MODFEN) set. In a master SPI, the MODF bit is set if the SS

pin goes low at any time with the MODFEN bit set. The e rror

interrupt enable bit, ERRIE, enables MODF CPU interrupt

requests. MODF, MODFEN, and ERRIE are in the SPI status and

control register.

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MC68HC908GR8 — Rev 4.0 Technical Data

MOTOROLA Resets and Interrupts 73

•Overflow bit (OVRF) — The OVRF bit is set if software does not

read the byte in the receive data register before the next full byte

enters the shift register. The error interrupt enable bit, ERRIE,

enables OVRF CPU interrupt requests. OVRF and ERRIE are in

the SPI status and control register.

4.4.2.8 SCI

SCI CPU interrupt sources:

•SCI transmitter empty bit (SCTE) — SCTE is set when the SCI

data register transfers a character to the transmit shift register.

The SCI tr ansmi t i n ter rupt enable bit, SCTIE, enab le s tr an sm it ter

CPU interrupt requests. SCTE is in SCI status register 1. SCTIE is

in SCI control register 2.

•Transmission complete bit (TC) — TC is set when the transmit

shift r egi ster an d the S CI data re gister are empt y and n o br eak o r

idle character has been generated. The transmission complete

interrupt enable bit, TCIE, enables transmitter CPU interrupt

requests. TC is in SCI status register 1. TCIE is in SCI control

•SCI receiver full bit (SCRF) — SCRF is set when the receive shift

receive interrupt enable bit, SCRIE, enables receiver CPU

interrupts. SCRF is in SCI status register 1. SCRIE is in SCI

control register 2.

•Idle input bit (IDLE) — IDLE is set when 10 or 11 consecutive logic

1s shift in from the RxD pin. The idle line interrupt enable bit, ILIE,

enables IDLE CPU interrupt requests. IDLE is in SCI status

•Receiver overrun bit (OR) — OR is set when the receive shift

was re ad from the SC I data registe r. The overr un interr upt enable

bit, ORIE, enables OR to generate SCI error CPU interrupt

requests. OR is in SCI status register 1. ORIE is in SCI control

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Technical Data MC68HC908GR8 — Rev 4.0

74 Resets and Interrupts MOTOROLA

•Noise flag (NF) — NF is set when the SC I detects noise on

incoming data or break characters, including start, data, and stop

bits. The noise error interrupt enable bit, NEIE, enables NF to

generate SCI error CPU interru pt re qu ests. NF is in SCI status

•Framing error bit (FE) — FE is set when a logic 0 occurs where the

receiver expects a stop bit. The framing error interrupt enable bit,

FEIE, enab les FE to generate SCI error CPU interrupt requests.

FE is in SCI status register 1. FEIE is in SCI control register 3.

•Parity error bit (PE) — PE is set when the SCI detects a parity error

in incoming data. The parity error interrupt enable bit, PEIE,

enables PE to generate SCI error CPU interrupt requests. PE is in

SCI status register 1. PEIE is in SCI control register 3.

4.4.2.9 KBD0–KBD4 Pins

A logic 0 on a keyboard interrupt pin latches an external interrupt

request.

4.4.2.10 ADC (Analog-to-Digital Converter)

When the AIEN bit is set, the ADC module is capable of generating a

CPU interrupt after each ADC conversion. The COCO/IDMAS bit is not

used as a conversion complete flag when interrupts are enabled.

4.4.2.11 TBM (Timebase Module)

The timebase module can interrupt the CPU on a regular basis with a

rate defined by TBR2–TBR0. When the timebase counter chain rolls

over, the TBIF flag is set. If the TBIE bit is set, enabling the timebase

interrupt, the counter chain overflow will generate a CPU interrupt

request.

Interrupts must be acknowledged by writing a logic 1 to the TACK bit.

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MC68HC908GR8 — Rev 4.0 Technical Data

MOTOROLA Resets and Interrupts 75

4.4.3 Interrupt Status Registers

The flags in the interrupt status registers iden tify maskable interrupt

sources. Table 4-2 summarizes the interrupt sources and the interrupt

status register flags that they set. The interrupt status registers can be

useful for debugging.

Table 4-2. Interrupt Source Flags

Interrupt Source Interrupt Status Register Flag

Reset —

SWI instruction —

IRQ pin IF1

CGM (PLL) IF2

TIM1 channel 0 IF3

TIM1 channel 1 IF4

TIM1 overflow IF5

TIM2 channel 0 IF6

Reserved IF7

TIM2 overflow IF8

SPI receive IF9

SPI transmit IF10

SCI error IF11

SCI receive IF12

SCI transmit IF13

Keyboard IF14

ADC conversion complete IF15

Timebase IF16

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76 Resets and Interrupts MOTOROLA

4.4.3 .1 Interrupt Status Regis ter 1

IF6–IF1 — Interrupt Flags 6–1

These flags indicate the presence of interrupt requests fr om the

sources shown in Table 4-2.

1 = Interru pt re qu est pr ese nt

0 = No interrupt request present

Bit 1 and B it 0 — Always read 0

4.4.3 .2 Interrupt Status Regis ter 2

IF14–IF7 — Int errupt Flags 14–7

These flags indicate the presence of interrupt requests fr om the

sources shown in Table 4-2.

1 = Interru pt re qu est pr ese nt

0 = No interrupt request present

Address: $FE04

Bit 7654321Bit 0

Read: IF6 IF5 IF4 IF3 IF2 IF1 0 0

Write:RRRRRRRR

Reset:00000000

R = Reserved

Figure 4-7. Interrupt Status Register 1 (INT1)

Address: $FE05

Bit 7654321Bit 0

Read: IF14 IF13 IF12 IF11 IF10 IF9 IF8 IF7

Write:RRRRRRRR

Reset:00000000

R = Reserved

Figure 4-8. Interrupt Status Register 2 (INT2)

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MOTOROLA Resets and Interrupts 77

4.4.3 .3 Interrupt Status Regis ter 3

IF16–IF15 — Interrupt Flags 16–15

This flag indicates the presence of an interrupt request from the

source shown in Ta bl e 4- 2.

1 = Interru pt re qu est pr ese nt

0 = No interrupt request present

Bits 7–2 — Always read 0

Address: $FE06

Bit 7654321Bit 0

Read: 000000IF16IF15

Write:RRRRRRRR

Reset:00000000

R = Reserved

Figure 4-9. Interrupt Status Register 3 (INT3)

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78 Resets and Interrupts MOTOROLA

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MC68HC908GR8 — Rev 4.0 Technical Data
MOTOROLA Analog-to-Digital Converter (ADC) 79
 
Technical Data — MC68HC908GR8
Section 5. Analog-to-Digital Converter (ADC)
5.1  Contents
5.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
5.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
5.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
5.5 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
5.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
5.7 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
5.8 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
5.2  Introduction
This section describes the 8-bit analog-to-digital converter (ADC).
For further information regarding analog-to-digital converters on 
Motorola microcontrollers, please consult the HC08 ADC Reference 
Manual, ADCRM/AD.
    
  
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Analog-to-Digital Converter (ADC)

Technical Data MC68HC908GR8 — Rev 4.0

80 Analog-to-Digital Converter (ADC) MOTOROLA

5.3 Features

Features of the ADC module include:

•Six channels with multiple xed input

•Line ar success ive approximation with monotonic ity

•8-bit resolut i on

•Sing le or co ntinuo us conv ersion

•Conversion complete flag or conversion complete interrupt

•Selectable ADC clock

5.4 Functional Description

The ADC provides six pins for sampling external sources at pins

PTB5/ATD5–PTB0/ATD0. An analog multiplexer allows the single ADC

converter to select o ne of six ADC chan nels as ADC voltage in (VADIN).

VADIN is converted by th e succ essive approximation registe r -based

analog-to-digital conv erter. When the conversion is complete d, ADC

places the result in the ADC data register and sets a flag or generates

an interrupt. See Figure 5-1.

NOTE: References to DMA (direct-memory access) and associated functions

are only valid if the MCU h as a DMA modul e. If the MCU h as no DMA,

any DMA-related register bits should be left in thei r reset state for

expe ct ed MCU operat ion.

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Functional Description

MC68HC908GR8 — Rev 4.0 Technical Data

MOTOROLA Analog-to-Digital Converter (ADC) 81

Figure 5-1. ADC Block Diag ram

5.4.1 ADC Port I/O Pins

PTB5/ATD5–PTB0/ATD0 are general-purpose I/O (input/output) pins

that shar e wi th th e ADC ch annels. Th e chann el se lect b its de fine wh ich

ADC channel /port pin will be used as the input sig na l. The ADC

overrides the port I/O logic by forcing that pin as input to the ADC. The

remaining ADC channels/port pins are controlled by the port I/O logic

and can be used as general-purpose I/O. Writes to the port register or

DDR will not have any affect on the port pin that is selected by the ADC.

Read of a p ort p in in use by the ADC will return a logic 0.

INTERNAL

DATA BUS

READ DDRBx

WRITE DDRBx

RESET

WRITE PTBx

READ P T Bx

PTBx

DDRBx

PTBx

INTERRUPT

LOGIC CHANNEL

SELECT

ADC

CLOCK

GENERATOR

CONVERSION

COMPLETE

ADC

ADIN

)

ADC CLOCK

CGMXCLK

BUS CLOCK

ADCH4–ADCH0

ADC DATA REGISTER

AIEN COCO

DISABLE

ADC CHANNEL x

ADIV2–ADIV0 ADICLK

VOLTAGE IN

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Technical Data MC68HC908GR8 — Rev 4.0

82 Analog-to-Digital Converter (ADC) MOTOROLA

5.4.2 Voltage Conversion

When the input voltage t o the A DC equals VREFH, the ADC converts the

signal to $FF (full scale). If the input voltage equals VREFL, the ADC

converts it to $00. Input voltages between VREFH and VREFL are a

straight-line linear conversion. All other input voltages will result in $FF,

if greater than VREFH.

NOTE: Inside the ADC module, the reference voltage, VREFH is connected to the

ADC ana l og power VDDAD; and VREFL is connected to t he ADC analog

ground VDDAD. Therefo re, the AD C input vo ltage sh ould not exce ed the

analog supply voltages

For operation, VDDAD should be tied to the same pot en ti al as VDD via

separa te tra c es

5.4.3 Conversion Time

Conversion s tarts afte r a write to the ADSCR. One conversion will take

between 16 and 17 ADC clock cycles. The ADIVx and ADICLK bits

should be set to provide a 1 MHz ADC clock frequency.

5.4.4 Conversion

In continuous conversion mode, the ADC data register will be filled with

new data after each conversion. Data from the previous conversion will

be overwritten whether that data has been read or not. Conversions will

continue until the ADCO bit is cleared. The COCO/IDMAS bit is set after

the first conversion and will stay set until the next write of the ADC status

and control register or the next read of the ADC data register.

In single conversion mode, conversion begins with a write to the

ADSCR. Only one conversion occurs between writes to the ADSCR.

16 to17 ADC cycles

ADC frequency

Conversion time =

Number of bus cycles = conversion time x bus frequency

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MC68HC908GR8 — Rev 4.0 Technical Data

MOTOROLA Analog-to-Digital Converter (ADC) 83

5.4.5 Accuracy and Precision

The conversion process is monotonic and ha s no missing codes.

5.5 Interrupts

When the AIEN bit is set, the ADC module is capable of generating CPU

interrupts after each ADC conversion. A CPU interrupt is generated if the

COCO/IDMAS bit is at logic 0. If COCO/IDMAS bit is set, a DMA interrupt

is generated. The COCO/IDMAS bit is not used as a conversion

complete flag when interrupts are enabled.

5.6 Low-Power Modes

The WAIT and STOP instruction can put the MCU in low power-

consumptio n standby mode s.

5.6.1 Wait Mode

The ADC continues normal operation during wait mode. Any enabled

CPU interrupt request from the ADC can bring the MCU out of wait

mode. If the ADC is not required to bring the MCU out of wait mode,

power down the ADC by setting ADCH4–ADCH0 bits in the ADC status

and control register before executing the WAIT instruction.

5.6.2 Stop Mode

The AD C module is inactiv e after the ex ecution of a STOP instruction.

Any pending conversion is aborted. ADC conversions resume when the

MCU exits stop mode after an external interrupt. A llow one conversi on

cycle to stabilize the analog circuitry.

5.7 I/O Signals

The ADC module has six pins shared with port B,

PTB5/AD5–PTB0/ATD0.

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Technical Data MC68HC908GR8 — Rev 4.0

84 Analog-to-Digital Converter (ADC) MOTOROLA

5.7.1 ADC Analog Power Pin (VDDAD)/ADC Voltage Reference High Pin (VREFH)

The ADC analog portion uses VDDAD as its power pin. Connect the

VDDAD pin to the same voltage potential as VDD. External filtering may be

necessary to ensure clean VDDAD for good re sults.

NOTE: For maximum noise immunity, route VDDAD carefully and p l ace b ypass

capacitors as close as possible to the package.

5.7.2 ADC Analog Ground Pin (VSSAD)/ADC Voltage Reference Low Pin (VREFL)

The ADC analog portion uses VSSAD as its ground pin. Connect t he

VSSAD pin to the same voltage po tential as VSS.

NOTE: Route VSSAD cleanly to avoid any offset errors.

5.7.3 ADC Voltage In (VADIN)

VADIN is the input voltage signal from one of the six ADC channels to the

ADC module.

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I/O Registers

MC68HC908GR8 — Rev 4.0 Technical Data

MOTOROLA Analog-to-Digital Converter (ADC) 85

5.8 I/ O Registers

These I/O registe rs cont ro l and monitor ADC operation :

•ADC status and control register (ADSCR)

•ADC data register (ADR)

•ADC clock register (ADCLK)

5.8.1 ADC Status and Control Register

Function of the ADC status and control register (ADSCR) is described

here.

COCO/IDMAS — Conversions Complete/Interrupt DMA Select Bit

When the AIEN bit is a logic 0, the COCO/IDMAS is a read-only bit

which is set each time a conversion is completed except in the

contin uous conversi on mode where it is set after the first co nversion.

This bit is cleared whenever the ADSCR is written or whenever the

ADR is read.

If the A IEN bit is a lo gic 1, the COCO/IDMAS is a re ad/write bit which

selects either CPU or DMA to service the ADC interrupt request.

Reset clears this bit.

1 = Conversion complete d (AIEN = 0)/DMA interrupt (AIEN = 1)

0 = Conversion not comp leted (AIEN = 0)/CPU interrupt (AIEN = 1)

CAUTION: Because the MC68HC908 GR8 does NOT have a DMA module, th e

IDMAS bit should NEVER be set when AIEN is set. Doing so will mask

ADC interrupts and cause unwanted results.

Address: $0003C

Bit 7654321Bit 0

Read: COCO/

IDMAS AIEN ADCO ADCH4 ADCH3 ADCH2 ADCH1 ADCH0

Write:

Reset:00011111

Figure 5-2. ADC Stat us and Control Register (ADSCR)

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Analog-to-Digital Converter (ADC)

Technical Data MC68HC908GR8 — Rev 4.0

86 Analog-to-Digital Converter (ADC) MOTOROLA

AIEN — ADC Interrupt Enable Bit

When this bit is set, an interrupt is generated at the end of an ADC

conversion. The interrupt signal is cleared when the data register is

read or the status/ control register is written. Reset clears the AIEN bit.

1 = ADC int errupt enable d

0 = ADC int errupt disabled

ADCO — ADC Continuous Conversion Bit

When this bit is set, the ADC will convert samples continuously and

update the ADR register at t he end o f each conver sion. Only one

conversion is comp leted between writes to the ADSCR when this bit

is cleared. Reset clears the ADCO bit.

1 = Continuous ADC conversion

0 = One ADC conversion

ADCH4–ADCH0 — ADC Channel Select Bits

ADCH4–ADCH0 form a 5-bit field which is used to select one of 16

ADC channels. Only six channels, AD5–AD0, ar e available on this

MCU. The channels are det ailed in Table 5-1. Care should be taken

when using a port pin as both an analog and digital input

simultaneously to prevent switching noise from corrupting the analog

signal. See Table 5-1.

The ADC subsystem is turne d off when the channel select bits are all

set to 1. This feature allows for reduced power consumption for the

MCU when the ADC is not being used.

NOTE: Recovery from the disabled state requires one conversion cycle to

stabilize.

The voltage levels supplied from internal reference nodes, as specified

in Tabl e 5-1, are used to verify the operation of the ADC converter both

in production test and for user applications.

Table 5-1. Mux Channel Selec t

ADCH4 ADCH3 ADCH2 ADCH1 ADCH0 Input Select

00000 PTB0/ATD0

00001 PTB1/ATD1

00010 PTB2/ATD2

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Analog-to-Digital Converter (ADC)

I/O Registers

MC68HC908GR8 — Rev 4.0 Technical Data

MOTOROLA Analog-to-Digital Converter (ADC) 87

5.8.2 ADC Data Register

One 8-bit result register, ADC data register (ADR), is provided. This

00011 PTB3/ATD3

00100 PTB4/ATD4

00101 PTB5/ATD5

00110 Reserved

00111 Reserved

↓↓↓↓↓ Reserved

11011 Reserved

11100 Reserved

11101 VREFH

11110 VREFL

1 1 1 1 1 ADC power off

NOTE: If an unknown channel is selected it should be made clear what value the user will read

from the ADC Data Register, unknown or reserved is no t specific enough.

Table 5-1. Mux Channel Selec t

ADCH4 ADCH3 ADCH2 ADCH1 ADCH0 Input Select

Address: $0003D

Bit 7654321Bit 0

Read: AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0

Write:

Reset:00000000

= Unimplemented

Figure 5-3. ADC Data Register (ADR)

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Analog-to-Digital Converter (ADC)

Technical Data MC68HC908GR8 — Rev 4.0

88 Analog-to-Digital Converter (ADC) MOTOROLA

5.8.3 ADC Clock Register

The ADC clock register (ADCLK) selects the clock frequency for the

ADC.

ADIV2–ADIV0 — ADC Clock Prescaler Bits

ADIV2–ADIV0 form a 3-bit field which selects the divide ratio used by

the ADC to generate the internal ADC clock. Table 5-2 shows the

availabl e clock configurations. The ADC clock should be set to

approximately 1 MHz.

ADICLK — ADC Input Clock Select Bit

ADICLK selects either the b us clock o r CGMXCLK as t he inp ut clock

source to generate the internal ADC clock. Reset selects CGMXCLK

as the ADC clock source.

Address: $0003E

Bit 7654321Bit 0

Read: ADIV2 ADIV1 ADIV0 ADICLK 0000

Write:

Reset:00000000

= Unimplemented

Figure 5-4. ADC Clock Register (ADCLK)

Table 5-2. ADC Clock Divide Ratio

ADIV2 ADIV1 ADIV0 ADC Clock Rate

0 0 0 ADC input clock ÷ 1

0 0 1 ADC input clock ÷ 2

0 1 0 ADC input clock ÷ 4

0 1 1 ADC input clock ÷ 8

1 X X ADC input clock ÷ 16

X = don’t care

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Analog-to-Digital Converter (ADC)

I/O Registers

MC68HC908GR8 — Rev 4.0 Technical Data

MOTOROLA Analog-to-Digital Converter (ADC) 89

If the external clock (CGMXCLK) is equal to or greater than 1 MHz,

CGMXCLK can be used as the clock source for the ADC. If

CGMXCLK is less than 1 MHz, use the PLL-genera ted bus clock as

the clock source. As long as the internal ADC clock is at

approximately 1 MHz, correct operation can be guaranteed.

1 = Internal bus clock

0 = External clock (CGMXCLK)

ADC input clock frequency

ADIV2 ADIV0–

----------------------------------------------------------------------- 1 M H z=

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Analog-to-Digital Converter (ADC)

Technical Data MC68HC908GR8 — Rev 4.0

90 Analog-to-Digital Converter (ADC) MOTOROLA

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MC68HC908GR8 — Rev 4.0 Technical Data
MOTOROLA Break Module (BRK) 91
 
Technical Data — MC68HC908GR8
Section 6. Break Module (BRK)
6.1  Contents
6.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
6.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
6.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
6.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
6.6 Break Modu le Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
6.2  Introduction
This se ction describ es the break module. The break module can 
generate a break interrupt that stops normal program flow at a defined 
address to enter a background program.
6.3  Features
Features of the break module include:
•Accessible input/output (I/O) registers during the break interrupt
•CPU-generated break interrupts
•Software-generated break interrupts
•COP disabling during break interrupts
    
  
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Break Module (BRK)

Technical Data MC68HC908GR8 — Rev 4.0

92 Brea k Module (BRK) MOTOROLA

6.4 Functional Description

When the internal address bus matches the value written in the break

address registers, the break module issues a breakpoint signal to the

CPU. The CPU then loads the instruction register with a software

inter r upt instruction (SWI) afte r compl et io n of the cur r ent CPU

instruction. The program count er vectors to $FFFC and $FFFD ($FEFC

and $FEFD in monitor mode).

The following events can cause a break interrupt to occur:

•A CPU-genera ted ad dress (the address in the program counter)

matches the contents of the break address register s.

•Software writes a logic 1 to the BRKA bit in the break status and

control register.

When a CPU-generated address matches the contents of the break

address registers, the break interrupt begins after the CPU completes its

current instruction. A return-from-interrupt instruction (RTI) in the break

routine ends the break interrupt and returns the MCU to normal

operation. Figure 6-1 shows the stru cture of the break module.

Figure 6-1. Break Module Block Diagram

IAB15–IAB8

IAB7–IAB0

8-BIT COMPARATOR

CONTROL

BREAK ADDRESS R EG IST ER LO W

BREAK ADDRESS REGISTER HIGH

IAB15–IAB0 BREAK

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Break Module (BRK)

Functional Description

MC68HC908GR8 — Rev 4.0 Technical Data

MOTOROLA Break Module (BRK) 93

6.4.1 Flag Protection During Break Interrupts

The BCFE bit in the SIM break flag control register (SBFCR) enables

software to clear status bits during the break state.

6.4.2 CPU During Break Interrupts

The CPU starts a break interrupt by:

•Loading the instruction register with the SWI instruction

•Loading the program counter with $FFFC and $FFFD ($FEFC and

$FEFD in monitor mode)

Addr.Register Name Bit 7654321Bit 0

$FE00 SIM Break Status Register

(SBSR)

Read: 000100BW0

Write:RRRRRRNOTER

Reset:00010000

$FE03 SIM Break Flag Control

Read: BCFERRRRRRR

Write:

Reset: 0

$FE09 Break Address Register

High (BRKH)

Read: Bit 15 14 13 12 11 10 9 Bit 8

Write:

Reset:00000000

$FE0A Break Address Register

Low (BRKL)

Read: Bit 7654321Bit 0

Write:

Reset:00000000

$FE0B Break Status and Control

Read: BRKE BRKA 000000

Write:

Reset:00000000

Note: Writing a logic 0 clears BW. = Unimplem ented R = Reserved

Figure 6-2. I/O Register Summary

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Break Module (BRK)

Technical Data MC68HC908GR8 — Rev 4.0

94 Brea k Module (BRK) MOTOROLA

The break interrupt begins after completion of the CPU instruction in

progress. If the brea k address register match occurs on the last cycle of

a CPU instruction, the break interrupt begins immediately.

6.4.3 TIMI and TIM2 During Break Interrupts

A break interrupt stops the timer counters.

6.4.4 COP During Break Interrupts

The COP is disabled during a break interrupt when V TST is pr esent on

the RST pin.

6.5 Low-Power Modes

The WAIT and STOP instructions put the MCU in low power-

consumptio n standby mode s.

6.5.1 Wait Mode

If enabled, the break module is active in wait mode. In the break routine,

the user can subtract one from the return address on the stack if SBSW

is set. See Low Power Modes. Clear the BW bit by writing logic 0 to it.

6.5.2 Stop Mode

A break interrupt causes exit from stop mode and sets the SBSW bit in

the break status register.

6.6 Break Module Registers

These r egisters cont rol and monitor operation of the b r eak module:

•Break status and control register (BRKSCR)

•Brea k address register high (BRKH)

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Break Module (BRK)

Break Module Registers

MC68HC908GR8 — Rev 4.0 Technical Data

MOTOROLA Break Module (BRK) 95

•Break addr ess register lo w (BRKL)

•SIM break status register (SBSR)

•SIM break flag control register (SBFCR)

6.6.1 Break Status and Control Register

The break status and control register (BRKSCR) contains break module

enable and st atus bits.

BRKE — Break Enable Bit

This read/write bit enables breaks on break address register matches.

Clear BRKE by writing a logic 0 to bit 7. Reset clears the BRKE bit.

1 = Breaks enabled on 16-bit address match

0 = Breaks disabled on 16-bit address match

BRKA — Break Active Bit

This read/write status and control bit is set when a break address

match occurs. Writing a logic 1 to BRKA generates a break interrupt.

Clear B RK A by w ri ti ng a lo gic 0 to it befor e exi ti n g the br ea k ro uti n e.

Reset clears the BR KA bit.

1 = (When read) Break addr ess mat c h

0 = (When read) No break address match

Address: $FE0E

Bit 7654321Bit 0

Read: BRKE BRKA 000000

Write:

Reset:00000000

= Unimplemented

Figure 6-3. Break Status and Control Register (BRKSCR)

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Break Module (BRK)

Technical Data MC68HC908GR8 — Rev 4.0

96 Brea k Module (BRK) MOTOROLA

6.6.2 Break Address Registers

The break address registers (BRKH and BRKL) contain the high and low

bytes of the desired breakpoint address. Reset clears the break address

registers.

6.6.3 Break Status Register

The break status register (SBSR) contains a flag to indicate that a break

caused an exit from wait mode. The flag is useful in applications

requiring a return to wait mode after exiting from a break interrupt.

Address: $FE09

Bit 7654321Bit 0

Read: Bit 15 14 13 12 11 10 9 Bit 8

Write:

Reset:00000000

Figure 6-4. Break Address Register High (BRKH)

Address: $FE0A

Bit 7654321Bit 0

Read: Bit 7654321Bit 0

Write:

Reset:00000000

Figure 6-5. Break Address Register Low (BRKL)

Address: $FE00

Bit 7654321Bit 0

Read: 000100BW0

Write:RRRRRRNOTER

Reset:00010000

Note: Writing a logic 0 clears BW. R = Reserved

Figure 6-6. SIM Break St atus Re gist er (S BSR )

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Break Module (BRK)

Break Module Registers

MC68HC908GR8 — Rev 4.0 Technical Data

MOTOROLA Break Module (BRK) 97

BW — Break Wait Bit

This read/write bit is set when a break interrupt causes an exi t from

wait mode. Clear BW by writing a logic 0 to it. Reset clears BW.

1 = Break interrupt during wait mode

0 = No break interrupt d uring wait mode

BW can be read within the break interrupt routine. The user can modify

the return address on the stack by subtracting 1 from it. The following

code is an example.

This code works if the H register was stacked in the break interrupt

routine. Execute this code at the end of the break interrupt routine.

HIBYTE EQU 5

LOBYTE EQU 6

; If not BW, do RTI

BRCLR BW,BSR, RETURN ;

;See if wait mode or stop mode

was exited by break.

TST LOBYTE,SP ; If RETURNLO is not 0,

BNE DOLO ; then just decrement low byte.

DEC HIBYTE,SP ; Else deal with high byte also.

DOLO DEC LOBYTE,SP ; Point to WAIT/STOP opcode.

RETURN PULH

RTI ; Restore H register.

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Break Module (BRK)

Technical Data MC68HC908GR8 — Rev 4.0

98 Brea k Module (BRK) MOTOROLA

6.6.4 Break Flag Control Register

The brea k flag control register (SBFCR) contains a bit that enables

software to clear st atus bits while the MCU is in a break state.

BCFE — Break Clear Flag En able Bit

This re ad/ wr ite bi t en ab l es sof tw are to cl ea r sta tu s bi ts by a ccessing

status registers whil e the MCU is in a brea k state. To clear status bit s

during the break state, the BCFE bit must be set.

1 = Status bits clearable during break

0 = Status bits not cle ar ab le dur i ng break

Address: $FE03

Bit 7654321Bit 0

Read: BCFERRRRRRR

Write:

Reset: 0

R= Reserved

Figure 6-7. SIM Break Flag Control Register (SBFCR)

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MC68HC908GR8 — Rev 4.0 Technical Data
MOTOROLA Clock Generator Module (CGMC) 99
 
Technical Data — MC68HC908GR8
Section 7. Clock Generator Module (CGMC)
7.1  Contents
7.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
7.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100
7.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100
7.5 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112
7.6 CGMC Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114
7.7 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123
7.8 Special Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123
7.9 Acquisition/Lock Time Specifications . . . . . . . . . . . . . . . . . . .125
7.2  Introduction
This sectio n descri bes the  clock gener at or  modul e. The CG MC  
generates the crystal clock signal, CGMXCLK, which operates at the 
frequency of the crystal. The CGMC also generates the base clock 
signal, CGMOUT, which is based on ei th er  the crystal clo ck divided  by 
two or the ph ase-locked loop (PLL) clock, CGMVCLK, divided b y two. In 
user mo de, CGMOUT is the clock from which the SIM derives the 
system clocks, including the bus clock, which is at a frequency of 
CGMOUT/2. In monitor mode, PTC3 determines the bus clock. The PLL 
is a fully functional frequency generator designed for use with crystals or 
ceramic resonators. The PLL can generate an 8-MHz bus frequency 
using a 32-kHz crystal.
    
  
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Clock Generator Module (CGMC)

Technical Data MC68HC908GR8 — Rev 4.0

100 Clock Generator Module (CGMC) MOTOROLA

7.3 Features

Features of the CGMC include:

•Phase-locked loop with output frequency in integer multiples of an

integer dividend of the crystal reference

•Low-freq uency crystal operat ion with low-power operation and

high-output fr equency res olution

•Programmable prescaler for power-of-two inc reases in frequency

•Programmable hardware voltage-cont rolled osci llator (VCO) for

low-jitter operation

•Automatic bandwidth control mode for low-jitter operation

•Automatic frequency lock detector

•CPU interrupt on entry or exit from locked condition

•Configuration register bit to allow oscillator operation during stop

mode

7.4 Functional Description

The CGMC consists of three major submodules:

•Crystal oscillator circuit — The crystal oscillator circuit generates

the constant crystal frequency clock, CGMXCLK.

•Phas e-locked loop (PLL) — The PLL generates the

programmable VCO fr eque nc y cloc k, CGMVCL K.

•Base clock selector circuit — This software-controlled circuit

selects either CGMXCLK divided by two or the VCO clock,

CGMVCLK, divided by two as the base clock, CGMOUT. The SIM

derives the system clocks from either CGMOUT or CGMXCLK.

Figure 7-1 shows the structure of the CGMC.

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Clock Generator Module (CGMC)

Functional Description

MC68HC908GR8 — Rev 4.0 Technical Data

MOTOROLA Clock Generator Module (CGMC) 101

Figure 7-1. CGMC Block Diagram

BCS

PHASE

DETECTOR LOOP

FILTER

FREQUENCY

DIVIDER

VOLTAGE

CONTROLLED

OSCILLATOR

AUTOMATIC

MODE

CONTROL

LOCK

DETECTOR

CLOCK

CGMXCLK

CGMOUT

CGMVDV

CGMVCLK

SIMOSC EN (F RO M SI M)

OSCILLATOR (O SC)

INTERRUPT

CONTROL PLLIREQ

CGMRDV

PLL ANALOG

CGMRCLK

OSC2

OSC1

SELECT

CIRCUIT

VDDA CGMXFC VSSA

LOCK AUTO ACQ

VPR1–VPR0

PLLIE PLLF

MUL11–MUL0

REFERENCE

DIVIDER

VRS7–VRS0

FREQUENCY

DIVIDER

PRE1–PRE0

OSCSTOPENB

(FROM CONFIG)

(TO: SIM, TIMTB15A, ADC)

PHASE-LOCKED LOOP (PLL)

(TO SIM)

(TO S IM )

RDS3–RDS0

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Clock Generator Module (CGMC)

Technical Data MC68HC908GR8 — Rev 4.0

102 Clock Generator Module (CGMC) MOTOROLA

7.4.1 Crys tal Oscillator Circuit

The crystal oscillator circuit consists of an inverting amplifier and an

external crystal. The OSC1 pin is the input to the amplifier and the OSC2

pin is the ou tput. The SIMOSCEN signal from the system integration

module (SIM) or the OSCSTOPENB bit in the CONFIG register enable

the crystal oscillator circuit.

The CGMXCLK signal is the output of the crystal oscillator circuit and

runs at a rate equal to the crystal frequency. CGMXCLK is then buffered

to produce CGMRCLK, the PLL reference clock.

CGMXCLK can be used by other mo du le s which require pr ecis e ti mi ng

for operation . The duty cycle of CGMXCLK is no t guaranteed t o be 50%

and depends on external factors, including the crystal and related

external componen ts. An externally ge nerat ed clock also can feed t he

OSC1 pin of the crystal oscillator circuit. Connect the exte rnal clock to

the OSC1 pin and let the OSC2 pin float.

7.4.2 Phase-Locked Loop Circuit (PLL)

The PLL is a frequ ency gen er at or that can op er ate in eithe r acqui si ti on

mode or tracking mode, depending on the accuracy of the output

frequency. The PLL can change between acquisition and tracking

modes either automatically or manually.

7.4.3 PLL Circuits

The PLL consists of these circuits:

•Voltage-controlled oscillator (VCO)

•Reference div ider

•Frequency prescaler

•Modulo VCO fre que ncy divi de r

•Phase detector

•Loop filter

•Lock detector

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Clock Generator Module (CGMC)

Functional Description

MC68HC908GR8 — Rev 4.0 Technical Data

MOTOROLA Clock Generator Module (CGMC) 103

The operating range of the VCO is programmable for a wide range of

frequencies and for ma ximum immunity to external noise, including

supply and CGM/XFC noise. The VCO frequency is bound to a range

from roughly one-half to twice the center-of-range frequency, fVRS.

Modulati ng the voltage on the CGM/XFC pin changes the frequency

within this range. By design, fVRS is equal to the nominal center-of-range

freque ncy, fNOM, (38.4 kHz) times a linear factor, L, and a power-of-two

factor, E, or (L ×2E)fNOM.

CGMRCLK is the PLL reference clock, a buffered version of CGMXCLK.

CGMRCLK runs at a frequency, fRCLK, and is fed to the PLL through a

programmable modulo reference divider, which divides fRCLK by a

factor, R. The divider’s output is the final reference clock, CGMRDV,

running at a frequency, fRDV =f

RCLK/R. With an external c ryst al

(30 kHz–100 kH z), alwa ys set R = 1 for spe cif ied pe rf ormance . With an

external high-frequency clock source, use R to divide the external

freq uenc y to between 30 kHz and 100 kHz.

The VCO’s output clock, CGMVCLK, running at a frequency, fVCLK, is

fed back through a programmable prescale divider and a programmable

modulo divi der. The pr escale r divide s th e VCO cl ock by a p owe r-of -two

factor P and the mo dulo divider reduces the VCO c lock by a factor, N.

The divi ders’ out put is the VCO feedb ack clock, CGMVDV, runn ing at a

frequency, fVDV =f

VCLK/(N ×2P). (S ee Programming the PLL for more

information.)

The phase detector then compares the VCO feedback clock, CGMVDV,

with the final reference clock, CGMRDV. A correction pulse is generated

based on the phase difference between the two signals. The loop filter

then slightly alters the DC voltage on the external capacitor connected

to CGM/XFC based on the width and direction of the correction pulse.

The filter can make fast or slow corrections depending on its mode,

described in Acquis itio n and Tr acking Mo des . The value of th e exter nal

capacitor and the reference frequency determine the speed of the

corrections and the stability of the PLL.

The lock detector compares the frequencies of the VCO feedback clock,

CGMVDV, and the final reference clock, CGMRDV. Therefore, the

speed of the lock detector is directly proportional to the final reference

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Clock Generator Module (CGMC)

Technical Data MC68HC908GR8 — Rev 4.0

104 Clock Generator Module (CGMC) MOTOROLA

frequency, fRDV. The circuit determines the mode of the PLL and the lock

condition based on this comparison.

7.4.4 Acquisition and Tracking Modes

The PLL filter is manually or automatically configurable into one of two

operating modes:

•Acquisi tion mode — In acquisition mode, the filter can make large

frequency corrections to the VCO. This mode is used at PLL

startup or when the PLL has suffered a severe noise hit and the

VCO frequency is far off the desired frequency. When in

acquisition mode, the ACQ bit is clear in the PLL bandwidth control

•Tracking mode — In tracking mode, the filter makes only small

corrections to the frequency of the VCO. PLL jitter is much lower

in tracking mode, but the response to noise is also slower. The

PLL enters tracking mode when the VCO frequency is nearly

correct, such as when the PLL is selected as the base clock

source. (See Base Clock Selector Circuit.) The PLL is

automatically in tracking mode when no t in acquisition mo de or

when the ACQ bit is set.

7.4.5 Manual and Automatic PLL Bandwidth Modes

The PLL can change the bandwidth or operational mode of the loop filter

manual ly or a uto matically. Automatic mode is recommended for most

users.

In automatic bandwidth control mode (AUTO = 1), the lock detector

automatically switches between acquisition and tracking modes.

Automatic bandwidth control mode also is used to determine when the

VCO clock, CGMVCLK, is saf e to use a s the sou rce fo r the b ase clock,

CGMOUT. (See PLL Bandwidth Control Register.) If PLL interrup ts are

enable d, the software can wait for a PLL interrupt request and then

check the LOCK bit. If interrupts are disabled, software can poll the

LOCK bit continuous ly (during PLL startup, usually) o r at periodic

intervals. In either case , when the LOCK bit is set, the VCO clock is safe

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Clock Generator Module (CGMC)

Functional Description

MC68HC908GR8 — Rev 4.0 Technical Data

MOTOROLA Clock Generator Module (CGMC) 105

to use as the source for the base clock. (See Base Clock Selector

Circuit.) If the VCO is se lecte d a s th e so urce for t he ba se c lock a nd the

LOCK bit is clear, the PLL ha s suffered a severe noise hit and the

softwar e mu st take app r opr iate action, depend ing on the applicatio n.

(See Interrupts for information and precautions on using interrupts.)

The following conditions apply when the PLL is in automatic bandwidth

control mode:

•The ACQ bit ( see PLL Bandwidth Control Register) is a read -only

indicator of the mode of the filter. (See Acquisition and Tracki ng

Modes.)

•The ACQ bit is set when the VCO frequency is within a certain

tolerance and is cleared when the VCO frequency is out of a

certain tolerance. (See Acquisition/Lock Time Specifications for

more i nfo rm at i on.)

•The LOCK bit is a read-only indicator of the locked state of the PLL.

•The LOCK bit is set when the VCO frequency is within a certain

tolerance and is cleared when the VCO frequency is out of a

certain tolerance. (See Acquisition/Lock Time Specifications for

more i nfo rm at i on.)

•CPU interrupts can occur if enabled (PLLIE = 1) when the PLL’s

lock condition changes, toggling the LOCK b i t. (See PLL Control

The PLL also may operate in manual mode (AUTO = 0). Manual mode is

used by systems that do not require an indicator of the lock condition for

proper operation. Such systems typically operate well below f

BUSMAX

The following conditions apply when in manual mode:

•ACQ is a writable control bit that controls the mode of the filter.

Before turning on the PLL in manual mode, the ACQ bit must be

clear.

•Before entering tracking mode (ACQ = 1), software must wait a

given time, tACQ (see Acqu isit ion/Lock Ti me Speci fication s), af ter

turning on the PLL by setting PLLON in the PLL control register

(PCTL).

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Clock Generator Module (CGMC)

Technical Data MC68HC908GR8 — Rev 4.0

106 Clock Generator Module (CGMC) MOTOROLA

•Software must wait a given time, tAL, aft er entering t racking mode

before selecting the PLL as the clock source to CGMOUT

(BCS = 1).

•The LOCK bit is disabled.

•CPU interrupts from the CGMC are disabled.

7.4.6 Programming the PLL

The follow i ng pr oce dur e shows how to pr og ram the PLL.

NOTE: The round function in the following equations means that the real

number should be rounded to the nearest integer number.

1. Choose the desired bus frequency, fBUSDES.

2. Calcu late the desired VC O fr equ ency (four time s the de sir e d b us

frequency).

3. Choose a practical PLL (crystal) reference frequency, fRCLK, and

the reference clock divider, R. Typically, the reference crystal is

32.768 kHz and R = 1.

Frequency errors to the PLL are corrected at a rate of fRCLK/R. For

stability and lock time reduction, this rate must be as fast as

possible. The VCO frequency must be an integer multiple of this

rate. The relationship between the VCO frequency, fVCLK, and the

reference frequency, fRCLK, is

P, the power of two multiplier, and N, the range multiplier, are

integers.

In cases where desired bus frequency has some tolerance,

choose fRCLK to a value determined either by other module

requirements (such as modules which are clocked by CGMXCLK),

cost requirements, or ideally, as high as the specified range

fVCLKDES 4f

BUSDES

×=

fVCLK 2PN

----------- f RCLK

()=

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Clock Generator Module (CGMC)

Functional Description

MC68HC908GR8 — Rev 4.0 Technical Data

MOTOROLA Clock Generator Module (CGMC) 107

allows. See Electrical Specifications. Choose the reference

divider, R = 1. After choosing N and P, the actual bus frequency

can be determined using equation in 2 above.

When t he tolerance on the bu s frequency i s tight, choose fRCLK to

an integer divisor of fBUSDES, and R = 1. If fRCLK cannot m eet this

requireme nt, use the following equation to solve for R with

practical choices of fRCLK, and choose the fRCLK that gives the

lowest R.

4. Select a VCO frequency multiplier, N.

Reduce N/R to the lowest possible R.

5. If N is < Nmax, use P = 0. If N > Nmax, choose P using this table:

Then recal c ulate N:

6. Calculate and verify the adequacy of the VCO and bus

frequencies fVCLK and f BUS.

7. Select the VCO’s power-of-two range multiplier E, accor ding to

Current N Value P

R round RMAX fVCLKDES

fRCLK

--------------------------







integer fVCLKDES

fRCLK

--------------------------







–







N round Rf

VCLKDES

×fRCLK

-------------------------------------







0N<N

max

≤

Nmax N<N

max 2×≤

Nmax 2×N<N

max 4×≤

Nmax 4×N<N

max 8×≤

N round Rf

VCLKDES

fRCLK 2P

-------------------------------------







fVCLK 2PNR⁄×()fRCLK

×=

fBUS fVCLK

()4⁄=

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Clock Generator Module (CGMC)

Technical Data MC68HC908GR8 — Rev 4.0

108 Clock Generator Module (CGMC) MOTOROLA

this table:

8. Select a VCO linear range multiplier, L, where fNOM = 38.4 kHz

9. Calculate and verify the adequacy of the VCO programmed

center-of-range frequency, fVRS. The center-of-range frequency is

the midpoint between the minimum and maximum frequencies

attainable by the PLL.

For proper operation,

10. Verify the choice of P, R, N, E, and L by comparing fVCLK to fVRS

and fVCLKDES. For pr oper operation, fVCLK must be within the

application’s toleran ce of fVCLKDES, and fVRS must be as cl ose as

possible to fVCLK.

NOTE: Exceeding the recommended maximum bus frequency or VCO

freque ncy can cra sh t he MCU.

11. Program the PLL registers accordingly:

a. In the PRE bits of the PLL control register (PCTL), program

the binary equivalent of P.

b. In the VPR bits of the PLL control register (PCTL), program

the binary equivalent of E.

Frequency Range E

0 < fVCLK < 9,830,400 0

9,830,400 ≤ fVCLK < 19,660,800 1

19,660,800 ≤ fVCLK < 39,321,600 2

NOTE: Do not program E to a value of 3.

L round fVCLK

2EfNOM

--------------------------







fVRS L2

×()fNOM

fVRS fVCLK

–fNOM 2E

--------------------------

≤

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Clock Generator Module (CGMC)

Functional Description

MC68HC908GR8 — Rev 4.0 Technical Data

MOTOROLA Clock Generator Module (CGMC) 109

c. In the PLL multiplier select register low (PMSL) and the PLL

multiplier select register high (PMSH), program the binary

equivalent of N.

d. I n the PLL VCO range selec t regist er (PMRS ) , program the

binary coded equivalent of L.

e. In the PLL reference divider select register (PMDS), program

the bin ary cod ed equivalent of R.

Table 7-1 provides numeric examples (numbers are in he xadecimal

notation):

7.4.7 Special Programming Exceptions

The prog ra m mi n g me th od d escr i bed in Programming the PLL does not

account fo r three possible e xceptions. A value of 0 for R, N, or L is

meaningless when used in the equations given. To account for these

exceptions:

•A 0 value for R or N is interpreted exactly the same as a value of 1.

•A 0 val ue for L disables the PL L a nd pr e vent s i ts se le cti on as the

source for the base clock.

(See Base Clock Selector Circuit.)

Table 7-1. Numeric Example

fBUS fRCLK RNPEL

2.0 MHz 32.768 kHz 1 F5 0 0 D1

2.4576 MHz 32.768 kHz 1 12C 0 1 80

2.5 MHz 32.768 kHz 1 132 0 1 83

4.0 MHz 32.768 kHz 1 1E9 0 1 D1

4.9152 MHz 32.768 kHz 1 258 0 2 80

5.0 MHz 32.768 kHz 1 263 0 2 82

7.3728 MHz 32.768 kHz 1 384 0 2 C0

8.0 MHz 32.768 kHz 1 3D1 0 2 D0

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Clock Generator Module (CGMC)

Technical Data MC68HC908GR8 — Rev 4.0

110 Clock Generator Module (CGMC) MOTOROLA

7.4.8 Base Clock Selector Circuit

This circuit is used to select either the crystal clock, CGMXCLK, or the

VCO clock, CGMVCLK, as the source of the base clock, CGMOUT. The

two input clocks go through a transition control circuit that waits up to

three CGMXCLK cycles and three CGMVCLK cycles to change from

one clock source to the other. During this time, CGMOUT is held in

stasis. The output of the transition control circuit is then divided by two

to correct the duty cycle. Therefore, the bus clock frequency, which i s

one-h alf of th e ba se cl ock fr eq uen cy, is one-f our th the frequency of the

selected clock (CGMXCLK or CGMVCLK).

The BCS bit in the PLL control register (PCTL) selects which clock drives

CGMOUT. The VCO clock cann ot be selected as the base clock so urce

if the PLL is not turned on. The PLL cannot be turned off if the VCO clock

is selected. The PLL cannot be turned on or off simultaneously with the

selection or de selection of the VCO clock. The VCO clock also cannot

be selected as th e b ase clo ck sou rce if the facto r L is prog rammed to a

0. This value would set up a condition inconsistent with the operation of

the PLL, so t hat t he PLL wo uld be disabled an d the cr ystal clock would

be forced as the sour ce of the base clock.

7.4.9 CGMC External Connections

In its typical configuration, the CGMC requires up to nine external

components. Five of these ar e for the crystal os cill ator and two or four

are f or the PLL.

The crystal oscillator is normally connec ted in a Pierce oscillator

config uration, as shown in Figure 7-2. Fi gure 7-2 shows o nly the logica l

representation of the internal components a nd may not represent a ctual

circuitry. The oscillator configuration uses five components:

•Crystal, X1

•Fixed capacitor, C1

•Tuning capacitor, C2 (can also be a fi xed capaci tor)

•Feedback re sistor, RB

•Series resistor, RS

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Clock Generator Module (CGMC)

Functional Description

MC68HC908GR8 — Rev 4.0 Technical Data

MOTOROLA Clock Generator Module (CGMC) 111

The series resistor (RS) is included in the diagram to follow strict Pierce

oscillator guidelines. R efer to the crystal manu facturer’s data for more

informa tion regarding values for C1 and C2.

Figure 7-2 als o shows t he external components for the PLL:

•Bypass capacitor, CBYP

•Filter ne twork

Routing should be done with great care to minimize signal cross talk and

noise.

See CG M Co m ponent Specific a t ions for capacitor and resistor values.

Figure 7-2. CGMC External Connections

OSC1

C1 C2

SIMOSCEN

CGMXCLK

RS CBYP

OSC2 CGMXFC VDDA

Note: Filter network in box can be replaced with a 0. 47 µF capacitor, but will degrade stability.

VDD

OSCSTOPENB

(FROM CONFIG)

10 k 0.01 µF

0.033 µF

VSSA

0.1 µF

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Clock Generator Module (CGMC)

Technical Data MC68HC908GR8 — Rev 4.0

112 Clock Generator Module (CGMC) MOTOROLA

7.5 I/O Signals

The following paragraphs describe the CGMC I/O signals.

7.5.1 Crystal Amplifier Input Pin (OSC1)

The OSC1 pin is an input to the crystal oscill ator amplifier.

7.5.2 Crystal Amplifier Output Pin (OSC2)

The OSC2 pin is the output of the crystal oscillator inverting amplifier.

7.5.3 External Filter Capaci tor Pin (CGMX FC)

The CGMXFC pin is required by the loop filter to filter out phase

corrections. An external filter network is connected to this pin. (See

Figure 7-2.)

NOTE: To prevent noise pr oblems, the filter network shou ld be placed as close

to the CGMXFC pin as possible, with minimum routing distan ces and no

routing of other signals across the ne twork.

7.5.4 PLL Analog Power Pin (VDDA)

VDDA is a power pin used by the analog portions of the PLL. Connect the

VDDA pin to the s ame voltage potential as the VDD pin.

NOTE: Route VDDA carefully for ma ximum noise immu nity and place bypass

capacitors as close as possible to the package.

7.5.5 PLL Analog Ground Pin (VSSA)

VSSA is a ground pin used by the analog port ions of the PLL. Connect

the VSSA pin to the same voltage potential as the VSS pin.

NOTE: Route VSSA carefully for maximum noise immunity and place bypass

capacitors as close as possible to the package.

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Clock Generator Module (CGMC)

I/O Signals

MC68HC908GR8 — Rev 4.0 Technical Data

MOTOROLA Clock Generator Module (CGMC) 113

7.5.6 Oscillator Enable Signal (SIMOSCEN)

The SIMOSCEN signal comes from the system integration module (SIM)

and enables the oscillator and PLL.

7.5.7 Oscillator Stop Mode Enable Bit (OSCSTOPENB)

OSCSTOPENB is a bit in the CONFIG register that enables the oscillator

to continue operating during stop mode. If this bit is set, the Oscillator

continues running during stop mode. If this bit is not set (default), the

oscillator is con trolled by the SIMOSCEN signa l which will disable the

oscillator during stop mode.

7.5.8 Crystal Output Frequency Signal (CGMXCLK)

CGMXCLK is the crystal oscillator output signal. It runs at the full speed

of the crystal (fXCLK) and comes directly from the crystal oscillator circuit.

Figure 7-2 shows only the logical relati on of CGMXCLK to OSC1 and

OSC2 and may not represent the actual circuitry. The duty cycle of

CGMXCLK is unkno w n and ma y depend on the cryst al and other

external factors. Also, the frequency and amplitude of CGMXCLK can be

unstable at startup.

7.5.9 CGMC Base Clock Output (CGMOUT)

CGMOUT i s the clock o utput of the CGMC. This si gnal goes to the SIM,

which generates the MCU clocks. CGMOUT is a 50 percent duty cycle

clock running at twice the bus frequency. CGMOUT is software

prog rammable to be either the oscillator output, CGMXCLK, di vided by

two or the VCO clock, CGMVCL K, divided by two.

7.5.10 CGMC CPU Interrupt (CGMINT)

CGMINT is the interrupt signal generated by the PLL lock detector.

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Clock Generator Module (CGMC)

Technical Data MC68HC908GR8 — Rev 4.0

114 Clock Generator Module (CGMC) MOTOROLA

7.6 CGMC Registers

These registers control and monitor operation of the CGMC:

•PLL control register (PCTL)

(See PLL Control Register .)

•PLL bandwidth control register (PBWC)

(See PLL Bandwid th Control Regi ster.)

•PLL multiplier select register high (PMSH)

(See PLL Multiplier Select Register High.)

•PLL multiplier select register low (PMSL)

(See PLL Multiplier Select Register Low.)

•PLL VCO range select register (PMRS)

(See PLL VCO Range Select Register.)

•PLL re ference divider select register (PMDS)

(See PLL Reference Divider Select Register.)

Figure 7-3 is a summary of the CGMC re gisters.

Addr.Register Name Bit 7654321Bit 0

$0036 PLL Control Register

(PCTL)

Read: PLLIE PLLF PLLON BCS PRE1 PRE0 VPR1 VPR0

Write:

Reset:00100000

$0037 PLL Bandwidth Control

Read: AUTO LOCK ACQ 0000R

Write:

Reset:00000000

$0038 PLL Multiplier Select High

MUL11 MUL10 MUL9 MUL8

Write:

Reset:00000000

$0039 PLL Multiplier Select Low

Read: MUL7 MUL6 MUL5 MUL4 MUL3 MUL2 MUL1 MUL0

Write:

Reset:01000000

Figure 7-3. CGMC I/O Register Summar y

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Clock Generator Module (CGMC)

CGMC Registers

MC68HC908GR8 — Rev 4.0 Technical Data

MOTOROLA Clock Generator Module (CGMC) 115

7.6.1 PLL Control Register

The PLL control register (PCTL) contains the interrupt enable and flag

bits, t he on/off swi tch, the ba se clock selecto r bit, the prescaler bits , and

the VCO power-of-two range selector bits.

PLLIE — PLL Interrupt Enable Bit

This read/write bit enables the PLL to generate an interrupt request

when the LOCK bit toggles, setti ng the PLL flag, PLLF. When the

AUTO bit in the PLL bandwidth control register (PBWC) is clear,

PLLIE cannot be written and reads as logic 0. Reset clears the PLLIE

bit.

$003A PLL VCO Select Range

Read: VRS7 VRS6 VRS5 VRS4 VRS3 VRS2 VRS1 VRS0

Write:

Reset:01000000

$003B PLL Reference Divider

Select Register (PMDS)

RDS3 RDS2 RDS1 RDS0

Write:

Reset:00000001

= Unimplemented R = Reserved

NOTES:

1. When AUTO = 0, PLLIE is forced clear and is read-only.

2. When AUTO = 0, PLLF and LOCK read as clear.

3. When AUTO = 1, ACQ is read-only.

4. When PLLON = 0 or VRS7:VRS0 = $0, BCS is forced clear and is read-only.

5. When PLLON = 1, the PLL programming register is read-only.

6. When BCS = 1, PLLON is forced set and is read-only.

Figure 7-3. CGMC I/O Register Summar y

Address: $0036

Bit 7654321Bit 0

Read: PLLIE PLLF PLLON BCS PRE1 PRE0 VPR1 VPR0

Write:

Reset:00100000

= Unimplemented

Figure 7-4. PLL Control Register (PCTL)

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116 Clock Generator Module (CGMC) MOTOROLA

1 = PLL interrupts enabled

0 = PLL interrupts disabled

PLLF — PLL Interrupt Flag Bit

This r ead-only bit is set whenever the LOCK bit to ggles. PLLF

generates an interrupt request if the PLLIE bit also is set. PLLF

always reads as logic 0 when the AUTO bit in the PLL bandwidth

control register (PBWC) is clear. Clear the PLLF bit by reading the

PLL control register. Reset clears the PLLF bit.

1 = Change in lock condition

0 = No change in lock condition

NOTE: Do not inadv erten tly cl ear the PLLF bit. Any read or re ad-modify-w rite

operation on the PLL control register clears the PLLF bit.

PLLON — PLL On Bi t

This read/write bit activates the PLL and enables the VCO clock,

CGMVCL K. PLLON canno t be cleared if th e VCO clock is driv ing the

base clock, CGMOUT (BCS = 1). (See Base Clock Selector Circuit.)

Reset sets this bit so that the loop can stabilize as the MCU is

powering up.

1 = PL L on

0 = PL L off

BCS — Base Clock Select Bit

This read/write bit selects either the crystal oscillator output,

CGMXCLK, or the VCO clock, CGMVCLK, as the source of the

CGMC output, CGMOUT. CGMOUT frequency is one- half the

freque ncy of the selec ted clock. BCS cannot be set while the PLL ON

bit is clear. After toggling BCS, it may take up to three CGMXCLK and

three CGMVCLK cycles to complete the transition from one source

clock to the other. Du ri n g the tr ansit io n, CGMOUT is held in stasis .

(See Base Clock Selector Circuit.) Reset clears the BCS bi t.

1 = CGMVCLK divided by two drives CGMOUT

0 = CGMXCLK divided by two drives CGMOUT

NOTE: PLLON and BCS have built-in protection that prevents the base clock

selector circuit from selecting the VCO clock as the source of the base

clock if the PLL is off. Therefore, PLLON cannot be cleared when BCS

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Clock Generator Module (CGMC)

CGMC Registers

MC68HC908GR8 — Rev 4.0 Technical Data

MOTOROLA Clock Generator Module (CGMC) 117

is set, and BCS cannot be set when PLLON is clear. If the PLL is off

(PLLON = 0), selecting CGMVCLK requires two writes to the PLL control

PRE1 and P RE0 — Prescaler Pr ogram Bits

These read/write bits control a prescaler that selects the prescaler

power-of-two multiplier, P. (See PLL Circ u it s and Programmin g the

PLL. ) P RE1 and PRE0 canno t be wr i tte n when the PLLON b it is se t.

Reset clears these bits.

NOTE: The value of P is normally 0 when using a 32.768-kHz crystal as the

reference.

VPR1 and 0 — VCO Power-of-Two Range Select Bits

These read/write bits control the VCO’s hardware power-of-two range

multiplier E that, in conjunction with L (See PLL Circui ts,

Programming the PLL, and PLL VCO Range Select Register.)

controls the hardware center-of-range frequency, fVRS. VPR1:VPR0

cannot be w ritt en wh en the PLL ON bi t i s set . R eset cle ar s th ese b i ts.

Table 7-2. PRE 1 and PRE0 Programming

PRE1 and PRE0 P Prescaler Multiplier

00 0 1

01 1 2

10 2 4

11 3 8

Table 7-3. VPR1 and VPR0 Programming

VPR1 and VPR0 E VCO Power-of-Two

Range Multiplier

00 0 1

01 1 2

10 2 4

11 3(1)

1. Do not program E to a value of 3.

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Technical Data MC68HC908GR8 — Rev 4.0

118 Clock Generator Module (CGMC) MOTOROLA

7.6.2 PLL Bandwidth Cont rol Regist er

The PLL bandwidth control register (PBWC):

•Selects automatic or ma nual (software-controlled) bandwidth

control mode

•Indicates when the PLL is locked

•In automatic bandwidth control mode, indicates when the PLL is in

acquisition or tracking mode

•In manual operation, forces the PLL into acquisition or tracking

mode

AUTO — Automatic Bandwidth Control Bit

This read/write bit selects automatic or manual bandwidth control.

When i nit ial iz i ng th e PL L for manu al operation ( A UTO = 0), clear t he

ACQ bit before turning on the PLL. Reset clears the AUTO bit.

1 = Automatic ban dw idth control

0 = Manual bandwidth control

LOCK — Lock Indicator Bit

When the AUTO bit is set, LOCK is a read-only bit that becomes set

when th e VCO clock, CGMVCLK, is locked (runn i ng at the

programmed frequency). When the AUTO bit is clear, LOCK reads as

logic 0 and has no meanin g. The write one function of this bit is

reserved fo r test, so this bit must always be written a 0. Reset clears

the LOCK bit.

Address: $0037

Bit 7654321Bit 0

Read: AUTO LOCK ACQ 0000R

Write:

Reset:00000000

= Unimplemented R= Reserved

Figure 7-5. PLL Bandwidth Control Register (PBWC)

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Clock Generator Module (CGMC)

CGMC Registers

MC68HC908GR8 — Rev 4.0 Technical Data

MOTOROLA Clock Generator Module (CGMC) 119

1 = VCO frequency correct or locked

0 = VCO frequency incorrect or unlocked

ACQ — Acquisition Mo de Bit

When the AUTO bit is set, ACQ is a read-only bit that indicates

whethe r the PLL is in acquisition mode or tracking mode. When the

AUTO bit is clear, ACQ is a read/write bit that controls whether the

PLL is in ac quisi ti o n or tracki ng mode .

In automatic bandwidth control mode (AUTO = 1), the last-written

value from manual operation is stored in a temporary location and is

recovered when manual operation resumes. Reset clears this bit,

enabl i ng acqu i si t ion mode.

1 = Tracking mo de

0 = Acquis it ion mode

7.6.3 PLL Multiplier Select Register High

The PLL multiplier select register high (PMSH) contains the

programming information for the high byte of the modulo feedback

divider.

MUL11–MUL8 — Multiplier Select Bits

These read/write bits control the high byte of the modulo feedback

divider that selects the VCO frequency multiplier N. (See PLL Circuits

and Programming the PLL.) A value of $0000 in the multiplier select

registers configures the modulo feedback divider the same as a value

of $00 01. Reset initializes th e register s to $0040 for a default mul tiply

value of 64.

Address: $0038

Bit 7654321Bit 0

MUL11 MUL10 MUL9 MUL8

Write:

Reset:00000000

= Unimplemented

Figure 7-6. PLL Multiplier Select Register High (PMSH)

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Clock Generator Module (CGMC)

Technical Data MC68HC908GR8 — Rev 4.0

120 Clock Generator Module (CGMC) MOTOROLA

NOTE: The multiplier select bits have built-in protection such that they cannot

be writt en when the PLL is on (P LLON = 1).

PMSH[7:4] — Unimplemented Bits

These bits have no function and always read as logic 0s.

7.6.4 PLL Multiplier Sele ct Register Low

The PLL multiplier select register low (PMSL) contains the programming

information for the low byte of the modulo feedback divider.

MUL7–MUL0 — Multiplier Select Bits

These read/write bits control the low byte of the modulo feedback

divider that selects the VCO frequency multiplier, N. (See PLL Circuits

and Programming the PLL.) MUL7–MUL0 cannot be written when the

PLLON bit in the PCTL is set. A value of $0000 in the multiplier select

registers configures the modulo feedback divider the same as a value

of $0001. Reset initializes the register to $40 for a default multiply

value of 64.

NOTE: The multiplier select bits have built-in protection such that they cannot

be writt en when the PLL is on (P LLON = 1).

Address: $0038

Bit 7654321Bit 0

Read: MUL7 MUL6 MUL5 MUL4 MUL3 MUL2 MUL1 MUL0

Write:

Reset:01000000

Figure 7-7. PLL Multiplier Select Register Low (PMSL)

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Clock Generator Module (CGMC)

CGMC Registers

MC68HC908GR8 — Rev 4.0 Technical Data

MOTOROLA Clock Generator Module (CGMC) 121

7.6.5 PLL VCO Range Select Register

NOTE: PMRS may be called PVRS on other HC08 derivatives.

The PLL VCO range select register (PMRS) cont ains the prog ramming

information required for the hardware configuration of the VCO.

VRS7–VRS0 — VCO Range Se lect Bits

These r ead/wr ite bits control the hardware center-of-range lin ear

multiplier L which, in conjunction with E (see PLL Circ ui ts,

Programming the PLL, and PLL Cont rol Register), cont ro ls the

hardware center-of-range frequency, fVRS. VRS7–VRS0 cann ot be

written when the PLLON bit in the PCTL is set. (See Special

Programming Exceptions.) A value of $00 in the VCO range select

regist er di sables the PLL and clear s the BCS bit in t he PLL control

Programming Exceptions.). Reset initializes the register to $40 for a

default range multiply value of 64.

NOTE: The VCO range select bits ha ve built-in protect ion such that they cannot

be written when the PLL is on (PLLON = 1) and such that the VCO clock

cannot be selected as the source of the base clock (BCS = 1) if the VCO

range select bits are all clear.

The PLL VCO range select register must be programmed correctly.

Incorrect programming can result in failure of the PLL to achieve lock.

Address: $003A

Bit 7654321Bit 0

Read: VRS7 VRS6 VRS5 VRS4 VRS3 VRS2 VRS1 VRS0

Write:

Reset:01000000

Figure 7-8. PLL VCO Ran ge Select Regist er (PMRS)

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Clock Generator Module (CGMC)

Technical Data MC68HC908GR8 — Rev 4.0

122 Clock Generator Module (CGMC) MOTOROLA

7.6.6 PLL Reference Divider Select Register

NOTE: PMDS may be called PRDS on other HC08 derivatives.

The PLL refer e nce di vi de r sel ect re gi ste r (P MD S ) cont ai ns the

programming information for the modulo reference divider.

RDS3–RDS0 — Reference Divider Select Bits

These read/write bits control the modulo reference divider that selects

the reference division factor, R. (See PLL Circuits and Programm ing

the PLL.) RDS7–RDS0 cannot be written when the PLLON bit in the

PCTL is set. A value o f $00 in the reference divider select register

configures the reference divider the same as a value of $01. (See

Specia l Pr ogramming Except ions.) Reset initializes the register to

$01 for a default divide value of 1.

NOTE: The refere nce divider s elect bits h ave built-in protecti on such that they

cannot be written when the PLL is on (PLLON = 1).

NOTE: The default divide value o f 1 is recommended for all applica tions.

PMDS7–PMDS4 — Unimplemented Bits

These bits have no function and always read as logic 0s.

Address: $003B

Bit 7654321Bit 0

RDS3 RDS2 RDS1 RDS0

Write:

Reset:00000001

= Unimplemented

Figure 7-9. PLL Reference Divider Select Register (PMDS)

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Clock Generator Module (CGMC)

Interrupts

MC68HC908GR8 — Rev 4.0 Technical Data

MOTOROLA Clock Generator Module (CGMC) 123

7.7 Interrupts

When the AUTO bit is set in the PLL bandwidth control register (PBWC),

the PLL can generate a CPU interrupt request every time the LOCK bit

changes state. The PLLIE bit in the PLL control register (PCTL ) enables

CPU interrupts from the PLL. PLLF, the interrupt flag in the PCTL,

become s set whether interrup ts are en abled or n ot. When t he AUTO bit

is clear, CPU interrupts from the PLL are disabled and PLLF reads as

logic 0.

Software should read the LOCK bit after a PLL interrupt request to see

if the request was due to an entry into lock or an exit from lock. When the

PLL enters lock, the VCO clock, CGMVCLK, divided by two can be

selected as the CGMOUT source by setting BCS in the PCTL. When the

PLL exits lock, the VCO clock frequency is corrupt, and appropriate

precautions should be taken. If the application is not frequency sensitive,

interrupts should be disabled to prevent PLL interrupt service routines

from impeding software performance or from exceeding stack

limitations.

NOTE: Software can select the CGMVCLK divided by two as the CGMOUT

source even if the PLL is not locked (LOCK = 0). Therefore, software

should make sure the PLL is locked before setting the BCS bit.

7.8 Special Modes

The WAIT in str ucti o n p uts the M C U i n l o w pow e r-co nsu mption standby

modes.

7.8.1 Wait Mode

The WAIT instruction does not affect the CGMC. Before entering wait

mode, software can disengage and turn off the PLL by clearing the BCS

and PLLON bits in the PL L cont rol reg ister (PCT L) to save pow er. Less

power-s ensi tive applications can disengage the PLL without turning it

off, so that the PLL clock is immediately available at WAIT exit. This

would be the case also when the PLL is to wake the MCU from wait

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Clock Generator Module (CGMC)

Technical Data MC68HC908GR8 — Rev 4.0

124 Clock Generator Module (CGMC) MOTOROLA

mode, such as when the PLL is first enabled and waiting for LOCK or

LOCK is lost.

7.8.2 Stop Mode

If the OSCSTOPENB bit in the CONFIG register is cleared (default),

then the STOP instruction disables the CGMC (oscillator and phase

locked loop) and holds low all CGMC outputs (CGMXCLK, CGMOUT,

and CGMINT).

If the STOP instruction is executed with the VCO clock, CGMVCLK,

divided by two driving C GM OU T, th e P LL automatica lly clears the B CS

bit in the PLL control register (PCTL), thereby selecting the crystal clock,

CGMXCL K, d ivid ed by two as the source of CGM OUT . W he n t he MC U

recovers from STOP, the crystal clock divided by two drives CGMOUT

and BCS remains clear.

If the OSCSTOPENB bit in the CONFIG register is set, then the phase

locked loop is shut off but the oscilla tor will continue to operate in stop

mode.

7.8.3 CGMC During Break Interrupts

The system integration module (SIM) controls whether status bits in

other modules can be cleared during the break state. The BCFE bit in

the SIM brea k flag control register (SBFCR) enables software to clear

status bits during the break state. (See SIM Break Flag Control

To allow software to clear status bits during a break interrupt, write a

logic 1 to the BCFE bit. If a status bit is cleared during the break state, it

remains cleared when the MCU exits the break state.

To protect the PLLF bit during the break state, write a logic 0 to the BCFE

bit. Wi t h BC FE a t l og ic 0 ( it s default state) , soft ware can read an d w r it e

the PLL control register during the break state without affecting the PLLF

bit.

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Clock Generator Module (CGMC)

Acquisition/Lock Time Specifications

MC68HC908GR8 — Rev 4.0 Technical Data

MOTOROLA Clock Generator Module (CGMC) 125

7.9 Acquisition/Lock Time Specifications

The acqu isiti on a nd lock times o f the PLL are, i n many ap plicati ons, the

most cri ti ca l PLL de si gn pa ra meters. Prope r design and use of the PL L

ensures the highest stability an d lowest acquisition/lock times.

7.9.1 Acquisition/Lock Time Definitions

Typical control systems refer to the acquisition time or lock time as the

reaction time, within specif ied tole rance s, of th e system to a ste p inp ut.

In a PLL, the step input occurs when the PLL is turned on or when it

suffers a no ise hit. The toler ance is usuall y specified as a per centage of

the step input or when the output settles to the de sired value plus or

minus a percentage of the frequency change. Therefore, the reaction

time is constant in this definition, regardless of the size of the step input.

For example, consider a system with a 5 percent acquisition time

tolerance. If a command instructs the system to change from 0 Hz to

1 MHz, the acquisition time is the time taken for the frequency to reach

1MHz±50 kHz. Fifty kHz = 5% of the 1-MHz step input. If the system is

operating at 1 MHz and suffers a –100-kHz noise hit, the acquisition time

is the time taken to return from 900 kHz to 1 MHz ±5 kHz. Five kHz = 5%

of the 100-kHz step input.

Other systems refer to acquisition and lock times as the time the system

takes to reduce the error between the actual output and the desired

output to within specifie d tolerances. Therefore, the acquisition or lo ck

time varies according to the original error in the output. Minor errors may

not even be registered. Typical PLL applications prefer to use this

definition because the system requires the output frequency to be within

a certain tolerance of the desired frequency regardless of the size of the

initial error.

7.9.2 Parametric Influences on Reaction Time

Acquisi tion and lock time s are designed to be as short as p ossible while

still providing the highest possible stability. These reaction times are not

constant, however. Many factors directly and indirectly affect the

acquisition time.

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Clock Generator Module (CGMC)

Technical Data MC68HC908GR8 — Rev 4.0

126 Clock Generator Module (CGMC) MOTOROLA

The most critical parameter which affects the reaction times of the PLL

is the reference frequency, fRDV. This frequency is the input to the phase

detector and controls how often the PLL makes corrections. For stability,

the corrections must be small compared to the de sired freque ncy, so

several corrections are required to reduce the frequency error.

Therefor e, the slower the reference the longer it takes to make these

corrections. This parameter is under user control via the choice of crystal

freque ncy fXCLK and the R value programm ed in the reference divider.

(See PLL Ci rcuits, Programming the PLL, and PLL Reference Divider

Select Register.)

Another critical parameter is the external filter network. The PLL

modifies the voltage on the VCO by adding or subtracting charge from

capacitors in this network. Therefore, the rate at which the voltage

changes for a given frequency error (thus change in charge) is

proportional to the capacitance. The size of the capacitor also is related

to the stability of the PLL. If the capacitor is too small, the PLL cannot

make small enough adjustments to the voltage and the system cannot

lock. If the capacitor is too large, the PLL may not be able to adjust the

voltage in a reasonable time. (See Choosing a Filter.)

Also important is the operating voltage potential applied to VDDA. The

power supply potential alters the characteristics of the PLL. A fixed value

is best. Var iable supplie s, such as batte ries, ar e accepta ble if they vary

within a known ra nge at very s low speeds. Noise on the power sup ply is

not acceptable, because it causes small frequency errors which

continually change the acquisition time of the PLL.

Temperature and processing also can affect acquisition time because

the electrical characteristics of the PLL change. The part operates as

specified as long as thes e infl ue nces stay wi th in the speci f ie d lim i ts.

External factors, however, can cause drastic changes in the operation of

the PLL. These fact ors include noise injected into the P LL thro ugh the

filter capacitor, filter capaci tor leakage, stray im pedan ces on t he circuit

board, and even humidity or circuit board contamination.

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Clock Generator Module (CGMC)

Acquisition/Lock Time Specifications

MC68HC908GR8 — Rev 4.0 Technical Data

MOTOROLA Clock Generator Module (CGMC) 127

7.9.3 Choosing a Filter

As described in Parametric Influences on Reaction Time, the external

filter network is critical to th e stability and reaction ti me of the PLL. The

PLL is also dep en de nt on re fer en ce fre qu en cy and supp ly vol ta ge.

Either of th e fi lt er networks in Figure 7- 10 is re com m en ded when using

a 32.768-kHz reference crystal. In low-cost applications, where stability

and reaction time of the PLL is not critical, this filter network can be

replaced by a single capacitor.

Figure 7-10. PLL Filter

CGMXFC

10 k 0.01 µF

0.033 µF

VSSA

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Clock Generator Module (CGMC)

Technical Data MC68HC908GR8 — Rev 4.0

128 Clock Generator Module (CGMC) MOTOROLA

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MC68HC908GR8 — Rev 4.0 Technical Data

MOTOROLA Configuration Register (CONFIG) 129

Technical Data — MC68HC908GR8

Section 8. Configuration Register (CONFIG)

8.1 Contents

8.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129

8.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129

8.2 Introduction

This section describes the configuratio n regis ters, CONFIG1 and

CONFIG2. The configuration registers enable or disable th ese options:

•Stop mode recovery time (32 CGMXCLK cycles or 4096

CGMXCLK cycles)

•COP timeout period (218 – 24 or 213 – 24 CGMXCLK cycles)

•STOP instruction

•Computer operating properly module (COP)

•Low- volt ag e in hi bit (LVI) module contr ol and vol tage trip point

selection

•Enable/disable the oscillator (OSC) during stop mode

8.3 Functional Description

The configuration registers are used in the initialization of various

options. The configuration registers can be written once after each reset.

All of the configuration register bits are cleared during reset. Since the

vario us options aff ect the ope ration of th e MCU, it i s recommen ded that

these registers be written im mediately after reset. The configuration

registers are located at $001E and $001F. The configuration register

may be read at anyti me.

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Configuration Register (CONF IG)

Technical Data MC68HC908GR8 — Rev 4.0

130 Configuration Register (CONFIG) MOTOROLA

NOTE: To ens ure correct operation of the MCU under all operating conditions,

the us er must wr ite d ata $1 C to add ress $0 033 im mediat ely af ter r eset.

This i s to ens ure proper te rmination of an unused m odule within the

MCU.

NOTE: On a FLASH device, the options except LVI5OR3 are one-time writeable

by the user after each reset. The LVI5OR3 bit is one-time writeable by

the user only after each POR (power-on reset). The CONFIG registers

are not in the FLASH memory but are special registers cont aining one-

time writeable latches after each reset. Upon a reset, the CONFIG

registers default to predetermined settings as shown in Figu re 8-1 and

Figure 8-2.

Address: $001E

Bit 7654321Bit 0

Read: 000000OSC-

STOPEN

SCIBD-

SRC

Write:

Reset:00000000

= Unimplemented

Figure 8-1. Configuration Register 2 (CONFIG2)

Address: $001F

Bit 7654321Bit 0

Read: COPRS LVISTOP LVIRSTD LVIP-

WRD LVI5OR3 SSREC STOP COPD

Write:

Reset:0000See Note000

Note: LVI5OR3 bit is only reset via POR (power-on reset)

Figure 8-2. Configuration Register 1 (CONFIG1)

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Configuration Register (CONFIG)
Functional Description
MC68HC908GR8 — Rev 4.0 Technical Data
MOTOROLA Configuration Register (CONFIG) 131
 
OSCSTOPENB— Oscillator Stop Mode Enable Bar Bit
OSCSTOPENB enables the oscillator to continue operating during stop 
mode. Setting  t he OSCST OPEN B bit allows  th e o s c illa t or  to operate  
continuously even during stop mode. This is useful for driving the 
timebase mo du le to allow it to gene rate p eriodic wake up  wh ile in stop 
mode. (See Clock G enerator M odule (C G M) subsection St op  M o de .)
1 = Oscillator enabled to operate during stop mode
0 = Oscillator  disabl ed durin g stop mode (default)
SCIBDSRC — SCI Baud Rate Clock Source Bit
SCIBDSRC controls th e clock source used for the SCI.  The setting of 
this bit affects the frequency at which the SCI operates.
1 = Internal data bus clock used as clock source for SCI
0 = External oscil lator used as clock source for SCI
COPRS — COP Rate Select Bit
COPRS selects the COP timeout period. Reset clears COPRS. See 
Computer Operating Properly (COP).
1 = COP timeout period = 2 13 – 24 CGMXCLK cycles
0 = COP timeout period = 2 18 – 24 CGMXCLK cycles
LVISTOP — LVI Enable in Stop Mode Bit
When the LVIPWRD bit is clear, setting the LVISTOP bit enables the 
LVI to operate during stop mode. Reset clears  LVISTOP. See Stop 
Mode.
1 = LVI enabled during stop mode
0 = LVI disabled during stop mode
LVIRSTD — LVI Reset Disable Bi t
LVIRSTD disables the reset signal from the LVI module. See Low-
Voltage Inhibit (LVI).
1 = LVI module resets disabled
0 = LVI module  reset s enabled
LVIPWRD — LVI Power Disable Bit
LVIPWRD disables the LVI module. See Low-Voltage Inhibit (LVI).
1 = LVI module power disabled
0 = LVI module power enabled
    
  
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Configuration Register (CONF IG)

Technical Data MC68HC908GR8 — Rev 4.0

132 Configuration Register (CONFIG) MOTOROLA

LVI5OR3 — LVI 5V or 3V Operating Mode Bit

LVI5OR 3 selects th e voltage op erati ng mode of th e LVI mod ule. See

Low-Voltage I nhibit (LVI). The voltage mode selected for the LVI

should match th e operatin g VDD. See Electrical Sp ecifications fo r the

LVI’s voltage trip points for each of the modes.

1 = LVI operates in 5V mode.

0 = LVI operates in 3V mode.

SSREC — Short Stop Recovery Bit

SSREC enables the CPU to exit stop mode with a delay of 32

CGMXCLK cycles instead of a 4096-CGMXCLK cycle delay.

1 = Stop mode recovery after 32 CGMXCLK cycles

0 = Stop mode recovery after 4096 CGMXCLKC cycles

NOTE: Exiti ng stop mode by pulling reset will result in the long stop reco very.

If using an external crystal oscillator, do not set the SSREC bit.

NOTE: When the LVISTOP is enabled, the system stabilizatio n time for power

on reset and long stop recovery (both 4096 CGMXCLK cycles) gives a

delay longer than the ena ble ti m e fo r th e LVI. There i s no pe ri o d wh er e

the MCU is not protected from a low power condi tion. However, when

using the short stop recovery configuration option, the 32-CGMXCLK

delay is less than the LVI ’s turn-on time and there exists a period in

startup where the LVI is not protec ting the MCU.

STOP — STOP Instruction Enable Bit

STOP enables the STOP instruction.

1 = STOP in struction enabled

0 = STOP instruction treated as illegal opcode

COPD — COP Disable Bit

COPD d isable s the COP module . See Computer Operating Properly

(COP).

1 = COP mo dule disabled

0 = COP module enabled

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MC68HC908GR8 — Rev 4.0 Technical Data
MOTOROLA Computer Operating Properly (COP) 133
 
Technical Data — MC68HC908GR8
Section 9. Computer Operating Properly (COP)
9.1  Contents
9.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133
9.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133
9.4 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135
9.5 COP Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 36
9.6 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136
9.7 Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137
9.8 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 37
9.9 COP Module During Break Mode. . . . . . . . . . . . . . . . . . . . . .137
9.2  Introduction
The comp uter operating properly (COP) module contains a free-running 
counter that generates a reset if allowed to overflow. The COP module 
helps software recover from runaway code . Prevent a COP reset by 
clearing the COP counter periodically. The COP module can be disabled 
through the COPD bi t in the CONFIG register.
9.3  Functional Description
Figure 9-1 shows the structure of the COP module.
    
  
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Computer Operating Properly (COP)

Technical Data MC68HC908GR8 — Rev 4.0

134 Computer Operating Properly (COP) MOTOROLA

Figure 9-1. COP Block Dia gram

The COP counter is a free-running 6-bit counter preceded by a 12-bit

prescaler counter. If not cleared by software, the COP counter overflows

and gener a tes an asynch r ono us re set afte r 218 – 24 or 213 – 24

CGMXCLK cycles, depending on the state of the COP rate select bit,

COPRS, in the c onfiguration regi ster. Wit h a 213 – 24 CGMXCLK cycle

overflow option, a 32.768-kH z crystal gives a COP t i meout period o f

250 ms. Writing any value to location $FFFF before an overflow occurs

prevents a COP reset by clearing the COP counter and stages 12

through 5 of the prescaler.

NOTE: Service the COP immediately after reset and before entering or after

exiting sto p mo de to guaran tee the maximum time befo re the first COP

counter overflow.

A COP reset pulls the RST pin low for 32 CGMXCLK cycles and sets the

COP bit in the reset status register (RSR).

COPCTL WRITE

CGMXCLK

RESET VEC T OR F ETCH

RESET CIRCUIT

RESET ST AT U S REGIST ER

INTER NAL RESET SO URCES

CLEAR STAGES 5–12

12-BIT COP PRESCALER

CLEAR ALL STAGES

6-BIT COP COUNTER

COP DISABLE

RESET

COPCTL WRITE CLEAR

COP MODULE

COPEN (FROM SIM)

COP COUNTER

COP CLOCK

COP TIMEOUT

STOP INSTRUCTION

(FROM CONFIG)

COP RATE SEL

(FROM CONFIG)

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Computer Operating Properly (COP)

I/O Signals

MC68HC908GR8 — Rev 4.0 Technical Data

MOTOROLA Computer Operating Properly (COP) 135

In monitor mod e, the COP is disab led if th e RST pin or th e IRQ1 is he ld

at VTST. During th e break state , VTST on the RST pin disab les the COP.

NOTE: Pl ace COP c leari ng instructio ns in the main program an d not in an

interrupt subroutine. Such an interrupt subroutine could keep the COP

from generating a reset even while the main program is not working

properly.

9.4 I/O Signals

The following paragraphs describe the signals shown in Figure 9-1.

9.4.1 CGMXCLK

CGMXCLK is the crystal oscillator output sig nal. CGMXCLK frequency

is equa l to the crystal frequency.

9.4.2 STOP Instruction

The STOP instruction clears the COP prescaler.

9.4.3 COPCTL Write

Writing any value to the COP control register (COPCTL) (see COP

Control Register) clears the COP counter and clears bits 12 through 5 of

the prescal er. Reading the COP control register returns the low byte of

the reset vector.

9.4.4 Power-On Reset

The power-on reset (POR) circuit clears the COP prescaler 4096

CGMXCLK cycles afte r power-up.

9.4.5 Internal Reset

An internal reset clears the COP prescaler and the COP counter.

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Computer Operating Properly (COP)

Technical Data MC68HC908GR8 — Rev 4.0

136 Computer Operating Properly (COP) MOTOROLA

9.4.6 Reset Vector Fetch

A reset vector fetch occurs when the vector address appears on the data

bus. A reset vector fetch clears the COP pr escaler.

9.4.7 COPD (COP Disable)

The COPD signal reflects the state of the COP disable bit (COPD) in the

configuration register. See C onf i gur a ti on Re gi ste r (CO NFIG ) .

9.4.8 COPRS (COP Rate Select)

The COPRS signal reflects the state of the COP rate select bit (COPRS)

in the configuratio n register. S ee Configuration Register (CONFIG).

9.5 COP Control Register

The COP co ntro l re giste r is loca ted at addr ess $FFFF a nd ove rlaps th e

reset vector. Writing any value to $FFFF clears the COP counter and

starts a new timeout period. Reading location $FFFF returns the low

byte of the reset vector.

9.6 Interrupts

The COP does not generate CPU interrupt requests.

Address: $FFFF

Bit 7654321Bit 0

Read: Low byte of reset vector

Write: Clear COP counter

Reset: Unaf f ec ted by res et

Figure 9-2. COP Control Register (COPCTL)

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Computer Operating Properly (COP)

Monitor Mode

MC68HC908GR8 — Rev 4.0 Technical Data

MOTOROLA Computer Operating Properly (COP) 137

9.7 Monitor Mode

When monitor mode is entered with VTST on th e IRQ pin, the COP is

disabled as long as VTST remains on the IRQ pin or the RST pi n. Whe n

monitor mode is entered by having blank reset vectors and not having

VTST on the IRQ pin, the COP is autom atic a l ly di sab led until a POR

occurs.

9.8 Low-Power Modes

The WAIT and STOP instructions put the MCU in low power-

consumptio n standby mode s.

9.8.1 Wait Mode

The COP remains active during wait mode. To prevent a COP reset

during wait mode, periodically clear the COP counter in a CPU interrupt

routine.

9.8.2 Stop Mode

Stop mode turns off the CGMXCLK input to the COP and clears the COP

prescaler . Ser v ic e the C OP i mmed i ate ly be for e en ter i ng or a fte r exi ti ng

stop m ode to ensure a full CO P timeout period afte r entering or exiting

stop mode.

To prevent inadvertently turning off the COP with a STOP instruction, a

configuration option is available that disables the STOP instruction.

When the STOP bit in the configuration register has the STOP

instruction disabled, execution of a STOP instruction results in an illegal

opcode reset.

9.9 COP Module During Break Mode

The COP is disabled during a break interrupt when V TST is present on

the RST pin.

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Computer Operating Properly (COP)

Technical Data MC68HC908GR8 — Rev 4.0

138 Computer Operating Properly (COP) MOTOROLA

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MC68HC908GR8 — Rev 4.0 Technical Data
MOTOROLA Central Processing Unit (CPU) 139
 
Technical Data — MC68HC908GR8
Section 10. Central Processing Unit (CPU)
10.1  Contents
10.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139
10.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 39
10.4 CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140
10.5 Arithmetic/logic unit (ALU) . . . . . . . . . . . . . . . . . . . . . . . . . . .145
10.6 Low-power modes  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145
10.7 CPU during break interrupts. . . . . . . . . . . . . . . . . . . . . . . . . .146
10.8 Instruction Set Summary  . . . . . . . . . . . . . . . . . . . . . . . . . . . .147
10.9 Opcode Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 54
10.2  Introduction
The M68HC08 CPU ( central proces sor unit) is an enhanced  and fully 
object-code-com patible version of the M68HC05 CPU. The CPU08 
Reference Manual (Motorola document order numb er CPU08RM/AD) 
contains a description of the CPU instruction set, addressing modes, 
and archi te ctur e .
10.3  Features
•Object code fully upward-compatible with M68HC05 Family
•16-bit stack pointe r with stack manipulation instructions
•16-bit index register wi th x-register manipulation instructions
•8-MHz CPU internal bus frequency
    
  
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Central Processing Unit (CPU)

Technical Data MC68HC908GR8 — Rev 4.0

140 Central Processing Unit (CPU) MOTOROLA

•64K byte prog r am/data memory space

•16 address ing m odes

•Memory-to-memory data moves witho ut using accumulator

•Fast 8-bit by 8-bit multiply and 16-bit by 8-bit divide instructions

•Enhanced binary-coded decimal (BCD) data handling

•Modular architecture with expandable internal bus definiti on for

extension of addressing range beyond 64K bytes

•Low-power stop and wait modes

10.4 CPU registers

Figure 10-1 shows the five CPU regist ers. CPU registe rs are not part of

the memory map.

Figure 10-1. CPU registers

ACCUMULATOR (A)

INDEX REGISTER (H:X)

STAC K PO INTER (SP)

PROGRAM COUNTER (PC)

CONDITION CODE REGISTER (CCR)

CARRY/BORROW FLAG

ZERO FLAG

NEGATIVE FLAG

INTERRUPT MASK

HALF-CARRY FLAG

TWO’S COMPLEMENT OVERFLOW FLAG

V11HINZC

H X

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Central Processing Unit (CPU)

CPU registers

MC68HC908GR8 — Rev 4.0 Technical Data

MOTOROLA Central Processing Unit (CPU) 141

10.4.1 Accumulator (A)

The accumu lato r is a ge nera l-pur pose 8-bi t regist er. Th e CPU use s the

accumulator t o hold operands and the r es ults of arithme tic/log ic

operations.

10.4.2 Index register (H:X)

The 16-bit index register allows indexed addressing of a 64K byte

memory space. H is the upper byte of the index register and X is the

lower byte. H:X is the concatenated 16-bit index register.

In the indexed addressing modes, the CPU uses the contents of the

index register to determine the conditional address of the operand.

The index register can also be used as a temporary data storage

location.

Bit 7654321Bit 0

ARead:

Write:

Reset: Unaffected by reset

Figure 10-2. Accumulator (A)

Bit

151413121110987654321

Bit

H:X Read:

Write:

Reset:00000000XXXXXXXX

X = Indeterminate

Figure 10-3. Index register (H:X)

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Central Processing Unit (CPU)

Technical Data MC68HC908GR8 — Rev 4.0

142 Central Processing Unit (CPU) MOTOROLA

10.4.3 Stack pointer (SP)

The stack pointer is a 16-bit register that contains the address of the next

location on the stack. During a reset, the stack pointer is preset to

$00FF. The reset stack pointer (RSP) instruction sets the least

significant byte to $FF and does not affect t he most significant byte. The

stack pointer decrements as data is pushed onto the stack and

increments as data is pulled from the stack.

In the stack pointer 8-bit offset and 16-bit offset addressing mo des, the

stack pointer can function as an index register to access data on the

stack. The C PU u ses th e co ntents of the stack poi nte r to d ete rm ine th e

conditi onal addre ss of the op eran d.

NOTE: The location of t he st ack i s a rbit rar y and m ay be r eloca te d an yw he re in

RAM. Moving the SP out of page zero ($0000 to $00FF) frees direct

address (page zero) space. For correct operation, the stack pointer must

point only to RAM locat ions.

10.4.4 Program counter (PC)

The program counter is a 16-bit register that contains the address of the

next instruction or operand to be fetched.

Normally, the program counter automatically increments to the next

sequential memory location ev ery time an instructio n or operand is

fetched. Jump, branch, and interrupt operations load the program

counter with an address other than that of the next sequential location.

Bit

151413121110987654321

Bit

SP Read:

Write:

Reset:0000000011111111

Figure 10-4. Stack pointer (SP)

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Central Processing Unit (CPU)

CPU registers

MC68HC908GR8 — Rev 4.0 Technical Data

MOTOROLA Central Processing Unit (CPU) 143

During rese t, the pr og ram counter is load ed wit h the re set vecto r

address located at $FFFE and $FFFF. The vector address is the

address of the first instruction to be executed after exiting the reset state.

10.4.5 Condition code register (CCR)

The 8-bit condition code register contains the interr upt mask and five

flags that i ndicate the re sults o f the instruct ion ju st exec uted. Bit s 6 and

5 are set perman en tl y to ‘1’. The following paragraphs des cribe the

functions of the co ndition code register.

V — Overflow flag

The CPU sets the overflow flag when a two's complement overflow

occurs. The signed branch instructions BGT, BGE, BLE, and BLT use

the overflow flag.

1 = Overflow

0 = No ove r flow

H — Half- car ry fl ag

Bit

151413121110987654321

Bit

PC Read:

Write:

Reset: Loaded with vector from $FFFE and $FFFF

Figure 10-5. Program counter (PC)

Bit 7654321Bit 0

CCR Read: V11HINZC

Write:

Reset:X11X1XXX

X = Indeterminate

Figure 10-6. Condition code register (CCR)

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Technical Data MC68HC908GR8 — Rev 4.0

144 Central Processing Unit (CPU) MOTOROLA

The CPU sets the half-carry flag when a carr y occurs between

accumulator bi ts 3 and 4 during an ADD or ADC operation. The half-

carry flag is required for binary-coded decimal (BCD) arithmetic

opera tions . The DAA ins tructi on uses the sta tes of the H and C flags

to determine the appropriate corre ction factor.

1 = Carry between bits 3 and 4

0 = No carry between bits 3 and 4

I — Interrupt mask

When the interrupt mask is set, all maskable CPU interrupts are

disabled. CPU interrupts are enabled when the interrupt mask is

cleared. When a CPU interrupt occurs, the interrupt mask is set

automatically after the CPU registers are saved on the stack, but

before the interrupt vector is fetched.

1 = Interrupts disabled

0 = Interrupts enabled

NOTE: To maintain M6805 compatibility, the upper byte of the index register (H)

is not stacked automatically. If the interrupt service routine modifies H,

then the user must stack and unstack H using the PSHH and PULH

instructions.

After the I bit is cleared, the highest-priority interrupt request is

serviced first.

A return from interrupt (RTI) in struction pulls th e CPU registers from the

stack and restores the interrupt mask from the stack. After any reset, the

interrupt mask is set and can only be cleared by the clear interrupt mask

softwar e instr uct io n (C LI ).

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Central Processing Unit (CPU)

Arithmetic/logic unit (ALU)

MC68HC908GR8 — Rev 4.0 Technical Data

MOTOROLA Central Processing Unit (CPU) 145

N — Negative flag

The CPU sets the negative flag when an arithmetic operation, logic

operation, or data manipulation produces a negative result, setting bit

7 of the result.

1 = Negative result

0 = Non-negative result

Z — Zero flag

The CPU sets the zero flag when an arithm etic operation, logic

operation, or data manipulation produces a result of $00.

1 = Zero result

0 = Non-zero result

C — Carry/bo rrow flag

The CPU sets the carry/borrow flag when an addition operation

produces a carry out of bit 7 of the accumulator or when a subtraction

opera tion req uires a borrow. So me instruc tions - such as bit te st and

branch, shift, and rotate - also clear or set the carry/borrow flag.

1 = Carry out of bit 7

0 = No carry out of bit 7

10.5 Arithmetic/logic unit (ALU)

The ALU performs the arithmetic and logic operations defined by the

instruction set.

Refer to the CPU08 Reference Manual (Moto r ola doc ument number

CPU08RM/AD) for a description of the instructions and addressing

modes and more detail about CPU architec ture.

10.6 Low-power modes

The WAIT and STOP instructions put the MCU in low--p ower

consumptio n standby mode s.

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Central Processing Unit (CPU)

Technical Data MC68HC908GR8 — Rev 4.0

146 Central Processing Unit (CPU) MOTOROLA

10.6.1 WAIT mode

The WAIT instruction:

•clears the interrupt mask (I bit) in the condition code register,

enabling i nterrupts. After exit from WAIT mode by interrupt, the I

bit remains clear. After exit by reset, the I bit is set.

•Disables the CPU clock

10.6.2 STOP mode

The STOP instruction:

•clears the interrupt mask (I bit) in the condition code register,

enabling external interrupts. After exit from STOP mode by

external interrupt, the I bit remains clear. After exit by reset, the I

bit is set.

•Disables the CPU clock

After exiting STOP mode, the CPU clock begins running after the

oscillator stab ilization delay.

10.7 CPU during break interrupts

If the break module is enabled, a break interrupt causes the CPU to

execu te the softwa re inte rrupt instr uction ( SWI) at the com pletion of the

current CPU instruction. See Break Module (BRK). The program counter

vectors to $FFFC–$FFFD ($FEFC–$FEFD in moni tor mode).

A return-from-interrupt instruction (RTI) in the break routine ends the

break interrupt and r eturns the MCU to normal op eratio n if the break

interrupt has been deasserted.

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Central Processing Unit (CPU)

Instruction Set Summary

MC68HC908GR8 — Rev 4.0 Technical Data

MOTOROLA Central Processing Unit (CPU) 147

10.8 Instruction Set Summary

Table 10-1 provides a summary of the M68HC08 instruction set.

Table 10-1. Instruction Set Summary

Source

Form Operation Description

Effect on

CCR

Address

Mode

Opcode

Operand

Cycles

VHI NZC

ADC #opr

ADC opr

ADC opr,X

ADC ,X

ADC opr,SP

Add with Carry A ← (A) + (M) + (C) ↕↕–↕↕↕

IMM

DIR

EXT

IX2

IX1

SP1

SP2

9EE9

9ED9

hh ll

ee ff

ADD #opr

ADD opr

ADD opr,X

ADD ,X

ADD opr,SP

Add without Carry A ← (A) + (M) ↕↕–↕↕↕

IMM

DIR

EXT

IX2

IX1

SP1

SP2

9EEB

9EDB

hh ll

ee ff

AIS #opr Add Immediate Value (Signed) to SP SP ← (SP) + (16 « M) ––––––IMM A7 ii 2

AIX #opr Add Immediate V alue (Signed) to H:X H:X ← (H:X) + (16 « M) ––––––IMM AF ii 2

AND #opr

AND opr

AND opr,X

AND ,X

AND opr,SP

Logical AND A ← (A) & (M) 0 ––↕↕–

IMM

DIR

EXT

IX2

IX1

SP1

SP2

9EE4

9ED4

hh ll

ee ff

ASL opr

ASLA

ASLX

ASL opr,X

ASL ,X

ASL opr,SP

Arithmetic Shift Left

(Same as LSL) ↕––↕↕↕

DIR

INH

IX1

SP1

9E68

ASR opr

ASRA

ASRX

ASR opr,X

ASR opr,SP

Arithmetic Shift Right ↕––↕↕↕

DIR

INH

IX1

SP1

9E67

BCC rel Branch if Carry Bit Clear PC ← (PC) + 2 + rel ? (C) = 0 ––––––REL 24 rr 3

Cb0

b7 0

b7 C

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BCLR n, opr Clear Bit n in M Mn ← 0 ––––––

DIR (b0)

DIR (b1)

DIR (b2)

DIR (b3)

DIR (b4)

DIR (b5)

DIR (b6)

DIR (b7)

BCS rel Branch if Carry Bit Set (Same as BLO) PC ← (PC) + 2 + rel ? (C) = 1 ––––––REL 25 rr 3

BEQ rel Branch if Equal PC ← (PC) + 2 + rel ? (Z) = 1 ––––––REL 27 rr 3

BGE opr Branch if Greater Than or Equal To

(Signed Operands) PC ← (PC) + 2 + rel ? (N ⊕ V) = 0 ––––––REL 90 rr 3

BGT opr Branch if Greater Than (Signed

Operands) PC ← (PC) + 2 + rel ? (Z) | (N ⊕ V) = 0 ––––––REL 92 rr 3

BHCC rel Branch if Half Carry Bit Clear PC ← (PC) + 2 + rel ? (H) = 0 ––––––REL 28 rr 3

BHCS rel Branch if Half Carry Bit Set PC ← (PC) + 2 + rel ? (H) = 1 ––––––REL 29 rr 3

BHI rel Branch if Higher PC ← (PC) + 2 + rel ? (C) | (Z) = 0 ––––––REL 22 rr 3

BHS rel Branch if Higher or Same

(Same as BCC) PC ← (PC) + 2 + rel ? (C) = 0 ––––––REL 24 rr 3

BIH rel Branch if IRQ Pin High PC ← (PC) + 2 + rel ? IRQ = 1 ––––––REL 2F rr 3

BIL rel Branch if IRQ Pin Low PC ← (PC) + 2 + rel ? IRQ = 0 ––––––REL 2E rr 3

BIT #opr

BIT opr

BIT opr,X

BIT ,X

BIT opr,SP

Bit Test (A) & (M) 0 ––↕↕–

IMM

DIR

EXT

IX2

IX1

SP1

SP2

9EE5

9ED5

hh ll

ee ff

BLE opr Bran ch if Less Than or Equal To

(Signed Operands) PC ← (PC) + 2 + rel ? (Z) | (N ⊕ V) = 1 ––––––REL 93 rr 3

BLO rel Branch if Lower (Same as BCS) PC ← (PC) + 2 + rel ? (C) = 1 ––––––REL 25 rr 3

BLS rel Branch if Lower or Same PC ← (PC) + 2 + rel ? (C) | (Z) = 1 ––––––REL 23 rr 3

BLT opr Branch if Le ss Than (Signed Operands) PC ← (PC) + 2 + rel ? (N ⊕ V) =1––––––REL 91 rr 3

BMC rel Branch if Interrupt Mask Clear PC ← (PC) + 2 + rel ? (I) = 0 ––––––REL 2C rr 3

BMI rel Branch if Minus PC ← (PC) + 2 + rel ? (N) = 1 ––––––REL 2B rr 3

BMS rel Branch if Interrupt Mask Set PC ← (P C) + 2 + rel ? (I) = 1 ––––––REL 2D rr 3

Table 10-1. Instruction Set Summ ary (Continued)

Source

Form Operation Description

Effect on

CCR

Address

Mode

Opcode

Operand

Cycles

VHI NZC

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Central Processing Unit (CPU)

Instruction Set Summary

MC68HC908GR8 — Rev 4.0 Technical Data

MOTOROLA Central Processing Unit (CPU) 149

BNE rel Branch if Not Equal PC ← (PC) + 2 + rel ? (Z) = 0 ––––––REL 26 rr 3

BPL rel Branch if Plus PC ← (PC) + 2 + rel ? (N) = 0 ––––––REL 2A rr 3

BRA rel Branch Always PC ← (PC) + 2 + rel ––––––REL 20 rr 3

BRCLR n,opr,rel Branch if Bit n in M Clear PC ← (PC) + 3 + rel ? (Mn) = 0 –––––↕

DIR (b0)

DIR (b1)

DIR (b2)

DIR (b3)

DIR (b4)

DIR (b5)

DIR (b6)

DIR (b7)

dd rr

BRN rel Branch Never PC ← (PC) + 2 ––––––REL 21 rr 3

BRSET n,opr,rel Branch if Bit n in M Set PC ← (P C) + 3 + rel ? (Mn) = 1 –––––↕

DIR (b0)

DIR (b1)

DIR (b2)

DIR (b3)

DIR (b4)

DIR (b5)

DIR (b6)

DIR (b7)

dd rr

BSET n,opr Set Bit n in M Mn ← 1 ––––––

DIR (b0)

DIR (b1)

DIR (b2)

DIR (b3)

DIR (b4)

DIR (b5)

DIR (b6)

DIR (b7)

BSR rel Branch to Subroutine PC ← (PC) + 2; push (PCL)

SP ← (SP) – 1; push (PCH)

SP ← (SP) – 1

PC ← (PC) + rel ––––––REL AD rr 4

CBEQ opr,rel

CBEQA #opr,rel

CBEQX #opr,rel

CBEQ opr,X+,rel

CBEQ X+,rel

CBEQ opr,SP,rel

Compare and Branch if Equal

PC ← (PC) + 3 + rel ? (A) – (M) = $00

PC ← (PC) + 3 + rel ? (X) – (M) = $00

PC ← (PC) + 3 + rel ? (A) – (M) = $00

PC ← (PC) + 2 + rel ? (A) – (M) = $00

PC ← (PC) + 4 + rel ? (A) – (M) = $00

––––––

DIR

IMM

IX1+

IX+

SP1

9E61

dd rr

ii rr

ff rr

CLC Clear Carry Bi t C ← 0 –––––0INH 98 1

CLI Clear Interrupt Mask I ← 0 ––0–––INH 9A 2

CLR opr

CLRA

CLRX

CLRH

CLR opr,X

CLR ,X

CLR opr,SP

Clear

M ← $00

A ← $00

X ← $00

H ← $00

M ← $00

0––01–

DIR

INH

IX1

SP1

9E6F

Table 10-1. Instruction Set Summ ary (Continued)

Source

Form Operation Description

Effect on

CCR

Address

Mode

Opcode

Operand

Cycles

VHI NZC

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150 Central Processing Unit (CPU) MOTOROLA

CMP #opr

CMP opr

CMP opr,X

CMP ,X

CMP opr,SP

Compare A with M (A) – (M) ↕––↕↕↕

IMM

DIR

EXT

IX2

IX1

SP1

SP2

9EE1

9ED1

hh ll

ee ff

COM opr

COMA

COMX

COM opr,X

COM ,X

COM opr,SP

Complement (One’s Complement)

M ← (M) = $FF – (M)

A ← (A) = $FF – (M)

X ← (X) = $FF – (M)

M ← (M) = $FF – (M)

0––↕↕1

DIR

INH

IX1

SP1

9E63

CPH X #opr

CPHX opr Compare H:X with M (H:X) – (M:M + 1) ↕––↕↕↕

IMM

DIR 65

75 ii ii+1

dd 3

CPX #opr

CPX opr

CPX ,X

CPX opr,X

CPX opr,SP

Compare X with M (X) – (M) ↕––↕↕↕

IMM

DIR

EXT

IX2

IX1

SP1

SP2

9EE3

9ED3

hh ll

ee ff

DAA Decimal Adjust A (A)10 U––↕↕↕INH 72 2

DBNZ opr,rel

DBNZA rel

DBNZX rel

DBNZ opr,X,rel

DBN Z X,rel

DBNZ opr,SP,rel

Decrement and Branch if Not Zero

A ← (A) – 1 or M ← (M) – 1 or X ← (X) – 1

PC ← (PC) + 3 + rel ? (result) ≠ 0

PC ← (PC) + 2 + rel ? (result) ≠ 0

PC ← (PC) + 3 + rel ? (result) ≠ 0

PC ← (PC) + 2 + rel ? (result) ≠ 0

PC ← (PC) + 4 + rel ? (result) ≠ 0

––––––

DIR

INH

IX1

SP1

9E6B

dd rr

ff rr

DEC opr

DECA

DECX

DEC opr,X

DEC ,X

DEC opr,SP

Decrement

M ← (M) – 1

A ← (A) – 1

X ← (X) – 1

M ← (M) – 1

↕––↕↕–

DIR

INH

IX1

SP1

9E6A

DIV Divide A ← (H:A)/(X)

H ← Remainder ––––↕↕INH 52 7

EOR #opr

EOR opr

EOR opr,X

EOR ,X

EOR opr,SP

Exclusive OR M with A A ← (A ⊕ M) 0––↕↕–

IMM

DIR

EXT

IX2

IX1

SP1

SP2

9EE8

9ED8

hh ll

ee ff

Table 10-1. Instruction Set Summ ary (Continued)

Source

Form Operation Description

Effect on

CCR

Address

Mode

Opcode

Operand

Cycles

VHI NZC

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Central Processing Unit (CPU)

Instruction Set Summary

MC68HC908GR8 — Rev 4.0 Technical Data

MOTOROLA Central Processing Unit (CPU) 151

INC opr

INCA

INCX

INC opr,X

INC ,X

INC opr,SP

Increment

M ← (M) + 1

A ← (A) + 1

X ← (X) + 1

M ← (M) + 1

↕––↕↕–

DIR

INH

IX1

SP1

9E6C

JMP opr

JMP opr,X

JMP ,X

Jump PC ← Jump Address ––––––

DIR

EXT

IX2

IX1

hh ll

ee ff

JSR opr

JSR opr,X

JSR ,X

Jump to Subroutine PC ← (P C) + n (n = 1, 2, or 3)

Push (PC L ); SP ← (SP) – 1

Push (PCH); SP ← (SP) – 1

PC ← Unconditional Addr ess ––––––

DIR

EXT

IX2

IX1

hh ll

ee ff

LDA #opr

LDA opr

LDA opr,X

LDA ,X

LDA opr,SP

Load A from M A ← (M) 0 ––↕↕–

IMM

DIR

EXT

IX2

IX1

SP1

SP2

9EE6

9ED6

hh ll

ee ff

LDHX #opr

LDHX opr Load H:X from M H:X ← (M:M + 1)0––↕↕–IMM

DIR 45

55 ii jj

dd 3

LDX #opr

LDX opr

LDX opr,X

LDX ,X

LDX opr,SP

Load X from M X ← (M) 0 ––↕↕–

IMM

DIR

EXT

IX2

IX1

SP1

SP2

9EEE

9EDE

hh ll

ee ff

LSL opr

LSLA

LSLX

LSL opr,X

LSL ,X

LSL opr,SP

Logical Shift Left

(Same as ASL) ↕––↕↕↕

DIR

INH

IX1

SP1

9E68

LSR opr

LSRA

LSRX

LSR opr,X

LSR ,X

LSR opr,SP

Logical Shift Right ↕––0↕↕

DIR

INH

IX1

SP1

9E64

MOV opr,opr

MOV opr,X+

MOV # opr,opr

MOV X+,opr Move (M)Destination ← (M)Source

H:X ← (H:X) + 1 (IX+D, DIX+) 0––↕↕–DD

DIX+

IMD

IX+D

dd dd

ii dd

MUL Unsigned multiply X:A ← (X) × (A) – 0 –––0INH 42 5

Table 10-1. Instruction Set Summ ary (Continued)

Source

Form Operation Description

Effect on

CCR

Address

Mode

Opcode

Operand

Cycles

VHI NZC

Cb0

b7 0

b7 C0

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Central Processing Unit (CPU)

Technical Data MC68HC908GR8 — Rev 4.0

152 Central Processing Unit (CPU) MOTOROLA

NEG opr

NEGA

NEGX

NEG opr,X

NEG ,X

NEG opr,SP

Negate (Two’s Complement)

M ← –(M) = $00 – (M)

A ← –(A) = $00 – (A)

X ← –(X) = $00 – (X)

M ← –(M) = $00 – (M)

↕––↕↕↕

DIR

INH

IX1

SP1

9E60

NOP No Operation None ––––––INH 9D 1

NSA Nibble Swap A A ← (A[3:0]:A[7:4]) ––––––INH 62 3

ORA #opr

ORA opr

ORA opr,X

ORA ,X

ORA opr,SP

Inclusive OR A and M A ← (A) | (M) 0 ––↕↕–

IMM

DIR

EXT

IX2

IX1

SP1

SP2

9EEA

9EDA

hh ll

ee ff

PSHA Push A onto Stack Push (A); SP ← (SP) – 1 ––––––INH 87 2

PSHH Push H onto Stack Push (H); SP ← (SP) – 1 ––––––INH 8B 2

PSHX Push X onto Stack Push (X); SP ← (SP) – 1 ––––––INH 89 2

PULA Pull A from Stack SP ← (SP + 1); Pull (A)––––––INH 86 2

PULH Pull H from Stack SP ← (SP + 1); Pull (H)––––––INH 8A 2

PULX Pull X from Stack SP ← (SP + 1); Pull (X)––––––INH 88 2

ROL opr

ROLA

ROLX

ROL opr,X

ROL ,X

ROL opr,SP

Rotate Left through Carry ↕––↕↕↕

DIR

INH

IX1

SP1

9E69

ROR opr

RORA

RORX

ROR opr,X

ROR ,X

ROR opr,SP

Rotate Ri g h t th r o ugh Car ry ↕––↕↕↕

DIR

INH

IX1

SP1

9E66

RSP Reset Stack Pointer SP ← $F F ––––––INH 9C 1

RTI Return from Interrupt

SP ← (SP) + 1; Pull (CCR)

SP ← (SP) + 1; Pull (A)

SP ← (SP) + 1; Pull (X)

SP ← (SP) + 1; Pull (PCH)

SP ← (SP) + 1; Pull (PCL)

↕↕↕↕↕↕INH 80 7

RTS Ret urn from Subroutine SP ← SP + 1; Pull (PCH)

SP ← SP + 1; Pull (PCL) ––––––INH 81 4

Table 10-1. Instruction Set Summ ary (Continued)

Source

Form Operation Description

Effect on

CCR

Address

Mode

Opcode

Operand

Cycles

VHI NZC

Cb0

b7 C

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Central Processing Unit (CPU)

Instruction Set Summary

MC68HC908GR8 — Rev 4.0 Technical Data

MOTOROLA Central Processing Unit (CPU) 153

SBC #opr

SBC opr

SBC opr,X

SBC ,X

SBC opr,SP

Subtract with Carry A ← (A) – (M) – (C) ↕––↕↕↕

IMM

DIR

EXT

IX2

IX1

SP1

SP2

9EE2

9ED2

hh ll

ee ff

SEC Set Carry Bit C ← 1 –––––1INH 99 1

SEI Set Interrupt Mask I ← 1 ––1–––INH 9B 2

STA opr

STA opr,X

STA ,X

STA opr,SP

Store A in M M ← (A) 0 ––↕↕–

DIR

EXT

IX2

IX1

SP1

SP2

9EE7

9ED7

hh ll

ee ff

STHX opr St ore H:X in M (M:M + 1) ← (H:X) 0 ––↕↕–DIR 35 dd 4

STOP Enable IRQ Pin; Stop Oscillator I ← 0; Stop Oscillator ––0–––INH 8E 1

STX opr

STX opr,X

STX ,X

STX opr,SP

Store X in M M ← (X) 0 ––↕↕–

DIR

EXT

IX2

IX1

SP1

SP2

9EEF

9EDF

hh ll

ee ff

SUB #opr

SUB opr

SUB opr,X

SUB ,X

SUB opr,SP

Subtract A

← (A) – (M) ↕––↕↕↕

IMM

DIR

EXT

IX2

IX1

SP1

SP2

9EE0

9ED0

hh ll

ee ff

SWI Software Interrupt

PC ← (PC) + 1; Push (PCL)

SP ← (SP ) – 1; Push (PCH)

SP ← (SP ) – 1; Push (X)

SP ← (SP ) – 1; Push (A)

SP ← (SP) – 1; Push (CCR)

SP ← (SP) – 1; I ← 1

PCH ← Interrupt Vector High Byte

PCL ← Interrupt Vector Low Byte

––1–––INH 83 9

TAP Transfer A to CCR CCR ← (A) ↕↕↕↕↕↕INH 84 2

TAX Transfer A to X X ← (A) ––––––INH 97 1

TPA Transfer CCR to A A ← (CCR) ––––––INH 85 1

Table 10-1. Instruction Set Summ ary (Continued)

Source

Form Operation Description

Effect on

CCR

Address

Mode

Opcode

Operand

Cycles

VHI NZC

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Central Processing Unit (CPU)

Technical Data MC68HC908GR8 — Rev 4.0

154 Central Processing Unit (CPU) MOTOROLA

10.9 Opcode Map

See Table 10-2.

TST opr

TSTA

TSTX

TST opr,X

TST ,X

TST opr,SP

Test for Negative or Zero ( A) – $00 or (X) – $00 or (M) – $00 0 ––↕↕–

DIR

INH

IX1

SP1

9E6D

TSX Transfer SP to H:X H:X ← (SP) + 1 ––––––INH 95 2

TX A Transfer X to A A ← (X) ––––––INH 9F 1

TXS Transfer H:X to SP (SP) ← (H:X) – 1 ––––––INH 94 2

A AccumulatornAny bit

CC arry/ borrow bitopr Operand (one or two bytes)

CCRCondition code registerPC Program counter

ddDirect address of operandPCH Program counter high byte

dd rrDirect address of operand and relative offset of branch instructionPCL Progr am counter low byte

DDDirect to direct addressing modeREL Relative addressing mode

DIRDirect addressing moderel Relative program counter offset byte

DIX+Direct to indexed with post increment addressing moderr Relative program counter offset byte

ee ffHigh and low bytes of offset in indexed, 16-bit offset addressingSP1 Stack pointer, 8-bit offset addressing mode

EXTExtended addressing modeSP2 St ack pointer 16-bit offset addressing mode

ff Offset byte in indexed, 8-bit offset addressingSP Stack pointer

HH alf-carry bitU Undefined

HIndex regist er high byteV Overflow bit

hh llHigh and low bytes of operand address in extended addressingX Index register low byte

I Interrupt maskZ Zero bit

ii Immediate operand byte& Logical AND

IMDImmediate source to direct destination addressing mode| Logical OR

IMMImmediate addressing mode ⊕Logical EXCLUSIVE OR

INHInherent addressing mode( ) Contents of

IXIndexed, no offset addressing mode–( ) Negat ion (two’s complement)

IX+Indexed, no offset, post increment addressing mode# Immediate value

IX+DIndexed with post increment to direct addressing mode«Sign extend

IX1Indexed, 8-bit offset addressing mode←Loaded with

IX1+Indexed, 8-bit offset, po st increm ent addressing mode? If

IX2Indexed, 16-bit offset addressing mode: Concatenated with

MMemory location↕Set or cleared

NN egative bit—Not affect ed

Table 10-1. Instruction Set Summ ary (Continued)

Source

Form Operation Description

Effect on

CCR

Address

Mode

Opcode

Operand

Cycles

VHI NZC

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Technical Data MC68HC908GR8 — Rev 4.0

155 Centra l Processing Unit (CPU) MO TOROLA

Central Processing Unit (CPU)

Bit Ma nipulation Branch Read-Modify-Write Control Regis ter/Memory

DIR DIR REL DIR INH INH IX1 SP1 IX INH INH IMM DIR EXT IX2 SP2 IX1 SP1 IX

01234569E6789ABCD9EDE9EEF

BRSET0

3DIR

BSET0

2DIR

BRA

2REL

NEG

2DIR

NEGA

1INH

NEGX

1INH

NEG

2IX1

NEG

3SP1

NEG

1IX

RTI

1INH

BGE

2REL

SUB

2IMM

SUB

2DIR

SUB

3EXT

SUB

3IX2

SUB

4 SP2

SUB

2IX1

SUB

3SP1

SUB

1IX

BRCLR0

3DIR

BCLR0

2DIR

BRN

2REL

CBEQ

3DIR

CBEQA

3IMM

CBEQX

3IMM

CBEQ

3IX1+

CBEQ

4SP1

CBEQ

2IX+

RTS

1INH

BLT

2REL

CMP

2IMM

CMP

2DIR

CMP

3EXT

CMP

3IX2

CMP

4 SP2

CMP

2IX1

CMP

3SP1

CMP

1IX

BRSET1

3DIR

BSET1

2DIR

BHI

2REL

MUL

1INH

DIV

1INH

NSA

1INH

DAA

1INH

BGT

2REL

SBC

2IMM

SBC

2DIR

SBC

3EXT

SBC

3IX2

SBC

4 SP2

SBC

2IX1

SBC

3SP1

SBC

1IX

BRCLR1

3DIR

BCLR1

2DIR

BLS

2REL

COM

2DIR

COMA

1INH

COMX

1INH

COM

2IX1

COM

3SP1

COM

1IX

SWI

1INH

BLE

2REL

CPX

2IMM

CPX

2DIR

CPX

3EXT

CPX

3IX2

CPX

4 SP2

CPX

2IX1

CPX

3SP1

CPX

1IX

BRSET2

3DIR

BSET2

2DIR

BCC

2REL

LSR

2DIR

LSRA

1INH

LSRX

1INH

LSR

2IX1

LSR

3SP1

LSR

1IX

TAP

1INH

TXS

1INH

AND

2IMM

AND

2DIR

AND

3EXT

AND

3IX2

AND

4 SP2

AND

2IX1

AND

3SP1

AND

1IX

BRCLR2

3DIR

BCLR2

2DIR

BCS

2REL

STHX

2DIR

LDHX

3IMM

LDHX

2DIR

CPHX

3IMM

CPHX

2DIR

TPA

1INH

TSX

1INH

BIT

2IMM

BIT

2DIR

BIT

3EXT

BIT

3IX2

BIT

4 SP2

BIT

2IX1

BIT

3SP1

BIT

1IX

BRSET3

3DIR

BSET3

2DIR

BNE

2REL

ROR

2DIR

RORA

1INH

RORX

1INH

ROR

2IX1

ROR

3SP1

ROR

1IX

PULA

1INH

LDA

2IMM

LDA

2DIR

LDA

3EXT

LDA

3IX2

LDA

4 SP2

LDA

2IX1

LDA

3SP1

LDA

1IX

BRCLR3

3DIR

BCLR3

2DIR

BEQ

2REL

ASR

2DIR

ASRA

1INH

ASRX

1INH

ASR

2IX1

ASR

3SP1

ASR

1IX

PSHA

1INH

TAX

1INH

AIS

2IMM

STA

2DIR

STA

3EXT

STA

3IX2

STA

4 SP2

STA

2IX1

STA

3SP1

STA

1IX

BRSET4

3DIR

BSET4

2DIR

BHCC

2REL

LSL

2DIR

LSLA

1INH

LSLX

1INH

LSL

2IX1

LSL

3SP1

LSL

1IX

PULX

1INH

CLC

1INH

EOR

2IMM

EOR

2DIR

EOR

3EXT

EOR

3IX2

EOR

4 SP2

EOR

2IX1

EOR

3SP1

EOR

1IX

BRCLR4

3DIR

BCLR4

2DIR

BHCS

2REL

ROL

2DIR

ROLA

1INH

ROLX

1INH

ROL

2IX1

ROL

3SP1

ROL

1IX

PSHX

1INH

SEC

1INH

ADC

2IMM

ADC

2DIR

ADC

3EXT

ADC

3IX2

ADC

4 SP2

ADC

2IX1

ADC

3SP1

ADC

1IX

BRSET5

3DIR

BSET5

2DIR

BPL

2REL

DEC

2DIR

DECA

1INH

DECX

1INH

DEC

2IX1

DEC

3SP1

DEC

1IX

PULH

1INH

CLI

1INH

ORA

2IMM

ORA

2DIR

ORA

3EXT

ORA

3IX2

ORA

4 SP2

ORA

2IX1

ORA

3SP1

ORA

1IX

BRCLR5

3DIR

BCLR5

2DIR

BMI

2REL

DBNZ

3DIR

DBNZA

2INH

DBNZX

2INH

DBNZ

3IX1

DBNZ

4SP1

DBNZ

2IX

PSHH

1INH

SEI

1INH

ADD

2IMM

ADD

2DIR

ADD

3EXT

ADD

3IX2

ADD

4 SP2

ADD

2IX1

ADD

3SP1

ADD

1IX

BRSET6

3DIR

BSET6

2DIR

BMC

2REL

INC

2DIR

INCA

1INH

INCX

1INH

INC

2IX1

INC

3SP1

INC

1IX

CLRH

1INH

RSP

1INH

JMP

2DIR

JMP

3EXT

JMP

3IX2

JMP

2IX1

JMP

1IX

BRCLR6

3DIR

BCLR6

2DIR

BMS

2REL

TST

2DIR

TSTA

1INH

TSTX

1INH

TST

2IX1

TST

3SP1

TST

1IX

NOP

1INH

BSR

2REL

JSR

2DIR

JSR

3EXT

JSR

3IX2

JSR

2IX1

JSR

1IX

BRSET7

3DIR

BSET7

2DIR

BIL

2REL

MOV

3DD

MOV

2DIX+

MOV

3IMD

MOV

2IX+D

STOP

1INH *2

LDX

2IMM

LDX

2DIR

LDX

3EXT

LDX

3IX2

LDX

4 SP2

LDX

2IX1

LDX

3SP1

LDX

1IX

BRCLR7

3DIR

BCLR7

2DIR

BIH

2REL

CLR

2DIR

CLRA

1INH

CLRX

1INH

CLR

2IX1

CLR

3SP1

CLR

1IX

WAIT

1INH

TXA

1INH

AIX

2IMM

STX

2DIR

STX

3EXT

STX

3IX2

STX

4 SP2

STX

2IX1

STX

3SP1

STX

1IX

INH Inherent REL Relative SP1 Stack Pointer, 8-Bit Offset

IMM Immediate IX Indexed, No Offset SP2 Stack Pointer, 16-Bit Offset

DIR Direct IX1 Indexed, 8-Bit Offset IX+ Indexed, No Offset with

EXT Extended IX2 Indexed, 16-Bit Offset Post Increment

DD Direct-Direct IMD Immediate-Direct IX1+ Indexed, 1-Byte Offset with

IX+ D Indexed-Direct DI X+ Direct-Inde xed Post Incr ement

*Pre-byte for stack pointer indexed instructions

0 High Byte of Opcode in Hexadecimal

Low Byte of Opcode in Hexadecimal 0 5

BRSET0

3DIR

Cycles

Opcode Mnemonic

Number of Bytes / Addressing Mode

Table 10-2. Opcode Map

MSB

LSB

MSB

LSB

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Central Processing Unit (CPU)

Technical Data MC68HC908GR8 — Rev 4.0

156 Central Processing Unit (CPU) MOTOROLA

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MC68HC908GR8 — Rev 4.0 Technical Data
MOTOROLA Flash Memory 157
 
Technical Data — MC68HC908GR8
Section 11. Flash Memory
11.1  Contents
11.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .157
11.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 57
11.4 FLASH Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . .159
11.5 FLASH Page Erase Operation . . . . . . . . . . . . . . . . . . . . . . . .160
11.6 FLASH Mass Erase Operation . . . . . . . . . . . . . . . . . . . . . . . .161
11.7 FLASH Program/Read Operation. . . . . . . . . . . . . . . . . . . . . .162
11.8 FLASH Block Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . .163
11.9 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .166
11.10 STOP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .166
11.2  Introduction
This secti on  describe s th e op eratio n of t he em bedd ed FLA SH me mory.  
This memory can be read, programmed, and erased from a single 
external supply. The program, erase, and read operations are enabled 
through the use of an internal charge pump.
11.3  Functional Description
The FLASH memory is an array of 7,680 bytes for the MC68HC908GR8 
or 4,096 bytes for the MC68HC908GR4 with an additional 36 bytes of 
user vectors and one byte  used for block protection. An erased bit reads 
as logi c 1 and a programmed bit reads as a logic 0. The program and 
erase op erat ions ar e faci litate d thro ugh cont rol  bits in the Fl ash Contr ol 
    
  
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Flash Memory

Technical Data MC68HC908GR8 — Rev 4.0

158 Flash Memory MOTOROLA

section.

The FLASH is organized internally as a 8192-word by 8-bit CMOS page

erase, byte (8-bit) program Embedded Flash Memory. Each page

consists of 64 bytes. The page erase operation erases all wo rds within

a page. A page is composed of two adjacent rows.

The address ranges for the user memory and vectors are as follows:

•$E000–$FDFF; user memo ry for the MC68HC908GR8

$EE00–$FDFF; user memo ry for the MC68HC908GR4.

•$FF7 E; FLAS H block prote ct reg ister .

•$FE08; FLASH control register.

•$FFDC–$FFFF; these locations are reserved for user-defined

interrupt and reset vectors.

Programming tools are available from Motorola. Contact your local

Motorola representative for more information.

NOTE: A security feature pr eve nts vie w ing of the FLASH conten ts. (1)

1. No security feature is absolutely se cure . Howe ve r, Moto rola ’s strategy is to make reading or

copying the FLASH difficult for unauthoriz ed users.

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Flash Memory

FLASH Control Register

MC68HC908GR8 — Rev 4.0 Technical Data

MOTOROLA Flash Memory 159

11.4 FLASH Control Register

The FLASH control register (FLCR) controls FLASH program and erase

operations.

HVEN — High-Voltage Enable Bit

This read/write bit enables the charge pump to drive high voltages for

program and erase operations in the array. HVEN can only be set if

either PG M = 1 or ER AS E = 1 an d the proper sequence for program

or erase is followed.

1 = High voltage enab led to array and char ge pump on

0 = High voltage disabled to array and charge pump off

MASS — Mass Erase Control Bit

Setting this read/write bit configures the 8K byte FLASH array for

mass erase operation.

1 = MASS erase operation selected

0 = MASS erase operation unselected

ERASE — Erase Control Bit

This read/write bi t config ures the memo ry for er ase operatio n.

ERASE is interlocked w ith the PGM bit su ch t ha t bo th bi ts can not be

equal to 1 or set to 1 at the same time.

1 = Erase operation selected

0 = Erase operation unselected

Address: $FE08

Bit 7654321Bit 0

HVEN MASS ERASE PGM

Write:

Reset:00000000

Figure 11-1. FLASH Control Register (FLCR)

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Flash Memory

Technical Data MC68HC908GR8 — Rev 4.0

160 Flash Memory MOTOROLA

PGM — Program Control B it

This read/write bit configures the memory for program operation.

PGM i s i nte r locked w it h the ERASE bit such t hat bo th bits cannot be

equal to 1 or set to 1 at the same time.

1 = Progra m operation sele cte d

0 = Progra m operation unse le cted

11.5 FLASH Page Erase Operation

Use this step-by-step procedure to erase a page (64 bytes) of FLASH

memory to read as logic 1:

1. Set the ERASE bit, and clear the MASS bit in the FLASH control

2. Read the FLASH block protect register.

3. Write any data to any FLASH address within the page address

range desir ed.

4. Wait for a time, tnvs (min. 10µs)

5. Set the HVEN bit.

6. Wait for a time, tErase (min. 1ms)

7. Clear the ERASE bit.

8. Wait for a time, tnvh (min. 5µs)

9. Clear the HVEN bit.

10. After a time, trcv (typ. 1µs), the memory can be accessed again in

read mod e.

NOTE: While these operations must be performed in t he order shown, othe r

unrelated operations may occur between the steps.

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Flash Memory

FLASH Mass Erase Operation

MC68HC908GR8 — Rev 4.0 Technical Data

MOTOROLA Flash Memory 161

11.6 FLASH Mass Erase Operation

Use thi s step-b y-step proc edure to erase en tire FLASH memo ry to read

as logic 1:

1. Set both the ERASE bit, and the MASS bit in the FLASH control

2. Read from the FL ASH bloc k protect register.

3. Write any data to any FLA SH address* within the FLASH memory

address range.

4. Wait for a time, tnvs (min. 10µs)

5. Set the HVEN bit.

6. Wait for a time, tMErase (mi n. 4ms)

7. Clear the ERASE bit.

8. Wait for a time, tnvhl (min. 100µs)

9. Clear the HVEN bit.

10. After a time, trcv (min. 1µs), the memory can be accessed again in

read mod e.

* When in Moni tor mode, with secu rity sequence faile d Monitor ROM (MON), write to t he FLASH

block protect register instead of any FLASH address.

NOTE: Programm ing and era si ng of FLASH lo cati o ns cann ot be per fo r med by

code bei ng execu ted fr om the FLASH m em ory . W hil e the se op er at io ns

must be pe rformed in the or de r sh ow n, other unrelated o per a t ions m ay

occur between the steps.

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Flash Memory

Technical Data MC68HC908GR8 — Rev 4.0

162 Flash Memory MOTOROLA

11.7 FLASH Program/Read Operation

Programming of th e FLASH memory is done on a row basis. A row

consists of 32 consecutive bytes starting from addresses $XX00,

$XX20, $XX40, $XX60, $XX80, $XXA0, $XXC0, and $XXE0. Use this

step-by-ste p proced ure to prog ram a row of FLASH memor y (Figure 11-

2 is a flowchart representation):

1. Set the PGM bit. This configures the memory for program

operation and enables the latching of address and data for

programming.

2. Read from the FL ASH bloc k protect register.

3. Write any data to any FLASH address within the row address

range desir ed.

4. Wait for a time, tnvs (min. 10µs).

5. Set the HVEN bit.

6. Wait for a time, tpgs (min. 5µs).

7. Write data to the FLASH address to be programm ed.*

8. Wait for a time, tPROG (min. 30µs).

9. Repeat step 7 and 8 until all the bytes wit hin th e row are

programmed.

10. Clear the PGM bit .*

11. Wait for a time, tnvh (min. 5µs).

12. Clear the HVEN bit.

13. After time , trcv (min. 1µs), the memory can be accessed in read

mode again.

* The tim e betwee n each FL ASH addres s chan ge, or the ti me betwe en the la st FL ASH addres s

progra mmed to clearing PGM bit, mu st not exceed the maxim um programmin g time, tPROG max.

This program sequence is repeated throughout the memory until all data

is programmed.

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Flash Memory

FLASH Block Protecti on

MC68HC908GR8 — Rev 4.0 Technical Data

MOTOROLA Flash Memory 163

NOTE: Programm ing and era si ng of FLASH lo cati o ns cann ot be per fo r med by

code bei ng execu ted fr om the FLASH mem or y. W hi le the s e op er at io ns

must be pe rformed in the or de r sh ow n, other unrelated o per a t ions m ay

occur between the steps. Do not exceed tPROG maximum. See Memory

Characteristics.

11.8 FLASH Block Protection

Due to the ability of the on-board charge pump to erase and program the

FLASH memory in the target application, provision is made for protecting

a block of memory from unintentional erase or program operations due

to system malfunction. This protection is done by using of a FLASH

Block Protect Register (FLBPR). The FLBPR determines the range of

the FLASH memory which is to be protected. The range of the protected

area starts fr om a locatio n defined by FLBP R and ends at the bottom of

the FLASH memory ($FFFF). When the memory is protected, the HVEN

bit cannot be set in either ERASE or PROGRAM operations.

NOTE: In performing a program or erase operation, the FLASH block protect

asserting the HVEN bit

When the FLBPR is programmed with all 0s, the entire memory is

protected from being programmed and erased. When all the bits are

erased (all 1s ), the entire me mory is accessible for progr am and erase.

When bits within the FLBPR are programmed, they lock a block of

memory with address ranges as shown in FLASH Block Protect

any erase or program of the FLBPR or the protected block of FLASH

memory is prohibited. The FLBPR itself can be erased or programmed

only with an external voltage, VTST, present on the IRQ pin. This voltage

also allows entry from reset into the monitor mode.

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Flash Memory

Technical Data MC68HC908GR8 — Rev 4.0

164 Flash Memory MOTOROLA

Figure 11-2. FLASH Programming Flowchart

Set HVEN bit

Read the FLASH block protect register

Write any data to any FLASH address

within the row addre s s rang e de sired

Wa it for a time, t

nvs

Set PGM bit

W ait for a time, t

pgs

Write da ta to the FLA SH ad dr ess

to be programmed

Wa it for a time, t

PROG

Clear PGM bit

Wait for a time, t

nvh

Clear HVEN bit

Wa it for a time, t

rcv

Completed

programming

this row ?

End of pro gram m ing

The time between each FLASH address change (step 7 to step 7), or

must not exceed the maximum program m ing

time, t

PROG

max.

the time between t he last FLASH address programm ed

to clearing PGM bit (step 7 to step 10)

NOTE:

Algorithm for progra m m ing

a row (32 bytes) of FLA SH m emory

This row progra m alg orithm assu me s the row /s

to be programmed are initially erased.

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Flash Memory

FLASH Block Protecti on

MC68HC908GR8 — Rev 4.0 Technical Data

MOTOROLA Flash Memory 165

11.8.1 FLASH Block Protect Register

The FLASH block protect register (FLBPR) is implemented as a byte

within the FLASH memory, and therefore can only be written during a

programming sequence of the FLASH memory. The value in this register

determines the starting location of the protected range within the FLASH

memory.

BPR[7:0] — FLASH Block Protect Bits

These eight bits represent bits [13:6] of a 16-bit memory address.

Bits [15:14] are logic 1s and bits [5:0] are logic 0s.

The resultant 16-bit address is used for specifying the start address

of the FLASH memory for block protection. The FLASH is protected

from this start address to the end of FLASH memory, at $FFFF. With

this mechanism, the protect start address can be $XX00, $XX40,

$XX80, and $XXC0 (64 bytes page boundaries) within the FLASH

memory.

Figure 11-4. FLASH Block Protect Start Address

Address: $FF7E

Bit 7654321Bit 0

Read: BPR7 BPR6 BPR5 BPR4 BPR3 BPR2 BPR1 BPR0

Write:

Reset:UUUUUUUU

U = Unaffected by reset. Initial value from factory is 1.

Write to this register is by a programming sequence to the FLASH memory.

Figure 11-3. FLASH Block Protect Register (FLBPR)

1FLBPR value

16-bit memory address

000000

Start address of FLASH block protect 1

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Flash Memory

Technical Data MC68HC908GR8 — Rev 4.0

166 Flash Memory MOTOROLA

Examples of protect start address:

11.9 Wait Mode

Puttin g th e M C U into wait mo de while the FLASH is in r ead m ode does

not affect the operation of the FLASH memory directly, but there will not

be any memory activity since the CPU is inactive.

The WAIT instruction should not be executed while performing a

program or erase operation on the FLASH, otherwise the operation will

disc ontinue, and th e FLASH will be on St andby Mode.

11.10 STOP Mode

Putting the MCU into stop mode while the FLASH is in read mode does

not affect the operation of the FLASH memory directly, but there will not

be any memory activity since the CPU is inactive.

The STOP instruction should not be executed while performing a

program or erase operation on the FLASH, otherwise the operation will

disc ontinue, and th e FLASH will be on St andby Mode

NOTE: Standby Mode is the power saving mode of the FLASH module in which

all internal control signals to the FLASH are inactive and the current

consumption of the FLASH is a t a minimum.

Table 11-1. Examples of protect start address:

BPR[7:0] Start of Address of Protect Range

$80 The entire FLASH memory is prote cted.

$81 (1000 0001) $E040 (1110 0000 0100 0000)

$82 (1000 0010) $E080 (1110 0000 1000 0000)

and so on...

$FE (1111 1110) $FF80 (1111 1111 1000 0000)

$FF The entire FLASH memory is not protected.

Note:

The end address of the protected range is always $FFFF.

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MC68HC908GR8 — Rev 4.0 Technical Data
MOTOROLA External Interrupt (IRQ) 167
 
Technical Data — MC68HC908GR8
Section 12. External Interrupt (IRQ)
12.1  Contents
12.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .167
12.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 67
12.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 68
12.5 IRQ1 Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .170
12.6 IRQ Module During Break Interrupts  . . . . . . . . . . . . . . . . . . .171
12.7 IRQ Status and Control Register . . . . . . . . . . . . . . . . . . . . . .172
12.2  Introduction
The I RQ (externa l interru pt) module  provides  a maskable  interrup t input.
12.3  Features
Features of the IRQ module include:
•A dedicated external interrupt pin (IRQ1)
•IRQ interrupt control bits
•Hysteresis buffer
•Programmable edge-only or edge and level interrupt sensitivity
•Automatic interrupt acknowledge
•Internal pullup resistor
    
  
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External Interrupt (IRQ)

Technical Data MC68HC908GR8 — Rev 4.0

168 External Interrupt (IRQ) MOTOROLA

12.4 Functional Description

A logic 0 applied to the external interrupt pin can latch a CPU interrupt

request. Figure 12-1 shows the structur e of the IRQ module.

Interrupt signals on the IRQ1 pin are latched into the IRQ latch. An

interrupt latch remain s set until one of the following actions occurs:

•Vector fetch — A vector fetch automatically generates an interrupt

acknowledge signal that clears the latch that caused the vector

fetch.

•Softwar e clear — Software can clear an interrupt latch by writing

to the appropriate ackno wledge b it in the interrupt status and

control register (INTSCR). Writing a logic 1 to the ACK bit clears

the IRQ latch.

•Reset — A reset automatically clears the interrupt latch.

The external in terrup t pin is falling -edge-trigg ered an d is software-

configurable to be either falling-edge or falling-edge and low-level-

triggered. The MODE bit in the INTSCR controls the triggering sensitivity

of the IRQ1 pin.

When an interrupt pi n is edge-triggered only, the interrupt remains set

until a vector fetch, software clear, or reset occurs.

When an interrupt pin is b oth falling-edge and low-leve l-triggered, the

interrupt remains set until both of the following occur:

•Vector fetch or software clear

•Return of the inte rrupt pin to logic 1

The vector fetch or software clear may occur before or after the interrupt

pin returns to logic 1. As long as the pin is low, the interrupt request

remains pending. A reset will clear the latch and the MODE control bit,

thereby clearing the interrupt even if the pin stays low.

When set, th e IMASK bit in the INTSCR mask all external interrupt

requests. A latched interrupt request is not presented to the interrupt

priority logic un less th e IMASK bit is clear.

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External Interrupt (IRQ)

Functional Description

MC68HC908GR8 — Rev 4.0 Technical Data

MOTOROLA External Interrupt (IRQ) 169

NOTE: The interrupt mask (I) in the condition code register (CCR) masks all

interrupt requests, including external interrupt requests.

Figure 12-1. IRQ Module Block Diagram

IRQ1

ACK

IMASK

CLR IRQ

HIGH

INTERRUPT

TO MO D E

SELECT

LOGIC

IRQ

REQUEST

VDD

MODE

VOLTAGE

DETECT

SYNCHRO-

NIZER

IRQF

TO CPU FOR

BIL/BIH

INSTRUCTIONS

VECTOR

FETCH

DECODER

INTER N AL ADDRES S BUS

RESET

VDD

INTERNAL

PULLUP

DEVICE

Addr.Register Name Bit 7654321Bit 0

$001D IRQ Status and Control

Read: 0000IRQF0

IMASK MODE

Write: ACK

Reset:00000000

= Unimplemented

Figure 12-2. IRQ I/O Register Summary

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External Interrupt (IRQ)

Technical Data MC68HC908GR8 — Rev 4.0

170 External Interrupt (IRQ) MOTOROLA

12.5 IRQ1 Pin

A logic 0 on the IRQ1 pin can latch an interrupt request into the IRQ

latch. A vector fetch, software clear, or reset clears the IRQ latch.

If the MODE bit is set, the IRQ1 pin is both falling-edge-sensitive and

low-level-sensitive. With MODE set, both of the following a c ti ons must

occur to clear IRQ:

•Vector fetch or software clear — A vector fetch generates an

interrupt acknowledge signal to clear the latch. Software may

generate the interrupt acknowledge signal by writing a logic 1 to

the ACK bit in the interrupt status and control register (INTSCR).

The ACK bit is useful in applications that poll the IRQ1 pin and

require software to clear the IRQ latch. Writing to the ACK bit prior

to leavi ng an in te rr up t servic e rou tine can also preve nt spuri ou s

interrup ts due to noise. Setting ACK does not affect subsequent

transitions on the IRQ1 pin . A fall ing edge t hat occurs after wri ting

to the ACK bit another interrupt request. If the IRQ mask bit,

IMASK, is clear, the CPU loads the program cou nte r with the

vector address at locations $FFFA and $FFFB.

•Return of the IRQ1 pin to lo gic 1 — As long as the IRQ1 pin is at

logic 0, IRQ remains active.

The vector fetc h or software clear and the return of the IRQ1 pin to logi c

1 may occur in any order. The interrupt request remains pending as long

as the IRQ1 pin is at logic 0. A reset will clear the latch and the MODE

control bit, thereby clearing the interrupt even if the pin stays low.

If the MODE bit is cle ar, the IRQ1 pin is falli ng-edge-s ensitive onl y. With

MODE clear, a vector fetch or software clear immediately clears the IRQ

latch.

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External Interrupt (IRQ)

IRQ Module During Break Interrupts

MC68HC908GR8 — Rev 4.0 Technical Data

MOTOROLA External Interrupt (IRQ) 171

The IRQF bit in the INTSCR register can be used to check for pending

interrupts. The IRQF bit is not affect ed by the IMASK bit, which makes it

useful in application s where polling is preferred.

Use the BIH or BIL instruction to read the logic level on the IRQ1 pin.

NOTE: When using the level-sensitive interrupt trigger, avoid false interrupts by

masking interrupt requests in the interrupt routine.

12.6 IRQ Module During Break Interrupts

The BCFE bit in the SIM break flag control register (SBFCR) enables

software to clear the latch during the break state. See Break Module

(BRK).

To allow software to clear th e IRQ latch during a break interrupt, write a

logic 1 to the BCFE bit. If a latch is cleared during the break state, it

remains cleared when the MCU exits the break state.

To protect CPU interrupt flags during the break state, write a logic 0 to

the BC FE bit. With BCFE at l ogic 0 (i ts defaul t state) , writin g to the A CK

bit in the IRQ status and control register during the break state has no

effect on the IRQ interrupt flags.

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External Interrupt (IRQ)

Technical Data MC68HC908GR8 — Rev 4.0

172 External Interrupt (IRQ) MOTOROLA

12.7 IRQ Status and Control Register

The IRQ status and contro l register (INTSCR) controls and monitors

operation of the IRQ module. The INTSCR:

•Shows the state of the IRQ flag

•Clears the IRQ latch

•Masks IRQ interrupt request

•Controls triggering sensitivity of the IRQ1 interrupt pin

IRQF — IRQ Flag Bit

This read-only status bit is high when the IRQ interrupt is pending.

1 = IRQ interrupt pending

0 = IRQ interrupt not pending

ACK — IRQ Interrupt Request Acknowledg e Bit

Writing a logic 1 to this write-only bit clears the IRQ latch. ACK always

reads as logic 0. Reset clears ACK.

IMASK — IRQ Interrupt Mask Bit

Writ ing a log ic 1 to t his rea d/write bi t disable s IRQ inter rupt r equests.

Reset clears IMASK.

1 = IRQ interrupt requests disabled

0 = IRQ interrupt requests enabled

Address: $001D

Bit 7654321Bit 0

Read: IRQF 0 IMASK MODE

Write: ACK

Reset:00000000

= Unimplemented

Figure 12-3. IRQ Status and Control Register (INTSCR)

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External Interrupt (IRQ)

IRQ Status and Control Register

MC68HC908GR8 — Rev 4.0 Technical Data

MOTOROLA External Interrupt (IRQ) 173

MODE — IRQ Edge/Level Select Bit

This read/write bit controls the trigge ring sensitivity of the IRQ1 pin.

Reset clears MODE.

1 = IRQ1 interru pt requests on falling edges and low lev els

0 = IRQ1 interrupt requests on falling edges only

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External Interrupt (IRQ)

Technical Data MC68HC908GR8 — Rev 4.0

174 External Interrupt (IRQ) MOTOROLA

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MC68HC908GR8 — Rev 4.0 Technical Data
MOTOROLA Keyboard Interrupt (KBI) 175
 
Technical Data — MC68HC908GR8
Section 13. Keyboard Interrupt (KBI)
13.1  Contents
13.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175
13.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 75
13.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 76
13.5 Keyboard Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .179
13.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .180
13.7 Keyboard Module During Break Interrupts . . . . . . . . . . . . . . .180
13.8 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 81
13.2  Introduction
The keyboard interrupt module (KBI) provides four independently 
maskable external interrupts. 
13.3  Features
•Four keyboard interrupt pins with separate keyboard interrupt 
enable  bits and one keyboard interr upt mask
•Hysteresis buffers
•Programmable edge-only or edge- and level- interrupt sensitivity
•Exit from low-p ower modes
•I/O (input/output) port bit(s) so ftware conf igurable with pullup 
device(s) if configured as input port bit(s)
    
  
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Keyboard Interrupt (KBI)

Technical Data MC68HC908GR8 — Rev 4.0

176 Keyboard Interrupt (KBI) MOTOROLA

13.4 Functional Description

Writing to the KBIE3–KBIE0 bits in the keyboard interrupt enable register

independe ntly enables or disables each port A pin as a keyboard

interrupt pin. Enabling a keyboard interrupt pin also enables its internal

pullup device. A logic 0 applied to an enabled key board in terrupt pin

latch es a keyboard i nterrupt requ est.

A keyboard interrupt is latched when one or more keyboard pins goes

low after all were high. The MODEK bit in the keyboard status and

control register controls the triggering mode of the keyboard interrupt.

•If the keyboard interrupt is edge-sensitive only, a falling edge on a

keyboard pin does not latch an interrupt request if another

keyboard pin is already low. To prevent losing an interrupt request

on one pin because ano ther pin is still low, software can disable

the latter pin while it is low.

•If the keyboard interrupt is falling-edge and low-level sensitive, an

interrupt request is present as long as any keyboard interrupt pin

is low and the pin is keyboard interrupt enabled.

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Keyboard Interrupt (KBI)

Functional Description

MC68HC908GR8 — Rev 4.0 Technical Data

MOTOROLA Keyboard Interrupt (KBI) 177

Figure 13-1. Keyboard Module Block Diagram

KB0IE

KB3IE

.KEYBOARD

INTERRUPT

CLR

VDD

MODEK

IMASKK

KEYBOARD

INTERRUPT FF

REQUEST

VECTOR FETCH

DECODER

ACKK

INTERNAL BUS

RESET

TO PULLUP

KBD3

KBD0

TO PULLUP

SYNCHRONIZER

KEYF

ENABLE

Addr.Register Name Bit 7654321Bit 0

$001A Keyboard Status

and Control Register

(INTKBSCR)

Read: 0000KEYF0

IMASKK MODEK

Write: ACKK

Reset:00000000

$001B Keyboard Interrupt Enable

Read: KBIE3 KBIE2 KBIE1 KBIE0

Write:

Reset: 0000

= Unimplemented

Figure 13-2. I/O Register Summary

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Keyboard Interrupt (KBI)

Technical Data MC68HC908GR8 — Rev 4.0

178 Keyboard Interrupt (KBI) MOTOROLA

If the MODEK bit is set, the keyboard interrupt pins are both falling edge-

and low-level sensitive, and both of the following actions must occur to

clear a keyboa rd interrupt request:

•Vector fetch or software clear — A vector fetch generates an

interrupt acknowledge signal to clear the interru pt request.

Soft ware may generate the interrupt ac knowledge signal by

writing a logic 1 to the ACKK bit in the keyboard status and control

poll the keyboard interrupt pins and require software to clear the

keyboard interrupt request. Writing to the ACKK bit prior to leaving

an interrupt service routine can also prevent spurious interrupts

due to noise. Setting ACKK does not affect subsequent transitions

on the keyboard interrupt pins. A fal ling edge that occurs after

writing to the ACKK bit latches another interrupt request. If the

keyboard interrupt mask bit, IMASKK, is clear, the CPU loads the

program co unt er w it h th e ve ctor a dd ress at locations $F FDE and

$FFDF.

•Retur n of all enable d keyboard interrupt pins to logic 1 — As lo ng

as any enabled keyboard interrupt pin is at logic 0, the keyboard

inte rrupt remai ns set.

The vector fetch or software clear and the return of all enabled keyboard

interrupt pins to logic 1 may occur in any order.

If the MODEK bit is clear, the keyboard interrupt pin is falling-edge-

sensitive only. With MODEK clear, a vector fetch or software clear

immediately clears the keyboa rd interrupt re quest.

Reset clears the keyboard interrupt request and the MODEK bit, clearing

the int errupt request even if a keyboard interru pt pin stays a t logic 0.

The keyboard flag bit (KEYF) in the keyboard status and control registe r

can be used to see if a pending interrupt exists. The KEYF bit is not

affected by the keyboard interrup t mask bit (IMASKK) which makes it

useful in application s where polling is preferred.

To determine the logic level on a keyboard interrupt pin, use the data

dire ction register to config ure the pin as an inpu t and re ad the data

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Keyboard Interrupt (KBI)

Keyboard Initialization

MC68HC908GR8 — Rev 4.0 Technical Data

MOTOROLA Keyboard Interrupt (KBI) 179

NOTE: Setting a keyboard interrupt enable bit (KBIEx) forces the corresponding

keyboard interrupt pin to be an input, overriding the data direction

regist er. However, the dat a direction register bit must be a logic 0 for

software to read the pin.

13.5 Keyb oa rd Ini tia li za tion

When a keyboard interrupt pin is enabled, it takes time for the internal

pullup to reach a logic 1. Therefore, a false interrupt can occur as soon

as the pin is enabled.

To preven t a false interrupt on keyboard initialization:

1. Mask keyboard interrupts by setting the IMASKK bit in the

keyboard status and control register.

2. Enable the KBI pins by setting the appropriate KBIEx bits in the

keyboard interrupt enable register.

3. Write to the ACKK bit in the keyboard status and control registe r

to clear any false interrupts.

4. Clear the IMASKK bit.

An interrupt signal on an edge-triggered pin can be acknowledged

immediately after enabling the pin. An interrupt signal on an edge- and

level-triggered interrupt pin must be acknowledged after a delay that

depends on the external load.

Anoth er way to avoid a false interrupt is:

1. Configure the keyboard pins as outputs by setting the appropriate

DDRA bits in data direction register A.

2. Write logic 1s to the appropriate port A data register bits.

3. Enable the KBI pins by setting the appropriate KBIEx bits in the

keyboard interrupt enable register.

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Keyboard Interrupt (KBI)

Technical Data MC68HC908GR8 — Rev 4.0

180 Keyboard Interrupt (KBI) MOTOROLA

13.6 Low-Power Modes

The WAIT and STOP instructions put the MCU in low power-

consumptio n standby mode s.

13.6.1 Wait Mode

The keyboard module remains active in wait mode. Cle aring the

IMASKK bit in the keyboard status and control register enables keyboard

interrupt requests to bring the MCU out of wait mode.

13.6.2 Stop Mode

The keyboard module remains active in stop mode. Clearing the

IMASKK bit in the keyboard status and control register enables keyboard

interrupt requests to bring the MCU out of stop mode.

13.7 Keyboard Module During Break Interrupts

The system integration module (SIM) controls whether the keyboard

interrupt latch can be cleared during the break state. The BCFE bit in the

SIM break flag control register (SBFCR) enables software to clear status

bits during the break state.

To allow software to clear the keyboard interrupt latch during a break

interrupt, write a logic 1 to the BCFE bit. If a latch is cleared during the

break state, it remains cleared when the MCU exits the break state.

To protect the latch during the break state, write a logic 0 to the BCFE

bit. With BCFE at logic 0 (its default state), writing to the keyboard

acknowledge bit (ACKK) in the keyboard status and control register

during the break state has no effect. See Keyboard Status and Control

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Keyboard Interrupt (KBI)

I/O Registers

MC68HC908GR8 — Rev 4.0 Technical Data

MOTOROLA Keyboard Interrupt (KBI) 181

13.8 I/O Registers

These registers control and monitor operation of the keyboard module:

•Keyboard status and control register (INTKBSCR)

•Keyboard interrupt enable register (INTKBIER)

13.8.1 Keyboard Status and Control Register

The keyboard status and control register:

•Flags keyboard interrupt requests

•Acknowledges keyboard interrupt requests

•Masks keyboard interrupt requests

•Contro ls keyboard interrupt trig gering se nsitivity

Bits 7–4 — Not us ed

These read-only bits always read as logic 0s.

KEYF — Keyboard Flag Bit

This read-only bit is set when a keyboard interrupt is pending. Reset

clears the KEYF bit.

1 = Keyboard interrupt pending

0 = No keyboard interrupt pending

Address: $001A

Bit 7654321Bit 0

Read: 0000KEYF0

IMASKK MODEK

Write: ACKK

Reset:00000000

= Unimplemented

Figure 13-3. Keyboard Status and Control Register (INTKBSCR)

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Keyboard Interrupt (KBI)

Technical Data MC68HC908GR8 — Rev 4.0

182 Keyboard Interrupt (KBI) MOTOROLA

ACKK — Keyboard Acknowledge Bit

Writing a logic 1 to this write-only bit clears the keyboard interrupt

request. ACKK always reads as logic 0. R eset clears ACKK.

IMASKK — Keyboard Interrupt Mask Bit

Writing a logic 1 to this read/write bit prevents the output of the

keyboard interrupt mask from generating interrupt requests. Reset

clears the IMASKK bit.

1 = Keyboard int er ru pt re qu ests ma sked

0 = Keyboard int er rupt re qu ests not masked

MODEK — Keyboard Triggering Sensitivity Bit

This read/write bit controls the triggering sensitivity of the keyboard

interrupt pins. Reset clears MODEK.

1 = Keyboard interr upt requests on falling edges and low levels

0 = Keyboard interrupt requests on falling edges only

13.8.2 Keyboard Interrupt Enable Register

The keyboard interrupt enable register enables or disables each port A

pin to operate as a keyboard interrupt pin.

KBIE3–KBIE0 — Keyboard Interrupt Enable Bits

Each of these read/write bits enables the corresponding keyboar d

interrupt pin to latch interrupt requests. Reset clears the keyboard

interrupt enable register.

1 = PTA x pin en abled as keyboard interrupt pin

0 = PTAx pin not enabled as keyboard interrupt pin

Address: $001B

Bit 7654321Bit 0

Read: KBIE3 KBIE2 KBIE1 KBIE0

Write:

Reset: 0000

Figure 13-4. Keyboard Interrupt Enable Register (INTKBIER)

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MC68HC908GR8 — Rev 4.0 Technical Data
MOTOROLA Low-Voltage Inhibit (LVI) 183
 
Technical Data — MC68HC908GR8
Section 14. Low-Vol tage Inhibit (LVI)
14.1  Contents
14.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .183
14.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 83
14.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 84
14.5 LVI Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .187
14.6 LVI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .188
14.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .188
14.2  Introduction
This section de scribes the low-voltage inhibit (LVI) module, which 
monitors the voltage on the VDD pin a nd can for ce a reset whe n the VDD 
voltage falls below th e LVI tr ip falling voltage, VTRIPF.
14.3  Features
Features of the LVI module include:
•Programmabl e LVI reset
•Selectable LVI trip voltage
•Programmabl e stop mode operation
    
  
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Low-Voltage Inhibit (LVI)

Technical Data MC68HC908GR8 — Rev 4.0

184 Low-Voltage Inhibit (LVI) MOTOROLA

14.4 Functional Description

Figure 14-1 shows the structure of the LVI module. The LVI is enabled

out of reset. The LVI module contains a bandgap reference circuit and

compar ator . Cleari ng the LVI power disabl e bit , LVIPW RD, ena bles the

LVI to monitor VDD voltage. Clearing the LVI reset disable bit, LVIRSTD,

enables the LVI module to generate a reset when VDD falls below the trip

point voltage, VTRIPF. Setting the LVI enable in stop mode bit, LVISTOP,

enable s the LVI to operate in stop mode. Setting the LVI 5V or 3V trip

point bit, LVI5OR3 , enable s VTRIPF to be conf ig ur ed for 5V ope r ati o n.

Clearin g t he LVI 5OR3 bi t ena bles VTRIPF to be configured for 3V

operation. The actual trip points are shown in Electrical Specifications.

NOTE: After a powe r-on reset (POR) the LVI’s default mode of operation is 3 V.

If a 5V system is used, the user must set the LVI5OR3 bit to raise the trip

point to 5V operation. Note that this must be done after every POR since

the default will revert back to 3V mode after each POR. If the VDD supply

is below the 5V mode trip voltage but above the 3V mode trip voltage

when POR is released, the part will operate because VTRIPF defaults to

3V mode af ter a POR. So, in a 5V syst em care must be take n to ensure

that VDD is above the 5V mode trip voltage after POR is released.

NOTE: If the user requires 5V mode and sets the LVI5OR3 bit after a POR while

the VDD supply is not above the VTRIPR for 5V mode, the MCU will

immediately go into reset. The LVI in this case will hold the part in reset

until eithe r VDD goes above the rising 5V trip point, VTRIPR, which will

release reset or VDD decreases to approximately 0 V which will re-trigger

the POR and reset the trip point to 3V operation.

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Low-Voltage Inhibit (LVI)

Functional Description

MC68HC908GR8 — Rev 4.0 Technical Data

MOTOROLA Low-Voltage Inhibit (LVI) 185

LVIS TOP, LVIPWRD, LVI5OR3 , and LVIRSTD are in the configuration

LVI’s configuration bits. Once an LVI reset occurs, the MCU remains in

reset unt il VDD rises above a voltage, VTRIPR, which causes the MCU to

exit reset. See Low-Voltage Inhibit ( LVI) Reset for details of the

interaction be tween the SIM and the LVI. The output of the comparator

controls the state of the LVIOUT flag in the LVI status re gister (LVISR).

An LVI reset also drives the RST pin low to provide low-voltage

protection to external peripheral dev ices .

Figure 14-1. LVI Module Block Diagram

LOW VDD

DETECTOR

LVIPWRD

STOP INSTRUCTION

LVISTOP

LVI RESET

LVIOUT

VDD > LVITrip = 0

VDD ≤ LVITrip = 1

FROM CONFIG

VDD

FROM CONFIG

LVIRSTD

LVI5OR3

FROM CONFIG

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Low-Voltage Inhibit (LVI)

Technical Data MC68HC908GR8 — Rev 4.0

186 Low-Voltage Inhibit (LVI) MOTOROLA

14.4.1 Polled LVI Operation

In applications that can operate at VDD leve ls below the VTRIPF level,

software can monitor VDD by polling the LVIOUT bit. In the configuration

and the LVIRSTD bi t must be at logic 1 to di sable LVI resets.

14.4.2 Forced Reset Operation

In applications that require VDD to remain above the VTRIPF level,

enabling LVI resets allows the LVI module to reset the MCU when VDD

falls below the VTRIPF level. In the conf igura tion r egister , the LVIPW RD

and LVIRSTD bits mus t be at logic 0 to enable the LVI mo dule and to

enable LVI resets.

14.4.3 Voltage Hysteresis Protection

Once the LVI has triggered (by having VDD fall below VTRIPF), the LVI

will maintain a reset condition until VDD rises above the rising trip point

voltage, VTRIPR. This prevents a condition in which the MC U is

continually entering and exiting reset if VDD is approxi m ate ly eq ual to

VTRIPF. VTRIPR is greater than VTRIPF by the hysteresis voltage, VHYS.

Addr.Register Name Bit 7654321Bit 0

$FE0C LVI Status Register

(LVISR)

Read: LVIOUT 0000000

Write:

Reset:00000000

= Unimplemented

Figure 14-2. LVI I/O Register Summary

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Low-Voltage Inhibit (LVI)

LVI Status Register

MC68HC908GR8 — Rev 4.0 Technical Data

MOTOROLA Low-Voltage Inhibit (LVI) 187

14.4.4 LVI Trip Selection

The LVI5OR3 bit in the configuration register selects whether the LVI is

configured for 5V or 3V protection.

NOTE: The microcontroller is guaranteed to operate at a minimum supply

voltage. The trip point (VTRIPF [5 V] or VTRIPF [3 V]) may be lower than

this. (See Electrical Specification s for the actual trip point voltages.)

14.5 LVI Status Register

The LVI status register (LVISR) indicates if the VDD voltage was

detected below the VTRIPF level.

LVIOUT — LVI Output Bit

This read-only flag becomes set when the VDD voltage falls below the

VTRIPF trip voltage. See Table 14-1. Reset clears the LVIOUT bit.

Address: $FE0C

Bit 7654321Bit 0

Read: LVIOUT 0000000

Write:

Reset:00000000

= Unimplemented

Figure 14-3. LVI Status Register (LVISR)

Table 14-1. LVIOUT Bit Indication

VDD LVIOUT

VDD > VTRIPR 0

VDD < VTRIPF 1

VTRIPF < VDD < VTRIPR Previous value

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Low-Voltage Inhibit (LVI)

Technical Data MC68HC908GR8 — Rev 4.0

188 Low-Voltage Inhibit (LVI) MOTOROLA

14.6 LVI Interrupts

The LVI module does not generate interrupt requests.

14.7 Low-Power Modes

The STOP an d WAIT instructions put the MCU in low power-

consumption standby modes.

14.7.1 Wait Mode

If enabl ed, the LVI modu le remains active i n wait mode. If enabled to

generate resets, the LVI module can generate a reset and bring the MCU

out of wait mode.

14.7.2 Stop Mode

If enabled in stop mode (LVISTOP set), the LVI module remains active

in stop mode. If enabled to generate resets, the LVI module can

generate a reset and bring the MCU out of stop mode.

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MC68HC908GR8 — Rev 4.0 Technical Data

MOTOROLA Monitor ROM (MON) 189

Technical Data — MC68HC908GR8

Section 15. Monitor ROM (MON)

15.1 Contents

15.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .189

15.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 89

15.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 90

15.5 Security. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .202

15.2 Introduction

This section describes the monitor ROM (MON) and the monito r mode

entry methods. The monitor ROM allows complete testing of the MCU

through a single-wire interface with a host computer. Monitor mode entry

can be achi eved without use of the higher te st voltag e, VTST, as long as

vector addresses $FFFE and $FFFF are blank, thus reducing the

hardware requirements for in-circu it pro gramming.

15.3 Features

Features of the monitor ROM includ e:

•Normal user-mode pin functionality

•One pin dedicated to serial communication between monitor ROM

and host comp ute r

•Standard ma rk/space non-return-to-zero (NRZ) commun ication

with host comp ute r

•Execution of code in RAM or FLASH

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Monitor ROM (MON)

Technical Data MC68HC908GR8 — Rev 4.0

190 Mon itor ROM (MON) MOTOROLA

•FLASH memory security feature(1)

•FLASH memory programming interface

•Enhanced PLL (phase-locked loop) option to allow use of external

32.768-kHz crystal to generate internal frequency of 2.4576 MHz

•310 byte monitor ROM code size ($FE20 to $FF55)

•Monitor mode entry without high volta ge, VTST, if reset vector is

blank ($FFFE and $FFFF contain $FF)

•Standard monitor mode entry if high voltage, VTST, is applied to

IRQ

15.4 Functional Description

The monitor ROM re ceives and executes commands from a host

computer. Figure 15-1 shows an example c ircuit used to enter monitor

mode and communicat e with a host computer via a standard RS-232

interface.

Simple monitor commands can access any memory address. In monitor

mode, the MCU can execute code downloaded into RAM by a host

compute r while most MCU pins retain normal operating mode functions.

All communication between the host computer and the MCU is through

the PTA0 pin. A level-sh ifting and multiplexing interface is required

between PTA0 and the host computer . PTA0 is used in a wired-OR

configuration and requires a pullup resistor.

1. No security feature is absolutely se cure . Howe ve r, Moto rola ’s strategy is to make reading or

copying the FLASH difficult for unauthoriz ed users.

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Monitor ROM (MON)

Functional Description

MC68HC908GR8 — Rev 4.0 Technical Data

MOTOROLA Monitor ROM (MON) 191

Figure 15-1. Monitor Mode Circuit

DDA

MC145407

MC74HC125

RST

IRQ

DDA

CGMXFC

OSC1

OSC2

PTA0

10 k

Ω

0.1

10 k

Ω

DB-25

F10

0.1

PTB0

PTB1

68HC08

$FFFF

$FFFE

RESET VECTORS

SSAD

REFL

SSA

DDAD

REFH

6–30 pF

32.768 kHz XTAL

10 M

Ω

SW2

SW4

SW3

(SEE NO TE 2)

(SEE NOTES 2

(SEE NOTE 2)

(SEE NO TE 3)

Notes:

1. SW2, SW3, and SW4: Position C — Enter monitor mode using external oscillator.

SW2, SW3, and SW4: Position D — Enter monitor mode using external XTAL and internal PLL.

2. See . Monitor Mode Signal Requirements and Options for IRQ voltage level requirements.

10 k

0.01

0.033 µF

TST

330 k

Ω

AND 3)

PTA1

10 k

Ω

10 k

Ω

10 k

Ω

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Monitor ROM (MON)

Technical Data MC68HC908GR8 — Rev 4.0

192 Mon itor ROM (MON) MOTOROLA

The monitor code has been updated from previous versions to allow

enabling the PLL to generate the internal clock, provided the reset vector

is blank, when the device is being clocked by a low-frequency crystal.

This addition, which is enabled when IRQ is held low out of rest, is

intended to support serial communication/ programming at 9600 baud in

monitor mode by stepping up the external freque ncy (as sumed to be

32.768 kHz) by a fixed amount to generate the desired internal

frequency (2.4576 MHz). Since this feature is enabled only when IRQ is

held low out of reset, it cannot be used when the reset vector is not blank

because entry into monitor mode in this case requires VTST on IRQ.

15.4.1 Entering Monitor Mode

Table 15-1 shows the pin conditi on s for ent er i ng mo ni to r mo de . As

specif ied in th e table, monitor mode may be en tered after a power-on

reset (POR) and will allow communication at 9600 baud provided one of

the following se ts of conditions is met:

1. If $FFFE and $FFFF contain values not cared:

–The external clock is 9.8304 MHz

– IRQ = VTST (PLL off)

2. If $FFFE and $FFFF contain $FF, blank state:

–The external clock is 9.8304 MHz

– IRQ = VDD (thi s can be i mpl em en ted thr o ugh th e i nt erna l IRQ

pullup; PLL of f)

3. If $FFFE and $FFFF contain $FF, blank state:

–The external clock is 32.768 kHz (crystal)

– IRQ = VSS (this setting i nitiates the PLL to boost the external

32.768 kHz to an internal bus frequency of 2.4576 MHz)

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Monitor ROM (MON)

Functional Description

MC68HC908GR8 — Rev 4.0 Technical Data

MOTOROLA Monitor ROM (MON) 193

If entering monitor mode with VTST applied on IRQ (condition se t 1), the

CGMOUT frequency is equal to the CGMXCLK frequency and the OSC1

input directly generates internal bus clocks. In this case, the OSC1

signal must have a 50% duty cycle at maximum bus frequency.

If enter ing monit or mode wit hout high vo ltage applied on IRQ (condition

set 2 or 3, where applied voltage is either VDD or VSS), then all port B pin

Table 15-1. Monitor Mode Signal Requirements and Options

IRQ RESET $FFFE/

$FFFF PLL PTB0 PTB1 External

Clock(1) CGMOUT Bus

Freq COP

For Serial

Communication Comment

PTA0 PTA1 Baud

Rate(2) (3)

X GND X X X X X 0 0 Disabled X X 0 No operati o n until

reset goes high

VTST

VDD

VTST

XOFF1 0

9.8304

MHz 4.9152

MHz 2.4576

MHz Disabled

1 0 9600 PTB0 and PTB1

voltages only

required if

IRQ =V

TST

X1DNA

VDD VDD $FFFF OFF X X 9.8304

MHz 4.9152

MHz 2.4576

MHz Disabled 1 0 9600 External frequency

always divided by

X1DNA

GND VDD $FFFF ON X X 32.768

kHz 4.9152

MHz 2.4576

MHz Disabled 1 0 9600 PLL enabled (BCS

set) in monitor

code

X1DNA

VDD

GND VTST $FFFF OFF X X X ——Enabled X X —

Enters user mode

— will encounter

an illegal address

reset

VDD

GND

VDD

VTST

Not

$FFFF OFF X X X ——Enabled X X —Enters user mode

Notes:

1. External clock is derived by a 32.768 kHz crystal or a 9.8304 MHz off-chip oscillator

2. PTA0 = 1 if serial communication; PTA0 = X if parallel communication

3. PTA1 = 0 → serial, PTA1 = 1 → parallel communi cation for secur ity code entry

4. DNA = does not apply, X = don’t care

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Monitor ROM (MON)

Technical Data MC68HC908GR8 — Rev 4.0

194 Mon itor ROM (MON) MOTOROLA

requirements and conditions, are not in effect. This is to reduce circuit

requirements when performing in-circuit programming.

NOTE: If the reset vector is blank and monitor mode is entered, the chip will see

an additional reset cycle after the initial POR reset. Once the part has

been programmed, the traditional method of applying a voltage, VTST, to

IRQ must be used to enter monitor mode.

The COP module is disabled in monitor mode based on these

conditions:

•If monitor mode w as ent er ed as a result of the re set vecto r being

blank (condition set 2 or 3), the COP is always disabled regardless

of the state of IRQ or R ST.

•If monitor mode was entered with VTST on IRQ (condition set 1),

then the COP is disabled as long as VTST is applied to eithe r IRQ

or RST.

The second c ondition s tates that as long as VTST is maintained on the

IRQ pin after entering monitor mode, or if VTST is appli ed to RST after

the initial reset to get into monitor mode (when VTST was applied to IRQ),

then the COP will be disabled. In the latter situation, after VTST is applied

to the RS T pi n, VTST can be removed from the IRQ pin in th e in teres t of

freeing the IRQ for normal functionality in monitor mode .

Figure 15-2 shows a si mplified d iagram of the monitor m ode entry wh en

the reset vector is blank and just 1 x VDD voltage is applied to the IRQ

pin. An exte rnal oscillator o f 9.8304 MHz is required for a baud rate of

9600, as the internal bus frequency is automatically set to the external

frequency divided by four.

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Monitor ROM (MON)

Functional Description

MC68HC908GR8 — Rev 4.0 Technical Data

MOTOROLA Monitor ROM (MON) 195

Figure 15-2. Low-Voltage Monitor Mode Entry Flowchart

Enter monitor mode with pin configuration shown in Figure 15-1 by

pulling RST low and then high. The rising edge of RST latches monitor

mode. Once monitor mode is la tched, the values on the specified pins

can change.

Once out of reset, the MCU waits for the host to send eight security

bytes. (See Security.) After the security bytes, the MCU sends a break

signal (10 consecutive logic 0s) to the host, indicating that it is ready to

receive a co mmand.

NOTE: The PTA1 pin must remain at logic 0 for 24 bu s cycles after the RST pi n

goes high to enter monitor mode properly.

In monitor mode, the MCU uses different vectors for reset, SWI

(software interrupt), and break interrupt than those for user mode. The

alterna te vectors are in the $FE page instead of t he $FF page and allow

code execution from the internal mo nitor firmware instead of user code.

NOTE: Exiting monitor mode after it has been initiated by having a blank reset

vector requires a power-o n reset. Pulling RST low will not exit monitor

mode in this situation.

IS VECTOR

BLANK?

POR

TRIGGERED?

NORMAL USER

MODE

MON ITOR MO DE

EXECUTE

MONITOR

CODE

YES

POR RESET

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Monitor ROM (MON)

Technical Data MC68HC908GR8 — Rev 4.0

196 Mon itor ROM (MON) MOTOROLA

Table 15-2 summarizes the differences between user mode and monitor

mode.

15.4.2 Data Format

Communication with the monitor ROM is in standard non-return-to-zero

(NRZ) mark /space data fo rmat. Transmit and receive bau d ra tes must

be identical.

Figure 15-3. Monitor Data Format

15.4.3 Break Signal

A start bit (logic 0) followed by nine logic 0 bits is a break signal. When

the monitor receiv es a br eak signal, it drives the PTA0 pin high for t he

duration of two bits and then echoes back the break signal.

Figure 15-4. Break Transaction

Table 15-2. Mode Differences

Modes

Functions

Reset

Vector

High

Reset

Vector

Low

Break

Vector

High

Break

Vector

Low

SWI

Vector

High

SWI

Vector

Low

User $FFFE $FFFF $FFFC $FFFD $FFFC $FFFD

Monitor $FEFE $FEFF $FEFC $FEFD $FEFC $FEFD

BIT 5

START

BIT BIT 1

STOP

BIT

START

BIT

BIT 2 BI T 3 BIT 4 BIT 7BIT 0 BIT 6

01234567 0 1 2 3 4 5 6 7

MISSIN G ST O P BI T 2-STOP BIT DELAY BEFORE ZERO ECHO

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Monitor ROM (MON)

Functional Description

MC68HC908GR8 — Rev 4.0 Technical Data

MOTOROLA Monitor ROM (MON) 197

15.4.4 Baud Rate

The communication baud rate is controlled by the crystal frequency upon

entry into mo nitor mode. The divide by ratio is 1024.

If monitor mode was entered with VDD on IRQ, then the divid e by ra tio is

also set at 1024. If monitor mode was entered with VSS on IRQ, then the

internal PLL steps up the ex ternal frequency, presumed to be 32.768

kHz, to 2.4 576 MHz. The se latter two condit ions f or monito r mode entr y

require that the reset vector is blank.

Table 15-3 lists extern al fr equencies required to achieve a standard

baud rate of 9600 BPS. Other standard baud rates can be accomplished

using proportionally higher or lower frequency generators. If using a

crystal as the clock source, be aware of the upper frequency limit that the

internal clock module can handl e. See 5.0 V Control Timing and 3.0 V

Control Timing for this limit.

15.4.5 Commands

The monitor ROM firmware uses these commands:

•READ (read memory)

•WRITE (write memory)

•IREAD (indexed read)

•IWRITE (indexed write)

•READSP (read stack pointer)

•RUN (run user program)

Table 15-3. Monitor Baud Rate Selection

External

Frequency IRQ Internal

Frequency Baud Rate

(BPS)

9.8304 MHz VTST 2.4576 MHz 9600

9.8304 MHz VDD 2.4576 MHz 9600

32.768 kHz VSS 2.4576 MHz 9600

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Monitor ROM (MON)

Technical Data MC68HC908GR8 — Rev 4.0

198 Mon itor ROM (MON) MOTOROLA

The monitor ROM firmware echoes each received byte back to the PTA0

pin for error checking. An 1 1-bit delay at the end of each c ommand

allows the host to send a break character to cancel the command. A

delay of two bit times occurs before each echo and before READ,

IREAD, or READSP data is returned. The data returned by a read

command appears after the echo of the last byte of the command.

NOTE: Wait one bit time after each echo before sending the next byte.

Figure 15-5. Read Transaction

Figure 15-6. Write Transaction

READREAD

ECHO

FROM

HOST

ADDRESS

HIGH ADDRESS

LOW ADDRESS

LOW DATA

RETURN

13, 21144

Notes:

2 = Data return delay, 2 bit times

3 = Cancel command delay, 11 bit times

4 = Wait 1 bit time before sending next byte.

1 = Echo delay, 2 bit times

WRITE

ECHO

FROM

HOST

ADDRESS

HIGH ADDRESS

LOW ADDRESS

LOW DATA DATA

Notes:

2 = Cancel command delay, 11 bit times

3 = Wait 1 bit time before sending next byte.

113113332, 3

1 = Echo delay, 2 bit times

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Monitor ROM (MON)

Functional Description

MC68HC908GR8 — Rev 4.0 Technical Data

MOTOROLA Monitor ROM (MON) 199

A brief description of each monitor mode command is given in Table 15-

4 through Table 15-9.

Table 15-4. READ (Read Memory) Command

Description Read byte from memory

Operand 2-byte address in high-byte:low-byte order

Data

Returned Returns contents of specified address

Opcode $4A

Command Sequence

Table 15-5. WRITE (Write Memory) Command

Description Write byte to memory

Operand 2-byte address in high-byte:low-byte order; low byte followed by

data byte

Data

Returned None

Opcode $49

Command Sequence

READREAD

ECHO

SENT TO

MONITOR

ADDRESS

HIGH ADDRESS

LOW DATA

RETURN

ADDRESS

LOW

WRITEWRITE

ECHO

FROM

HOST

ADDRESS

HIGH ADDRESS

LOW ADDRESS

LOW DATA DATA

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Technical Data MC68HC908GR8 — Rev 4.0

200 Mon itor ROM (MON) MOTOROLA

Table 15-6. IREAD (Indexed Read) Comman d

Description Read next 2 bytes in memory from last address accessed

Operand 2-byte address in high byte:low byte order

Data

Returned Returns contents of next two addresses

Opcode $1A

Command Sequence

Table 15-7. IWRITE (Indexed Write) Command

Description Write to last address accessed + 1

Operand Single data byte

Data

Returned None

Opcode $19

Command Sequence

IREAD

ECHO

FROM

HOST

DATA

RETURN

DATA

IWRITEIWRITE

ECHO

FROM

HOST

DATA DATA

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Monitor ROM (MON)

Functional Description

MC68HC908GR8 — Rev 4.0 Technical Data

MOTOROLA Monitor ROM (MON) 201

A sequence of IREAD or IWRITE commands can access a block of

memory sequentially over the full 64K byte memory map.

Table 15-8. READSP (Read Stack Pointer) Command

Description Reads stack pointer

Operand None

Data

Returned Returns incremented stac k pointe r value (SP + 1 ) in hig h-by te:l ow-

byte order

Opcode $0C

Command Sequence

Table 15-9. RUN (Run User Program) Command

Description Executes PULH and RTI instructions

Operand None

Data

Returned None

Opcode $28

Command Sequence

READSPREADSP

ECHO

FROM

HOST

RETURN

HIGH LOW

RUNRUN

ECHO

FROM

HOST

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Monitor ROM (MON)

Technical Data MC68HC908GR8 — Rev 4.0

202 Mon itor ROM (MON) MOTOROLA

The MCU executes the SWI and PSHH instructions when it enters

monitor mode. The RUN command tells the MCU to execute the PULH

and RTI instructions. Before sending the RUN command, the host can

modify the stacked CP U registers to prepare to run the host prog ram.

The READSP command returns the incremented stack pointer value,

SP + 1. The high and low bytes of the program counter are at addresses

SP+5 and SP+6.

Figure 15-7. Stack Pointer at Monitor Mode Entry

15.5 Security

A security feature discourages unauthorized reading of FLASH locations

while in monitor mode. The host can bypass the security feature at

monitor mode entry by sending eight security bytes that match the bytes

at locations $FFF6–$FFFD. Locations $FFF6–$FFFD contain user-

define d dat a.

NOTE: Do not leave locations $FFF6–$FFFD blank. For security reasons, they

should be prog rammed even if they are not used for vectors.

During monitor mode en try, the MCU waits after the power-on reset for

the host to send the eight security bytes on pin PTA0. If the received

bytes match those at locations $FFF6–$FFFD, the host bypasses the

security feature and can read all FLASH locations and execute code

from FLASH. Se curity remains b ypassed un til a po wer-on reset occurs.

If the reset was not a power-on reset, security remains bypassed and

security code entry is not required. (See Figure 15-8.)

CONDITION CODE REGISTER

ACCUMULATOR

LOW BYTE OF INDEX REGISTER

HIGH BYTE OF PROGRAM COUNTER

LOW BYTE OF PROGRAM COUNTER

SP + 1

SP + 2

SP + 3

SP + 4

SP + 5

SP + 6

HIGH BYTE OF INDEX REGISTER

SP + 7

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Monitor ROM (MON)

Security

MC68HC908GR8 — Rev 4.0 Technical Data

MOTOROLA Monitor ROM (MON) 203

Figure 15-8. Monitor Mode Entry Timing

Upon power-on reset, if th e received bytes of the security code do not

match the data at locations $FFF6–$FFFD, the host fails to bypass the

security feature . The MCU remains in monitor mode, but reading a

FLASH location returns an invalid value and trying to execute code from

FLASH causes an illegal address reset. After receiving the eight security

bytes from the host, the MCU transmits a break character, signifying that

it is ready to receive a command.

NOTE: The MCU does not t ransmi t a break ch aracter u ntil af ter the ho st sends

the eight security bytes.

To determine whether the security co de entered is correct, check to see

if bit 6 of R AM address $40 is set. If it is, then the correct security code

has been entered and FLAS H can be acces sed.

BYTE 1

BYTE 1 ECHO

BYTE 2

BYTE 2 ECHO

BYTE 8

BYTE 8 ECHO

COMMAND

COMMAND ECHO

PA0

PA1

RST

VDD

4096 + 32 CGMXCLK CYCLES

24 BUS CYCLE S

256 BUS CYCLES (MINIMUM)

141121

BREAK

NOTES:

2 = Data return delay, 2 bit times

4 = Wait 1 bit time before sending next byte.

FROM HOST

FROM MCU

1 = Echo delay, 2 bit times

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Monitor ROM (MON)

Technical Data MC68HC908GR8 — Rev 4.0

204 Mon itor ROM (MON) MOTOROLA

If the security sequence fails, the device can be reset and brought up in

monitor mode to attempt another en tr y. After failin g the security

sequence, the FLASH mode can also be bulk erased by executing an

erase routine that was downloaded into internal RAM. The bulk erase

operation clears the secur ity code locations so that all eight security

bytes become $FF (blank).

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MC68HC908GR8 — Rev 4.0 Technical Data
MOTOROLA Input/Out put Ports  (I/O) 20 5
 
Technical Data — MC68HC908GR8
Section 16. Input/Output Ports (I/O)
16.1  Contents
16.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .205
16.3 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .209
16.4 Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .213
16.5 Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 16
16.6 Port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 20
16.7 Port E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .225
16.2  Introduction
Twenty one (21) bidirectional input-output (I/O) pins form five parallel 
ports. All I/O pins are programmable as inputs or outputs. All individual 
bits within port A, port C, and port D are software configurable with pullup 
devices if configured as input port bits . The pullup devices are 
automatically and dynamically disabled wh en a port bit is switched to 
output mode.
NOTE: Connect an y unused I/O pins to  an appropriat e logic level, e ither VDD or 
VSS. Although the I/O ports do not require termination for proper 
operation, termination reduces excess current consumption and the 
possibility of el ectrostatic damage. 
    
  
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Input/Output Ports (I/O)

Technical Data MC68HC908GR8 — Rev 4.0

206 Input/O ut put Ports (I/O) MOTORO LA

Addr.Register Name Bit 7654321Bit 0

$0000 Port A Data Register

(PTA)

PTA3 PTA2 PTA1 PTA0

Write:

Reset: Unaffected by reset

$0001 Port B Data Register

(PTB)

Read: 0 0 PTB5 PTB4 PTB3 PTB2 PTB1 PTB0

Write:

Reset: Unaffected by reset

$0002 Port C Data Register

(PTC)

PTC1 PTC0

Write:

Reset: Unaffected by reset

$0003 Port D Data Register

(PTD)

Read: 0 PTD6 PTD5 PTD4 PTD3 PTD2 PTD1 PTD0

Write:

Reset: Unaffected by reset

$0004 Data Direction Register A

(DDRA)

DDRA3 DDRA2 DDRA1 DDRA0

Write:

Reset:00000000

$0005 Data Direction Register B

(DDRB)

Read: 0 0 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0

Write:

Reset:00000000

$0006 Data Direction Register C

(DDRC)

DDRC1 DDRC0

Write:

Reset:00000000

$0007 Data Direction Register D

(DDRD)

Read: 0 DDRD6 DDRD5 DDRD4 DDRD3 DDRD2 DDRD1 DDRD0

Write:

Reset:00000000

= Unimplemented

Figure 16-1. I/O Port Register Summary

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Input/Output Ports (I/O)

Introduction

MC68HC908GR8 — Rev 4.0 Technical Data

MOTOROLA Input/Out put Ports (I/O) 20 7

$0008 Port E Data Register

(PTE)

PTE1 PTE0

Write:

Reset: Unaffected by reset

$000C Data Direction Register E

(DDRE)

DDRE1 DDRE0

Write:

Reset:00000000

$000D Port A Input Pullup Enable

PTAPUE3 PTAPUE2 PTAPUE1 PTAPUE0

Write:

Reset:00000000

$000E Port C Input Pullup Enable

PTCPUE1 PTCPUE0

Write:

Reset:00000000

$000F Port D Input Pullup Enable

Read: 0 PTDPUE6 PTDPUE5 PTDPUE4 PTDPUE3 PTDPUE2 PTDPUE1 PTDPUE0

Write:

Reset:00000000

Addr.Register Name Bit 7654321Bit 0

= Unimplemented

Figure 16-1. I/O Port Register Summary (Continued)

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Input/Output Ports (I/O)

Technical Data MC68HC908GR8 — Rev 4.0

208 Input/O ut put Ports (I/O) MOTORO LA

Table 16-1. Port Control Register Bits Summary

Port Bit DDR Module Control Pin

0 DDRA0

KBD

KBIE0 PTA0/KBD0

1 DDRA1 KBIE1 PTA1/KBD1

2 DDRA2 KBIE2 PTA2/KBD2

3 DDRA3 KBIE3 PTA3/KBD3

--- - --

0 DDRB0

ADC

CH0 PTB0/ATD0

1 DDRB1 CH1 PTB1/ATD1

2 DDRB2 CH2 PTB2/ATD2

3 DDRB3 CH3 PTB3/ATD3

4 DDRB4 CH4 PTB4/ATD4

5 DDRB5 CH5 PTB5/ATD5

--- - --

0 DDRC0 PTC0

1 DDRC1 PTC1

--- --

0 DDRD0

SPI

PTD0/SS

1 DDRD1 PTD1/MISO

2 DDRD2 PTD2/MOSI

3 DDRD3 PTD3/SPSCK

4 DDRD4 TIM1 PTD4/T1CH0

5 DDRD5 PTD5/T1CH1

6 DDRD6 TIM2 PTD6/T2CH0

--- --

E0 DDRE0 SCI PTE0/TxD

1 DDRE1 PTE1/RxD

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Input/Output Ports (I/O)

Port A

MC68HC908GR8 — Rev 4.0 Technical Data

MOTOROLA Input/Out put Ports (I/O) 20 9

16.3 Port A

Port A is an 4- bit special- function po rt that sh ares all four of its pins wi th

the keyboard interrupt (KBI) mod ule . Port A also has software

configurable pullup devices if configured as an input port.

16.3.1 Port A Data Register

The por t A data registe r (P TA) con tains a data latch for each o f the fo ur

port A pins.

PTA3–PTA0 — Port A Data Bits

These read/write bits ar e soft ware pr ogrammable. Data direction of

each port A pin is under the control of the corr esponding bit in data

directi on re gister A. Reset has no effect on por t A data.

KBD3–KBD0 — Keyboard Inputs

The keyboard interrupt enable bits, KBIE3–KBIE0, in the keyboard

interrupt control register (KBICR) enable the port A pins as external

interrupt pins. See Keyboard Inte rrupt (KBI).

Address: $0000

Bit 7654321Bit 0

PTA3 PTA2 PTA1 PTA0

Write:

Reset: Unaffected by reset

Alternate

Function: KBD3 KBD2 KBD1 KBD0

Figure 16-2. Port A Data Register (PTA)

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Input/Output Ports (I/O)

Technical Data MC68HC908GR8 — Rev 4.0

210 Input/O ut put Ports (I/O) MOTORO LA

16.3.2 Data Direction Register A

Data dir ection r egister A ( DDRA) det ermines w hether each port A pi n is

an in put or an outpu t. Writi ng a lo gic 1 to a DDRA bit enab les th e outpu t

buff er for the corres ponding port A pin; a logic 0 dis ables the output

buffer.

DDRA3–DDRA0 — Data Direction Register A Bits

These read/write bits control port A data direction. Reset clears

DDRA3–DDRA0, configuring all port A pins as inputs.

1 = Corr esponding port A pin configured as output

0 = Corr esponding po rt A pin config ured as input

NOTE: Avoid glitch es on port A pi ns by writing to the port A dat a register bef ore

changin g data direction register A bits from 0 to 1.

Figure 16-4 shows the port A I/O logic.

Address: $0004

Bit 7654321Bit 0

DDRA3 DDRA2 DDRA1 DDRA0

Write:

Reset:00000000

Figure 16-3. Data Direc tion Register A (DDRA)

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Input/Output Ports (I/O)

Port A

MC68HC908GR8 — Rev 4.0 Technical Data

MOTOROLA Input/Out put Ports (I/O) 21 1

Figure 16-4. Port A I/O Circuit

When bit DDRAx is a logic 1, reading address $0000 reads the PTAx

data latch. When bit DDRAx is a logic 0, reading address $0000 reads

the voltage level on the pin. The data latch can always be written,

regardless of the state of its data direction bit. Table 16-2 summarizes

the operat ion of the port A pins .

READ DDRA ($0004)

WRITE DDRA ($0004)

RESET

WRITE PTA ($0000)

READ PTA ($0000)

PTAx

DDRAx

PTAx

INTERNAL DATA BUS

PTAPUEx INTERNAL

PULLUP

DEVICE

Table 16-2. Port A Pin Functions

PTAPUE Bit DDRA Bit PTA Bit I/O Pin Mode Accesses to DDRA Accesses to PTA

Read/Write Read Write

X(1) Input, VDD(4) DDRA3–DDRA0 Pin PTA3–PTA0(3

)

00X

Input, Hi-Z(2) DDRA3–DDRA0 Pin PTA3–PTA0(3

)

X 1 X Output DDRA3–DDRA0 PTA3–PTA0 PTA3–PTA0

NOTES:

1. X = Don’t care

2. Hi-Z = High impedance

3. Writing affects data register, but does not affect input.

4. I/O pin pulled up to VDD by internal pullup device

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Input/Output Ports (I/O)

Technical Data MC68HC908GR8 — Rev 4.0

212 Input/O ut put Ports (I/O) MOTORO LA

16.3.3 Port A Input Pullup Enable Register

The port A input pullup enable register (PTAPUE) contains a software

configurable pullup device for each of the four port A pins. Each bit is

individually configu r able an d requires that the data direct ion regist er,

DDRA, bit be configu red as an input. Each pullup is automatically and

dyna mically dis abled when a port bit’s DDRA is co nfigur ed for output

mode.

PTAPUE3–PTAPUE0 — Port A Input Pullup Enable Bits

These writeable bits are software programmable to enable pullup

devices on an inpu t port bit .

1 = Corr esponding po rt A pin configured to have internal pullu p

0 = Corresponding port A pin has internal pullup disconnected

Address: $000D

Bit 7654321Bit 0

PTAPUE3 PTAPUE2 PTAPUE1 PTAPUE0

Write:

Reset:00000000

Figure 16-5. Port A Input Pullup Enable Register (PTAPUE)

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Input/Output Ports (I/O)

Port B

MC68HC908GR8 — Rev 4.0 Technical Data

MOTOROLA Input/Out put Ports (I/O) 21 3

16.4 Port B

Port B is an 6-bit special-function port that shares all six of its pins with

the analog-to-digital convert er (ADC) module.

16.4.1 Port B Data Register

The port B data register (PTB) contains a data latch for each of the six

port pins.

PTB5–PTB0 — Port B Data Bits

These read/write bi ts are software-programmable. Data direction of

each port B pin is under the control of the corr esponding bit in data

directi on re gister B. Reset has no effect on por t B data.

AD5–AD0 — Analog-to-Digital Input Bits

AD5–AD0 are pins used for the input channels to the analog-to-digital

converter module. The channel select bits in the ADC status and

control register define which port B pin will be used as an ADC input

and overrides any control from the port I/O logic by forcing that pin as

the input to the analog circuitry.

NOTE: Care must be taken when reading p ort B while applying analog voltages

to AD5–AD0 pins. If the appropriate ADC channel is not enabled,

excessive current drain may occur if analog voltages are applied to the

PTBx/ADx pin, while PTB is read as a digital input. Those ports not

selected as analog input channels are considered digital I/O ports.

NOTE: PTB4 and 5 are not available in a 28-pin DIP and SOIC package

Address: $0001

Bit 7654321Bit 0

Read: 0 0 PTB5 PTB4 PTB3 PTB2 PTB1 PTB0

Write:

Reset: Unaffected by reset

Alternate

Function: AD5 AD4 AD3 AD2 AD1 AD0

Figure 16-6. Port B Data Register (PTB)

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Input/Output Ports (I/O)

Technical Data MC68HC908GR8 — Rev 4.0

214 Input/O ut put Ports (I/O) MOTORO LA

16.4.2 Data Direction Register B

Data dir ection r egister B ( DDRB) det ermines w hether each port B pi n is

an in put or an outpu t. Writi ng a lo gic 1 to a DDRB bit enab les th e outpu t

buff er for the corres ponding port B pin; a logic 0 dis ables the output

buffer.

DDRB5–DDRB0 — Data Direction Register B Bits

These read/write bits control port B data direction. Reset clears

DDRB5–DDRB0], conf iguring all po rt B pins as inputs.

1 = Corr esponding port B pin configured as output

0 = Corr esponding po rt B pin config ured as input

NOTE: Avoid glitch es on port B pi ns by writing to the port B dat a register bef ore

changin g data direction register B bits from 0 to 1.

NOTE: For those devices packaged in a 28-pin DIP and SOIC package, PTB5,4

are not connected. Set DDRB5,4 to a 1 to configure PTB5,4 as outputs.

Figure 16-8 shows the port B I/O logic.

Address: $0005

Bit 7654321Bit 0

Read: 0 0 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0

Write:

Reset:00000000

Figure 16-7. Data Direc tion Register B (DDRB)

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Input/Output Ports (I/O)

Port B

MC68HC908GR8 — Rev 4.0 Technical Data

MOTOROLA Input/Out put Ports (I/O) 21 5

Figure 16-8. Port B I/O Circuit

When bit DDRBx is a logic 1, reading address $0001 reads the PTBx

data latch. When bit DDRBx is a logic 0, reading address $0001 reads

the voltage level on the pin. The data latch can always be written,

regardless of the state of its data direction bit. Table 16-3 summarizes

the operation of the port B pins .

READ DDRB ($0005)

WRITE DDRB ($0005)

RESET

WRITE PTB ($0001)

READ PTB ($0001)

PTBx

DDRBx

PTBx

INTERNAL D ATA B U S

Table 16-3. Port B Pin Functions

DDRB Bit PTB Bit I/O Pin Mode

Accesses

to DDRB Accesses to PTB

Read/Write Read Write

0X(1) Input, Hi-Z(2) DDRB5–DDRB0 Pin PTB5–PTB0(3)

1 X Output DDRB5–DDRB0 PTB5–PTB0 PTB5–PTB0

Notes:

1. X = Don’t care

2. Hi-Z = High impedance

3. Writing affects data register, but does not affect input.

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Input/Output Ports (I/O)

Technical Data MC68HC908GR8 — Rev 4.0

216 Input/O ut put Ports (I/O) MOTORO LA

16.5 Port C

Port C is a 2-bit, general-purpose bidirectional I/O port. Port C also has

software configurable pullup devices if co nfigur ed as an input port.

16.5.1 Port C Data Register

The port C data r egister (PTC) cont ains a data latch for each of th e two

port C pins.

PTC1–PTC0 — Port C Data Bits

These read/write bi ts are software-programmable. Data direction of

each port C pin is under the control of the corresponding bit in data

direction register C. Reset has no effect on port C data.

NOTE: PTC is not available in a 28-pin DIP and SOIC package

Address: $0002

Bit 7654321Bit 0

PTC1 PTC0

Write:

Reset: Unaffected by reset

= Unimplemented

Figure 16-9. Port C Data Register (PTC)

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Input/Output Ports (I/O)

Port C

MC68HC908GR8 — Rev 4.0 Technical Data

MOTOROLA Input/Out put Ports (I/O) 21 7

16.5.2 Data Direction Register C

Data direction register C (DDRC) determines whether each port C pin is

an inpu t or an output. Writ ing a logic 1 to a DDRC bi t enables the output

buffer for the corresponding port C pin; a logic 0 disables the output

buffer.

DDRC1–DDRC0 — Data Direction Register C Bits

These read/write bits control port C data direction. Reset clears

DDRC1–DDRC0, configuring all port C pins as inputs.

1 = Corresponding port C pin configured as output

0 = Corresponding port C pin configured as input

NOTE: Avoid gl itches on port C pins by wr iting to the port C data re gister be fore

changing data direction register C bits from 0 to 1.

Figure 16-11 shows the port C I/O logic.

NOTE: For those devices packaged in a 28-pin DIP and SOIC package, PTC1,0

are not connected. Set DDRC1,0 to a 1 to configure PTC1,0 as outputs.

Address: $0006

Bit 7654321Bit 0

DDRC1 DDRC0

Write:

Reset:00000000

= Unimplemented

Figure 16-10. Data Direction Register C (DDRC)

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Input/Output Ports (I/O)

Technical Data MC68HC908GR8 — Rev 4.0

218 Input/O ut put Ports (I/O) MOTORO LA

Figure 16-11. Port C I/O Circuit

When bit DDRCx is a logic 1, rea din g address $0002 reads the PTCx

data latch. When bit DDRCx is a logic 0, reading address $0002 reads

the voltage level on the pin. The data latch can always be written,

regardless of the state of its data direction bit. Table 16-4 summarizes

the operation of the port C pins.

READ DDRC ($0006)

WRITE DDRC ($0006)

RESET

WRITE PTC ($0002)

READ PTC ($0002)

PTCx

DDRCx

PTCx

INTERNAL D ATA B U S

INTERNAL

PTCPUEx

PULLUP

DEVICE

Table 16-4. Port C Pi n Functions

PTCPUE Bit DDRC Bit PTC Bit I/O Pin Mode Accesses to DDRC Accesses to PTC

Read/Write Read Write

X(1) Input, VDD(4) DDRC1–DDRC0 Pin PTC1–PTC0(3)

00X

Input, Hi-Z(2) DDRC1–DDRC0 Pin PTC1–PTC0(3)

X 1 X Output DDRC1–DDRC0 PTC1–PTC0 PTC1–PTC0

Notes:

1. X = Don’t care

2. Hi-Z = High impedance

3. Writing affects data register, but does not affect input.

4. I/O pin pulled up to VDD by internal pullup device.

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Input/Output Ports (I/O)

Port C

MC68HC908GR8 — Rev 4.0 Technical Data

MOTOROLA Input/Out put Ports (I/O) 21 9

16.5.3 Port C Input Pullup Enable Register

The port C input pullup enable regi ster (PTCPUE) contain s a softw are

configurable pullup device for each of the two port C pins. Each bit is

individually configu r able an d requires that the data direct ion regist er,

DDRC, bit be configured as an inpu t. Each pullup is automatically and

dyna mically dis abled when a port bit’s DDRC is configured for output

mode.

PTCPUE1–PTCPUE0 — Port C Input Pullup Enable Bits

These writeable bits are software programmable to enable pullup

devices on an inpu t port bit .

1 = Corresponding port C pin configured to have internal pullup

0 = Corresponding port C pin internal pullup disconnected

Address: $000E

Bit 7654321Bit 0

Read: 0 0 0 0 0 0 PTCPUE1 PTCPUE0

Write:

Reset:00000000

= Unimplemented

Figure 16-12. Port C Input Pullup Enable Register (PTCPUE)

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Input/Output Ports (I/O)

Technical Data MC68HC908GR8 — Rev 4.0

220 Input/O ut put Ports (I/O) MOTORO LA

16.6 Port D

Port D is an 7-bit special-function port that shares four of its pins with the

serial peripheral interface (SPI) module and three of its pins with two

timer interface (TIM1 and TIM2) modules. Port D also has so ftware

configurable pullup devices if configured as an input port.

16.6.1 Port D Data Register

The port D data register (PTD) contains a data latch for each of the

seven port D pins.

PTD6–PTD0 — Port D Data Bits

These read/write bi ts are software-programmable. Data direction of

each port D pin is under the control of the corresponding bit in data

direction register D. Reset has no effect on port D data.

T2CH0 — Timer 2 Channel I/O Bits

The PTD6/T2CH0 pin is the TIM2 input capture/output compare pin.

The edge/level select bits, ELSxB:ELSxA, determine whether the

PTD6/T2CH0 pin is a timer cha nn el I/O pi n or a g eneral-pu rp ose I/O

pin. See Timer Interface Module (TIM).

Address: $0003

Bit 7654321Bit 0

Read: 0 PTD6 PTD5 PTD4 PTD3 PTD2 PTD1 PTD0

Write:

Reset: Unaffected by reset

Alternate

Function: T2CH0 T1CH1 T1CH0 SPSCK MOSI MISO SS

Figure 16-13. Port D Data Re gister (PTD)

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Input/Output Ports (I/O)

Port D

MC68HC908GR8 — Rev 4.0 Technical Data

MOTOROLA Input/Out put Ports (I/O) 22 1

T1CH1 and T1CH0 — Timer 1 Channel I/O Bits

The PTD5/T1CH1–PTD4/T1CH0 pins are the TIM1 input

capture/ ou tp ut compa r e pins. The edg e/le v el sel ect bits, ELSxB and

ELSxA, de termine wh ether th e PTD5/T1CH1–PTD4/T1CH0 pins are

timer channel I/O pins or general-purpose I/O pins. See Timer

Interface Module (TIM).

SPSCK — SPI Serial Clock

The PTD3/SPSCK pin is the serial clock input of the SPI module.

When the SPE bit is clear, the PTD3/SPSCK pin is available for

general-purp ose I/O.

MOSI — Master Out/Slave In

The PTD2/MOSI pin is the master out/slave in terminal of the SPI

module. When the SPE bit is clear, the PTD2/MOSI pin is available

for general-purpose I/O.

MISO — Master In/Slave Out

The PTD1/MISO pin is the master in/slave out terminal of the SPI

module. When the SPI enable bit, SPE, is clear, the SPI module is

disabled, and t he PTD0/SS pin is available for general-purpose I/O.

Data direction register D (DDRD) does not affect the data direction of

port D pins that are being used by the SPI module. However, the

DDRD bits always determine whether reading port D returns the

stat es of the lat ches or the state s of the pins. See Table 16-5.

SS — Slave Select

The PTD0/SS pin is the slave select input of the SPI module. When

the SPE bit is clear, or when the SPI master bit, SPMSTR, is set, the

PTD0/SS pin is available for general-purpose I/O. When the SPI is

enabled, the DDRB0 bit in data direction register B (DDRB) has no

effect on the PTD0/SS pin.

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Input/Output Ports (I/O)

Technical Data MC68HC908GR8 — Rev 4.0

222 Input/O ut put Ports (I/O) MOTORO LA

16.6.2 Data Direction Register D

Data direction register D (DDRD) determines whether each port D pin is

an inpu t or an output. Writ ing a logic 1 to a DDRD bi t enables the output

buffer for the corresponding port D pin; a logic 0 disables the output

buffer.

DDRD6–DDRD0 — Data Direction Register D Bits

These read/write bits control port D data direction. Reset clears

DDRD6–DDRD0, configuring all port D pins as inputs.

1 = Corresponding port D pin configured as output

0 = Corresponding port D pin configured as input

NOTE: Avoid gl itches on port D pins by wr iting to the port D data re gister be fore

changing data direction register D bits from 0 to 1.

Figure 16-15 shows the port D I/O logic.

Address: $0007

Bit 7654321Bit 0

Read: 0 DDRD6 DDRD5 DDRD4 DDRD3 DDRD2 DDRD1 DDRD0

Write:

Reset:00000000

Figure 16-14. Data Direction Register D (DDRD)

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Input/Output Ports (I/O)

Port D

MC68HC908GR8 — Rev 4.0 Technical Data

MOTOROLA Input/Out put Ports (I/O) 22 3

Figure 16-15. Port D I/O Circuit

When bit DDRDx is a logic 1, rea din g address $0003 reads the PTDx

data latch. When bit DDRDx is a logic 0, reading address $0003 reads

the voltage level on the pin. The data latch can always be written,

regardless of the state of its data direction bit. Table 16-5 summarizes

the operation of the port D pins.

READ DDRD ($0007)

WRITE DDRD ($0007)

RESET

WRITE PTD ($0003)

READ PTD ($0003)

PTDx

DDRDx

PTDx

INTERNAL DATA BUS

VDD

INTERNAL

PTDPUEx

PULLUP

DEVICE

Table 16-5. Port D Pin Functions

PTDPUE Bit DDRD Bit PTD Bit I/O Pin Mode Accesses to DDRD Accesses to PTD

Read/Write Read Write

X(1) Input, VDD(4) DDRD6–DDRD0 Pin PTD6–PTD0(3)

00X

Input, Hi-Z(2) DDRD6–DDRD0 Pin PTD6–PTD0(3)

X 1 X Output DDRD6–DDRD0 PTD6–PTD0 PTD6–PTD0

Notes:

1. X = Don’t care

2. Hi-Z = High impedance

3. Writing affects data register, but does not affect input.

4. I/O pin pulled up to VDD by internal pullup device.

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Input/Output Ports (I/O)

Technical Data MC68HC908GR8 — Rev 4.0

224 Input/O ut put Ports (I/O) MOTORO LA

16.6.3 Port D Input Pullup Enable Register

The port D input pullup enable regi ster (PTDPUE) contain s a softw are

config urable pull up device for ea ch of the se ven por t D pins. E ach bit is

individually configu r able an d requires that the data direct ion regist er,

DDRD, bit be configured as an inpu t. Each pullup is automatically and

dyna mically dis abled when a port bit’s DDRD is configured for output

mode.

PTDPUE6–PTDPUE0 — Port D Input Pullup Enable Bits

These writeable bits are software programmable to enable pullup

devices on an inpu t port bit .

1 = Corresponding port D pin configured to have internal pullup

0 = Corresponding port D pin has int ernal pullup disconnected

Address: $000F

Bit 7654321Bit 0

Read: 0 PTDPUE6 PTDPUE5 PTDPUE4 PTDPUE3 PTDPUE2 PTDPUE1 PTDPUE0

Write:

Reset:00000000

Figure 16-16. Port D Input Pullup Enable Register (PTDPUE)

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Input/Output Ports (I/O)

Port E

MC68HC908GR8 — Rev 4.0 Technical Data

MOTOROLA Input/Out put Ports (I/O) 22 5

16.7 Port E

Port E is a 2 -b it spe c ia l-f unction port that sh ar es two of its pins with th e

serial communications interface (SCI) module.

16.7.1 Port E Data Register

The por t E da ta register con tai ns a d ata l at c h f or ea ch o f t he two port E

pins.

PTE1 and P TE0 — Port E Data Bits

PTE1 and PT E0 are read/ w rite, software programmable bits. Data

direction of each port E pin is under the control of the corresponding

bit in data direction register E.

NOTE: Data dir ection register E (DDRE) does not affect the data dir ection of

port E pins th at are being used by th e SCI m odule. H owever, t he DD RE

bits always determi ne whet her read ing port E retu rns the s tates of the

latches or the states of the pins. See Table 16-6.

RxD — SCI Receive Data Input

The PTE1/RxD pin is the receive data input for the SCI module. When

the enable SCI bit, ENSCI, is clear, the SCI module is disabled, and

the PTE1/RxD pin is available for general-purpose I/O. See Serial

Communications Interface (SC I).

Address: $0008

Bit 7654321Bit 0

PTE1 PTE0

Write:

Reset: Unaffected by reset

Alternate

Function: RxD TxD

= Unimplemented

Figure 16-17. Port E Data Register (PTE)

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Input/Output Ports (I/O)

Technical Data MC68HC908GR8 — Rev 4.0

226 Input/O ut put Ports (I/O) MOTORO LA

TxD — SCI Transmit D ata Output

The PTE0/TxD pin is the transmit data output for the SCI module.

When the enable SCI bit, ENSCI, is clear, the SCI module is disabled,

and the PTE0/TxD pin is available for general-purpose I/O. See Serial

Communications Interface (SC I).

16.7.2 Data Direction Register E

Data dir ection r egister E ( DDRE) det ermines w hether each port E pi n is

an in put or an outpu t. Writi ng a lo gic 1 to a DDRE bit enab les th e outpu t

buff er for the corres ponding port E pin; a logic 0 dis ables the output

buffer.

DDRE1 and DDRE0 — Data Direction Register E Bits

These read/write bits control port E data direction. Reset clears

DDRE1 and DDRE0, configuring all port E pins as inputs.

1 = Corr esponding port E pin configured as output

0 = Corr esponding po rt E pin config ured as input

NOTE: Avoid glitch es on port E pi ns by writing to the port E dat a register bef ore

changin g data direction register E bits from 0 to 1.

Figure 16-19 shows the port E I/O logic.

Address: $000C

Bit 7654321Bit 0

DDRE1 DDRE0

Write:

Reset:00000000

= Unimplemented

Figure 16-18. Da t a Direct ion Regi ster E (DDR E )

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Input/Output Ports (I/O)

Port E

MC68HC908GR8 — Rev 4.0 Technical Data

MOTOROLA Input/Out put Ports (I/O) 22 7

Figure 16-19. Port E I/O Circuit

When bit DDREx is a logic 1, reading address $0008 reads the PTEx

data latch. When bit DDREx is a logic 0, reading address $0008 reads

the voltage level on the pin. The data latch can always be written,

regardless of the state of its data direction bit. Table 16-6 summarizes

the operation of the port E pins .

READ DDRE ($000C)

WRITE DDRE ($000C)

RESET

WRITE PTE ($0008)

READ PTE ($0008)

PTEx

DDREx

PTEx

INTERNAL D ATA B U S

Table 16-6. Port E Pin Functions

DDRE Bit PTE Bit I/O Pin Mode Accesses to DDRE Accesses to PTE

Read/Write Read Write

0X(1) Input, Hi-Z(2) DDRE1–DDRE0 Pin PTE1–PTE0(3)

1 X Output DDRE1–DDRE0] PTE1–PTE0 PTE1–PTE0

Notes:

1. X = Don’t care

2. Hi-Z = High impedance

3. Writing affects data register, but does not affect input.

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Input/Output Ports (I/O)

Technical Data MC68HC908GR8 — Rev 4.0

228 Input/O ut put Ports (I/O) MOTORO LA

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MC68HC908GR8 — Rev 4.0 Technical Data

MOTOROLA RAM 229

Technical Data — MC68HC908GR8

Section 17. RAM

17.1 Contents

17.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .229

17.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 29

17.2 Introduction

This section describes the 384 bytes of RAM (random-access memory).

17.3 Functional Description

Addresses $0040 through $01BF are RAM locations. The location of the

stack RAM is programmable. The 16-bit stack pointer allows the stack to

be any where in the 64K byte m emory space.

NOTE: For correc t oper ation, the stack poin ter must point only to RAM

locations.

Within page zero are 192 bytes of RAM. Because the location of the

stack RAM i s programmable, a ll page zero RAM loca ti ons can be us ed

for I/O control and user data or code. When the stack po inter is moved

from its reset location at $00FF out of page zero, direct addressing mode

instructions can efficiently access all page zero RAM locations. Page

zero RAM, therefore, provides ideal locations for frequently accessed

glob al variables.

Before processing an interrupt, the CPU uses five bytes of the stack to

save the contents of the CPU registers.

NOTE: For M6805 compatibility, the H register is no t stacked.

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RAM

Technical Data MC68HC908GR8 — Rev 4.0

230 RAM MOTOROLA

During a subroutine call, the CPU uses two bytes of t he stac k to sto re

the return add r ess. Th e stack poin ter decr ements during pu shes an d

increments during pulls.

NOTE: Be careful when using nested subroutines. The CPU may overwrite data

in the RAM during a subroutine or during the interrupt stacking

operation.

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MC68HC908GR8 — Rev 4.0 Technical Data
MOTOROLA Serial Communications Interface (SCI) 231
 
Technical Data — MC68HC908GR8
Section 18. Serial Communications Interface (SCI)
18.1  Contents
18.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .231
18.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 32
18.4 Pin Name Conventions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .233
18.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 33
18.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .250
18.7 SCI During Break Module Interrupts. . . . . . . . . . . . . . . . . . . .2 51
18.8 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .251
18.9 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 52
18.2  Introduction
This sectio n descri bes the  seri al com mu nic at i ons in ter fa ce (SCI) 
module, which allows high-speed asynchronous communications with 
peripheral devices and other MCUs.
NOTE: References to DMA (direct-memory access) and associated functions 
are only valid  if the MCU has a DMA module. This MCU does n ot ha ve 
the DMA function. Any DMA-related register bits should be left in their 
reset state for normal MCU operation.
    
  
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Serial Communications Interface (SCI)

Technical Data MC68HC908GR8 — Rev 4.0

232 Serial Communications Interface (SCI) MOTOROLA

18.3 Features

Features of the SCI module include:

•Full-duplex operation

•Standard mark/space non-return-to-zero (NRZ) forma t

•32 programma ble bau d rates

•Prog rammable 8-bit or 9-bit character length

•Separately enabled transmitter and receiver

•Separate receiver and transmitter CPU interrupt requests

•Programmable tra nsmitter output pol arity

•Two receiver wakeup methods:

–Idle line wakeup

–Address mark wakeup

•Interrupt-driven operation with eight interrupt flags:

–Transmitter empty

–Transmission complete

–Receiver full

–Idle receiver input

–Receiver overrun

–Noise erro r

–Framing error

–Parity error

•Receiver framing error detection

•Hardware parity checking

•1/16 bit-time noise detection

•Configuration register bit, SCIBDSRC, to allow selectio n of baud

rate clock source

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Serial Communications Interface (SCI)

Pin Name Conventions

MC68HC908GR8 — Rev 4.0 Technical Data

MOTOROLA Serial Communications Interface (SCI) 233

18.4 Pin Name Conventions

The generic names of the SCI I/O pins are:

•RxD (receive data)

•TxD (transmit data)

SCI I/O (i nput/ou tput) line s are impl emented by sha ring para llel I/O port

pins. The full name of an SCI input or output reflects the name of the

shared port pin. Table 18-1 shows the full names and the generic names

of the SCI I/O pins.

The generic pin names appear in the text of this section.

18.5 Functional Description

Figure 18-1 shows the structure of the SCI module. The SCI allows full-

duple x, asynchro nous, NRZ se rial com municati on among the MCU and

remote devices, inclu ding other MCUs. The transmitter an d receiv er of

the SCI operate independently, although they use the same baud rate

gener ator. Duri ng no rmal oper atio n, the C PU mo nito rs the sta tus of the

SCI, writes the data to be transmitted, and processes received data.

The baud rate clock source for the SCI can be selected via the

configuration bit, SCIBDSRC, of the CONFIG2 register ($001E). Source

selection values are shown in Figure 18-1.

Table 18-1. Pin Name Conventions

Generic Pin Names: RxD TxD

Full Pin Names: PE1/RxD PE0/TxD

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Serial Communications Interface (SCI)

Technical Data MC68HC908GR8 — Rev 4.0

234 Serial Communications Interface (SCI) MOTOROLA

Figure 18-1. SCI Module Block Diagram

SCTE

SCRF

IDLE

SCTIE

TCIE

SCRIE

ILIE

RWU

SBK

DMATE

ORIE

FEIE

PEIE

BKF

RPF

SCI DATA

RECEIVE

SHIFT REGISTER

SCI DATA

TRANSMIT

SHIFT REG ISTER

NEIE

WAKE

ILTY

FLAG

CONTROL TRANSMIT

CONTROL

RECEIVE

CONTROL

DATA SELECTION

CONTROL

WAKEUP

PTY

PEN

DMA

INTERRUPT

CONTROL

TRANSMITTER

INTERRUPT

CONTROL

RECEIVER

INTERRUPT

CONTROL

ERROR

INTERRUPT

CONTROL

DMARE

ENSCI

LOOPS

ENSCI

PE1/RxD PE2/TxD

INTERNAL BUS

TXINV

LOOPS

÷ 4

∏ ÷ 16

PRE-

SCALER BAUD

DIVIDER

CGMXCLK

IT12 A

BSL

SCIBDSRC

FROM

SL = 0 => X = A

SL = 1 => X = B

CONFIG

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Serial Communications Interface (SCI)

Functional Description

MC68HC908GR8 — Rev 4.0 Technical Data

MOTOROLA Serial Communications Interface (SCI) 235

Addr.Register Name Bit 7654321Bit 0

$0013 SCI Control Register 1

(SCC1)

Read: LOOPS ENSCI TXINV M WAKE ILTY PEN PTY

Write:

Reset:00000000

$0014 SCI Control Register 2

(SCC2)

Read: SCTIE TCIE SCRIE ILIE TE RE RWU SBK

Write:

Reset:00000000

$0015 SCI Control Register 3

(SCC3)

Read: R8 T8 DMARE DMATE ORIE NEIE FEIE PEIE

Write:

Reset:UU000000

$0016 SCI Status Register 1

(SCS1)

Read: SCTE TC SCRF IDLE OR NF FE PE

Write:

Reset:11000000

$0017 SCI Status Register 2

(SCS2)

Read: BKF RPF

Write:

Reset:00000000

$0018 SCI Data Register

(SCDR)

Read: R7 R6 R5 R4 R3 R2 R1 R0

Write: T7 T6 T5 T4 T3 T2 T1 T0

Reset: Unaffected by reset

$0019 SCI Baud Rate Register

(SCBR)

Read: SCP1 SCP0 R SCR2 SCR1 SCR0

Write:

Reset:00000000

= Unimplemented R = Reserved U = Unaffected

Figure 18-2. SCI I/O Register Summary

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Serial Communications Interface (SCI)

Technical Data MC68HC908GR8 — Rev 4.0

236 Serial Communications Interface (SCI) MOTOROLA

18.5.1 Data Format

The SCI uses the standard non-return-to-zero mark/space data format

illustrated in Figure 18-3.

Figure 18-3. SCI Data Formats

18.5.2 Transmitte r

Figure 18-4 shows the structure of the SCI transmitter.

The baud rate clock source for the SCI can be selected via the

configuration bit, SCIBDSRC. Source selection values are shown in

Figure 18-4.

BIT 5

START

BIT BIT 0 BIT 1

STOP

BIT

START

BIT

8-BIT DATA FORMAT

BIT M IN SCC1 CLEAR

START

BIT BIT 0

STOP

BIT

START

BIT

9-BIT DATA FORMAT

BIT M IN SCC1 SET

BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 BIT 8

BIT 2 BIT 3 BIT 4 BIT 6 BIT 7

PARITY

BIT

PARITY

BIT

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Serial Communications Interface (SCI)

Functional Description

MC68HC908GR8 — Rev 4.0 Technical Data

MOTOROLA Serial Communications Interface (SCI) 237

Figure 18-4. SCI Transmitter

18.5.2.1 Character Length

The transmitter can accommodate either 8-bit or 9-bit data. The state of

the M bit in SCI control register 1 (SCC1) determines character length.

When transmitting 9-bit data, bit T8 in SCI control register 3 (SCC3) is

the ninth bit (bit 8).

DMATE

SCTE

PEN

PTY

H876543210L

11-BIT

TRANSMIT

STOP

START

DMATE

SCTE

SCTIE

TCIE

SBK

PARITY

GENERATION

MSB

SCI DATA REGISTER

LOAD FROM SCDR

SHIFT ENABLE

PREAMBLE

ALL 1s

BREAK

ALL 0s

TRANSMITTER

CONTROL LOGIC

SHIFT REGISTER

DMATE

SCTIE

TCIE

SCTE

TRANSMITTER CPU INTERRUPT REQUEST

TRANSMITTER DMA SERVICE REQUEST

ENSCI

LOOPS

PE2/TxD

TXINV

INTERNAL BUS

÷ 4PRE-

SCALER

SCP1

SCP0

SCR2

SCR1

SCR0

BAUD

DIVIDER ÷ 16

SCTIE

CGMXCLK

IT12 A

BSL

SL = 0 => X = A

SL = 1 => X = B

SCIBDSRC

FROM

CONFIG2

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Serial Communications Interface (SCI)

Technical Data MC68HC908GR8 — Rev 4.0

238 Serial Communications Interface (SCI) MOTOROLA

18.5.2.2 Character Transmission

During an SCI tr ansmission, th e transmi t shift reg ister shift s a charac ter

out to the PE2/TxD pin. The SCI data register (SCDR) is the write-o nly

buffer between the internal data bus and the transmit shift register. To

initiate an SCI transmission:

1. Enable the SCI by writing a logic 1 to the enable SCI bit (ENSCI)

in SCI control register 1 (SCC1).

2. Enable the transmitter by writing a logic 1 to the transmitter enable

bit (TE) in SCI control register 2 (SCC2).

3. Clear the SCI transmitter empty bit by first reading SCI status

4. Repeat step 3 for each subsequent transmission.

At the start of a transmission, transmitter control logic au tomatically

loads the transmit shift register with a preamble of logic 1s. After the

preamble shifts out, control logic transfers the SCDR data into the

transmit shift re gister. A logic 0 start bit au tomatically goes into the lea st

significant bit position of the transmit shift register. A logic 1 stop bit goes

into the most significant bit position.

The SCI transmitter empty bit, SCTE, in SCS1 becomes set when the

SCDR transfers a byte to the transmit shift register. The SCTE bit

indicates that the SCDR can accept new data from the internal data bus.

If the SCI transmit interrupt enable bit, SCTIE, in SCC2 is also set, the

SCTE bit generates a transmitter CPU interrupt request.

When the transmit shift register is not transmitting a character, the

PE2/ TxD pin goes to the idle condition, logic 1. If at any time so ftware

clears the ENSCI bit in SCI control register 1 (SCC1), the transmitter and

receiver relinquish control of the port E pins.

18.5.2.3 Break Characters

Writ in g a logic 1 to the send b re ak bi t, SBK, in S CC2 l o ads th e transmit

shift register with a break character. A break character contains all logic

0s and has no start, stop, or parity bit. Break character length depends

on the M bit in SCC1. As long as SBK is at logic 1, transmitter logic

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Serial Communications Interface (SCI)

Functional Description

MC68HC908GR8 — Rev 4.0 Technical Data

MOTOROLA Serial Communications Interface (SCI) 239

continuously loa ds break characters into the transmit shift register. After

software clears the SBK bit, the shift register finishes transmitting the

last break character and then transmits at least one logic 1. The

automatic logic 1 at the end of a break character guarantees the

recognition of the start bit of the next character.

The SCI recognizes a break char acter when a start bit is followed by

eight or nine log ic 0 data b its and a logic 0 whe re the st op bit shoul d be.

Receiving a break character has these effects on SCI registers:

•Sets the framing error bit (FE) in SCS1

•Sets the SCI receiver full bit (SCRF) in SCS1

•Clears the SCI data register (SCDR)

•Clears the R8 bit in SCC3

•Sets the break flag bit (BKF) in SCS2

•May set the ov errun (OR), no ise flag (NF), parity error (PE), or

reception in progress flag (RPF) bits

18.5.2.4 Idle Cha racters

An idle character contains all logic 1s and has no start, stop, or parity bit.

Idle character length depends on the M bit in SCC1. The preamble is a

synchronizing idle character that begins every transmission.

If the TE b it is clea red duri ng a tra nsmission, th e PE2/TxD pin beco mes

idle after completion of the transmission in pr ogress. Clearing and then

setting the TE bit during a transmission queues an idle character to be

sent after the character currentl y being transmitted.

NOTE: When queu eing an i dle char acter , retu rn the TE bit to log ic 1 befor e the

stop bit of the current character shifts out to the TxD pin. Setting TE after

the stop bit appears on TxD causes data previously written to the SCDR

to be lost.

Toggle the TE bit for a queued idle character when the SCTE bit

becomes set and just before writing the next byte to the SCDR.

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Serial Communications Interface (SCI)

Technical Data MC68HC908GR8 — Rev 4.0

240 Serial Communications Interface (SCI) MOTOROLA

18.5.2.5 Inversion of Transmitted Output

The transmit inversion bit (TXINV) in SCI control register 1 (SCC1)

reverses the polarity of transmitted data. All transmitted values, including

idle, break, start, and stop bits, ar e inverted when TXINV is at logic 1.

See SCI Control Register 1.

18.5.2.6 Tran smitter Interrupts

These conditions can generate CPU interrupt requests from the SCI

transmitter:

•SCI transmitter e mpty (SCTE) — The SCTE bit in SCS1 indicates

that the SCDR has transferred a characte r to the transmit shift

Setting the SCI transmit interrupt enable bit, SCTIE, in SCC2

enables the SCTE bit to generate transmitter CPU interrupt

requests.

•Transmission complete (TC) — The TC bit in SCS1 i ndicates t hat

the transmit shift register and the SCDR are empty and that no

break or idle character ha s been generated. The transmission

complete interrupt enable bit, TCIE, in SCC2 enables the TC bit to

generate transmitter CPU interrupt requests.

18.5.3 Receiv er

Figure 18-5 shows the structure of the SCI receiver.

18.5.3.1 Character Length

The receiver can accommodate either 8-bit or 9-bit data. The state of the

M bit in SCI co ntrol register 1 (SCC1) determin es characte r length.

When receiving 9-bit data, bit R8 in SCI control register 2 (SCC2) is the

ninth bi t ( b it 8) . W h en receiving 8- b it data, bit R8 i s a copy of the e ighth

bit (b it 7).

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Serial Communications Interface (SCI)

Functional Description

MC68HC908GR8 — Rev 4.0 Technical Data

MOTOROLA Serial Communications Interface (SCI) 241

18.5.3.2 Character Reception

During an SCI reception, the receive shift register shifts characters in

from the PE1/RxD pin. The SCI data register (SCDR) is the read-only

buffer between the internal data bus and the receive shift register.

After a complete cha r acte r sh ifts into th e re ceive shift re giste r, the da ta

portion of the character transfers to the SCDR. The SCI receiver full bit,

SCRF, in SCI status register 1 (SCS1) becomes set, indicating that the

received byte can be read. If the SCI receive interrupt enable bit, SCRIE,

in SCC2 is also set, the SCRF bit generates a receiver CPU interrupt

request.

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Technical Data MC68HC908GR8 — Rev 4.0

242 Serial Communications Interface (SCI) MOTOROLA

Figure 18-5. SCI Receiver Block Diagram

ALL 1s

ALL 0s

WAKE

ILTY

PEN

PTY

BKF

RPF

H876543210L

11-BIT

RECEIVE SHIFT REGIS TE R

STOP

START

DATA

RECOVERY

DMARE

SCRF

ORIE

NEIE

FEIE

PEIE

DMARE

SCRIE

SCRF

ILIE

IDLE

WAKEUP

LOGIC

PARITY

CHECKING

MSB

ERROR CPU INTERRUPT REQUEST

DMA SERVICE REQUEST

CPU INTERRUPT REQUEST

SCI DATA REGISTER

DMARE

ORIE

NEIE

FEIE

PEIE

SCRIE

ILIE

RWU

SCRF

IDLE

PE1/RxD

INTERNAL BUS

PRE-

SCALER BAUD

DIVIDER

÷ 4÷ 16

SCP1

SCP0

SCR2

SCR1

SCR0

SCRIE

DMARE

CGMXCLK

IT12 A

BSL

SCIBDSRC

FROM

SL = 0 => X = A

SL = 1 => X = B

CONFIG2

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Serial Communications Interface (SCI)

Functional Description

MC68HC908GR8 — Rev 4.0 Technical Data

MOTOROLA Serial Communications Interface (SCI) 243

18.5.3.3 Data Sampling

The receiver samples the PE1/RxD pin at the RT clock rate. The RT

clock is an internal signal with a frequency 16 times the baud rate. To

adjust for baud rate mismatch, the RT clock is resynchronized at the

follow i ng time s (see Figure 18-6):

•After every start bit

•After th e recei ver de tects a d ata bit ch ange fro m logi c 1 to log ic 0

(after the majority of data bit samples at RT8, RT9, and RT10

retur ns a va li d lo gi c 1 a nd th e m aj o rity of the next RT8, R T9 , an d

RT10 samples returns a valid logic 0)

To locate the start bit, data recovery logic does an asynchronous search

for a logic 0 preceded by three logic 1s. When the falling edge of a

possible start bit occurs, the RT clock begins to count to 16.

Figure 18-6. Receiver Da ta Sampli ng

To verify the start bit and to detect noise, data recovery logic takes

samples at RT3, RT5, and RT7. Table 18-2 summarizes the results of

the start bit verification samples.

RT CLOCK

RESET

RT1

RT2

RT3

RT4

RT5

RT8

RT7

RT6

RT11

RT10

RT9

RT15

RT14

RT13

RT12

RT16

RT1

RT2

RT3

RT4

START BIT

QUALIFICATION START BI T

VERIFICATION DATA

SAMPLING

SAMPLES

CLOCK

RT CLOCK

STATE

START BIT LSB

PE1/RxD

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244 Serial Communications Interface (SCI) MOTOROLA

Start bit verification is not successful if any two of the three verification

samples are logic 1s. If start bit verification is not successful, the RT

clock is reset and a new search for a start bit begins.

To determine the value of a data bit and to detect noise, recovery logic

takes samples at RT8, RT9, and RT10. Tabl e 18-3 summarizes the

results of the data bit samples.

Table 18-2. Start Bit Verification

RT3, RT5, and RT7 Samples Start Bit

Verification Noise Flag

000 Yes 0

001 Yes 1

010 Yes 1

011 No 0

100 Yes 1

101 No 0

110 No 0

111 No 0

Table 18-3. Data Bit Recovery

RT8, RT9, and RT10 Samples Data Bit Determination Noise Flag

000 0 0

001 0 1

010 0 1

011 1 1

100 0 1

101 1 1

110 1 1

111 1 0

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Serial Communications Interface (SCI)

Functional Description

MC68HC908GR8 — Rev 4.0 Technical Data

MOTOROLA Serial Communications Interface (SCI) 245

NOTE: The RT8, RT9, and RT10 samples do not affect star t bit verification. If

any or all of th e RT8, RT9, and RT10 start bit samples are logic 1s

followi ng a successfu l start bit ve rificati on, the noi se flag (NF) is set and

the receiver assumes that the bit is a start bit.

To verify a st op bit and to detect noise , reco very logic ta kes samples at

RT8, RT9, an d RT10 . Table 18-4 summarizes the results of the stop bit

samples.

18.5.3.4 Framing Errors

If the data recovery logic does not detect a logic 1 where the stop bit

should be in an incoming character, it sets the framing error bit, FE, in

SCS1. A break character also sets the FE bit because a break character

has no stop bit. The FE bit is set at the same time that the SCRF bit is

set.

18.5.3.5 Baud Rate Tolerance

A trans mitting device ma y be operating at a baud rate belo w or above

the receiver baud rate. Accumulated bit time misalignment can cause

one of the three stop bit data sam pl es to f all outsid e the actual stop bit.

Then a noise error occurs. If more than one of the samples is outside the

stop bit, a framing error occurs. In most applications, the baud rate

Table 18-4. Stop Bit Recovery

RT8, RT9, and RT10

Samples Framing

Error Flag Noise Flag

000 1 0

001 1 1

010 1 1

011 0 1

100 1 1

101 0 1

110 0 1

111 0 0

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tolerance is much more than the degree of misalignment that is likely to

occur.

As the receiver samples an incoming character, it resynchronizes the RT

clock on any valid falling edge within the character. Resynchronization

within characters corrects misalignments between transmitter bit times

and receiver bit times.

18.5.3.6 Slow Data Tolerance

Figure 18-7 shows how much a slow received character can be

misalig ned without c ausing a noise error or a framing er ror. The slow

stop bit begins at RT8 instead of RT1 but arrives in time for the stop bit

data samples at RT8, RT9, and RT10.

Figure 18-7. Slow Data

For an 8-bit character, data sampling of the stop bit takes the receiver

9bit times ×16 RT cycles + 10 RT cycles = 154 RT cycles.

With the misaligned character shown in Figure 18-7, the receiver counts

154 RT cycles at the point when the count of the transmitting device is

9bit times ×16 RT cycles + 3 RT cycles = 147 RT cycles.

The maximum percent difference between the receiver count and the

transmitter count of a slow 8-bit character with no errors is

For a 9-bit ch aracter, data samp ling of the stop bit t akes t he receiver

10 bit ti mes ×16 RT cycles + 10 RT cycles = 170 RT cycles.

MSB STOP

RT1

RT2

RT3

RT4

RT5

RT6

RT7

RT8

RT9

RT10

RT11

RT12

RT13

RT14

RT15

RT16

DATA

SAMPLES

RECEIVER

RT CLOCK

154 147–

154

--------------------------100×4.54%=

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Serial Communications Interface (SCI)

Functional Description

MC68HC908GR8 — Rev 4.0 Technical Data

MOTOROLA Serial Communications Interface (SCI) 247

With the misaligned character shown in Figure 18-7, the receiver counts

170 RT cycles at the point when the count of the transmitting device is

10 bit ti mes ×16 RT cycles + 3 RT cycles = 163 RT cycles.

The maximum percent difference between the receiver count and the

transmitter count of a slow 9-bit character with no errors is

18.5.3.7 Fast Data Tolerance

Figure 18-8 shows how much a fast received character can be

misaligned without causing a noise error or a framing error. The fast stop

bit ends at RT10 instead of RT16 but is still there for the stop bit data

samples at RT8, RT9, and RT10.

Figure 18-8. Fast Data

For an 8-bit character, data sampling of the stop bit takes the receiver

9bittimes×16 RT cycles + 10 RT cycles = 154 RT cycles.

With the misaligned character shown in Figure 18-8, the receiver counts

154 RT cycles at the point when the count of the transmitting device is

10 bit times ×16 RT cycles = 160 RT cycles.

The maximum percent difference between the receiver count and the

transmitter count of a fast 8-bit character with no errors is

170 163–

170

--------------------------100×4.12%=

IDLE OR NEXT CHARACTERSTOP

RT1

RT2

RT3

RT4

RT5

RT6

RT7

RT8

RT9

RT10

RT11

RT12

RT13

RT14

RT15

RT16

DATA

SAMPLES

RECEIVER

RT CLOCK

154 160–

154

--------------------------100×3.90%

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For a 9-bit ch aracter, data samp ling of the stop bit t akes t he receiver

10 bit times ×16 RT cycles + 10 RT cycles = 170 RT cycles.

With the misaligned character shown in Figure 18-8, the receiver counts

170 RT cycles at the point when the count of the transmitting device is

11 bit times ×16 RT cycles = 176 RT cycles.

The maximum percent difference between the receiver count and the

transmitter count of a fast 9-bit character with no errors is

18.5.3.8 Receiver Wakeup

So that the MCU can ignore transmissions intended only for other

receivers in multiple-receiver systems, the receiver can be put into a

standby state. Setting the receiver wakeup bit, RWU, in SCC2 puts the

receiver into a standby state during which receiver interrupts are

disabled.

Depending on the state of the WAKE bit in SCC1, either of two

condit ions on the PE1/Rx D pin can bring th e receiver ou t of the stan dby

state:

•Address mark — An address mark is a logic 1 in the most

significant bit position of a received character. When the WAKE bit

is set, an address mark wakes the receiver from the standby state

by clearing the RWU bit. The address mark also sets the SCI

receiver full bit, SCRF. Software can then compare the character

containing the address mark to the user-defined address of the

receiver. If they are the same, the receiver remains awake and

processes the characters that follow. If they are not the same,

software can set the RWU bit and put the receiver back into the

standby state.

•Idle input li ne condition — When the WAKE bit is clear, an idle

character on the PE1/RxD pin wakes the receiver from the

standby state by clearing the RWU bit. The idle character that

wakes the re ceive r does not set the receive r id le bit, IDL E, o r the

170 176–

170

--------------------------100×3.53%=

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Serial Communications Interface (SCI)

Functional Description

MC68HC908GR8 — Rev 4.0 Technical Data

MOTOROLA Serial Communications Interface (SCI) 249

SCI receiver full bit, SCRF. The idle line type bit, ILTY, determines

whether the receiver begins counting logic 1s as idle character bits

after the start bit or after the stop bit.

NOTE: With the WAKE bit clea r, setting th e RWU bit after the RxD pin has been

idle may cause the receiver to wake up immediately.

18.5.3.9 Receiver Interrupts

The following sources can generate CPU interrupt requests from the SCI

receiver:

•SCI receiver full (SCRF) — The SCRF bit in SCS1 indicates that

the receive shift register has transferred a character to the SCDR.

SCRF can generate a receiver CPU interrupt request. Setting the

SCI receive interrupt enable bit, SCRIE, in SCC2 enables the

SCRF bit to generate receiver CPU interrupt s.

•Idle input (IDLE) — The IDLE bit in SCS1 indica tes that 10 or 11

consecutive logic 1s shifted in from the PE1/RxD pin. The idle line

interrupt enable bit, ILIE, in SCC2 enables the IDLE bit to generate

CPU interrupt requests.

18.5.3.10 Error Interrupts

The following receiver err or flags in SCS1 can generate CPU interrupt

requests:

•Receiver overrun (OR) — The OR bit indicates that the receive

shift register shifted in a new character before the previous

character was read from the SCDR. The previous charac ter

remains in the SCDR, and the new character is lost. The overrun

interrupt enable bit, ORIE, in SCC 3 enables OR to gene rate SCI

error CPU interrupt re quests.

•Noise flag (NF) — The NF bit is set when the SCI detects noise on

incoming data or break characters, including start, data, and stop

bits. The nois e error interr upt enable bit, NEIE, in SCC3 enables

NF to generate SCI error CPU interrupt requests.

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Technical Data MC68HC908GR8 — Rev 4.0

250 Serial Communications Interface (SCI) MOTOROLA

•Framing e rror (FE) — The FE bit in SCS1 is set when a logic 0

occurs where the receiver expects a stop bit. The framing error

interrup t enable bit, FEIE, in SCC3 enables FE to generate SCI

error CPU interrupt re quests.

•Parity error (PE) — The PE bit in SCS1 is set when the SCI

detects a parity error in incoming data. The parity error interrupt

enable b it, PEIE, in S CC3 enables P E to generate SCI error CPU

interrupt requests.

18.6 Low-Power Modes

The WAIT and STOP instructions put the MCU in low power-

consumptio n standby mode s.

18.6.1 Wait Mode

The SCI module remains active after the execution of a WAIT

instruction. In wait mode, the SCI module registers are not accessible by

the CPU. Any enabled CPU interrupt request from the SCI module can

bring the MCU out of wait mod e.

If SCI module functions are not required during wait mode, reduce power

consumption by disabling the module before executing the WAIT

instruction.

Refer to Low Power Modes for information on exiting wait mode.

18.6.2 Stop Mode

The SCI module is inactive after the execution of a STOP instruction.

The STOP instruction does not affect SCI register states. SCI module

operation resumes after an external interrupt.

Beca use the internal clock is inactive during st op mode , ente ring stop

mode during an SCI transmission or reception results in invalid data.

Refer to Low Power Modes for inf ormation on exiting s top mode.

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Serial Communications Interface (SCI)

SCI During Break Module Interrupts

MC68HC908GR8 — Rev 4.0 Technical Data

MOTOROLA Serial Communications Interface (SCI) 251

18.7 SCI During Break Module Interrupts

The system integration module (SIM) controls whether status bits in

other modules can be cleared during the break state. The BCFE bit in

the SIM brea k flag control register (SBFCR) enables software to clear

status bits during the break state.

To allow software to clear status bits during a break interrupt, write a

logic 1 to the BCFE bit. If a status bit is cleared during the break state, it

remains cleared when the MCU exits the break state.

To prote ct status bits dur ing the brea k state, writ e a logic 0 to th e BCFE

bit. Wi t h BC FE a t l og ic 0 ( it s default state) , soft ware can read an d w r it e

I/O registers during the break state without affecting status bits. Some

status bits have a 2-step read/write clearing pr ocedure. If sof tware does

the first step on such a bit before the break, the bit cannot change during

the br ea k state as lo ng a s B CFE is at l og ic 0. After the b reak, doing the

second step clears the status bit.

18.8 I/O Signals

Port E sha res two of its pins with the SCI module. The two SCI I/O pins

are:

•PE2/TxD — Tran smit data

•PE1/RxD — Receive data

18.8.1 PE2/TxD (Transmit Data )

The PE2/TxD pin is t he serial da ta out pu t fro m the S CI tra nsmitter. The

SCI shares the PE2/TxD pin with port E. When the SCI is enabled, the

PE2/TxD pin is an output regardless of the state of the DDRE0 bit in data

directi on re gi ste r E (DD RE) .

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18.8.2 PE1/RxD (Receive Data)

The PE1/RxD pin is the serial data input to the SCI receiver. The SCI

shares the PE1/RxD pin with port E. When the SCI is enabled, the

PE1/RxD pin is an input regardless of the state of the DDRE1 bit in data

directi on re gi ste r E (DD RE) .

18.9 I/O Registers

These I/O registers control and monitor SCI operation:

•SCI control regis ter 1 (SCC1)

•SCI control regis ter 2 (SCC2)

•SCI control regis ter 3 (SCC3)

•SCI status register 1 (SCS1)

•SCI status register 2 (SCS2)

•SCI data register (SCDR)

•SCI ba ud ra te re gi ste r (SCBR)

18.9.1 SCI Control Register 1

SCI control regi ster 1:

•Enables loop mode operation

•Enable s the SCI

•Contro ls outpu t polar ity

•Controls character length

•Controls SCI wakeup method

•Contro ls idle character detection

•Enables parity function

•Controls parity type

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Serial Communications Interface (SCI)

I/O Registers

MC68HC908GR8 — Rev 4.0 Technical Data

MOTOROLA Serial Communications Interface (SCI) 253

LOOPS — Loop Mode Select B it

This read/write bit enabl es loop mode operation. In lo op mode the

PE1/RxD pin is disconnected from the SCI, and the transmitter output

goes into the receiver input. Both the transmitter and the receiver

must be enabled to use loop mode. Reset clears the LOOPS bit.

1 = Loop mo de enabled

0 = Normal operation enabled

ENSCI — Enable SC I Bit

This read/write bit enables the SCI and the SCI baud rate generator.

Clearing ENSCI sets the SC TE and TC bits in SCI status register 1

and disables transmitter interrupts. Reset clea rs the ENSCI bit.

1 = SCI enable d

0 = SCI disabled

TXINV — Transmit Inversion Bit

This read/write bit reverses the polarity of transmitted data. Reset

clears the TXINV bit.

1 = Transmi tte r out put invert ed

0 = Transmitter output not inverted

NOTE: Setting the TXINV bit inverts all transmitted values, including idle, break,

start, and stop bits.

M — Mode (Character Length) Bit

This read/write bit determines whether SCI characters are eight or

nine bits long. See Table 18-5. The ninth bit can serve as an extra

stop bit, as a receiver wakeup signal, or as a parity bit. Reset clears

the M bit.

Address: $0013

Bit 7654321Bit 0

Read: LOOPS ENSCI TXINV M WAKE ILTY PEN PTY

Write:

Reset:00000000

Figure 18-9. SCI Control Register 1 (SCC1)

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254 Serial Communications Interface (SCI) MOTOROLA

1 = 9-bit SCI characters

0 = 8-bit SCI characters

WAKE — Wakeup Cond ition Bit

This read/write bit determines which cond ition wa kes up the SCI: a

logic 1 (address mark) in the most significant bit position of a received

character or an idle condition on the PE1/RxD pin. Reset clears the

WAKE bit.

1 = Address mark wakeup

0 = Idle line wakeup

ILTY — Idle Line Type Bit

This read/write bit determines when the SCI starts counting logic 1s

as idle character bi ts. Th e coun ti ng be gi n s ei th er a fte r the sta rt bi t or

after the stop bit. If the count be gins after the start bit, then a string of

logic 1s preceding the stop bit may cause false recognition of an idle

character. Beginning the count after the stop bit avoids false idle

character recognition, but requires properly synchronized

transmissions. Reset clears the ILTY bit.

1 = Idle character bit count begins after stop bit

0 = Idle character bit count begins after start bit

PEN — Parity Enable Bit

This read/write bit enables the SCI parity function. See Table 18-5.

When enabled, the parity function inserts a parity bit in the most

signifi cant bit posit ion. See Figure 18-3. Reset clears the PEN bit.

1 = Parity function enabled

0 = Parity function disabled

PTY — Parity Bit

This read/write bit determines whether the SCI generates and checks

for odd parity or even parity. See Table 18-5. Reset clears the PTY bit.

1 = Odd parity

0 = Even parity

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Serial Communications Interface (SCI)

I/O Registers

MC68HC908GR8 — Rev 4.0 Technical Data

MOTOROLA Serial Communications Interface (SCI) 255

NOTE: Changing the PTY bit in the middle of a transmission or reception can

generate a parity error.

18.9.2 SCI Control Register 2

SCI control regi ster 2:

•Enables the following CPU interrupt req ue sts:

–Enables the SCTE bit to generate transmitter CPU interrupt

requests

–Enables the TC bit to generate transmitter CPU interrupt

requests

–Enables the SCRF bit to generate receiver CPU interrupt

requests

–Enables the IDLE bit to generate receiver CPU interrupt

requests

•Enables the transmitter

•Enables the receiver

•Enables SCI wakeup

•Transmits SCI break characters

Table 18-5. Character Format Selection

Control Bits Character Format

MPEN and

PTY Start

Bits Data

Bits Parity Stop

Bits Character

Length

0 0 X 1 8 Non e 1 10 bits

1 0X 1 9 None 1 11 bits

0 10 1 7 Even 1 10 bits

0 11 1 7 Od d 1 10 bits

1 10 1 8 Even 1 11 bits

1 11 1 8 Odd 1 11 bits

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SCTIE — SCI Transmit Interrupt Enab le Bit

This read/write bit enables the SCTE bit to generate SCI transmitter

CPU interrupt requests. Reset clears the SCTIE bit.

1 = SCTE enabled to generate CPU interr upt

0 = SCTE not enabled to generate CPU interrup t

TCIE — Transmission Complete Inte rru pt Enable Bit

This read/write bit enables the TC bit to generate SCI transmitter CPU

interrupt requests. Reset clears the TCIE bit.

1 = TC enabled to generate CPU interrupt requests

0 = TC not enabled to generate CPU interrupt requests

SCRIE — SCI Receive Interrupt Enable Bit

This read/write bit enables the SCRF bit to generate SCI receiver

CPU interrupt requests. Reset clears the SCRIE bit.

1 = SCRF enabled to ge nerate CPU interru pt

0 = SCRF not enabled to generate CPU interrupt

ILIE — Idl e Line Interrupt Enable Bit

This read/write bit enables the IDLE bit to generate S CI receiver CPU

interrupt requests. Reset clears the ILIE bit.

1 = IDLE enabled to generate CPU interrupt requests

0 = IDLE not enabled to generate CPU interrupt requests

TE — Transmitter Enable Bit

Setting this read /write bit begins the transmission by sending a

preamble of 10 or 11 logic 1s from the transmit shift register to the

PE2/TxD pin. If software clears the TE bit, the transmitter comp lete s

any transmission in prog ress before the PE2/TxD returns to the idle

Address: $0014

Bit 7654321Bit 0

Read: SCTIE TCIE SCRIE ILIE TE RE RWU SBK

Write:

Reset:00000000

Figure 18-10. SCI Control Register 2 (SCC2)

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Serial Communications Interface (SCI)

I/O Registers

MC68HC908GR8 — Rev 4.0 Technical Data

MOTOROLA Serial Communications Interface (SCI) 257

condition (logic 1). Clearing and then setting TE during a transmission

queues an idle character to be sent after the character currently being

transmitted. Reset clears the TE bit.

1 = Transmi tte r ena bl ed

0 = Transmitter disabled

NOTE: Writing to the TE bit is not allowed when the enable SCI bit (ENSCI) is

clear. ENSCI is in SC I control register 1.

RE — Receiver Enable Bit

Setting this read/write bit enables the receiver. Clearing the RE bit

disables the receiver but does not affect receiver interrupt flag bits.

Reset clears the RE bit.

1 = Receiver enabled

0 = Receiver disabled

NOTE: Writing to the RE bit is not allowed when the enable SCI bit (ENSCI) is

clear. ENSCI is in SC I control register 1.

RWU — Receiver Wakeup Bit

This read/write bit puts the receiver in a standby state during which

receive r interrupts are disabled. The WAKE bit in SCC1 determ ines

whether an idle input or an address mark brings the receiver out of the

standby state and clears the RWU bit. Reset clears the RWU bit.

1 = Standby state

0 = Normal operation

SBK — Send Br eak Bit

Sett ing and then c learing this rea d/write bit transmit s a break

characte r follo w ed by a lo gi c 1. The log ic 1 aft er the br ea k char acte r

guarantees recognition of a valid start bit. If SBK remains set, the

transmitter continuously transmits break characters with no logic 1s

betw een them. Reset c lears the S BK bit.

1 = Tran smit br eak cha r acters

0 = No br eak cha r acters being transmitted

NOTE: Do not toggle the SBK bit immediately after setting the SCTE bit.

Toggling SBK before the preamble begins causes the SCI to send a

break character instead of a preamble.

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Technical Data MC68HC908GR8 — Rev 4.0

258 Serial Communications Interface (SCI) MOTOROLA

18.9.3 SCI Control Register 3

SCI control regi ster 3:

•Stores the ninth SCI data bit received and the ninth S CI data bit to

be transmitted

•Enables these interrupts:

–Receiver overrun interru pts

–Noise error interrupts

–Framing e rror interrupts

•Parity error in terrupts

R8 — Received Bit 8

When the SCI is receiving 9-bit characters, R8 is th e read-only ninth

bit (bit 8) of the received character. R8 is received at the same time

that the SCDR recei v es the other 8 bits.

When the SCI is receivi ng 8-bit charac ters, R8 is a copy of the eigh th

bit (bit 7). Reset has no effect on the R8 bit.

T8 — Transmitted Bit 8

When the SCI is transmitting 9-bit characters, T8 is the read/write

ninth bit (bit 8) of the transmitted character. T8 is loaded into the

transmit shift register at the same time that the SCDR is loaded into

the transmit shift register. Reset has no effect on the T8 bit.

Address: $0015

Bit 7654321Bit 0

Read: R8 T8 DMARE DMATE ORIE NEIE FEIE PEIE

Write:

Reset:UU000000

= Unimplemented U = Unaffected

Figure 18-11. SCI Control Register 3 (SCC3)

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Serial Communications Interface (SCI)

I/O Registers

MC68HC908GR8 — Rev 4.0 Technical Data

MOTOROLA Serial Communications Interface (SCI) 259

DMARE — DMA Receive Ena ble Bit

CAUTION: The DMA mo dule is not included on this MCU. Writing a logic 1 to

DMARE or DMATE may adversely affect MCU performance.

1 = DMA not enabled to service SCI receiver DMA service requests

generated by the SCRF bit (SCI receiver CPU interrupt

requests enabled)

0 = DMA not enabled to service SCI receiver DMA service requests

generated by the SCRF bit (SCI receiver CPU interrupt

requests enabled)

DMATE — DMA Transfer Enable Bit

CAUTION: The DMA mo dule is not included on this MCU. Writing a logic 1 to

DMARE or DMATE may adversely affect MCU performance.

1 = SCTE DMA service requests enabled; SCTE CPU interrupt

requests disabled

0 = SCTE DMA servi ce reques ts dis abled; SCTE CPU in terrupt

reques ts enabled

ORIE — Receiver Overrun Interrupt Enable Bit

This read/write bit enables SCI error CPU interrupt requests

generated by the receiver overrun bit, OR.

1 = SCI error CPU interrupt requests from OR bit enabled

0 = SCI error CPU interrupt requests from OR bit disabled

NEIE — Receiver Noise Error Interrupt Enable Bi t

This read/write bit enables SCI error CPU interrupt requests

generated by the noise error bit, NE. Reset clears NEIE.

1 = SCI er ror CPU interrupt requ ests from NE bit enabled

0 = SCI er ror CPU interrupt requ ests from NE bit disabled

FEIE — Receiver Framing Error Interrupt Enable Bit

This read/write bit enables SCI error CPU interrupt requests

generated by the framing error bit, FE. Reset clears FEIE.

1 = SCI er ror CPU interrupt requ ests from FE bit enabled

0 = SCI er ror CPU interrupt requ ests from FE bit disabled

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Serial Communications Interface (SCI)

Technical Data MC68HC908GR8 — Rev 4.0

260 Serial Communications Interface (SCI) MOTOROLA

PEIE — Receiver Parity Error Interru pt Ena ble Bit

This read/write bit enables SCI receiver CPU interrupt requests

generated by the parity error bit, PE . See SCI Status Register 1.

Reset clears PEIE.

1 = SCI er ror CPU interrupt requests from PE bit enabled

0 = SCI error CPU interrupt requests from PE bit disabl ed

18.9.4 SCI Status Register 1

SCI status regi ster 1 (SCS1) cont ai ns flags to signal these conditions:

•Transfer of SCDR data to transmit shift register complete

•Transmission complete

•Transfer of receive shift register data to SCDR complete

•Receiver inpu t idle

•Receiver overrun

•Noisy data

•Framing error

•Parity error

SCTE — SCI Transmitter Empty Bit

This clearable, read-only bit is set when the SCDR transfers a

character to the transmit shift register. SCTE can generate an SCI

transmitter CPU interrupt request. When the SCTIE bit in SCC2 is set,

SCTE gen erates an SCI tr ansmitter CPU in terrupt re quest. In norm al

Address: $0016

Bit 7 6 5 4 3 2 1 Bit 0

Read: SCTE TC SCRF IDLE OR NF FE PE

Write:

Reset:11000000

= Unimplemented

Figure 18-12. SCI Status Register 1 (SCS1)

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Serial Communications Interface (SCI)

I/O Registers

MC68HC908GR8 — Rev 4.0 Technical Data

MOTOROLA Serial Communications Interface (SCI) 261

operation, clear the SCTE bit by reading SCS1 with SCTE set and

then writing to SCDR. Reset sets the SCTE bit.

1 = SCDR data transferr ed to transmit shift register

0 = SCDR data not transferred to transmit shift register

TC — Transmission Complete Bit

This read-only bit is set when the SCTE bit is set, and no data,

preamble, or break character is being trans mitte d. TC generates an

SCI transmitter CPU interrupt re qu est if the TCIE bit in SCC2 is also

set. TC is automatically clea red when data, preamble or break is

queued and ready to be sent. There may be up to 1.5 transmitter

clocks of latency between queueing data, preamble, an d break and

the transmission actually starting. Reset sets the TC bit.

1 = No transmission in progress

0 = Transmission in progress

SCRF — SCI Receiver Full Bit

This clearable, rea d-only bit is set whe n the data in the receive shift

receiver CPU interrupt request. When the SCRIE bit in SCC2 is set,

SCRF g ene r ate s a C PU i n ter r upt re qu est. In normal op er ation, clear

the SCRF bit by reading SCS1 with SCRF set and then reading the

SCDR. Reset clea rs SCRF.

1 = Received data available in SC DR

0 = Data not available in SCDR

IDLE — Receiver Idle Bit

This clearable, read-only bit is set when 10 or 11 consecutive logic 1s

appear on the receiver input. IDLE generates an SCI error CPU

interru pt re quest if th e ILIE bi t in SC C2 i s also set. C lear th e IDLE bit

by reading SCS1 with IDLE set and then reading the SCDR. After the

receiver is enabled, it must receive a valid character that sets the

SCRF bit before an idle condition c an set the IDLE bit . Also, after the

IDLE bit has been cleared, a valid character must again set the SCRF

bit before an idle condition can set the IDLE bit. Reset clears the IDLE

bit.1 = Receiver input idle

0 = Rece iver inp ut active (or idle since the IDLE bit was cleared)

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Serial Communications Interface (SCI)

Technical Data MC68HC908GR8 — Rev 4.0

262 Serial Communications Interface (SCI) MOTOROLA

OR — Receiver Overrun Bit

This clearable, read-only bit is set when software fails to read the

SCDR be fore the receive shift register receives the next character.

The OR bit generat es an SCI e rror CPU interr upt requ est if the O RIE

bit in SCC3 is also set. The data in the shift register is lost, but the data

already in the SCDR is not affected. Clear the OR bit by reading SCS1

with OR set and then reading the SCDR. Reset clears the OR bit.

1 = Receive shift reg ister full and SCRF = 1

0 = No receiver overrun

Software latency may allow an overrun to occur between reads of

SCS1 and SC DR i n the fla g- cl eari ng sequ ence . Figure 18-13 shows

the normal flag-clearing sequence and an example of an overrun

caused by a delayed flag-clearing sequence. The delayed read of

SCDR does not clear the OR bit because OR was not set when SCS1

was read. Byte 2 caused the overrun and is lost. The next flag-

clearing sequence reads byte 3 in the SCDR instead of byte 2.

In applications that are subject to software latency or in which it is

important to know which byte is lost due to an overrun, the flag-

clearin g routine can che ck the OR bit in a second read of SCS1 after

reading the data register.

NF — Receiver Noi s e Flag Bit

This clearable, read-only bit is set when the SCI detects noise on the

PE1/RxD pin. NF generates an NF CPU interrupt request if the NEIE

bit in SCC3 is also set. Clear the NF bit by reading SCS1 an d then

reading the SCDR. Reset clears the NF bit.

1 = Noise detected

0 = No noise detected

FE — Receiver Fr aming Error Bit

This clearable, read-only bit is set when a logic 0 is accepted as the

stop bit. FE g enerates an SCI error CPU interru pt request if the FEIE

bit in SCC3 also is set. Clear the FE bit by reading SCS1 with FE set

and then reading the SCDR. Reset clears the FE bit.

1 = Framing error detected

0 = No framing error detected

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Serial Communications Interface (SCI)

I/O Registers

MC68HC908GR8 — Rev 4.0 Technical Data

MOTOROLA Serial Communications Interface (SCI) 263

Figure 18-13. Flag Clearing Sequence

PE — Receiver Parity Erro r Bit

This clearable, read-only bit is set when the SCI detects a parity error

in incoming data. PE generates a PE CPU inte rrupt request if the

PEIE bit in SCC3 is also set. Clear the PE bit by reading SCS1 with

PE set and then reading the SCDR. Reset clears the PE bit.

1 = Parity error detected

0 = No parity error detected

BYTE 1

NORMAL FLAG CLEARING SEQUENCE

READ SC S 1

SCRF = 1

READ SCDR

BYTE 1

SCRF = 1

BYTE 2 BYTE 3 BYTE 4

OR = 0

READ SC S 1

SCRF = 1

OR = 0

READ SCDR

BYTE 2

SCRF = 0

READ SC S 1

SCRF = 1

OR = 0

SCRF = 1

SCRF = 0

READ SCDR

BYTE 3

SCRF = 0

BYTE 1

READ SCS1

SCRF = 1

READ SCDR

BYTE 1

SCRF = 1

BYTE 2 BYTE 3 BYTE 4

OR = 0

READ SCS1

SCRF = 1

OR = 1

READ SCDR

BYTE 3

DELAYED FLAG CLEARING SEQUENCE

OR = 1

SCRF = 1

OR = 1

SCRF = 0

OR = 1

SCRF = 0

OR = 0

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Technical Data MC68HC908GR8 — Rev 4.0

264 Serial Communications Interface (SCI) MOTOROLA

18.9.5 SCI Status Register 2

SCI status register 2 contains flags to signal the following conditio ns:

•Break character detected

•Incoming data

BKF — Break Flag Bit

This clearable, read-only bit is set when the SCI detects a break

character on the PE1/RxD pin. In SCS1, the FE and SCRF bits are

also set. In 9-bit character transmissions, the R8 bit in SCC3 is

cleared. BKF does not generate a CPU interrupt request. Clear BKF

by reading SCS2 with BKF set and then reading the SCDR. Once

cleared, BKF can become set again only after logic 1s again appear

on the PE1/RxD pin followed by another break character. Reset

clears the BKF bit.

1 = Break character detec ted

0 = No break character detected

RPF — Reception in Pro gress Flag Bit

This read-only bit is se t when the receiver de tects a logic 0 during the

RT1 time period of the start bit search. RPF does not generate an

interrupt request. RPF is reset after the receiver detects false start bits

(usually from noise or a baud rate mismatch) or when the receiver

detects an idle charac ter. Polling RPF before disabling the SCI

module or entering stop mode can show whether a reception is in

progress.

1 = Rece ption in progress

0 = No reception in progress

Address: $0017

Bit 7654321Bit 0

Read: BKF RPF

Write:

Reset:00000000

= Unimplemented

Figure 18-14. SCI Status Register 2 (SCS2)

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Serial Communications Interface (SCI)

I/O Registers

MC68HC908GR8 — Rev 4.0 Technical Data

MOTOROLA Serial Communications Interface (SCI) 265

18.9.6 SCI Data Register

The SCI data register (SCDR) is the buffer between the internal data bus

and the receive and t ransmit shift registers. Re set has no effe ct on data

in the SCI data reg i ster.

R7/T7–R0/T0 — Receive/Transmit Data Bits

Reading address $0018 accesses the read-only received data bits,

R7:R0. Writing to address $0018 writes the data to be transmitted,

T7:T0. Reset ha s no effect on the SCI dat a regi ster .

NOTE: Do not use read/modify/write instructions on the SCI data register.

18.9.7 SCI Baud Rate Register

The baud rate register (SCBR) selects the baud rate for both the receiver

and the transmitter.

Address: $0018

Bit 7654321Bit 0

Read: R7 R6 R5 R4 R3 R2 R1 R0

Write: T7 T6 T5 T4 T3 T2 T1 T0

Reset: Unaffected by reset

Figure 18-15. SCI D ata Register (SCDR)

Address: $0019

Bit 7654321Bit 0

Read: SCP1 SCP0 R SCR2 SCR1 SCR0

Write:

Reset:00000000

= Unimplemented R = Reserved

Figure 18-16. SCI Baud Rate Register (SCBR)

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Serial Communications Interface (SCI)

Technical Data MC68HC908GR8 — Rev 4.0

266 Serial Communications Interface (SCI) MOTOROLA

SCP1 and S CP0 — SCI Baud Rate Prescaler Bits

These read/w rite bits select the baud r ate prescaler divisor as shown

in Table 18-6. Reset clears SCP1 and SCP0.

SCR2–SCR0 — SCI Baud Rate Select Bits

These read/write bits select the SCI baud rate divisor as shown in

Table 18-7. Reset clears SCR2–SCR0.

Table 18-6. SCI Baud Rate Prescaling

SCP1 and SCP0 Prescaler Divisor (PD)

00 1

01 3

10 4

11 13

Table 18-7. SCI Baud Rate Selection

SCR2, SCR1,

and SCR0 Baud Rate

Divisor (BD)

000 1

001 2

010 4

011 8

100 16

101 32

110 64

111 128

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Serial Communications Interface (SCI)

I/O Registers

MC68HC908GR8 — Rev 4.0 Technical Data

MOTOROLA Serial Communications Interface (SCI) 267

Use this formula to calculate the SCI baud rate:

where:

fBUS = bus frequency

PD = prescaler divisor

BD = baud ra te divisor

SCI_BDSRC is an input to the SCI. Normally it will be tied off low at the

top level to select the bus cl ock as the clock source. This makes the

formula:

Table 18-8 shows the SCI baud rates that can be generat ed with a

4.9152-MHz bus clock.

baud rate f BUS

64 PD BD××

------------------------------------=

baud rate f BUS

64 PD BD××

------------------------------------=

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Serial Communications Interface (SCI)

Technical Data MC68HC908GR8 — Rev 4.0

268 Serial Communications Interface (SCI) MOTOROLA

Table 18-8. SCI Baud Rate Sel ection Exampl es

SCP1 and

SCP0 Prescaler

Divisor (PD) S CR2, SCR1,

and SCR0 Baud Rate

Divisor (BD) Baud Rate

(fBUS = 4.9152 MHz)

00 1 000 1 76,800

00 1 001 2 38,400

00 1 010 4 19,200

00 1 011 8 9600

00 1 100 16 4800

00 1 101 32 2400

00 1 110 64 1200

00 1 111 128 600

01 3 000 1 25,600

01 3 001 2 12,800

01 3 010 4 6400

01 3 011 8 3200

01 3 100 16 1600

01 3 101 32 800

01 3 110 64 400

01 3 111 128 200

10 4 000 1 19,200

10 4 001 2 9600

10 4 010 4 4800

10 4 011 8 2400

10 4 100 16 1200

10 4 101 32 600

10 4 110 64 300

10 4 111 128 150

11 13 000 1 5908

11 13 001 2 2954

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Technical Data MC68HC908GR8 — Rev 4.0

269 Serial Communications Interface (SCI) MOTOROLA

11 13 010 4 1477

11 13 011 8 739

11 13 100 16 369

11 13 101 32 185

11 13 110 64 92

11 13 111 128 46

Table 18-8. SCI Baud Rate Sel ection Exampl es

SCP1 and

SCP0 Prescaler

Divisor (PD) S CR2, SCR1,

and SCR0 Baud Rate

Divisor (BD) Baud Rate

(fBUS = 4.9152 MHz)

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Technical Data MC68HC908GR8 — Rev 4.0

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MC68HC908GR8 — Rev 4.0 Technical Data
MOTOROLA System Integration Module (SIM) 271
 
Technical Data — MC68HC908GR8
Section 19. System Integration Module (SIM)
19.1  Contents
19.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .271
19.3 SIM Bus Cl ock Control and Generation . . . . . . . . . . . . . . . . .275
19.4 Reset and System Initialization. . . . . . . . . . . . . . . . . . . . . . . .276
19.5 SIM Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .281
19.6 Exception Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .282
19.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .290
19.8 SIM Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .293
19.2  Introduction
This section describes the system integration module (SIM). Together 
with the CPU, the SIM controls all MCU activities. A block diagram of the 
SIM is shown in Figu r e 19- 1. Table 19-1 is a summary of the SIM 
input/output (I/O) registers. The SIM is a system state cont roller that 
coordinates CPU and exception timing. The SIM is responsible for:
•Bus clock generation and control for CPU and peripherals:
–Stop/w ai t/rese t/break entry and recover y
–Internal clock control
•Master reset control, includ ing power-on reset (POR) and COP 
timeout
•Interrupt control:
–Acknowledge timing
–Arbitration control ti ming 
    
  
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System Integration Module (SIM)

Technical Data MC68HC908GR8 — Rev 4.0

272 System Integration Module (SIM) MOTOROLA

–Vector address generation

•CPU enable/disable timing

•Modular architecture expandable to 128 interrupt sources

Table 19-1 shows the internal signal names used in this section.

Figure 19-1. SIM Block Diagram

STOP/WAIT

CLOCK

CONTROL CLOCK GENERATORS

POR CONTROL

RESET PIN CONTROL

SIM RESET STATUS REGISTER

INTERRUPT CONTROL

AND PRIORITY DECODE

MOD U LE STO P

MODULE WAIT

CPU STOP (FROM CPU)

CPU WAIT (FROM CPU)

SIMOS C EN (TO CGM)

CGMOUT (FROM CGM)

INTERNAL CLOCKS

MASTER

RESET

CONTROL

RESET

PIN LOGIC LVI (FROM LVI MODULE)

ILLEGAL O PCODE (FROM CP U)

ILLEGAL ADDRESS (FROM ADDRESS

MAP DECODERS)

COP (FROM COP MODULE)

INTERRUPT SOURCES

CPU INTERFACE

RESET

CONTROL

SIM

COUNTER COP CLOCK

CGMXCLK (FROM CGM)

÷ 2

VDD

INTERNAL

PULLUP

DEVICE

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System Integration Module (SIM)

Introduction

MC68HC908GR8 — Rev 4.0 Technical Data

MOTOROLA System Integration Module (SIM) 273

Table 19-1. Signal Name Conventions

Signal Name Description

CGMXCLK Buffered version of OSC1 from clock generator module (CGM)

CGMVCLK P LL outp ut

CGMOUT PLL-based or OSC1-based clock output from CGM module

(Bus clock = CGMOUT divided by two)

IAB Internal address bus

IDB Internal data bus

PORRST Signal from the power-on reset module to the SIM

IRST Internal reset signal

R/W Read/write signal

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Technical Data MC68HC908GR8 — Rev 4.0

274 System Integration Module (SIM) MOTOROLA

Addr.Register Name Bit 7654321Bit 0

$FE00 SIM Break Status Register

(SBSR)

Read: RRRRRR

SBSW R

Write: NOTE

Reset:00000000

Note: Writing a logic 0 clears SBSW.

$FE01 SIM Reset Status Register

(SRSR)

Read: POR PIN COP ILOP ILAD MODRST LVI 0

Write:

POR:10000000

$FE02 SIM Upper Byte Address

Read: RRRRRRRR

Write:

Reset:

$FE03 SIM Break Flag Control

Read: BCFERRRRRRR

Write:

Reset: 0

$FE09 Interrupt Status Register 1

(INT1)

Read: IF6 IF5 IF4 IF3 IF2 IF1 0 0

Write:RRRRRRRR

Reset:00000000

$FE0A Interrupt Status Register 2

(INT2)

Read: IF14 IF13 IF12 IF11 IF10 IF9 IF8 IF7

Write:RRRRRRRR

Reset:00000000

$FE0B Interrupt Status Register 3

(INT3)

Read: 000000IF16IF15

Write:RRRRRRRR

Reset:00000000

= Unimplemented

Figure 19-2. SIM I/O Register Summary

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System Integration Module (SIM)

SIM Bus Clock Control and Generation

MC68HC908GR8 — Rev 4.0 Technical Data

MOTOROLA System Integration Module (SIM) 275

19.3 SIM Bus Clock Control and Generation

The bus clock g enerator provides system clock signals for t he CPU and

peripherals on the MCU. The system clocks are generated from an

incoming clock, CGMOUT, as shown in Figure 19-3. This clock can

come from either an external oscillator or from the on-chip PLL. See

Clock Generator Module (CGMC).

Figure 19-3. CGM Clock Signals

19.3.1 Bus Timing

In user mode, the i nterna l bus f r equency is either the cry stal oscillator

output (CGMXCLK) divided by four or the PLL output (CGMVCLK)

divided b y four. See External Interrupt (IRQ).

÷ 2BUS CLOCK

GENERATORS

SIM

SIM COUNTER

SIMOSCEN

OSCILLATOR (OSC)

OSC2

OSC1

PHASE-LO CKED LOOP (PLL)

CGMXCLK

CGMRCLK

IT12

CGMOUT

TO TIMTB15A, ADC

OSCSTOPENB

FROM

CONFIG

TO REST

OF CHIP

IT23

TO REST

OF CHIP

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19.3.2 Clock Startup from POR or LVI Reset

When the power-on reset module or the low-voltage inhibit module

generates a reset, the clocks to the CPU and peripherals are inactive

and held in an inactive phase until after the 4096 CG MXCLK cycle POR

timeout has completed. The RST pin is driven low by the SIM during this

entire period. The IBUS clocks start upon completion of the timeout.

19.3.3 Clocks in Stop Mode and Wait Mode

Upon exit from stop mode by an interrupt, break, or reset, the SIM allows

CGMXCL K to clock the S IM counter. The C PU and periphe ral clocks do

not become active until after the stop delay timeout. This timeout is

selectable as 4096 or 32 CGMXCLK cycles. See Stop Mode.

In wait mode, the CPU clocks are inactive. The SIM also produces two

sets of clocks for other modules. Refer to the wait mode subsection of

each module to see if the module is active or inactive in wait mode.

Some modules can be programmed to be active in wait mode.

19.4 Reset and System Ini t ialization

The MCU has these reset sources:

•Power-on reset module (POR)

•External reset pin (RST)

•Computer operating properly module (COP)

•Low- vol tag e in hi bi t mo dule (LVI)

•Illegal op code

•Illegal address

All of these resets produce the vector $FFFE:$FFFF ($FEFE:$FEFF in

monitor mode) an d assert the in ternal reset si gnal (IRST). IRST cau ses

all registers to be returned to their default values and all modules to be

returned to their rese t states.

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System Integration Module (SIM)

Reset and System Initialization

MC68HC908GR8 — Rev 4.0 Technical Data

MOTOROLA System Integration Module (SIM) 277

An internal reset clears the SIM counter (see SIM Counter), but an

exte rnal reset doe s not. Each of the res ets sets a corres ponding bit in

the SIM reset status register (SRSR). See SIM Registers.

19.4.1 Exte rnal Pin Reset

The RST pin circuit includes an internal pullup device. Pulling the

asynchronous RST pin low halts all processing. The PIN bit of the SIM

reset status register (SRSR) is set as long as RST is held low for a

minimum of 67 CGMXCLK cycles, assuming that neither the POR nor

the LVI was the source of the reset. See Table 19-2 for details. Figure

19-4 shows the relative timing.

Figure 19-4. External Reset Timing

19.4.2 Active Resets from Internal Sources

All internal rese t sources actively pull th e RST pin low for 32 CGMXCLK

cycles to allow resetting of external peripherals. The internal reset signal

IRST continues to be asserted for an additional 32 cycles. See Figure

19-5. An internal reset can be caused by an illegal address, illegal

opcode, COP timeout, LVI, or POR. See Figure 19-6.

NOTE: For LVI or POR resets, the SIM cycles through 409 6 CGMXCLK cycles

during which the SIM forces the RST pin lo w. The internal reset signal

Table 19-2. PIN Bit Set Timing

Reset Type Number of Cycles Required to Set PIN

POR/LVI 4163 (4096 + 64 + 3)

All others 67 (64 + 3)

RST

IAB PC VECT H VECT L

CGMOUT

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then follows the sequence from the falling edge of RST shown in Figure

19-5.

Figure 19-5. Internal Reset Timing

The COP reset is asynchronous to the bus clock.

Figure 19-6. Sources of Internal Reset

The active reset feature allows the part to issue a reset to peripherals

and other chips within a system built around the MCU.

19.4.2.1 Po wer-On Reset

When power is first applied to the MCU, the power-on reset module

(POR) generates a pulse to indicate that power-on has occurred. The

exte rnal reset pin (RST) is held low while the SIM counter counts ou t

4096 CGMXCLK cycles. Sixty-four CGMXCLK cycles later, the CPU and

memo ries are r eleased from reset to allo w the res et vector seq uence to

occur.

At power-on, these events occur:

•A POR pulse is generated.

IRST

RST

RST PULLED LOW BY MCU

IAB

32 CYCLES 32 CYCLES

VECTOR HIGH

CGMXCLK

ILLEGAL ADDRESS RST

ILLEGAL OPCODE RST

COPRST

LVI

POR

INTERNAL RESET

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Reset and System Initialization

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MOTOROLA System Integration Module (SIM) 279

•The internal reset signal is asserted.

•The SIM enables CGMOUT.

•Internal clocks to the CPU and modules are held inactive for 4096

CGMXCLK cycles to allow stabilization of the oscillator.

•The RST pin is driven low during the oscillator stabilization time.

•The POR bit of the SIM reset sta tus re gister (SRS R) is s et and all

other bits in the re gister are cleared.

Figure 19-7. POR Recovery

19.4.2.2 Computer Operating Properly (COP) Reset

An input to the SIM is reserved fo r the COP reset signal. The overflow of

the COP counter causes an internal reset and sets the COP bit in the

SIM re set st atus re giste r (SRS R). Th e SIM a ctivel y pul ls do wn th e RST

pin for all internal reset sources.

To prevent a COP module timeout, write any value to location $FFFF.

Writing to location $FFFF clears the COP counter and bits 12 through 4

of the SI M counter. Th e SIM counter output, whi ch occurs at least e very

213 – 24 CGMXCLK cycles, drives the COP counter. The COP should be

serviced as soon as possible out of reset to guarantee the maximum

amount of time before the first timeout.

PORRST

OSC1

CGMXCLK

CGMOUT

RST

IAB

4096

CYCLES 32

CYCLES

$FFFE $FFFF

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The CO P module is di sabled if the RST pin or the IRQ pin is held at Vtst

while the MCU is in monitor mode. The COP module can be disabled

only through combinational logic conditioned with the high voltage signal

on the RST or the IRQ pin. This prevents the COP from becoming

disabled as a result of ext ernal noise. During a break state, Vtst on the

RST pin disables the COP module.

19.4.2.3 Illegal Opcode Reset

The SIM decodes si gnals from the CPU to detect i llegal instructio ns. An

illegal instruction sets the ILOP bit in the SIM reset status register

(SRSR) and causes a reset.

If the stop enable bit, STOP, in the mask option register is logic 0, the

SIM treats the STOP instruction as an illegal opcode and causes an

illegal opcode reset. The SIM actively pulls down the RST pin for all

internal reset sources.

19.4.2.4 Illegal Addr ess Reset

An opcode fetch f rom an unmapped address generates a n illegal

address reset. The SIM verifies that the CPU is fetching an opcode prior

to asserting the ILAD bit in the SIM reset status register (SRSR) and

resetting the MCU. A data fetch from an un mapped address does not

generate a reset. The SIM actively pulls down the RST pin for all internal

reset sources.

19.4.2.5 Low-Voltage Inhibit (LVI) Reset

The low-voltage inhibit module (LVI) asserts its output to the SIM when

the VDD voltage falls to the LVITRIPF voltage. The LVI bit in the SIM reset

status register (SRSR) is set, and the external reset pin (RST) is held low

while the SIM counter counts out 4096 CGMXCLK cycles. Sixty- four

CGMXCLK cycles later, the CPU is released from reset to allow the reset

vector sequence to occ ur. The SIM active ly pulls down the RST pin for

all internal reset sources.

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System Integration Module (SIM)

SIM Counter

MC68HC908GR8 — Rev 4.0 Technical Data

MOTOROLA System Integration Module (SIM) 281

19.4.2.6 Monitor Mode Entry Module Reset (MODRST)

The monitor mode entry module reset (MODRST) asserts its output to

the SI M when monitor mo de i s entered in the co ndi ti o n whe r e th e r ese t

vectors are blank ($00). (See Entering Monitor Mode.) When MODRST

gets asserted, a n internal reset occurs. The SIM active ly pulls down the

RST pin for all internal r eset sources.

19.5 SIM Counter

The SIM counter is us ed by the power-on res et mod ule (POR) and in

stop mode recovery to allow the oscillator time to stabilize before

enabling the internal bus (IBUS) clocks. The SIM counter also serves as

a prescaler for the computer operating properly module (COP). The SIM

counter overflow supplies the clock for the COP module. The SIM

counter is 13 bits long and is cl ocked by the falling edge of CGMXCLK.

19.5.1 SIM Counter During Power-On Reset

The powe r-on reset module (POR) detects po wer appli ed to the MCU.

At power-on, the POR circuit a sserts the signal PORRST. Once the SIM

is initialized, it enables the clock generation module (CGM) to drive the

bus clock state machine.

19.5.2 SIM Counter During Stop Mode Recovery

The SIM counter also is used for stop mode recovery. The STOP

instruction clears the SIM counter. After an interrupt, break, or reset, the

SIM senses the state of the short stop recovery bit, SS REC, in the mask

option register. If the SSREC bit is a logic 1, then the stop recovery is

reduced from the normal delay of 4096 CGMXCLK cycles down to 32

CGMXCLK cycles. This is ideal for applications using canned oscillators

that do not require long startup times from stop mode. External crystal

applic a tions should use the full stop recover y ti m e, t hat i s, w ith SSREC

cleared.

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19.5.3 SIM Counter and Reset States

External reset has no effect on the SIM counter. (See Stop Mode for

details.) The SIM counter is free-running after all reset states. (See

Active Resets fr om Internal Sources for counter control and internal

reset recovery sequences.)

19.6 Exception Control

Normal, sequential program execution can be changed in three different

ways:

•Interrupts:

–Maskable hardware CPU interrupts

–Non-maskable software interrupt instruction (SWI)

•Reset

•Break interrupts

19.6.1 Interrupts

At the beginning of an interrupt, the CPU saves the CPU regi ster

contents on the stack and sets the interrupt mask (I bit) to prevent

additional interrupts. At the end of an interrupt, the RTI instruction

recovers the CPU register contents from the stack so that normal

processing can resume. Figure 19-8 shows interrupt entry timing. Figure

19-9 sho ws interrupt recovery timin g.

Interrupts are latched, and arbitration is performed in the SIM at the start

of interr upt processin g. The arbitrat ion result is a const ant that the CP U

uses to det ermine which vecto r to fetch. On ce an interru pt is latched by

the SIM, no other interrupt can take precedence, regardless of priority,

until the latched inte rrup t is serviced (o r the I bit is clea re d). S ee Figure

19-10.

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Exception Control

MC68HC908GR8 — Rev 4.0 Technical Data

MOTOROLA System Integration Module (SIM) 283

Figure 19-8. Interrupt Entry Timing

Figure 19-9. Interrupt Recovery Timing

MODULE

IDB

R/W

INTERRUPT

DUMMY SP SP – 1 SP – 2 SP – 3 SP – 4 VECT H VECT L START ADDR

IAB

DUMMY PC – 1[7:0] PC – 1[15:8] X A CCR V DATA H V DATA L OPCODE

I BIT

MODULE

IDB

R/W

INTERRUPT

SP – 4 SP – 3 SP – 2 SP – 1 SP PC PC + 1

IAB

CCR A X PC – 1 [7:0] PC – 1 [15:8] OPCODE OPERAND

I BIT

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Figure 19-10. Interrupt Processing

19.6.1.1 Hardware Interrupts

A hardware interrupt does not stop the current instructio n. Processing of

a hardware interru pt begins after completion of the current instruction.

When the current instruction is complete , the SIM checks all pending

hardware interrupts. If interrupts are not masked (I bit clear in the

YES

AS MANY INTERRUPTS

I BIT SET?

FROM RESET

BREAK

I BIT SET?

IRQ0

INTERRUPT?

IRQ

INTERRUPT?

SWI

INSTRUCTION?

RTI

INSTRUCTION?

FETCH NEXT

INSTRUCTION

UNSTACK CPU REGISTERS

STACK CPU REGISTERS

SET I BIT

LOAD PC WITH INTERRUPT VECTOR

EXECUTE INSTRUCTION

YES

AS EXIST ON CHIP

INTERRUPT?

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Exception Control

MC68HC908GR8 — Rev 4.0 Technical Data

MOTOROLA System Integration Module (SIM) 285

conditi on code register) and if the corresponding interrupt enable bit is

set, the SIM proceeds with interrupt processi ng; otherwis e, the next

instr uc tion is f etched and exec uted.

If more than on e interrupt is pending at the end of an instruction

execution, the highest priority interrupt is serviced fi rst. Figure 19-11

demons trates what happens when two interrupts are pending. If an

interrupt is pending upon exit from the original interrupt service routine,

the pen di n g i nt er rupt is service d b efo re th e LD A i n str uctio n i s e x ecu ted .

Figure 19-11. Interrupt Recognition Example

The LDA opcode is prefetched by both the INT1 and INT2 RTI

instructions. However, in the case of the INT1 RTI prefetch, this is a

redundant operation.

NOTE: To maintain compatibility with the M6805 Family, the H register is not

pushed on the stack during interrupt entry. If the interrupt service routine

modifies the H register or uses the indexed addressing mode, software

should save t he H r egist er and the n restor e it p rior to exi ting th e ro utine.

CLI

LDA

INT1

PULH

RTI

INT2

BACKGROUND

#$FF

PSHH

INT1 INTERRUPT SERVICE ROUTINE

PULH

RTI

PSHH

INT2 INTERRUPT SERVICE ROUTINE

ROUTINE

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19.6.1.2 SWI Instruction

The SWI instruction is a non-maskable instruction that causes an

interrupt regardless of the state of the interrupt mask (I bit) in the

condition code register.

NOTE: A software interrupt pushes PC onto the stack. A software interrupt does

not push PC – 1, as a hardware in terrup t does.

19.6.1.3 Interrup t Status Registers

The flags in the interrupt status registers iden tify maskable interrupt

sources. Table 19-3 summarizes the interrupt sources and the in terrupt

status register flags that they set. The interrupt status registers can be

useful for debugging.

Table 19-3. Interrupt Sources

Priority Interrupt Source Interrupt Status

Highest Reset —

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SWI instr uc tio n —

IRQ pin I1

PLL I2

TIM1 channel 0 I3

TIM1 channel 1 I4

TIM1 overflow I5

TIM2 channel 0 I6

Reserved I7

TIM2 overflow I8

SPI receiver full I9

SPI tra nsmi tter empty I10

SCI receive error I11

SCI receive I12

SCI transmit I13

Keyboard I14

ADC conversion complete I15

Lowest Timebase module I16

Table 19-3. Interrupt Sources

Priority Interrupt Source Interrupt Status

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19.6.1.4 Interrupt Status Register 1

I6–I1 — In terrupt Flags 1–6

These flags indicate the presence of interrupt requests fr om the

sources shown in Table 19-3.

1 = Interru pt re qu est pr ese nt

0 = No interrupt request present

Bit 0 and B it 1 — Always read 0

19.6.1.5 Interrupt Status Register 2

I14–I7 — Interrupt Flags 14–7

These flags indicate the presence of interrupt requests fr om the

sources shown in Table 19-3.

1 = Interru pt re qu est pr ese nt

0 = No interrupt request present

Address: $FE04

Bit 7654321Bit 0

Read: I6 I5 I4 I3 I2 I1 0 0

Write:RRRRRRRR

Reset:00000000

R= Reserved

Figure 19-12. I nterrupt Status Register 1 (INT1)

Address: $FE05

Bit 7654321Bit 0

Read: I14 I13 I12 I11 I10 I9 I8 I7

Write:RRRRRRRR

Reset:00000000

R= Reserved

Figure 19-13. I nterrupt Status Register 2 (INT2)

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19.6.1.6 Interrupt Status Register 3

Bits 7–2 — Always read 0

I16–I15 — Interrupt Flags 16–15

These flags indicate the presence of an interrupt request from the

source shown in Ta bl e 19- 3.

1 = Interru pt re qu est pr ese nt

0 = No interrupt request present

19.6.2 Reset

All reset sources always have equal and highest priority and cannot be

arbitrated.

19.6.3 Break Interrupts

The br eak module can stop normal program flow at a software-

programmable break point by ass erting its break inter r upt output. S ee

Timer Interface Module (TIM). The SIM puts the CPU into the break state

by forcing it to the SWI vector location. Refer to the break interrupt

subsection of each module to see how each module is affected by the

break state.

Address: $FE06

Bit 7654321Bit 0

Read: 000000I16I15

Write:RRRRRRRR

Reset:00000000

R= Reserved

Figure 19-14. I nterrupt Status Register 3 (INT3)

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19.6.4 Status Flag Protection in Break Mode

The SIM controls whether status flags contained in other modules can

be cleared d uring break mode. Th e user can select whether flags ar e

protect ed fr om being cleared b y properly initiali zi ng th e b reak cl e ar fl ag

enable bit (BCFE) in the SIM break fla g control register (SBFCR).

Protecting flags in break mode ensures that set flags will not be cleared

while in break mode. This pr otection allows registers to be freely read

and written dur ing brea k mode without lo sing st atus flag information.

Setting the BCFE bit en ables the clearing mechanisms. Once cleared in

break mode, a flag remains cleared even when break mode is exited.

Status flags with a 2-step clearing mechanism — for example, a read of

one register followed by the read or write of another — are prot ecte d,

even when the first step is accomplished prior to entering break mode.

Upon leaving break mode, execution of the second step will clear the flag

as normal .

19.7 Low-Power Modes

Executing the WAIT or STOP instruction puts the MCU in a low power-

consumption mode for standby situations. The SIM holds the CPU in a

non-clocked state. The operation of each of these modes is described in

the following subsections. Both STOP and WAIT clear the interrupt mask

(I) in the condit ion code register, allowing interrup ts to occur.

19.7.1 Wait Mode

In wait mode, the CPU clocks are inactive while the peripheral clocks

contin ue to run. Figure 19-15 shows the timing for wait mode entry.

A module that is active during wait mode can wake up the CPU with an

interrupt if the interrupt is enabled. Stacking for the interrupt begins one

cycle after the WAIT instruction during which the interrupt occurred. In

wait mode, the CPU clocks are inactive. Refer to the wait mode

subsection of each module to see if the module is active or inactive in

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wait mode. Some modules can be programmed to be active in wait

mode.

Wait mode also can be exited by a reset or break. A break interrupt

during wait mode sets the SIM break s top/wait bit, SBSW, in the SIM

break status register (SBSR). If the COP disable bit, COPD, in the mask

option register is logic 0, then the computer operating properly module

(COP) is enabled and remains active in wait mode.

Figure 19-15. Wait Mode Entry Timing

Figure 19-16 and Figure 19-17 show the timing for WAIT recovery.

Figure 19-16. Wait Recovery from Interrupt or Break

WAIT ADDR + 1 SAME SAMEIAB

IDB PREVIOUS DATA NEXT OPCODE SAME

WAIT ADDR

SAME

R/W

Note: Previous data can be operand data or the WAIT opcode, depending on the

last instruction.

$6E0C$6E0B $00FF $00FE $00FD $00FC

$A6 $A6 $01 $0B $6E$A6

IAB

IDB

EXITSTOPWAIT

Note: EXITSTOPWAIT = RST pin, CPU interrupt, or break interrupt

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Figure 19-17. Wait Recovery from Internal Reset

19.7.2 Stop Mode

In stop mode, the SIM counter is reset and the system clocks are

disabled. An interrupt request from a module can cause an exit from stop

mode. Stacking for interrupts begins after the selected stop recovery

time has elapsed. Reset or break also causes an exit from stop mode.

The SIM disables the clock generator module outputs (CGMOUT and

CGMXCLK) in stop mode, stoppi ng the CPU and peripherals. Stop

recovery time is selectable using the SSREC bit in the mask option

normal delay of 4096 CGMXCLK cycles down to 32. This is ideal for

applications using canned oscillators that do not require long startup

times from stop mode.

NOTE: Ext ernal cr ysta l applications should use the full stop r ecovery time by

clearing the SSREC bit.

A break interrupt during stop mode sets the SIM break stop/wait bit

(SBSW) in the SIM break status register (SBSR).

The SIM counter is held in reset from the execution of the STOP

instruction until the beginning of stop recovery. It is then used to time the

recovery period. Figure 19-18 shows stop mode entry timing.

NOTE: To minimize st op cur rent, all pins conf igured as in puts sho uld be d rive n

to a logic 1 or logic 0.

IAB

IDB

RST

$A6 $A6

$6E0B RST VCT H RST VCT L

$A6

CGMXCLK

CYCLES 32

CYCLES

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SIM R egisters

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Figure 19-18. Stop Mode Entry Timing

Figure 19-19. Stop Mode Recovery from Interrupt or Break

19.8 SIM Registers

The SIM has three memory-mapped registers. Table 19-4 shows the

mapping of these registers.

STOP ADDR + 1 SAME SAMEIAB

IDB PREVIOUS DAT A NEXT OPCODE SAME

STOP ADD R

SAME

R/W

CPUSTOP

Note : Previous data can be operand data or the STOP opcode, depending

on the last instruction.

CGMXCLK

INT/BREAK

IAB STOP + 2 STOP + 2 SP SP – 1 SP – 2 SP – 3

STOP +1

STOP RECOVERY PERIOD

Table 19 -4 . SIM Registers

Address Register Access Mode

$FE00 SBSR User

$FE01 SRSR User

$FE03 SBFCR User

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19.8.1 SIM Brea k Status R egister

The SIM break status register (SBSR) contains a flag to indicate that a

brea k caus ed an exit from stop mode o r wait mode.

SBSW — SIM Break Stop/Wait

This status bit is useful in applications requiring a return to wait or stop

mode after exiting from a break inte rrupt. Clear SBSW by wri ting a

logic 0 to it. Reset clears SBSW.

1 = Stop mode or wait mode was exited by break interrupt.

0 = Stop mode or wait mode was not exited by break interrupt.

SBSW can be read within the break state SWI routine. The user can

modify the return ad dress on the stack by subtracting one fro m it. The

follow ing code is an example of this. W rit in g 0 to th e SBSW bit clears it.

Address: $FE00

Bit 7654321Bit 0

Read: RRRRRR

SBSW R

Write: Note(1)

Reset:00000000

R= Reserved

Note: 1. Writing a logic 0 clears SBSW.

Figure 19-20. SIM Break Status Register (SBSR)

This code works if the H register has been pushed onto the stack in the break

service routine software. This code should be executed at the end of the break

service routine software.

HIBYTE EQU 5 ;

LOBYTE EQU 6 ;

If not SBSW, do RTI ;

BRCLR SBSW,SBSR, RETURN ;

;See if wait mode or stop mode was exited by

break.

TST LOBYTE,SP ;If RETURNLO is not zero,

BNE DOLO ;then just decrement low byte.

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19.8.2 SIM Reset Status Register

This regi ste r contai ns six fl ag s that show the sour ce of the last reset

provi ded all previous reset stat us bits h ave been cleared . Clear the SIM

reset status register by reading it. A power-on reset sets the POR bit and

clears all other bits in the register.

POR — Power-On Reset Bit

1 = Last reset caused by POR circuit

0 = Read of SRSR

PIN — E xternal Reset B it

1 = Last reset caused by external reset pin (RST)

0 = POR or read of SRSR

COP — Computer Operating Properly Reset Bit

1 = Last reset caused by COP counter

0 = POR or read of SRSR

ILOP — Illegal Opcode Reset Bit

1 = Last reset caused by an illegal opcode

0 = POR or read of SRSR

DEC HIBYTE,SP ;Else deal with high byte, too.

DOLO DEC LOBYTE,SP ;Point to WAIT/STOP opcode.

RETURN PULH

RTI ;Restore H register.

Address: $FE01

Bit 7654321Bit 0

Read: POR PIN COP ILOP ILAD MODRST LVI 0

Write:

Reset:10000000

= Unimplemented

Figure 19-21. SIM Reset Status Register (SRSR)

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ILAD — Illegal Address Reset Bit (opcode fetches only)

1 = Last reset caused by an opcode fetch from an illegal address

0 = POR or read of SRSR

MODRST — Monitor Mode Entry Module Reset Bit

1 = Last reset caused by monitor mode entry when vector locations

$FFFE and $FFFF are $00 after POR while IRQ = VDD

0 = POR or read of SRSR

LVI — Low-Voltage Inhibit Reset Bit

1 = Last reset caused by the LVI circuit

0 = POR or read of SRSR

19.8.3 SIM Break Flag Control Register

The SIM break control register contains a bit that enables software to

clear status bits while the MCU is in a break state.

BCFE — Break Clear Flag En able Bit

This read/write bit enables software to clear status bits by accessing

status registe rs w hile t he MCU is in a break stat e. To clea r stat us bi ts

during the break state, the BCFE bit must be set.

1 = Status bits clearable during break

0 = Status bits not cle ar ab le dur i ng break

Address: $FE03

Bit 7654321Bit 0

Read: BCFERRRRRRR

Write:

Reset: 0

R= Reserved

Figure 19-22. SIM Break Flag Control Register (SBFCR)

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MC68HC908GR8 — Rev 4.0 Technical Data
MOTOROLA Serial Peripheral Interface (SPI) 297
 
Technical Data — MC68HC908GR8
Section 20. Serial Peripheral Interface  (SPI)
20.1  Contents
20.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .297
20.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 98
20.4 Pin Name Conven tions and I/O Register Addresses . . . . . . .298
20.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 99
20.6 Transmission Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .303
20.7 Queuing Transmission Data. . . . . . . . . . . . . . . . . . . . . . . . . .309
20.8 Error Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .310
20.9 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .314
20.10 Resetting the SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 16
20.11 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 17
20.12 SPI During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . .318
20.13 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .318
20.14 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .322
20.2  Introduction
This section describes the serial peripheral interface (SPI) module, 
which allows full-duplex, synchronous, serial communications with 
peripheral devices.
    
  
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Serial Peripheral Interface (SPI)

Technical Data MC68HC908GR8 — Rev 4.0

298 Serial Peripheral Interface (SPI) MOTOROLA

20.3 Features

Features of the SPI module include:

•Full-duplex operation

•Master and slave modes

•Double-buffered operation with separate transmit and receive

registers

•Four master mode frequencies (maximum = bus frequency ÷2)

•Maximum slave mode frequency = bus frequency

•Serial clock with programmable polarity and phase

•Two separately enabled interrupts:

–SPRF (SPI receiver full)

–SPTE (SPI transmitter empty)

•Mode fault error flag with CPU interrupt capability

•Overflow erro r flag with CPU interrupt capability

•Programmable wired-OR mode

• I2C (inter-integrated circuit) compatibility

•I/O (input/output) port bit(s) so ftware conf igurable with pullup

device(s) if configured as input port bit(s)

20.4 Pin Name Conventions and I/O Register Addresses

The text that follows describes the SPI. The SPI I/O pin names are SS

(slave select), SPSCK (SPI serial clock), CGND (clock ground), MOSI

(master out slave in), and MISO (ma ster in/slave out). The SPI shares

four I/O pins with four parallel I/O ports.

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Serial Peripheral Interface (SPI)

Functional Description

MC68HC908GR8 — Rev 4.0 Technical Data

MOTOROLA Serial Peripheral Interface (SPI) 299

The full names of the SPI I /O pins are sho wn in Table 20-1. Th e generic

pin names ap pear in the text that follows.

20.5 Functional Description

Figure 20-1 summarizes the SPI I/O registers and Figure 20-2 shows the

structure of the SPI module.

Table 20-1. Pin Name Conventions

SPI Ge neric

Pin Names: MISO MOSI SS SPSCK CGND

Full SPI

Pin Names: SPI PTD1/ATD9 PTD2/ATD1

0PTD0/AT

D8 PTD3/ATD11 VSS

Addr.Register Name Bit 7654321Bit 0

$0010 SPI Control Register

(SPCR)

Read: SPRIE DMAS SPMSTR CPOL CPHA SPWOM SPE SPTIE

Write:

Reset:00101000

$0011 SPI Status and Control

Read: SPRF ERRIE OVRF MODF SPTE MODFEN SPR1 SPR0

Write:

Reset:00001000

$0012 SPI Data Register

(SPDR)

Read: R7 R6 R5 R4 R3 R2 R1 R0

Write: T7 T6 T5 T4 T3 T2 T1 T0

Reset: Unaffected by reset

= Unimplemented

Figure 20-1. SPI I/O Register Summary

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Serial Peripheral Interface (SPI)

Technical Data MC68HC908GR8 — Rev 4.0

300 Serial Peripheral Interface (SPI) MOTOROLA

Figure 20-2. SPI Module Block Diagram

The SPI module allows fu ll-duplex, synchro nous, serial communication

between the MCU and peripheral devic es, incl uding other MCUs.

Software can poll the SPI status flags or SPI operation can be interrupt-

driven.

If a port bit is configured for input, then an internal pullup device may be

enabled for that port bit. See Port D Input Pullup Enable Register.

TRANSMI TTER CPU INTE RRUPT REQUEST

RESERVED

RECEIVE R/ERROR CPU INT ERRUPT REQUEST

76543210

SPR1

SPMSTR

TRANSMIT DATA REGIST ER

SHIFT REGI STER

SPR0

CGMOUT ÷ 2

CLOCK

SELECT

÷ 2

CLOCK

DIVIDER ÷ 8

÷ 32

÷ 128

CLOCK

LOGIC

CPHA CPOL

SPI

SPRIE

DMAS

SPE

SPWOM

SPRF

SPTE

OVRF

RESERVED

CONTROL

LOGIC

RECEIVE DATA REGISTER

SPTIE

SPE

INTERNAL BUS

FROM SIM

MODFEN

ERRIE

CONTROL

MODF

SPMSTR

MOSI

MISO

SPSCK

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Serial Peripheral Interface (SPI)

Functional Description

MC68HC908GR8 — Rev 4.0 Technical Data

MOTOROLA Serial Peripheral Interface (SPI) 301

The following paragraphs describe the operation of the SPI module.

20.5.1 Master Mode

The SPI operates in master mode when the SPI master bit, SPMSTR, is

set.

NOTE: Configure the SPI modules as master or slave before enabling them.

Enabl e the master SPI bef ore enab ling the slave SPI. Disable the sl ave

SPI before di sabling the master SPI. See SPI Control Register.

Only a master SPI module can initiate transmissions. Software begins

the transmission from a master SPI module by writing to the transmit

data register. If the shift register is empty, the byte immediately transfers

to the shift register, setting the SPI transmitter empty bit, SPTE. The byte

begin s shifting ou t on the M OSI pin unde r the con trol of t he serial clo ck.

See Fig ur e 20-3.

Figure 20-3. Full-Duplex Master-Slave Connections

SHIFT R EGISTER

BAUD RATE

GENERATOR

MASTER MCU SLAVE MCU

VDD

MOSI MOSI

MISO MISO

SPSCK SPSCK

SS SS

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Serial Peripheral Interface (SPI)

Technical Data MC68HC908GR8 — Rev 4.0

302 Serial Peripheral Interface (SPI) MOTOROLA

The SPR1 and SPR0 bits control the baud rate generator and determine

the speed of the shift register. See SPI Status and Control Register.

Through the SPSCK pin, the baud rate generator of the master also

controls the shift register of the slave peripheral.

As the b yte shifts ou t on the MOSI pin of the mast er, anoth er byte shifts

in from the slave on the master’s MISO pin. The transmission ends when

the receiver full bit, SPRF, becomes set. At the same time that SPRF

becomes set, the byte from the slave transfers to the receive data

Software clears SPRF by reading the SPI status and control register with

SPRF set and then reading the SPI data register. Writing to the SPI data

20.5.2 Slave Mode

The SPI o perates in sl ave mode whe n the SPMSTR bit is clear. In sl ave

mode, the SPSCK pin is the input for the serial clock from the master

MCU. Before a data transmission occurs, the SS pin of the slave SPI

must be at logic 0. SS must remain low until the transmission is

complete. See Mod e Fault Error.

In a sl ave SPI m odule, data enter s the shift reg ister under the co ntrol of

the serial clock from the master SPI module. After a byte enters the shift

SPRF bit is set. To prevent an overflow condition, slave software then

must read the receive data register before another full byte enters the

shift register.

The maximum frequency of the SPSCK for an SPI configured as a slave

is the bus clock speed (which is twice as fast as the fastest master

SPSCK clock that can be generated). The frequency of the SPSCK for

an SPI configured as a slave does not have to correspond to an y SPI

baud ra te. The baud rate only controls the speed of the SPSCK

genera ted by an SPI configured as a ma ster. Therefore, the frequency

of the SPSCK for an SPI configured as a slave can be any frequency

less than or equal to the bus speed.

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Serial Peripheral Interface (SPI)

Transmi ssi on Form ats

MC68HC908GR8 — Rev 4.0 Technical Data

MOTOROLA Serial Peripheral Interface (SPI) 303

When the master SPI starts a transmission, the data in the slave shift

data register. The slave must write to its transmit data register at least

one bus cycle before the master starts the next transmission. Otherwise,

the byte already in the slave shift register shifts out on the MISO pin.

Data written to the slave shift register during a transmission remains in

a buffer until the end of the transmission.

When the cl ock p ha se b it (C PHA ) is se t, th e fir st ed ge of SPSCK starts

a transmission. When CPHA is clear, the falling edge of SS starts a

transmission. See Transmission Formats.

NOTE: SPSCK must be in the proper idle state before the slave is enabled to

prevent S PSCK from appearing as a c lock edge.

20.6 Transmission Formats

During an S PI tr an smi ssio n, da ta i s si mu l tan eo usly tr ansmi tte d ( shi fte d

out serially) and received (shifted in serially). A serial clock synchronizes

shifting and sampling on the two serial data lines. A slave select line

allows selection of an individual slave SPI device; slave devices that are

not s elected do no t inter fere with SPI bus activ ities. On a master SPI

device, the slave select line can optionally be used to indicate multiple-

master bus contention.

20.6.1 Clock Phase and Polarity Controls

Software can select any of four combinations of serial clock (SPSCK)

phase and polarity using two bits in the SPI control register (SPCR). The

clock polarity is specified by the CPOL control bit, which selects an

active high or low clock and has no significant effect on the transmission

format.

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Serial Peripheral Interface (SPI)

Technical Data MC68HC908GR8 — Rev 4.0

304 Serial Peripheral Interface (SPI) MOTOROLA

The clock phase (CPHA) control bit selects one of two fundamen tally

diff erent tran smission fo rmats. The clo ck phase and polarity should be

identical for the master SPI device and the communicating slave device.

In some cases, the phase and polarity are changed between

trans m issions to allow a master devi ce to communicate with periph eral

slaves having different requirements.

NOTE: Before writing to the CPOL bit or the CPHA bit, disable the SPI by

clearing the SPI enable bit (SPE).

20.6.2 Tra n smission For mat When CPHA = 0

Figure 20-4 shows an SPI transmission in which CPHA is logic 0. The

figure should not be used as a replacement for data sheet parametric

information.

Two waveforms are shown for SPSCK: one for CPOL = 0 and another

for CPOL = 1. The diagram may be interpreted as a master or slave

timing diagram since the serial clock (SPSCK), master in/slave out

(MISO), and master out/slave in (MOSI) pins are directly connected

between the master and the slave. The MISO signal is the output from

the slave, and the MOSI signal is the output from the master. The SS line

is the slave select input to the slave. The slave SPI drives its MISO

output only when its slave select input (SS) is at logic 0, so that only the

selec ted sl ave dr ives to the master. The SS pin of the master is not

shown b ut is a ssumed to be in active. The SS pin o f the m aster must b e

high or must be reconfigur ed as general-purp ose I/O not affecting the

SPI. See Mode Fault Error. When CPHA = 0, the first SPSCK edge is the

MSB ca pture st robe. Therefo r e, the s lave must be gin driving its data

before the first SPSCK edge, a nd a falling edge on the SS p in is used t o

start the slave data transmission. The slave’s SS pin must be togg led

back to hi gh and then low again between each byte transmitted as

shown in Figure 20-5.

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Serial Peripheral Interface (SPI)

Transmi ssi on Form ats

MC68HC908GR8 — Rev 4.0 Technical Data

MOTOROLA Serial Peripheral Interface (SPI) 305

Figure 20-4. Transmission Format (CPHA = 0)

Figure 20-5. CPHA/SS Ti m i ng

When CPHA = 0 for a slave, the falling edge of SS indicates the

begin ning of the transmission. This causes th e SPI to lea ve its idle state

and begin driving the MISO pin with the MSB of its data. Once the

transmission be gins, no new data is allowed into the shift regi ster from

the tran smit data register. Therefore, the SPI data register of the slave

must be loaded with transmit data before the falling edge of SS. Any data

written after the fal li ng ed ge is stor ed in the tran smi t da ta re gister and

transferred to the shift register after the current transmission.

20.6.3 Tra n smission Format When CPHA = 1

Figure 20-6 shows an SPI transmission in which CPHA is logic 1. The

figure should not be used as a replacement for data sheet parametric

information. Two waveforms are shown for SPSCK: one for CPOL = 0

and anot her for CPOL = 1. The diagram may be interpreted as a master

or slave timing dia gram since the se rial clock (SPS CK), master in/slave

BIT 6 BI T 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB

MSB

BIT 6 BI T 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB

MSB

12345678

SPSCK CYCLE #

FOR REFERENCE

SPSCK ; CPO L = 0

SPSCK; CPOL =1

MOSI

FROM MASTER

MISO

FROM SLAVE

SS; TO SLA VE

CAPTURE STROBE

BYTE 1 BYTE 3

MISO/MOSI BYTE 2

MAST ER SS

SLAVE SS

CPHA = 0

SLAVE SS

CPHA = 1

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Serial Peripheral Interface (SPI)

Technical Data MC68HC908GR8 — Rev 4.0

306 Serial Peripheral Interface (SPI) MOTOROLA

out (M ISO), and m aster out/sla ve in (MOS I) pins are d ire ctly con nected

between the master and the slave. The MISO signal is the output from

the slave, and the MOSI signal is the output from the master. The SS line

is the slave select input to the slave. The slave SPI drives its MISO

output only when its slave select input (SS) is at logic 0, so that only the

selec ted sl ave dr ives to the master. The SS pin of the master is not

shown b ut is a ssumed to be in active. The SS pin o f the m aster must b e

high or must be reconfigur ed as general-purp ose I/O not affecting the

SPI. See Mode Fault Error. When CPHA = 1, the m aste r begins drivi ng

its MOSI pin on the first SPSCK ed ge. Therefore, the slave uses the first

SPSCK e dge as a start tra nsmission sign al. The SS pin can remain low

between transmissions. This format m ay be preferable in systems

having only one master and only one slave driving the MISO data line.

Figure 20-6. Transmission Format (CPHA = 1)

BIT 6 BI T 5 BIT 4 BIT 3 BI T 2 BIT 1 LSB

MSB

BIT 6 BI T 5 BIT 4 BIT 3 BI T 2 BIT 1 LSB

MSB

12345678

SPSC K C YCL E #

FOR REFERENCE

SPSCK ; CPO L = 0

SPSCK ; C POL =1

MOSI

FROM MA STER

MISO

FROM SLAVE

SS; TO SLAVE

CAPTURE STROBE

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Serial Peripheral Interface (SPI)

Transmi ssi on Form ats

MC68HC908GR8 — Rev 4.0 Technical Data

MOTOROLA Serial Peripheral Interface (SPI) 307

When CPHA = 1 for a slave, the first edge of the SPSCK indicates the

begin ning of the transmission. This causes th e SPI to lea ve its idle state

and begin driving the MISO pin with the MSB of its data. Once the

transmission be gins, no new data is allowed into the shift regi ster from

the tran smit data register. Therefore, the SPI data register of the slave

must be loaded with transmit data before the first edge of SPSCK. Any

data written after the first edge is stored in the tran smit data register and

transferred to the shift register after the current transmission.

20.6.4 Transmission Initiation Latency

When the SPI is configured as a master (SPMSTR = 1), writing to the

SPDR starts a transmission. CPHA has no effect on the delay to the start

of the transmission, but it does affect the initial state of the SPSCK

signal. W hen CPHA = 0, the SPSCK signal remains inact ive for the fi rst

half of the first SPSCK cycle. When CPHA = 1, the first SPSCK cycle

begins with an edge on the SPSCK line from its inactive to its active

level. The SPI clock rate (selected by SPR1:SPR0) affects the delay

from the write to SPDR and the start of the SPI transmission. See Figure

20-7. The internal SPI clock in the master is a free-running derivative of

the internal MCU clock. To conserve power, it is enabled only when both

the SPE and SPMSTR bits are set. SPSCK edges occur halfway through

the low time of the internal MCU clock. Since the SPI clock is fr ee-

running, it is uncertain where the write to the SPDR occurs relative to the

slower SPSCK. This uncertainty causes the variation in the initiation

delay shown in Figu re 20-7. This de lay is no long er than a sing le SPI b it

time. That is, the maximum delay is two MCU bus cycles for DIV2, e ight

MCU bus cycles for DIV8, 32 MCU bus cycles for DI V32, and 128 MCU

bus cycles for DIV128.

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Serial Peripheral Interface (SPI)

Technical Data MC68HC908GR8 — Rev 4.0

308 Serial Peripheral Interface (SPI) MOTOROLA

Figure 20-7. Transmission Start Delay (Master)

WRITE

TO SPDR INITIATION DELA Y

BUS

MOSI

SPSCK

CPHA = 1

SPSCK

CPHA = 0

SPSCK CYCLE

NUMBER

MSB BIT 6

CLOCK

WRITE

TO SPDR

EARLIEST

LATEST

SPSCK = INT ERNAL CLOCK ÷ 2;

EARLIEST LATEST

2 POSSIBLE START POINTS

SPSC K = INTERN AL C LO C K ÷ 8;

8 POSSIBLE STAR T PO INTS

EARLIEST LATESTSPSCK = INTERNAL CLOCK ÷ 32;

32 POSSIBLE START POI N TS

EARLIEST LATESTSPSC K = INTERN AL CL O C K ÷ 128;

128 POSSIBLE ST A R T POI NTS

WRITE

TO SPD R

WRITE

TO SPD R

WRITE

TO SPD R

BUS

CLOCK

BIT 5

BUS

CLOCK

BUS

CLOCK

BUS

CLOCK









INITIATION DELAY FROM WRIT E SPDR TO TRANSFER BEGIN

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Serial Peripheral Interface (SPI)

Queuing Transmission Data

MC68HC908GR8 — Rev 4.0 Technical Data

MOTOROLA Serial Peripheral Interface (SPI) 309

20.7 Queuing Transmission Data

The double-buffered transmit da ta register allows a data byte to be

queued and tran smitted. For an SPI c onfigured as a master, a queued

data byt e is transmitted immediately af ter the previous transmission ha s

compl ete d. Th e SPI tr ansmi tte r empt y flag (SPTE ) in di cat es when the

transmit data buffer is ready to accept new data. Write to the transmit

data register only when the SPTE bit is high. Figure 20-8 shows the

timing associated with doing back-to-back transmissions with the SPI

(SPSCK has CPHA: CPOL = 1:0).

Figure 20-8. .SPRF/SPTE CPU Interrupt Timing

The transmit data buffer allows back-to-back transmissions without the

slave precisely timing its writes between transmissions as in a system

with a single data buffer. Also, if no new data is written to the data buffer,

the last value contained in the shift register is the next data word to be

transmitted.

BIT

MOSI

SPSCK

SPTE

WRITE TO SPDR 1

CPU WRITES BYTE 2 TO SPDR, QUEUEING BYTE 2

CPU WRITES BYTE 1 TO SPDR, CLEARING SPTE BIT.

BYTE 1 TRANSFERS FROM TRANSMIT DATA

SPRF

READ SPSCR

MSB BIT

6BIT

5BIT

4BIT

2BIT

1LSBMSB BIT

6BIT

5BIT

4BIT

3BIT

2BIT

1LSBMSB BIT

BYTE 2 TRANSFERS FROM TRANSMIT DATA

CPU WRITES BYTE 3 TO SPDR, QUEUEI NG BYTE

BYTE 3 TRANSFERS FROM TRANSMIT DATA

4FIRST INCOMING BYTE TRANSFERS FROM SHIFT

6CPU READS SPSCR WITH SPRF BIT SET.

SECOND INCOMING BYTE TRANSFERS FROM SHIFT

AND CLEARIN G SPTE BIT.

SPRF BIT.

3 AND CLEARING SPTE BIT.

SPRF BIT.

12 CPU READS SPDR, CLEARING SPRF BIT.

BIT

5BIT

BYTE 1 BYTE 2 BYTE 3

712

READ SPDR

7CPU READS SPDR, CLEARING SPRF BIT.

11 CPU READS SPSCR WITH SPRF BIT SET.

CPHA:CP OL = 1:0

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Serial Peripheral Interface (SPI)

Technical Data MC68HC908GR8 — Rev 4.0

310 Serial Peripheral Interface (SPI) MOTOROLA

For an idle ma ster or idle slave tha t has no data lo aded in to its transm it

buffer, the SPTE is set again no more than two bus cycles after the

transmit buffer empties into the shift register. This allows the user to

queue up a 16-bit value to send. For an already active slave, the load of

the shift register cannot occur until the transmission is completed. This

implies that a back-to-back wr ite to the transmit data register is not

possible. The SPTE indicates when the next write can occur.

20.8 Error Conditions

The following flags signal SPI error conditions:

•Overflow (OVRF) — Failing to read the SPI data register before

the next full byte enters the shift register sets the OVRF bit. The

new byte does not trans fer to the receiv e data register, and the

unread byte still can be read. OVRF is in the SPI status and control

•Mode fault error (MODF) — The MODF bit indicates that the

voltag e on the slave sel ect pi n (SS ) is inconsistent with the mode

of the SPI. MODF is in the SPI status and control register.

20.8.1 Overflow Error

The overflow fl ag (OVRF) becomes set if the receive data register still

has unread data from a previous transmission when the capture strobe

of bit 1 of the next transmission occurs . Th e bi t 1 ca pture strobe occ ur s

in the middle of SPSCK cycle 7. (See Figure 20-4 and Figure 20-6.) If an

overflow occurs, all data received after the overflow and before the

OVRF bit is cleared does not transfer to the receive data register and

does not set the SPI receiver full bit (SPRF). The unread data that

transferred to the receive data register before the overflow occurred can

still be read. Therefore, an overflow error al ways indicates the loss of

data. Clear the overflow flag by reading the SPI status and control

OVRF generates a receiver/error CPU interrupt request if the error

interrupt enable bit (ERRIE) is also set. The SPRF, MODF, and OVRF

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Serial Peripheral Interface (SPI)

Error Conditions

MC68HC908GR8 — Rev 4.0 Technical Data

MOTOROLA Serial Peripheral Interface (SPI) 311

interrupts share the same CPU interrupt vector. See Figure 20-11. It is

not possible to enable MODF or OVRF individually to generate a

receiver/erro r CPU interrupt request. However, leavin g MODFEN low

prevents MODF from being set.

If the CPU SPRF interrupt is enabled and the OVR F interrupt is not,

watch for an overflow condition. Figure 20-9 shows how it is possible to

miss an overflow. The first part of Figure 20-9 shows how it is possible

to read the SPSCR and SPDR to clear the SPRF without problems.

However , as illustrated by the second transmission exa mple, the OVRF

bit can be set in be tween the time that SPSCR a nd SPDR a r e read.

Figure 20-9. Missed Read of Overflow Condition

In this case, an overflow can be missed ea sily. Since no more SPRF

interr upts can be generate d until this OV RF is serviced, it is not obvious

that bytes are being lost as more tr ansmissions are completed. To

preven t this, e ithe r enabl e the OV RF in terrup t or do anoth er re ad of th e

SPSCR following the read of the SPDR. This ensures that the OVRF

was not set befor e the SPRF was cleared an d that futur e transmissions

can set t he SPRF bi t. Figure 20-10 illustrates this process. Generally, to

avoid t his second SPS CR read, enabl e the OVRF to the CPU by settin g

the ERRIE bit.

READ

OVRF

SPRF

BYTE 1 BYTE 2 BYTE 3 BYTE 4

BYTE 1 SETS SPR F BIT.

CPU READS SPSCR WITH SPRF BIT SET

CPU READS BYTE 1 IN SPDR,

BYTE 2 SETS SPRF BIT.

CPU READS SPSCR WITH SPRF BIT SET

BYTE 3 SETS OVRF BIT. BYTE 3 IS LOST.

CPU READS BYTE 2 IN SPDR, CLEARING SPRF BIT,

BYTE 4 FAILS TO SET SPRF BIT BECAUSE

CLEARIN G SP RF BIT. BUT NOT OVRF BIT.

OVRF BIT IS NOT CLEARED. BYTE 4 IS LOST.

AND OVRF BIT CLEA R. AND OVRF BIT CLEAR.

SPSCR

SPDR

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Figure 20-10. Clearing SPRF When OVRF Interrupt Is Not Enabled

20.8.2 Mode Fault Error

Setting the SPMSTR bit selects master mode and configures the

SPSCK and MOSI pins as outputs and the MISO pin as an input.

Clearing SPMSTR select s slave mode an d configures the SPSCK and

MOSI pi ns as inputs and the MISO pin a s an output. Th e mode faul t bit,

MODF, becomes set any time the state of the slave select pin, SS, is

inconsiste nt wit h the mode select ed by SPM STR.

To prevent SPI pin contention and da mage to the MCU, a mode fault

error occu rs if:

•The SS pin of a slave SPI goes high during a transmission

•The SS pin of a master SPI goes low at any time

For the MOD F fl ag to be set, th e m ode f ault error ena ble b it ( MODFEN )

must be set. Clearing the MODFEN bit does not clear the MODF flag but

does prevent MODF from being set again after MODF is cleared.

READ

OVRF

SPRF

BYTE 1 BYTE 2 BYTE 3 BYTE 4

BYTE 1 SETS SPRF BIT.

CPU READS SPSCR WITH SPRF BIT SET

CPU READS BYTE 1 IN SPDR,

CPU READS SPSCR AGAIN

BYTE 2 SETS SPRF BIT.

CPU READS SPSCR WITH SPRF BIT SET

BYTE 3 SETS OVRF BIT. BYTE 3 IS LOST.

CPU READS BYTE 2 IN SPDR,

CPU READS SPSCR AGAIN

CPU READS BYTE 2 SPDR,

BYTE 4 SETS SPRF BIT.

CPU READS SPSCR.

CPU READS BYTE 4 IN SPDR,

CPU READS SPSCR AGAIN

3CLEARING SPRF BIT.

4TO CHECK OVRF BIT.

CLEARING SPRF BIT.

TO CHECK OVRF BIT.

10 CLEARING OVRF BIT.

CLEARING SPRF BIT.

TO CHECK OVRF BIT.

SPI RECEIV E

COMPLETE

AND OVRF BIT CLEAR.

SPSCR

SPDR

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Serial Peripheral Interface (SPI)

Error Conditions

MC68HC908GR8 — Rev 4.0 Technical Data

MOTOROLA Serial Peripheral Interface (SPI) 313

MODF generates a receiver/error CPU interrupt request if the error

interrupt enable bit (ERRIE) is also set. The SPRF, MODF, and OVRF

interrupts share the same CPU interrupt vector. See Figure 20-11. It is

not possible to enable MODF or OVRF individually to generate a

receiver/erro r CPU interrupt request. However, leavin g MODFEN low

prevents MODF from being set.

In a ma ster SPI with the mode fa ult enable bit (MODFEN) set, the mode

fault flag (MODF) is set if SS goes to logic 0. A mode fault in a master

SPI causes the following events to occur:

•If ERRIE = 1, the SPI generates an SPI receiver/error CPU

interrupt request.

•The SPE bit is cleared.

•The SPTE bit is set.

•The SPI state counter is cleared.

•The data direction register of the shared I/O port regains control of

port drivers.

NOTE: To prevent bus contention with another master SPI after a mode fault

error, clear all SPI bits of the data direction register of the shared I/O port

before enabling the SPI.

When configured as a slave (SPMSTR = 0), the MODF flag is set if SS

goes high during a transmission. When CPHA = 0, a transmission begins

when SS goes low and ends once the incoming SPSCK goes back to its

idle level following the shift of the eighth data bit. When CPHA = 1, the

trans m ission begins when th e SPSCK leaves its idle level and SS is

already low. The transmission continues until the SPSCK returns to its

idle level following the shift of the last data bit. See Transmission

Formats.

NOTE: Setting the MODF flag does not clear the SPMSTR bit. The SPMSTR bit

has no function when SPE = 0. Reading SPMSTR when MODF = 1

shows the difference between a MODF occurring when the SPI is a

master and when it is a slave.

When CP HA = 0, a MODF occurs if a slave is sele cted (SS is at logic 0)

and later unselected (SS is at logic 1) even if no SPSCK is sent to that

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slave. This happens because SS at logic 0 indicates the start of the

transmission (MISO driven out with the value of MSB) for CPHA = 0.

When CPHA = 1, a slave can be selected and then later unselected with

no transmission occurring. Therefore, MODF does not occur since a

transmission was never begun.

In a slave SPI (MSTR = 0), the MODF bit generates an SPI

receiver/error CPU interrupt request if the ERRIE bit is set. The MODF

bit doe s not clea r the S PE bit or re set the S PI in any w ay. Sof tware ca n

abort the SPI transmission by clearing the SPE bit of the slave.

NOTE: A logic 1 voltage on the SS pin of a slave SPI puts the MISO pin in a high

impe dan ce state . Also , the sla ve SPI ignores all incoming SPSCK

clocks, even if it was already in the middle of a transmission.

To clear the MODF flag, read the SPSCR with the MODF bit set and then

write to the SPCR re gister. This entire clearing mechanism must occur

with no MODF c ondition existing or else the flag is not cleared.

20.9 Interrupts

Four SPI status flags can be enabled to generate CPU interrupt

requests.

Table 20-2. SPI Interrupts

Flag Request

SPTE

T ransmitter empty SPI transmitter CPU interrupt request

(DMAS=0, SPTIE=1, SPE=1)

SPRF

Receiver full SPI receiver CPU interrupt request

(DMAS=0, SPRIE=1)

OVRF

Overflow SPI receiver/error interrupt reque st (ERRIE = 1)

MODF

Mode fault SPI receiver/error interrupt reque st (ERRIE = 1)

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Serial Peripheral Interface (SPI)

Interrupts

MC68HC908GR8 — Rev 4.0 Technical Data

MOTOROLA Serial Peripheral Interface (SPI) 315

Reading the SPI status and control register with SPRF set and then

reading the receive data register clea rs SPRF. The clearing mechanism

for the SPTE flag is always just a write to the transmit data register.

The SPI tr ansmitter interrupt enable bit (SPTIE) enables the SPTE flag

to gener ate tr ansmit ter CP U int errupt r eques ts, provid ed that th e SPI is

enabled (SPE = 1).

The SPI re ceiver interrupt enable bit (SPRIE) enable s the SPRF bit to

gener ate recei ver CPU i nterru pt re quests, rega rdless o f the st ate of the

SPE bit. See Figure 20-11.

The error interrupt enable bit (ERRIE) enables both the MODF and

OVRF bits to ge nerate a receiver/error CPU interrupt request.

The mode fault enable bit (MODFEN) can prevent the MODF flag from

being set so that only the OVRF bit is enabled by the ERRIE bit to

generate receiver/erro r CPU interrupt requests.

Figure 20-11. SPI Interrupt Request Generation

SPTE SPTIE

SPRFSPRIE

DMAS

ERRIE

MODF

OVRF

SPE

CPU INTERRUPT REQUEST

NOT AVAILABLE

SPI TRANSMITTER

NOT AVAILABLE

SPI RECEIVER/ERR OR

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The following sources in the SPI status and control register can generate

CPU interrupt requests:

•SPI receiver full bit (SPRF) — The SPRF bit becomes set every

time a byte transfers from the shift register to the receive data

SPRF generates an SPI receiver/error CPU interrupt request.

•SPI transmitter empty (SPTE) — The SPTE bit becomes set every

time a byte transfers from the transmit data register to the shift

SPTE ge nerates an SPTE CPU i nterrupt request.

20.10 Resetting the SPI

Any system reset completely resets the SPI. Partial resets occur

whenever the SPI enable bit (SPE) is low. Whenever SPE is low, the

following occurs:

•The SPTE flag is set.

•Any transmission currently in progress is aborted.

•The shift register is cleared.

•The SPI state counter is cleared, making it ready for a new

complete transmission.

•All the SPI port logic is def aul te d back to bei n g gen eral -pur p ose

I/O.

These items ar e reset only by a system reset:

•All control bits in the SPCR register

•All control bits in the SPSCR register (MODFEN, ERRIE, SPR1,

and SPR0 )

•The status flags SPRF, OVRF, and MODF

By not resetting the control bits when SPE is low, the user can clear SPE

between transmissions wi tho ut h avin g to set all control bi ts ag ai n when

SPE is set ba ck high for the next transmission.

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Serial Peripheral Interface (SPI)

Low-Power Modes

MC68HC908GR8 — Rev 4.0 Technical Data

MOTOROLA Serial Peripheral Interface (SPI) 317

By not resetting the SPRF, OVRF , and MODF flags, the user can still

service these interru pts after the SPI has been disabled. The user can

disable the SPI by writing 0 to the SPE bit. The SPI can also be disabled

by a mode fault occurring in an SPI that was configured as a master with

the MODFEN bit set.

20.11 Low-Power Modes

The WAIT and STOP instructions put the MCU in low power-

consumptio n standby mode s.

20.11 .1 Wait Mode

The SPI module remains active after the execution of a WAIT instruction.

In wait mode the SPI module registers are not accessible by the CPU.

Any en abled CPU interr upt request from the SPI module can br ing the

MCU out of wait mode.

If SPI module functions are not required during wait mode, reduce power

consumption by disabling the SPI module before executing the WAIT

instruction.

To exit wai t mode when an ove rflow condition o ccurs, enable th e OVRF

bit to generate CPU interrupt requests by setting the error interrupt

enable bit (ERRIE). See Interrupts.

20.11.2 Stop Mode

The SPI mo dule is inactive after the execution of a STOP instruction.

The STOP in structio n does n ot affect regi ster condi tions. SP I oper atio n

resumes after an external inte rru pt. If stop mode is exited by reset, any

transfer in progress is aborted, and the S PI is res et.

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20.12 SPI During Break Interr upts

The system integration module (SIM) controls whether status bits in

other modules can be cleared during the break state. The BCFE bit in

the SIM brea k flag control register (SBFCR) enables software to clear

status bits duri ng the brea k state. See System Integration Module (SIM).

To allow software to clear status bits during a break interrupt, write a

logic 1 to the BCFE bit. If a status bit is cleared during the break state, it

remains cleared when the MCU exits the break state.

To prote ct status bits dur ing the brea k state, writ e a logic 0 to th e BCFE

bit. Wi t h BC FE a t l og ic 0 ( it s default state) , soft ware can read an d w r it e

I/O registers during the break state without affecting status bits. Some

status bits have a 2-step read/write clearing pr ocedure. If sof tware does

the first step on such a bit before the break, the bit cannot change during

the br ea k state as lo ng a s B CFE is at l og ic 0. After the b reak, doing the

second step clears the status bit.

Since the SPTE bi t ca nno t be cl ea re d du r ing a br ea k with the BCFE bi t

cleared, a write to the transmit data register in break mode does not

initiate a tran smission nor is this data transferred into the shift register.

Therefore, a write to the SPDR in break mode with the BCFE bit cleared

has no effect.

20.13 I/O Signals

The SPI m odule has five I/O pins an d shares four of them with a parallel

I/O port. They are:

•MISO — Data received

•MOSI — Data transmitted

•SPSCK — Serial clock

•SS — Slave select

•CGND — Clock groun d (internally connected to VSS)

The SPI has limited inter-integrated circuit (I2C) capability (requiring

software support) as a master in a single-master environment. To

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I/O Signals

MC68HC908GR8 — Rev 4.0 Technical Data

MOTOROLA Serial Peripheral Interface (SPI) 319

communicate with I2C peripherals, MOSI becomes an open-drain output

when the SPWOM bit in the SPI control register is set. In I2C

communication, the MOSI and MISO pins are connected to a

bidirectional pin from the I2C peripheral and throu gh a pul lup resisto r to

VDD.

20.13.1 MISO (Master In/Slave Out)

MISO is one of th e two SPI module pins that tran smits serial data. I n full

duplex operation, the MISO pin of the master SPI module is connected

to the MISO pin of the slave SPI module. The master SPI simultaneously

receives data on its MISO pin and transmits da ta from its MOSI pin.

Slave output data on the MISO pin is enabled only when the SPI is

configured as a slave. The SPI is configured as a slave when its

SPMSTR bit i s lo gi c 0 a nd its SS pin is at logic 0. To support a multiple-

slave system, a logic 1 on the SS pin puts the MISO pin in a high-

impedan ce state.

When enabled, the SPI controls data direction of the MISO pin

regardless of the state of the data direction register of the shared I/O

port.

20.13.2 MOSI (Mas ter Out/Slave In)

MOSI is one of the two SPI module pins that transmits serial data. In full-

duplex operation, the MOSI pin of the master SPI module is connected

to the MOSI pin of the slave SPI module. The master SPI simultaneously

transmits data from its MOSI pin and receives data on its MISO pin.

When enabled, the SPI controls data direction of the MOSI pin

regardless of the state of the data direction register of the shared I/O

port.

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20.13 .3 SPSCK (Seria l Clock)

The serial clock synchronizes data transmission between master and

slave devices. In a master MCU, the SPSCK pin is the clock output. I n a

slave MCU, the SPSCK pin is the clock input. In full-duplex operation,

the master and slave MCUs exchange a byte of data in eight serial clock

cycles.

When enabled, the SPI controls data direction of the SPSCK pin

regardless of the state of the data direction register of the shared I/O

port.

20.13.4 SS (Slave Select)

The SS pin has various functions depending on the cur r ent state of the

SPI. Fo r an SPI configured as a sl ave , th e SS is used to select a slave .

For CPHA = 0, the SS is u s ed to d efi ne t he star t of a transmission. See

Transmission Formats. Since it is used to indicate the start of a

transmission, the SS must be toggled high and low b etween each byte

transmitted for the CPHA = 0 format. However, it can remain low

between transmissions for the CPHA = 1 format. See Figu re 20-12.

Figure 20-12CPHA/SS Timin g

When an SPI is configured as a slave, the SS pin is always conf ig ur ed

as an input. It cannot be used as a general-purpose I/O regardless of the

state of the MODFEN control bit. However, the MODFEN bit can still

prevent the state of the SS from crea ting a MODF er ror. See SPI Sta tus

and Cont rol Register.

NOTE: A logic 1 voltage on the SS pin of a slave SPI puts the MISO pin in a high-

impedance state. The slave SPI ignores all incoming SPSCK clocks,

even if it was already in the middle of a transmission.

BYTE 1 BYTE 3

MISO/MOSI BYTE 2

MASTER SS

SLAVE SS

CPHA = 0

SLAVE SS

CPHA = 1

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Serial Peripheral Interface (SPI)

I/O Signals

MC68HC908GR8 — Rev 4.0 Technical Data

MOTOROLA Serial Peripheral Interface (SPI) 321

When an SPI is configured as a master, the SS input can be used in

conjun ction with the MODF flag to prevent mul tiple master s from driving

MOSI and SP SCK. See Mode Fault Error. For the state o f t he SS pi n to

set the MODF flag, the MODFEN bit in the SPSCK regi ster must be set.

If the MODFEN bit is low for an SPI master, the SS pin c an be us ed as

a general-purpose I /O under the control of the data directio n register of

the sha red I/O port. With MODFEN high, it is an input-only pin to the SPI

regardless of the state of the data direction register of the shared I/O

port.

The CPU can always read the state of the SS pin by configuring the

appropriate pin as an input and reading the port data register. See Table

20-3.

20.13.5 CGND (Clock Ground)

CGND is the ground return for the serial clock pin, SPSCK, and the

grou nd for the port outpu t buffers. It is internally con nected to VSS as

shown in Table 20-1 .

Table 20-3. SPI Configuration

SPE SPMSTR MODFEN SPI Configuration State of SS Logic

0X(1) X Not enable d General-purpose I/O;

SS ignored by SPI

1 0 X Slave Input-only to SPI

1 1 0 Master without MODF General-purpose I/O;

SS ignored by SPI

1 1 1 Master with MODF Input-only to SPI

Note 1. X = Don’t care

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20.14 I/O Registers

Three registers control and monitor SPI operatio n:

•SPI contro l register (SPCR )

•SPI status and control register (SPSCR)

•SPI data register (SPDR)

20.14.1 SPI Control Register

The SPI control register:

•Enables SPI module interrupt requests

•Configures the SPI module as master or s l ave

•Selects serial clock polarity and phase

•Configures the SPSCK, MOSI, and MISO pins as open-drain

outputs

•Enabl es the SPI mo dule

Address: $0010

Bit 7654321Bit 0

Read: SPRIE DMAS SPMSTR CPOL CPHA SPWOM SPE SPTIE

Write:

Reset:00101000

= Unimplemented

Figure 20-13. SPI Control Register (SPCR)

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Serial Peripheral Interface (SPI)

I/O Registers

MC68HC908GR8 — Rev 4.0 Technical Data

MOTOROLA Serial Peripheral Interface (SPI) 323

SPRIE — SPI Receiver Interrupt Enab le Bit

This read/write bit enables CPU interrupt requests generated by the

SPRF bit. The SPRF bit is set when a byte transfers from the shift

1 = SPRF CP U i nt errupt requests enabled

0 = SPRF CP U i nterrupt request s disabled

DMAS —DMA Sel ect Bit

This read only bit has no effect on th is version of the SPI. This bit

always reads as a 0.

0 = SPRF DMA and SPTE DMA servic e requests disabled

(SPRF CPU and SPTE CPU interrupt requests enabled)

SPMSTR — SPI Master Bit

This read/write bit selects master mode operation or slave mode

operation. Reset sets the SPMSTR bit.

1 = Master mode

0 = Sla ve mode

CPOL — Clock Polarity Bit

This read/write bit determines the logic state of the SPSCK pin

between tr ansm issi on s. (See Figure 20-4 and Figure 20-6.) To

transmit data between SPI modules, the SPI modules must have

identical CPOL values. Reset clears the CPOL bit.

CPHA — Clock Phase Bit

This read /w rit e bi t cont ro l s the ti mi n g re lati on shi p betwee n the serial

clock and SPI data. (See Figure 20-4 and Figure 20-6.) To transmit

data between SPI modules, the SPI modules must have identical

CPHA values. When CPHA = 0, the SS pin of th e slave SPI module

must be set to logic 1 between bytes. See Figure 20-12. Reset sets

the CPHA bit.

SPWOM — SPI Wired-OR Mode Bit

This read/write bit disables the pullup devices on pins SPSCK, MOSI,

and MISO so that those pins become open-drain outputs.

1 = Wired-OR SPSCK, MOSI, and MISO pins

0 = Normal push-pull SPSCK, MOSI, and MISO pins

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SPE — SPI Enable

This read/write bit enables the SPI module. Clearing SPE causes a

partial reset of the SPI. See Resett ing the SPI. Reset clears the SPE

bit.1 = SP I module enabled

0 = SPI module disabled

SPTIE— SPI Transmit Interrupt Enable

This read/write bit enables CPU interrupt requests generated by the

SPTE bit. SPTE is set when a byte transfers from the transmit data

1 = SPTE CPU interrupt requests enabled

0 = SPTE CPU interrupt r equest s disabled

20.14 .2 SPI Status and Control Register

The SPI status and contro l re gi ste r cont ai ns flags to sig na l these

conditions:

•Receive data register full

•Failure to clear SPRF bit before next byte is received (overflow

error)

•Inconsistent logic level on SS pin (mode fault error)

•Transmit data register empty

The SPI status and con trol register a lso contains bits that per form these

functions:

•Enable error interrupts

•Enable mode fault erro r detection

•Select master SPI baud rate

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Serial Peripheral Interface (SPI)

I/O Registers

MC68HC908GR8 — Rev 4.0 Technical Data

MOTOROLA Serial Peripheral Interface (SPI) 325

SPRF — SPI Receiver Full Bit

This clearable, read-only flag is set each time a byte transfers from

the s hift register to the receive data regi ster. SPRF g enerates a CPU

interru pt request if the SPRIE bit in the S PI control register is se t also.

During an SPRF CPU inter rupt, the CPU cl ears SPRF by rea ding the

SPI status and control register with SPRF set and then reading the

SPI data register.

Reset clears the SPRF bit.

1 = Receive data register full

0 = Receive data re gi ste r not full

ERRIE — Error Interrupt Enable Bit

This read/write bit enables the MODF and OVRF bits to generate

CPU interrupt requests. Reset clears the ERRIE bit.

1 = MODF and OVRF can generate CPU interrupt requests

0 = MODF and OVRF cannot generate CPU interrupt requests

OVRF — Overflow Bit

This clearable, read-only flag is set if software does not read the byte

in the recei ve data register before the next full byte enters the shift

regi ster. In an ov erflow cond ition, the byte alre ady in the rec eive data

OVRF bit by reading the SPI status and control register with OVRF set

and then reading the receive data register. Reset clears the OVRF bit.

1 = Overflow

0 = No ove r flow

Address: $0011

Bit 7654321Bit 0

Read: SPRF ERRIE OVRF MODF SPTE MODFEN SPR1 SPR0

Write:

Reset:00001000

= Unimplemented

Figure 20-14. SPI Status and Control Register (SPSCR)

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MODF — Mode Fault Bit

This clearable, read-only flag is set in a slave SPI if the SS pin goes

high during a transmission with the MODFEN bit set. In a master SPI,

the MODF flag is set if the SS pin goes low at any time with th e

MODFEN bit set. Clear the MODF bit by reading the SPI status and

control register (SPSCR) with MODF set and then writing to the SPI

control register (SPCR). Reset clears the MODF bit.

1 = SS pin at inappropriate logic level

0 = SS pi n at ap propriate logic lev el

SPTE — SPI Transmitter Empty Bit

This clearable, read-only flag is set each time the transmit data

SPTE CPU interrupt request or an SPTE D MA service request if the

SPTIE bit in the SPI control register is set also.

NOTE: Do not write to the SPI data register unless the SPTE bit is high.

During an SPTE CPU interrupt, the CPU clears the SPTE bit by

writi ng to the tran smit data regi ster.

Reset sets the SPTE bit.

1 = Transmit data register empty

0 = Transmit data register not empty

MODFEN — Mode Fault Enable Bit

This read/write bit, when set to 1, allows the MODF flag to be set. If

the MODF flag is set, clearing the MODFEN does not clear the MODF

flag. If the SPI is enabled as a master and the MODFEN bit is low,

then the SS pin is available as a general-purpose I/O.

If the MODFEN bit is set, then this pin is not avai lable as a general-

purpose I/O. When the SPI is enabled as a slave, the SS pin is not

available as a general-purpose I/O regardless of the value of

MODFEN. See SS (Slave Select).

If the MODFEN bit is low, the level of the SS pin does not affect the

opera ti on o f an enabled S PI co nfi gu r ed a s a master. For an enabl e d

SPI configured as a slave, having MODFEN low only prevents the

MODF flag from being set. It does not affect any other part of SPI

operation. See Mod e Faul t Er ro r.

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I/O Registers

MC68HC908GR8 — Rev 4.0 Technical Data

MOTOROLA Serial Peripheral Interface (SPI) 327

SPR1 and SPR0 — SPI Baud Rate Select Bits

In master mode, these read/write bits select one of four baud rates as

shown in Table 20-4. SPR1 and SP R0 have no effect in slave mode .

Reset clears SPR1 and SPR0.

Use this formula to calculate the SPI baud rate:

where:

CGMOUT = base clock output of the clock generator module (CGM)

BD = baud ra te divisor

Table 20-4. SPI Master Baud Rate Selection

SPR1 and SPR0 Baud Rate Divisor (BD)

00 2

01 8

10 32

11 128

Baud rate CGMOUT

2BD×

--------------------------=

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328 Serial Peripheral Interface (SPI) MOTOROLA

20.14.3 SPI Data Register

The SPI data register consists of the read-only receive data register a nd

the write-only transmit data register. Writing to the SPI data register

writes data into the transmit data regist er. Readin g the SPI d ata register

reads data from the receive data register. The transmit data and receive

data regist er s are sep arate regist er s that can cont ai n diffe re nt val ue s.

See Fig ur e 20-2.

R7–R0/T7–T0 — Receive/Transmit Data Bits

NOTE: Do not use r ead-modify- write in structions on the SPI d ata regi ster since

the register read is not the same as the register written.

Address: $0012

Bit 7654321Bit 0

Read: R7 R6 R5 R4 R3 R2 R1 R0

Write: T7 T6 T5 T4 T3 T2 T1 T0

Reset: Indeterminate after reset

Figure 20-15. SPI Dat a Re gi st er (SPDR)

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MC68HC908GR8 — Rev 4.0 Technical Data
MOTOROLA Timebase Module (TBM) 329
 
Technical Data — MC68HC908GR8
Section 21. Timeba se Module (TBM)
21.1  Contents
21.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .329
21.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 29
21.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 30
21.5 Timebase Register Description. . . . . . . . . . . . . . . . . . . . . . . .3 31
21.6 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .332
21.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .333
21.2  Introduction
This section describes the timebase  module  (TBM). The TBM will 
generate periodic interrupts at user selectable rates using a counter 
clocked by th e exte r nal cr ystal  clock. Thi s TBM  vers io n use s  15 divi de r 
stag es, eight of which are use r  selectable.
For further information regarding timers on M68HC08 family devices, 
please consult the HC08 Timer Reference Manual, TI M08RM/A D .
21.3  Features
Features of the TBM module include:
•Software programmable 1 Hz, 4 Hz, 16 Hz, 256 Hz, 512 Hz, 1024 
Hz, 2048 Hz, and 4096 Hz periodic interrupt using external 32.768 
kHz crystal
•User selectable oscillator clock source enable during stop mode to 
allow per iodic wakeup from stop
    
  
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Timebase Module (TBM)

Technical Data MC68HC908GR8 — Rev 4.0

330 Timebase Module (TBM) MOTOROLA

21.4 Functional Description

NOTE: This module is designed for a 32.768 kHz oscillator.

This module can gen erate a periodic interrupt by dividing the crys tal

frequency, CGMXCLK. The counter is initialized to all 0s when TBON bit

is clea red. The coun ter, sh own in Figur e 21- 1, starts coun ting when th e

TBON bit is set. When the counter overflows at the tap selected by

TBR2:TBR0, the TBIF bit gets set. If the TBIE bit is set, an interrupt

reque st is sent to the CPU. Th e TBIF flag is cleared by writin g a 1 to the

TACK bit. The first time the TBIF flag is set after enabling the timeb ase

module, the interrupt is generated at approximately half of the overflow

period. Subsequent events occur at the exact period.

Figure 21-1. Timebase Block Diagram

÷2÷2÷2÷2÷2÷2÷2

128

32,768

8192

2048

CGMXCLK

SEL

0 0 0

0 0 1

0 1 0

0 1 1

TBIF

TBR1

TBR0

TBIE

TBMINT

TBON

÷2

TACK

TBR2

1 0 0

1 0 1

1 1 0

1 1 1

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Timebase Module (TBM)

Timebase Register Description

MC68HC908GR8 — Rev 4.0 Technical Data

MOTOROLA Timebase Module (TBM) 331

21.5 Timebase Register Descrip tion

The timebase has one register, the TBCR, which is used to enable the

timebase interrupts and set the rate.

TBIF — Timebase Interru pt Flag

This read-only flag bit is set when the timebase counter ha s rolled

over.

1 = Timebase interrupt pending

0 = Timebase interr upt not pending

TBR2:TBR0 — Timebase Rate Selection

These read/write bits are used to select the rate of timebase interrupts

as shown in Table 21-1.

Address: $001C

Bit 7654321Bit 0

Read: TBIF TBR2 TBR1 TBR0 0TBIE TBON Reserved

Write: TACK

Reset:00000000

= Unimplemented

Figure 21-2. Timebase Control Register (TBCR)

Table 21-1. Timebase Rate Selection for OSC1 = 32.768 kHz

TBR2 TBR1 TBR0 Divider Timebase Interrupt Rate

Hz ms

0 0 0 32,768 1 1000

0 0 1 8192 4 250

0 1 0 2048 16 62.5

0 1 1 128 256 ~ 3.9

1 0 0 64 512 ~2

1 0 1 32 1024 ~1

1 1 0 16 2048 ~0.5

1 1 1 8 4096 ~0.24

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Technical Data MC68HC908GR8 — Rev 4.0

332 Timebase Module (TBM) MOTOROLA

NOTE: Do not chan ge TBR2–TBR0 bits while the timebase is enabled

(TBON = 1).

TACK— Timebase ACKnowledge

The TACK bit is a write-only bit and always reads as 0. Writing a logic

1 to this bit clears TBIF, the timebase interrup t flag bit. Writing a logic

0 to this bit has no effect.

1 = Clea r timebase interrupt flag

0 = No effect

TBIE — Timebase Interrupt Enabled

This read/write bit enables the timebase interrupt when the TBIF bit

becomes set. Reset clears the TBIE bit.

1 = Timebase interrupt enabled

0 = Timeb ase interrup t disabled

TBON — Timebase Enabled

This read/write bit enables the timebase. Timebase may be turned off

to reduce power consumption when its function is not necessary. The

counter can be initialized by clearing and then setting this bit. Reset

clears the TBON bit.

1 = Timebase enabled

0 = Timebase disabled and the coun ter initialized to 0s

21.6 Interrupts

The timebase module can interrupt the CPU on a regular basis with a

rate de fined by TBR2:TBR0. When the timebase counter chain rolls

over, the TBIF flag is set. If the TBIE bit is set, enabling the timebase

interrupt, the counter chain overflow will generate a CPU interrupt

request.

Interrupts must be acknowledged by writing a logic 1 to the TACK bit.

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Timebase Module (TBM)

Low-Power Modes

MC68HC908GR8 — Rev 4.0 Technical Data

MOTOROLA Timebase Module (TBM) 333

21.7 Low-Po wer Modes

The WAIT and STOP instructions put the MCU in low power-

consumptio n standby mode s.

21.7.1 Wait Mode

The timebase module remains active after execution of the WAIT

instruction. In wait mode, the timebase register is not accessible by the

CPU.

If the timebase functions are not required during wait mode, reduce the

power consumption by stopping the time base before enabling the WAIT

instruction.

21.7.2 Stop Mode

The timeba se module may remain active after execution of the STOP

instruction if the oscillator has been enabled to operate during stop mode

through the OSCSTOPEN bit in the CONFIG register. T he timebase

module can be used in this mode to generate a periodic wakeup from

stop mode.

If the oscillator has not been enabled to operate in st op mode, the

timebase module will not be active during STOP mode. In stop mode, the

timebase register is not accessible by the CPU.

If the ti meba se funct ions a re not r equir ed du ring stop mod e, re duce th e

power consumption by stopping the timebase before enabling the STOP

instruction.

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Timebase Module (TBM)

Technical Data MC68HC908GR8 — Rev 4.0

334 Timebase Module (TBM) MOTOROLA

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MC68HC908GR8 — Rev 4.0 Technical Data
MOTOROLA Timer Interface Module (TIM) 335
 
Technical Data — MC68HC908GR8
Section 22. Timer Interface Module (TIM)
22.1  Contents
22.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .335
22.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 36
22.4 Pin Name Conventions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .336
22.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 37
22.6 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .346
22.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .347
22.8 TIM During Break Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . .348
22.9 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .348
22.10 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .349
22.2  Introduction
This section describes the timer interface (TIM) module. The TIM on this 
part is a 2-channel and a1-channel timer that provides a timing reference 
with input capture,  output compare, and pulse-widt h-modulati on 
functions. Figure 22-1 is a block diagram of the TIM. This particular MCU 
has two timer in terface modules which are denoted as TIM1 and TIM2.
For further information regarding timers on M68HC08 family devices, 
please consult the HC08 Timer Reference Manual, TI M08RM/A D .
    
  
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Timer Interface Mod ule (TIM)

Technical Data MC68HC908GR8 — Rev 4.0

336 Timer Interface Module (TIM) MOTOROLA

22.3 Features

Features of t he TIM include:

•Three input capture/output compare channels:

–Rising-edge, falling-edge, or any-edge input captur e trigger

–Set, clear, or toggle output compare action

•Buffered and unbuffered pulse-width-modulation (PWM) signal

generation

•Programmable TIM clock input with 7-frequency internal bus clock

prescaler selection

•Free-r unning or modulo up -count oper ation

•Toggl e any channel pin on ov erflow

•TIM counter stop an d reset bits

•I/O port bit(s) software configurable with pullup device(s) if

configured as input port bit(s)

22.4 Pin Name Conventions

The text that follows describes both timers, TIM1 and TIM2. The TIM

input/output (I/O) pin names are T[1,2]CH0 (timer 1 channel 0, timer 2

channel 0) and T[1 ]CH 1 (tim er channe l 1) , where “1” is used to indicate

TIM1 and “2” is used to indicate TIM2. The two TIMs share three I/O pins

with three port D I/O port pins. The full names of the TIM I/O pins are

listed in Table 22-1. The generic pin names appear in the text that

follows.

Table 22-1. Pin Name Conventions

TIM Generic Pin Names: T[1,2]CH0 T[1,2]CH1

Full TIM

Pin Names: TIM1 PTD4/ATD12/TBLCK PTD5/T1CH1

TIM2 PTD6/ATD14/TACLK --

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Timer Interface Module (TIM)

Functional Description

MC68HC908GR8 — Rev 4.0 Technical Data

MOTOROLA Timer Interface Module (TIM) 337

NOTE: References to either timer 1 or timer 2 may be made in the following text

by omit ting the timer number. For e xample, TCH0 m ay refer gene rically

to T1CH0 and T2CH0, and TCH1 will refer to T1CH1.

NOTE: The Timer Interface Module in MC68HC908GR8 is constructed by TIM1

which is c ontained channel 0 and 1, and TIM2 whic h is contained

channel 0 only.

22.5 Functional Description

NOTE: References to TCLK and external TIM clock input are only valid if the

MCU has an external TCLK pin. If the MCU has no external TCLK pin,

the TIM module must use the internal bus clock prescaler selections.

Figure 22-1 shows the structure of the TIM. The central component of

the TIM is the 16-bit TIM counter that can operate as a free-running

counter or a modulo up-counter. The TIM counter provides the timing

reference for the input capture and output compare functions. The TIM

counter modulo regi sters, TMODH:TMOD L, control the modulo val ue of

the TIM counter. Software can read the TIM counter value at any time

without affecting the counting sequen ce.

The TIM cha nnels (per t imer) are programma ble indepen dently as i nput

capture or output compare channels. If a channel is configured as input

capture, then an internal pullup device may be enabled for that channel.

See Port D Input Pullup Enable Register.

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Timer Interface Mod ule (TIM)

Technical Data MC68HC908GR8 — Rev 4.0

338 Timer Interface Module (TIM) MOTOROLA

Figure 22-1. TIM Block Diagram

NOTE: References to either timer 1 or timer 2 may be made in the following text

by omitting the timer number. For example, TSC may generically refer to

both T1SC and T2SC.

NOTE: In Figure 22-1, channel 1 will only be available in TIM1 while channel 0

will be avai lable in both TIM1 and TIM2

PRESCALER PRESCALER SELECT

INTERNAL

16-BIT COMPARATOR

PS2 PS1 PS0

16-BIT COMPARATOR

16-BIT LATCH

TCH0H:TCH0L

MS0A

ELS0B ELS0A PORT

TOF

TOIE

INTER-

16-BIT COMPARATOR

16-BIT LATCH

TCH1H:TCH1L

CHANNEL 0

CHANNEL 1

TMODH:TMODL

TRST

TSTOP

TOV0

CH0IE

CH0F

ELS1B ELS1A TOV1

CH1IE

CH1MAX

CH1F

CH0MAX

MS0B

16-BIT COUNTER

INTERNAL BUS

BUS CLOCK

MS1A

LOGIC

RUPT

LOGIC

INTER-

RUPT

LOGIC

PORT

LOGIC

INTER-

RUPT

LOGIC

INTERNAL

TCLK

T[1,2]CH0

T[1]CH1

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Timer Interface Module (TIM)

Functional Description

MC68HC908GR8 — Rev 4.0 Technical Data

MOTOROLA Timer Interface Module (TIM) 339

Figure 22-2 summarizes the timer registers.

Addr.Register Name Bit 7654321Bit 0

$0020 Timer 1 Status and Control

Read: TOF TOIE TSTOP 00

PS2 PS1 PS0

Write: 0 TRST

Reset:00100000

$0021 Timer 1 Counter Register

High (T1CNTH)

Read: Bit 15 14 13 12 11 10 9 Bit 8

Write:

Reset:00000000

$0022 Timer 1 Counter Register

Low (T1CNTL)

Read: Bit 7 654321Bit 0

Write:

Reset:00000000

$0023 Timer 1 Counter Modulo

Read: Bit 15 14 13 12 11 10 9 Bit 8

Write:

Reset:11111111

$0024 Timer 1 Counter Modulo

Read: Bit 7654321Bit 0

Write:

Reset:11111111

$0025 Timer 1 Channel 0 Status

and Control Register

(T1SC0)

Read: CH0F CH0IE MS0B MS0A ELS0B ELS0A TOV0 CH0MAX

Write: 0

Reset:00000000

$0026 Timer 1 Channel 0

Read: Bit 15 14 13 12 11 10 9 Bit 8

Write:

Reset: Indeterminate after reset

$0027 Timer 1 Channel 0

Read: Bit 7654321Bit 0

Write:

Reset: Indeterminate after reset

$0028 Timer 1 Channel 1 Status

and Control Register

(T1SC1)

Read: CH1F CH1IE 0MS1A ELS1B ELS1A TOV1 CH1MAX

Write: 0

Reset:00000000

$0029 Timer 1 Channel 1

Read: Bit 15 14 13 12 11 10 9 Bit 8

Write:

Reset: Indeterminate after reset

$002A Timer 1 Channel 1

Read: Bit 7654321Bit 0

Write:

Reset: Indeterminate after reset

$002B Timer 2 Status and Control

Read: TOF TOIE TSTOP 00

PS2 PS1 PS0

Write: 0 TRST

Reset:00100000

$002C Timer 2 Counter Register

High (T2CNTH)

Read: Bit 15 14 13 12 11 10 9 Bit 8

Write:

Reset:00000000

= Unimplemented

Figure 22-2. TIM I/O Register Summary (Sheet 1 of 2)

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Timer Interface Mod ule (TIM)

Technical Data MC68HC908GR8 — Rev 4.0

340 Timer Interface Module (TIM) MOTOROLA

22.5.1 TIM Counter Prescaler

The TIM clock source can be one of the seven prescale r outpu ts or the

TIM clock pin, TCLK. The prescaler generates seven clock rates from

the internal bus clock. The prescaler select bits, PS[2:0 ], in the TIM

status and control register select the TIM clock source.

$002D Timer 2 Counter Register

Low (T2CNTL)

Read: Bit 7 654321Bit 0

Write:

Reset:00000000

$002E Timer 2 Counter Modulo

Read: Bit 15 14 13 12 11 10 9 Bit 8

Write:

Reset:11111111

$002F Timer 2 Counter Modulo

Read: Bit 7654321Bit 0

Write:

Reset:11111111

$0030 Timer 2 Channel 0 Status

and Control Register

(T2SC0)

Read: CH0F CH0IE MS0B MS0A ELS0B ELS0A TOV0 CH0MAX

Write: 0

Reset:00000000

$0031 Timer 2 Channel 0

Read: Bit 15 14 13 12 11 10 9 Bit 8

Write:

Reset: Indeterminate after reset

$0032 Timer 2 Channel 0

Read: Bit 7654321Bit 0

Write:

Reset: Indeterminate after reset

$0033 Unimplemented Read:

Write:

Reset:00000000

$0034 Unimplemented Read:

Write:

Reset: Indeterminate after reset

$0035 Unimplemented Read:

Write:

Reset: Indeterminate after reset

Addr.Register Name Bit 7654321Bit 0

= Unimplemented

Figure 22-2. TIM I/O Register Summary (Sheet 2 of 2)

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Timer Interface Module (TIM)

Functional Description

MC68HC908GR8 — Rev 4.0 Technical Data

MOTOROLA Timer Interface Module (TIM) 341

22.5.2 Input Capture

With the input capture function, the TIM can capture the time at which an

external event occurs. When an active edge occurs on the pin of an input

capture channel, the TIM latches the contents of the TIM counter into the

TIM channel registers, TCHxH:TCHxL. The polarity of the active edge is

programmable. Input captures can generate TIM CPU interrupt

requests.

22.5.3 Output Compare

With the output compare function, the TIM can generate a periodic pulse

with a programmable polarity, duration, and frequency. When the

counter reaches the value in the registers of an output compare channel,

the TIM can set, clear, or toggle the channel pin. Output compares can

generate TIM CPU interrupt requests.

22.5.4 Unbuffered Output Compare

Any output compare channel can gene rate u nbuffered output compare

pulse s as described in Output Compare. The pulses are unbuffered

because changing the output compare value requires writing the new

value over the ol d value curr en tly in the TIM channel registers.

An uns ynchronized write to the TIM channel registers to chan ge an

output comp are va lue coul d cause incorrect operation for up to two

counter overflow periods. For example, wr iting a new value before the

counter reaches the old value but after the counter reaches the new

value prevents any compare d uring that counter over flow period. Also,

using a TIM overflow int errupt routine to write a new, smaller output

compare value may cause the compare to be missed. The TIM may pass

the new value before it is written.

Use the following methods to synchronize unbuffered changes in the

output compare value on channel x:

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342 Timer Interface Module (TIM) MOTOROLA

•When changing to a smaller value, enable channel x output

compare interrupts an d write the new value in the output compare

interrupt routine. The output compare interrupt occurs at the end

of the current output compare pulse. The interrupt routine has until

the end of the counter overflow period to write the new value.

•When changing to a larger output compare value, enable TIM

overflow interrupts and write the new value in the TIM overflow

interrupt routine. The TIM overflow interrup t occu rs at the end of

the curr ent counter overflow period. Writing a larger value in an

output compare interr upt routine (at the end of the current pulse)

could cause two output compares to occur in the same counter

overflow period.

22.5.5 Buffered Output Compare

Channels 0 and 1 can be linked to form a buffered output compare

channel whose output appears on the TCH0 pin. The TIM channel

registers of t he linked pair alternately con trol the output .

Setting the MS0B bit in TIM channel 0 status and control register (TSC0)

links channel 0 and channel 1. Th e output compare value in the TIM

channel 0 registers initially controls the output on the TCH0 pin. Writing

to the TIM channel 1 registers enables the TIM channel 1 registers to

synch ronously control the output aft er the TIM overflows. At each

subseque nt over flow, the TIM chann el register s (0 or 1) th at control the

output are the ones written to last. TSC0 controls and monitors the

buffered output compare fun ction, and TIM channe l 1 status and control

TCH1, is available as a general-purpose I/O pin.

NOTE: In buffered output com pare opera tion, do not write ne w output co mpare

values to the currently active channe l registers. User software should

track the currently active channel to prevent writing a new value to the

active channel. Writing to the active channel registers is the same as

generating unbuffered output compares.

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Timer Interface Module (TIM)

Functional Description

MC68HC908GR8 — Rev 4.0 Technical Data

MOTOROLA Timer Interface Module (TIM) 343

22.5.6 Pulse Width Modulation (PWM)

By using the toggle-on-overflow feature with an output compare channel,

the TIM can generate a PWM signal. The value in the TIM counter

modulo registers determines the period of the PWM signal. The channel

pin toggles when th e counter reaches t he value in the TIM counter

modulo registers. The time between overflows is the period of the PWM

signal.

As Figure 22-3 shows, the output compare value in the TIM channel

registers determines the puls e width of the PWM signal. The time

between overflow and output compare is the pulse width. Program the

TIM to cle ar th e cha nn el pi n on o utp ut co m par e if the state of the P WM

pulse is logic 1. Program the TIM to set the pin if the state of the PWM

pul se is logic 0.

The value in the TIM counter modulo registers and the selected

prescaler output determines the frequency of the PWM output. The

frequency of an 8-bit PWM signal is variable in 256 increments. Writing

$00FF (255) to the TIM counter modulo registers produces a PWM

period of 256 times the internal bus clock per iod if the prescaler select

value is $000. See TIM Status and Control Register.

Figure 22-3. PWM Period and Pulse Width

The value in the TIM channel registers determines the pulse width of the

PWM output. The pulse width of an 8-bit PWM signal is variable in 256

PTEx/TCHx

PERIOD

PULSE

WIDTH

OVERFLOW OVERFLOW OVERFLOW

OUTPUT

COMPARE OUTPUT

COMPARE

OUTPUT

COMPARE

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Timer Interface Mod ule (TIM)

Technical Data MC68HC908GR8 — Rev 4.0

344 Timer Interface Module (TIM) MOTOROLA

increme nts. Wri ting $ 0080 (128) to the TIM ch an nel r egisters produces

a duty cycle of 128/256 or 50%.

22.5.7 Unbuffered PWM Signal Generation

Any output compare channel can generate unbuffered PW M pulses as

described in Pulse Width Mo dulation (PWM). The pulses are unbuffered

because changing the pulse width requires writing the new pulse width

value over the ol d value curr en tly in the TIM channel registers.

An unsyn chronized w rite to the TIM chann el register s to change a pulse

width value could cause incor rect operatio n for up to two PWM perio ds.

For example, writing a new value before the counter reaches the old

value but after the counter reaches the new value prevents any compare

during that P W M period. Also, using a TIM overfl ow interr upt routine to

write a new, smaller pulse width value may cause the compare to be

missed. The TIM may pass the new value before it is written.

Use the following methods to synchronize unbuffered changes in the

PWM pu lse width on channel x:

•When changing to a shorter pulse width, enable channel x output

compare interrupts an d write the new value in the output compare

interrupt routine. The output compare interrupt occurs at the end

of the curren t pulse. The interrupt r outine has until the end of the

PWM period to write the new value.

•When changing to a longer pulse width, enable TIM overflow

interrup ts a nd write the new value in the TIM overflow interrupt

routine. The TIM overflow interrupt occurs at the end of the current

PWM period. Writing a larger value in an output compare interrupt

routine (at the end of the current pulse) could cause two output

compares to occur in the same PWM period.

NOTE: In PWM signal generation, do not program the PWM channel to toggle

on output compare. Toggling on ou tput co mpare prevents reliable 0%

duty cycle generation and removes the ability of the channel to self-

correct in the event of soft w are error or noise. Toggling on output

compare also can cause incorrect PWM signal generation when

changing th e PWM pulse width to a new, much larger value.

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Timer Interface Module (TIM)

Functional Description

MC68HC908GR8 — Rev 4.0 Technical Data

MOTOROLA Timer Interface Module (TIM) 345

22.5.8 Buffered PWM Signal Generation

Channels 0 and 1 can be linked to form a buffered PWM channel whose

output appears on the TCH0 pin. The TIM channel registers of the linked

pair alterna tely control the pulse width of the out put.

Setting the MS0B bit in TIM channel 0 status and control register (TSC0)

links channel 0 and channel 1. The TIM channel 0 registers initially

control the pulse width on the TCH0 pin. Writing to the TIM channel 1

registers enables the TIM channel 1 registers to synchronously control

the pulse width at the beginning of the next PWM period. A t each

subseque nt over flow, the TIM chann el register s (0 or 1) th at control the

pulse width are the ones written to last. TSC0 controls and monitors the

buffer ed PW M fun c tion, and TI M cha nne l 1 status and control register

(TSC1) is unused. While the MS0B bit is set, the channel 1 pin, TCH1,

is available as a general-purpose I/O pin.

NOTE: In buffered PWM signal generation, do not write new pulse width values

to the cu rrently active ch annel registers. User sof tware should tra ck the

curren tly active channel to prevent writing a new value to the active

channel. Writing to the active channel registers is the same as

generating unbuffered PWM signals.

22.5.9 PWM Initialization

To ensure correct operation when generating unbuffered or buffered

PWM signals, use the following initialization procedure:

1. In the TIM status and control register (TSC):

a. Stop the TIM counter by setting the TIM stop bit, TSTOP.

b. Reset the TIM counter and prescaler by setting the TIM reset

bit, TRST.

2. In the TIM counter modulo registers (TMODH:TMODL), write the

value for the required PWM period.

3. In the TIM channel x registers (TCHxH:TCHxL), write the value for

the required pulse width.

4. In TIM channel x status and control register (TSCx):

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346 Timer Interface Module (TIM) MOTOROLA

a. Writ e 0:1 (f or unbuffe red output compare o r PWM si gnals) or

1:0 (for buffered output compare or PW M signals) to the

mode select bits, MSxB:MSxA. See Table 22-3.

b. Write 1 to the tog gle-on-overf low bit, TOVx.

c. Write 1:0 (to clear output on compare) or 1:1 (to set output on

compare) to the edge/level select bits, ELSxB:ELSxA. The

output action on compare must force the output to the

complement of the pulse width level. (See Table 22-3.)

NOTE: In PWM signal generation, do not program the PWM channel to toggle

on output compare. Toggling on ou tput co mpare prevents reliable 0%

duty cycle generation and removes the ability of the channel to self-

correct in the event of soft w are error or noise. Toggling on output

compare can also cause incorrect PWM signal generation when

changing th e PWM pulse width to a new, much larger value.

5. In the TIM status control registe r (TSC), clear the TIM stop bit,

TSTOP.

Setting MS0B links channels 0 and 1 and config ures them for buffered

PWM ope ration. The TIM channel 0 registers (TCH0H:TCH0L) initially

control the buffered PWM output. TIM status control register 0 (TSCR0)

controls and monitors the PWM signal from the linked channels.

Clearing the toggle-on-overflow bit, TOVx, inhibits output toggles on TIM

overflows. Subsequent output compares try to force the output to a state

it is already in and have no effect. The result is a 0% duty cycle output.

Setting the channel x maximum duty cycle bit (CHxMAX) and setting the

TOVx bit generates a 100% duty cycle output. (See TIM Channel Status

and Cont rol Registers.)

22.6 Interrupts

The following TIM sources can generate interrupt requests:

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Low-Power Modes

MC68HC908GR8 — Rev 4.0 Technical Data

MOTOROLA Timer Interface Module (TIM) 347

•TIM overflow flag (TOF) — The TOF bit is set when the TIM

counter value reaches the modulo value programmed in the TIM

counter modulo registers. The TIM overflow interrupt enable bit,

TOIE, enables TIM ove rflow CPU interrupt re qu ests. TOF and

TOIE are in the TIM statu s and co ntrol register.

•TIM channel flags (CH1F:CH0F) — The CHxF bit is set when an

input cap ture or outpu t comp ar e occu rs on cha nne l x. Channel x

TIM CPU interru pt requests and TIM DMA service requests are

controll ed by the chan nel x inter rupt enabl e bit, CHxIE. Cha nnel x

TIM CPU interrupt requests are enabled when CHxIE = 1. CHxF

and CHxIE are in the TIM ch annel x s tatus a nd control register.

DMAxS is in the TIM DMA select register.

22.7 Low-Power Modes

The WAIT and STOP instructions put the MCU in low power-

consumptio n standby mode s.

22.7.1 Wait Mode

The TIM remains active after the execution of a WAIT instruction. In wait

mode, the TIM registers are not acces sible by the CPU. Any en abled

CPU interrupt request from the TIM can bring the MCU out of wait mode.

If TIM functions are not required during wait mode, reduce power

consumption by stopping the TIM before executing the WAIT instruction.

22.7.2 Stop Mode

The TIM is inactive after the execution of a STOP instruction. The STOP

instruction does not affect register conditions or the state of the TIM

counter. TIM operation resumes when the MCU exits stop mode after an

external interrupt.

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Technical Data MC68HC908GR8 — Rev 4.0

348 Timer Interface Module (TIM) MOTOROLA

22.8 TIM During Break Interrupts

A break interrupt stops the TIM counter.

The system integration module (SIM) controls whether status bits in

other modules can be cleared during the break state. The BCFE bit in

the SIM brea k flag control register (SBFCR) enables software to clear

status bits during the break state. See SIM Break Flag Control Register.

To allow software to clear status bits during a break interrupt, write a

logic 1 to the BCFE bit. If a status bit is cleared during the break state, it

remains cleared when the MCU exits the break state.

To prote ct status bits dur ing the brea k state, writ e a logic 0 to th e BCFE

bit. Wi t h BC FE a t l og ic 0 ( it s default state) , soft ware can read an d w r it e

I/O registers during the break state without affecting status bits. Some

status bits have a 2-step read/write clearing pr ocedure. If sof tware does

the first step on such a bit before the break, the bit cannot change during

the br ea k state as lo ng a s B CFE is at l og ic 0. After the b reak, doing the

second step clears the status bit.

22.9 I/O Signals

Port D sh ar es thr ee o f it s p ins w ith th e TIM. (There i s an op ti on al TC LK

which can be used as an external clock input to the TIM prescaler, but is

not available on this MCU.) The three TIM channel I/O pins are T1CH0,

T1CH1 and T2CH0 as described in Pin Name Convention s.

Each channe l I/O pin is programma ble in de pe nde ntly as an input

capture pi n or an output c ompare pin. T1CH0 a nd T2CH0 c an be

configured as buffered output compare or buffered PWM pins.

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Timer Interface Module (TIM)

I/O Registers

MC68HC908GR8 — Rev 4.0 Technical Data

MOTOROLA Timer Interface Module (TIM) 349

22.10 I/O Registers

NOTE: References to either timer 1 or timer 2 may be made in the following text

by omitting the timer number. For example, TSC may generically refer to

both T1SC AND T2SC.

These I/O registers control and monitor operation of the TIM:

•TIM status and control register (TSC )

•TIM control registers (TCNTH:TCNTL)

•TIM counter modulo registers (TMODH:TMODL)

•TIM channel status and control registers (TSC0, TSC1)

•TIM channel registers (TCH0H:TCH0L, TCH1 H:TCH1L)

22.10.1 TIM Status and Control Register

The TIM status and control register (TSC):

•Enable s TIM overflow interrupts

•Flags TIM overflows

•Stops the TIM counter

•Resets the TIM counter

•Prescales the TIM counter clock

Address: T1SC, $0020 and T2SC, $002B

Bit 7654321Bit 0

Read: TOF TOIE TSTOP 00

PS2 PS1 PS0

Write: 0 TRST

Reset:00100000

= Unimplemented

Figure 22-4. TIM Status and Control Register (TSC)

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Technical Data MC68HC908GR8 — Rev 4.0

350 Timer Interface Module (TIM) MOTOROLA

TOF — TIM Overflow Flag Bit

This read /wr it e flag i s set wh en th e TIM cou nte r r each es the modul o

value programmed in the TIM counter modulo registers. Clear TOF by

reading the TIM status and control register when TOF is set and then

writing a logic 0 to TOF. If another TIM overflow occurs before the

clearing sequence is complete, then writing logic 0 to TOF has no

effect. Therefore, a TOF interrupt request cannot be lost due to

inadvertent clearing of TOF. Reset clears the TOF bit. Writing a logic

1 to TOF has no effect.

1 = TIM counter has reache d modulo v alue

0 = TIM counter has not reached modulo value

TOIE — TIM Overflow Interrupt Enable Bit

This read /wr it e bit ena bles TIM overfl ow interrupts when the TOF bit

becomes set. Reset clears the TOIE bit.

1 = TIM overflow inter r upts enabled

0 = TIM overfl ow inter r upts disabled

TSTOP — TIM Stop Bit

This read/write bit stops the TIM counter. Counting resumes when

TSTOP is cleared. Reset sets the TSTOP bit, stopping the TIM

counter until software cl ears the TSTOP bit.

1 = TIM counter stopped

0 = TIM counter active

NOTE: Do not set the TSTOP bit before entering wait mode if the TIM is required

to exit wait mode.

TRST — TIM Reset Bit

Setting this write-only bit resets the TIM coun ter and the TIM

prescaler. Setting TRST has no effect on any other registers.

Counting resumes from $0000. TRS T is cleared automatically af ter

the TIM counter is reset and always reads as logic 0. Reset clears the

TRST bit.

1 = Prescaler and TIM counter cleared

0 = No effect

NOTE: Setting the TSTOP and TRST bits simultaneously stops the TIM counter

at a value of $0000.

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Timer Interface Module (TIM)

I/O Registers

MC68HC908GR8 — Rev 4.0 Technical Data

MOTOROLA Timer Interface Module (TIM) 351

PS2–PS0 — Prescaler Select Bits

These read/write bits select either the TCLK pin or one of the seven

prescaler outputs as the input to the TIM counter as Table 22-2

shows. Reset clears the PS[2:0] bits.

Table 22-2. Prescaler Selection

PS2–PS0 TIM Clock Source

000 Internal bus clock ÷1

001 Internal bus clock ÷ 2

010 Internal bus clock ÷ 4

011 Internal bus clock ÷ 8

100 Internal bus clock ÷ 16

101 Internal bus clock ÷ 32

110 Internal bus clock ÷ 64

111 Not available

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Technical Data MC68HC908GR8 — Rev 4.0

352 Timer Interface Module (TIM) MOTOROLA

22.10.2 TIM Counter Registers

The two read -only TIM counte r regi sters co ntain th e hi gh and low byt es

of the val ue in the TIM counte r. Readin g the high byte (TCNTH) latches

the conten ts of the low byte ( TCNTL) into a bu ffer. Subsequent reads of

TCNTH do not affect the latched TCNTL value until TCNTL is read.

Reset clears the TIM cou nter registers. Sett ing the TIM reset bit (TRST)

also clears the TIM counter registers.

NOTE: If you read TCNTH during a break interr upt, be sure to unlatch TC NTL

by reading TCNTL before exiting the break interrupt. Otherwise, TCNTL

retains the value latched during the break.

Address: T1CNTH, $0021 and T2CNTH, $002C

Bit 7654321Bit 0

Read: Bit 15 14 13 12 11 10 9 Bit 8

Write:

Reset:00000000

= Unimplemented

Figure 22-5. TIM Counter Registers High (TCNTH)

Address: T1CNTL, $0022 and T2CNTL, $002D

Bit 7654321Bit 0

Read: Bit 7 654321Bit 0

Write:

Reset:00000000

= Unimplemented

Figure 22-6. TIM Counter Registers Low (TCNTL)

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Timer Interface Module (TIM)

I/O Registers

MC68HC908GR8 — Rev 4.0 Technical Data

MOTOROLA Timer Interface Module (TIM) 353

22.10.3 TIM Counter Modulo Registers

The read /write TIM modulo registers contain the modulo value for the

TIM counter. When the TIM counter reaches the modulo value, the

overflow flag (TOF) becomes set, and the TIM counter resumes counting

from $0000 at the next timer clock. Writing to the high byte (TMODH)

inhibits the TOF bit and overflow interrupts until the low byte (TMODL) is

written. Reset sets the TIM counter modulo registers.

NOTE: Reset the TIM cou nter befor e writi ng to the TIM co unt er mod ulo re gisters.

Address: T1MODH, $0023 and T2MODH, $002E

Bit 7654321Bit 0

Read: Bit 15 14 13 12 11 10 9 Bit 8

Write:

Reset:11111111

= Unimplemented

Figure 22-7. TIM Counter Modulo Register High (TMODH)

Address: T1MODL, $0024 and T2MODL, $002F

Bit 7654321Bit 0

Read: Bit 7 654321Bit 0

Write:

Reset:11111111

= Unimplemented

Figure 22-8. TIM Counter Modulo Register Low (TMODL)

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Timer Interface Mod ule (TIM)

Technical Data MC68HC908GR8 — Rev 4.0

354 Timer Interface Module (TIM) MOTOROLA

22.10.4 TIM Counter Registers

The two read -only TIM counte r regi sters co ntain th e hi gh and low byt es

of the val ue in the TIM counte r. Readin g the high byte (TCNTH) latches

the conten ts of the low byte ( TCNTL) into a bu ffer. Subsequent reads of

TCNTH do not affect the latched TCNTL value until TCNTL is read.

Reset clears the TIM cou nter registers. Sett ing the TIM reset bit (TRST)

also clears the TIM counter registers.

NOTE: If you read TCNTH during a break interr upt, be sure to unlatch TC NTL

by reading TCNTL before exiting the break interrupt. Otherwise, TCNTL

retains the value latched during the break.

Address: T1CNTH, $0021 and T2CNTH, $002C

Bit 7654321Bit 0

Read: Bit 15 14 13 12 11 10 9 Bit 8

Write:

Reset:00000000

= Unimplemented

Figure 22-9. TIM Counter Register High (TCNTH)

Address: T1CNTL, $0022 and T2CNTL, $002D

Bit 7654321Bit 0

Read: Bit 7 654321Bit 0

Write:

Reset:00000000

= Unimplemented

Figure 22-10. TIM Counter Register Low (TCNTL)

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Timer Interface Module (TIM)

I/O Registers

MC68HC908GR8 — Rev 4.0 Technical Data

MOTOROLA Timer Interface Module (TIM) 355

22.10.5 TIM Channel Status and Control Registers

Each of the TIM channel status and control registers:

•Flags input captures and output compares

•Enables input capture and output compare interrupts

•Selects input capture, output compare, or PWM operation

•Selects high , low, or togg li n g outp ut on ou tpu t comp ar e

•Selects rising edge, falling edge, or any edge as the active inpu t

capture trigger

•Selects output toggling on TIM overflow

•Selects 0% and 100% PWM duty cycle

•Selects buffered or unbuffered output compare/PWM operation

Address: T1SC0, $0025 and T2SC0, $0030

Bit 7654321Bit 0

Read: CH0F CH0IE MS0B MS0A ELS0B ELS0A TOV0 CH0MAX

Write: 0

Reset:00000000

Figure 22-11. TIM Channel 0 Status and Control Register (TSC0)

Address: T1SC1, $0028

Bit 7654321Bit 0

Read: CH1F CH1IE 0MS1A ELS1B ELS1A TOV1 CH1MAX

Write: 0

Reset:00000000

Figure 22-12. TIM Channel 1 Status and Control Register (TSC1)

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Technical Data MC68HC908GR8 — Rev 4.0

356 Timer Interface Module (TIM) MOTOROLA

CHxF — Channel x Flag Bit

When channel x is an input capture channel, this read/write bit is set

when an active edge occurs on th e channel x pin. Wh en channel x is

an out put compare channel, CHxF is set when the va lue in the TIM

counter registers matches the value in the TIM channel x registers.

When TIM CPU interrupt requests are enabled (CHxIE = 1), clear

CHxF by reading TIM channel x status and control register with CHxF

set and then writing a logic 0 to CHxF. If another interrupt request

occurs before the clearing sequence is complete, then writing logic 0

to CHxF h as no effect. There fore, an int errupt requ est can not be los t

due to inad ver ten t cle ari ng of CHxF.

Reset clears the CHxF bit. Writing a logic 1 to CHxF has no effect.

1 = Input capture or output compare on channel x

0 = No input capture or output compare on channel x

CHxIE — Channel x Interrupt Enable Bit

This read/write bit enables TIM CPU interrupt service requests on

channel x.

Reset clears the CHxIE bit.

1 = Channel x CPU interrupt service requests enable d

0 = Channel x CPU interrupt service requests disabled

MSxB — Mode Select Bit B

This read/write bit selects buffered output compare/PWM operation.

MSxB exists only in the TIM1 channel 0 and TIM2 channel 0 status

and control registers.

Settin g MS 0B di sa bl es the chan ne l 1 status and control r eg ist er and

reverts TCH1 to general-purpose I/O.

Reset clears the MSxB bit.

1 = Buffered output compare/PWM operation en abled

0 = Buffered output compare/PWM operation disabled

MSxA — Mode Select Bit A

When ELSx B:A ≠ 00, this read/write bit selects either input capture

operation or unbuffered output compare/PWM operation. See Table

22-3.

1 = Unbuffered output compare/PWM operation

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Timer Interface Module (TIM)

I/O Registers

MC68HC908GR8 — Rev 4.0 Technical Data

MOTOROLA Timer Interface Module (TIM) 357

0 = Input capture operation

When ELSxB:A = 00, this read/write bit selects the initial output level

of the TCHx pin. See Table 22-3. Reset clears the MSxA bit.

1 = Initial output level low

0 = Initia l output level high

NOTE: Before changing a chann el funct ion by w ritin g to the MSxB o r MSxA b it,

set the TSTOP and TRST bits in the TIM status and control register

(TSC).

ELS xB and ELS xA — Edge/Level Select Bits

When channel x is an input capture channel, these read/write bits

control the active edge-sensing logic on channel x.

When channel x is an output compare channel, ELSxB and ELSxA

control the channel x output behavior when an output compare

occurs.

When ELSxB and ELSxA are both clear, channel x is not connected

to port D, an d pin PTDx/TCHx is available as a general-purpose I/O

pin. Table 22-3 shows how ELSxB and ELSxA work. Reset clears the

ELS xB and ELS xA bits.

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Timer Interface Mod ule (TIM)

Technical Data MC68HC908GR8 — Rev 4.0

358 Timer Interface Module (TIM) MOTOROLA

NOTE: Before enabling a TIM channel register for input capture operation, make

sure that the PTD/TCHx pin is stable for at least two bus clocks.

TOVx — Toggle On Overflow Bit

When channel x is an output compare channel, this read/write bit

controls the behavior of the channel x output when the TIM counter

overflows. When chan nel x is an input capture channel, TOVx has no

effect. Reset clears the TOVx bit.

1 = Channel x pin toggles on TIM counter overflow.

0 = Channe l x pin does not tog gl e on TIM counte r over flo w.

NOTE: When TOVx is set, a TIM counter overflow t akes precede nce ove r a

channel x output compare if both occur at the same time.

Table 22-3. Mode, Edge, and Level Selection

MSxB:MSxA ELSxB:ELSxA Mode Configuration

X0 00 Output preset

Pin under port control;

initial output level high

X1 00 Pin under port control;

initial output level low

00 01

Input capture

Capture on rising edg e only

00 10 Capture on falling edge only

00 11 Capture on rising or

falling edge

01 01 Output

compar e or

PWM

Toggle output on compare

01 10 Clear output on compare

01 11 Set output on compare

1X 01 Buffered

output

compar e or

buffered PW M

Toggle output on compare

1X 10 Clear output on compare

1X 11 Set output on compare

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Timer Interface Module (TIM)

I/O Registers

MC68HC908GR8 — Rev 4.0 Technical Data

MOTOROLA Timer Interface Module (TIM) 359

CHxMAX — Channel x Maximum Duty Cycle Bit

When the TOVx bit is at logic 1, setting the CHxMAX bit forces the

duty cycle of buffered and unbuffered PWM signals to 100%. As .

CHxMAX Latency shows, the CHxMAX bit takes effect in the cycle

after it is set or cleared. The output stays at the 100% duty cycle level

until the cycle after CHxMAX is cleared.

Figure 22-13. CHxMAX Latency

22.10.6 TIM Channel Registers

These read/write registers contain the captured TIM counter value of the

input capture function or the output compare value of the output

compare function. The state of the TIM channel registers after reset is

unknown.

In inpu t capt ure mod e (MSxB :MSxA = 0:0), rea ding the hi gh byte of the

TIM channel x registers (TCHxH) inhibits in put captures until the low

byte (TCHxL) is read.

In output com pare mode (MSxB:MS xA ≠ 0:0), writing to th e hi gh b yte of

the TIM channel x registers (TCHxH) inhibits output compares until the

low byte (TCHxL) is written.

OUTPUT

OVERFLOW

PTEx/TCHx

PERIOD

CHxMAX

OVERFLOW OVERFLOW OVERFLOW OVERFLOW

COMPARE OUTPUT

COMPARE

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Technical Data MC68HC908GR8 — Rev 4.0

360 Timer Interface Module (TIM) MOTOROLA

Address: T1CH0H, $0026 and T2CH0H, $0031

Bit 7654321Bit 0

Read: Bit 15 14 13 12 11 10 9 Bit 8

Write:

Reset: Indeterminate after reset

Figure 22-14. TIM Channel 0 Register High (TCH0H)

Address: T1CH0L, $0027 and T2CH0L $0032

Bit 7654321Bit 0

Read: Bit 7654321Bit 0

Write:

Reset: Indeterminate after reset

Figure 22-15. TIM Channel 0 Register Low (TCH0L)

Address: T1CH1H, $0029

Bit 7654321Bit 0

Read: Bit 15 14 13 12 11 10 9 Bit 8

Write:

Reset: Indeterminate after reset

Figure 22-16. TIM Channel 1 Register High (TCH1H)

Address: T1CH1L, $002A

Bit 7654321Bit 0

Read: Bit 7654321Bit 0

Write:

Reset: Indeterminate after reset

Figure 22-17. TIM Channel 1 Register Low (TCH1L)

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MC68HC908GR8 — Rev 4.0 Technical Data
MOTOROLA Electrical Specifications 361
 
Technical Data — MC68HC908GR8
Section 23. Electrical Specificat ions
23.1  Contents
23.2 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . .362
23.3 Functional Operating Range. . . . . . . . . . . . . . . . . . . . . . . . . .363
23.4 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .363
23.5 5.0 V DC Electrical Characteristics. . . . . . . . . . . . . . . . . . . . .364
23.6 3.0 V DC Electrical Characteristics. . . . . . . . . . . . . . . . . . . . .366
23.7 5.0 V Control Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .368
23.8 3.0 V Control Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .369
23.9 Output High-Voltage Characteristics  . . . . . . . . . . . . . . . . . . .370
23.10 Output Lo w-Voltage Characteristics. . . . . . . . . . . . . . . . . . . .373
23.11 Typical Supply Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . .376
23.12 ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .378
23.13 5.0 V SPI Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .379
23.14 3.0 V SPI Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .380
23.15 Timer Interface Module Characteristics . . . . . . . . . . . . . . . . .3 83
23.16 Clock Generation Module Characteristics  . . . . . . . . . . . . . . .383
23.17 Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .385
    
  
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Electrical Specification s

Technical Data MC68HC908GR8 — Rev 4.0

362 Electrical Specific ations MOTOROLA

23.2 Absolu te Maximum Ratings

Maximum ratings are the extreme limits to which the MCU can be

expo sed without permanently damaging it .

NOTE: This device is not g uaranteed to operate properl y beyond the maxim um

ratings. Refer to 5.0 V DC Electrical Characte ristics for guaranteed

operating co nditions.

NOTE: This device cont ains circuitry to protect the inputs against da mage due

to high static voltages or electric fields; however, it is advised that normal

precautions be taken to avoid application of any voltage higher than

maximum-rated voltages to this hig h-impedance circu it. For proper

operation, it is recommended that VIn and VOut be constrained to the

range VSS ≤ (VIn or VOut) ≤ VDD. Reliability of operation is enhanced if

unused inputs are connected to an appropriate logic voltage level (for

example, either VSS or VDD).

Table 23-1. Absolute Maximum Ratings

Characteristic(1)

1. Voltages referenced to VSS

Symbol Value Unit

Supply voltage VDD –0.3 to + 5.5 V

Input voltage VIn VSS – 0.3 to VDD + 0.3 V

Maximum current per pin

excluding VDD, VSS,

and PTC0–PTC1 I± 15 mA

Maximum current for pins

PTC0–PTC1 IPTC0–PTC1 ± 25 mA

Maximum current into VDD Imvdd 150 mA

Maximum current out of VSS Imvss 150 mA

Storage temp er atu re Tstg –55 to +150 °C

Note:

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Electrical Specifications

Functional Operating Range

MC68HC908GR8 — Rev 4.0 Technical Data

MOTOROLA Electrical Specifications 363

23.3 Functional Operating Range

NOTE: To ens ure correct operation of the MCU under all operating conditions,

the us er must wr ite d ata $1 C to add ress $0 033 im mediat ely af ter r eset.

This i s to ens ure proper te rmination of an unused m odule within the

MCU.

23.4 Therm al Characteristics

Table 23-2. Functional Operation Range

Characteristic Symbol Value Unit

Operating temperature range TA–40 to +125 °C

Operating voltage range VDD 3.0 ±10%

5.0 ±10% V

Table 23-3. Thermal Characteristics

Characteristic Symbol Value Unit

Thermal resistance

PDIP (28-pin)

SOIC (28-pi n)

QFP (32-pin)

θJA 60

°C/W

I/O pin power dissipat ion PI/O User-Determined W

Power dissipation(1)

1. Power dissipation is a function of temperature.

PDPD = (IDD × VDD) + PI/O =

K/(TJ + 273 °C) W

Constant(2)

2. K is a constant unique to the device. K can be determined for a known TA and measured

PD. With this value of K, PD and TJ can be determined for any value of TA.

KPD x (TA + 273 °C)

+ PD2 × θJA W/°C

Average junct ion temperature TJTA + (PD × θJA)°C

Maximum junction temperature TJM 140 °C

Notes:

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Technical Data MC68HC908GR8 — Rev 4.0

364 Electrical Specific ations MOTOROLA

23.5 5.0 V DC Electri cal Characteristics

Table 23-4 . 5.0V DC Electrical Characte ristics

Characteristic(1) Symbol Min Typ(2) Max Unit

Output high voltage

(ILoad = –2.0 mA) all I/O pins

(ILoad = –10.0 mA) all I/O pins

(ILoad = –10.0 mA) pins PTC0–PTC1 only

Maximum combined IOH for port C, port E,

port PTD0–PTD3

Maximum combined IOH for port PTD4–PTD6,

port A, port B

Maximum total IOH for all port pins

VOH

IOH1

IOH2

IOHT

VDD – 0.8

VDD – 1.5

VDD – 0.8

—

100

Output low voltage

(ILoad = 1.6 mA) all I/O pins

(ILoad = 10 mA) all I/O pins

(ILoad = 15 mA) pins PTC0–PTC1 only

Maximum combined IOL for port C, port E,

port PTD0–PTD3

Maximum combined IOL for port PTD4–PTD6,

port A, port B

Maximum total IOL for all port pins

VOL

IOL1

IOL2

IOLT

—

0.4

1.5

1.0

100

Input high voltage

All ports, IRQs, RESET

OSC1 VIH 0.7 x VDD

0.8 x VDD

—VDD V

Input low voltage

All ports, IRQs, RESET, OSC1 VIL VSS —0.2 x VDD V

VDD supply current

Run(3)

Wait(4) IDD —

—15

420

8mA

Stop(5) (<85 °C)

Stop (>85 °C)

Stop with TBM enabled(6)

Stop with LVI and TBM ena ble d(6)

IDD

—

300

500

µA

I/O ports Hi-Z leakage current(7) IIL ——±10 µA

Input current IIn —— 1µA

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Electrical Specifications

5.0 V DC Electrical Characteristics

MC68HC908GR8 — Rev 4.0 Technical Data

MOTOROLA Electrical Specifications 365

Pullup resistors (as input only)

Ports PTA3/KBD3–PTA0/KBD0, PTC1–PTC0,

PTD6/T2CH0–PTD0/SS RPU 20 45 65 kΩ

Capacitance

Ports (as input or output) COut

CIn —

——

—12

8pF

Monitor mode entry voltage VTST VDD +2.5 —8V

Low-voltage inhibit, trip falling voltage – target VTRIPF 3.85 4.25 4.50 V

Low-voltage inhibit, trip rising voltage – target VTRIPR 3.95 4.35 4.60 V

Low-voltage inhibit reset/recover hysteresis – target

(VTRIPF + VHYS = VTRIPR)VHYS —100 —mV

POR rearm voltage(8) VPOR 0 — 100 mV

POR reset voltage(9) VPORRST 0 700 800 mV

POR rise time ramp rate(10) RPOR 0.035 ——V/ms

Notes:

1. VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted

2. Typical values reflect average measurements at midpoint of voltage range, 25 °C only.

3. Run (operating) IDD measured using external square wave clock source (fosc = 32.8 MHz). All inputs 0.2 V from rail. No

dc load s. Les s than 100 pF o n all o utputs . CL = 20 pF on OS C2. All p orts c onfigu red as i nputs . OS C2 capac itanc e line arly

affects ru n IDD. Measured with all modules enabled.

4. Wait IDD measured using ex ternal square wav e clock source (fosc = 32.8 MHz). All inputs 0.2 V from rail. No dc loads. Less

than 100 pF on all outputs. CL = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly affects wait

IDD. Measured with PLL and LVI enabled.

5. Stop IDD is measured with OSC1 = VSS.

6. St op IDD with TBM enabled is measured using an external square wave clock source (fOSC = 32.8 KHz). All inputs 0.2 V

from rail. No dc loads. Less than 100 pF on all outputs. All inputs configured as inputs.

7. Pullups and pulldowns are disabled. Port B leakage is specified in ADC Characteristics.

8. Maximum is highest voltage that POR is guaranteed.

9. Maximum is highest voltage that POR is possible.

10. If minimum VDD is not reached before the internal POR reset is rel eased, RST must be driven low externally until minimum

VDD is reached.

Table 23-4 . 5.0V DC Electrical Characte ristics

Characteristic(1) Symbol Min Typ(2) Max Unit

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Electrical Specification s

Technical Data MC68HC908GR8 — Rev 4.0

366 Electrical Specific ations MOTOROLA

23.6 3.0 V DC Electri cal Characteristics

Table 23-5. 3.0 V DC Elect rical Characteristics

Characteristic(1) Symbol Min Typ(2) Max Unit

Output high voltage

(ILoad = –0.6 mA) all I/O pins

(ILoad = –4.0 mA) all I/O pins

(ILoad = –4.0 mA) pins PTC0–PTC1 only

Maximum combined IOH for port C, port E,

port PTD0–PTD3

Maximum combined IOH for port PTD4–PTD6,

port A, port B

Maximum total IOH for all port pins

VOH

IOH1

IOH2

IOHT

VDD – 0.3

VDD – 1.0

VDD – 0.5

—

Output low voltage

(ILoad = 0.5 mA) all I/O pins

(ILoad = 6.0 mA) all I/O pins

(ILoad = 10.0 mA) pins PTC0–PTC1 only

Maximum combined IOL for port C, port E,

port PTD0–PTD3

Maximum combined IOL for port PTD4–PTD6,

port A, port B

Maximum total IOL for all port pins

VOL

IOL1

IOL2

IOLT

—

0.3

1.0

0.8

Input high voltage

All ports, IRQs, RESET

OSC1 VIH 0.7 x VDD

0.8 x VDD

—VDD V

Input low voltage

All ports, IRQs, RESET

OSC1 VIL VSS —0.3 x VDD

0.2 x VDD

VDD supply current

Run(3)

Wait(4) IDD —

—4.5

1.65 8

4mA

Stop(5)(<85 °C)

Stop (>85 °C)

Stop with TBM enabled(6)

Stop with LVI and TBM ena ble d(6)

IDD

—

200

300

µA

I/O ports Hi-Z leakage current(7) IIL ——±10 µA

Input current IIn —— 1µA

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Electrical Specifications

3.0 V DC Electrical Characteristics

MC68HC908GR8 — Rev 4.0 Technical Data

MOTOROLA Electrical Specifications 367

Pullup resistors (as input only)

Ports PTA3/KBD37–PTA0/KBD0, PTC1–PTC0,

PTD6/T2CH0–PTD0/SS RPU 20 45 65 kΩ

Capacitance

Ports (as input or output) COut

CIn —

——

—12

8pF

Monitor mode entry voltage VTST VDD +2.5 —8V

Low-voltage inhibit, trip falling voltage – target VTRIPF 2.35 2.60 2.70 V

Low-voltage inhibit, trip rising voltage – target VTRIPR 2.45 2.66 2.80 V

Low-voltage inhibit reset/recover hysteresis – target

(VTRIPF + VHYS = VTRIPR)VHYS —60 —mV

POR rearm voltage(8) VPOR 0 — 100 mV

POR reset voltage(9) VPORRST 0 700 800 mV

POR rise time ramp rate(10) RPOR 0.02 ——V/ms

Notes:

1. VDD = 3.0 Vdc ± 10%, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted

2. Typical values reflect average measurements at midpoint of voltage range, 25 °C only.

3. Run (operating) IDD measured using external square wave clock source (fosc = 16.4 MHz). All inputs 0.2 V from rail. No

dc load s. Les s than 100 pF o n all o utputs . CL = 20 pF on OS C2. All p orts c onfigu red as i nputs . OS C2 capac itanc e line arly

affects ru n IDD. Measured with all modules enabled.

4. Wait IDD measured using ex ternal square wav e clock source (fosc = 16.4 MHz). All inputs 0.2 V from rail. No dc loads. Less

than 100 pF on all outputs. CL = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly affects wait

IDD. Measured with PLL and LVI enabled.

5. Stop IDD is measured with OSC1 = VSS.

6. St op IDD with TBM enabled is measured using an external square wave clock source (fOSC = 32.8 KHz). All inputs 0.2 V

from rail. No dc loads. Less than 100 pF on all outputs. All inputs configured as inputs.

7. Pullups and pulldowns are disabled.

8. Maximum is highest voltage that POR is guaranteed.

9. Maximum is highest voltage that POR is possible.

10. If minimum VDD is not reached before the internal POR reset is rel eased, RST must be driven low externally until minimum

VDD is reached.

Table 23-5. 3.0 V DC Elect rical Characteristics

Characteristic(1) Symbol Min Typ(2) Max Unit

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Electrical Specification s

Technical Data MC68HC908GR8 — Rev 4.0

368 Electrical Specific ations MOTOROLA

23.7 5.0 V Control Timing

Table 23-6. 5.0 V Control Timing

Characteristic(1)

1. VSS = 0 Vdc; ti ming show n with respe ct to 20% VDD an d 70% VSS unl ess otherwis e noted.

Symbol Min Max Unit

Frequency of operation(2)

Crystal option

Extern al c l ock option (3)

2. See Clock Generation Module Characteristics for more information.

3. No more than 10% duty cycle deviation from 50%

fosc 32

dc(4)

4. Some modules may require a minimum frequency greater than dc for proper operation.

See appropriate table for this information.

100

32.8 kHz

MHz

Internal operating frequency fop —8.2 MHz

Internal clock period (1/fOP)t

cyc 122 —ns

RESET input pulse width low(5)

5. Minim um pulse width reset is guaran teed to be recognized. It is possible for a smaller pulse

width to cause a reset .

tIRL 50 —ns

IRQ interrupt pulse width low(6)

(edge-triggered)

6. Minimum pulse width is for guaranteed interrupt. It is possible for a smaller pulse width to

be recognized.

tILIH 50 —ns

IRQ interrupt pulse period tILIL Note 8 —tcyc

16-bit timer(7)

Input capture pulse width

Input capture period

7. Minimum pulse width is for guaranteed interrupt. It is possible for a smaller pulse width to

be recognized.

8. The minimum period , tILIL or tTLTL, shou ld not be less than the numbe r of cycle s it tak es to

execute the interrupt service routine plus tcyc.

tTH,tTL

tTLTL Note 8 —

—ns

tcyc

Notes:

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Electrical Specifications

3.0 V Control Timing

MC68HC908GR8 — Rev 4.0 Technical Data

MOTOROLA Electrical Specifications 369

23.8 3.0 V Control Timing

Table 23-7. 3.0 V Control Timing

Characteristic(1)

1. VSS = 0 Vdc; ti ming show n with respe ct to 20% VDD an d 70% VSS unl ess otherwis e noted.

Symbol Min Max Unit

Frequency of operation(2)

Crystal option

Extern al c l ock option (3)

2. See Clock Generation Module Characteristics for more information.

3. No more than 10% duty cycle deviation from 50%

fosc 32

dc(4)

4. Some modules may require a minimum frequency greater than dc for proper operation.

See appropriate table for this information.

100

16.4 kHz

MHz

Internal operating frequency fop —4.1 MHz

Internal clock period (1/fOP)t

cyc 244 —ns

RESET input pulse width low(5)

5. Minim um pulse width reset is guaran teed to be recognized. It is possible for a smaller pulse

width to cause a reset .

tIRL 125 —ns

IRQ interrupt pulse width low(6)

(edge-triggered)

6. Minimum pulse width is for guaranteed interrupt. It is possible for a smaller pulse width to

be recognized.

tILIH 125 —ns

IRQ interrupt pulse period tILIL Note 8 —tcyc

16-bit timer(7)

Input capture pulse width

Input capture period

7. Minimum pulse width is for guaranteed interrupt. It is possible for a smaller pulse width to

be recognized.

8. The minimum period , tILIL or tTLTL, shou ld not be less than the numbe r of cycle s it tak es to

execute the interrupt service routine plus tCYC.

tTH,tTL

tTLTL Note 8 —

—ns

tcyc

Notes:

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Electrical Specification s

Technical Data MC68HC908GR8 — Rev 4.0

370 Electrical Specific ations MOTOROLA

23.9 Output High-Voltage Characteristi cs

Figure 23-1. Typical High- Side Driver Characteristics –

Port PT A3–PTA0 (VDD = 4.5 Vdc)

Figure 23-2. Typical High- Side Driver Characteristics –

Port PT A3–PTA0 (VDD = 2.7 Vdc)

–35

–30

–25

–20

–15

–10

–5

–40

(mA)

–40

VOH (V)

3 3.4 3.6 3.8 4.0 4.23.2

VOH > VDD –0.8 V @ IOH = –2.0 mA

VOH > VDD –1.5 V @ IOH = –10.0 mA

–25

–20

–15

–10

–5

–40

(mA)

1.3 1.7 1.9 2.1 2.3 2.51.5

VOH (V)

VOH > VDD –0.3 V @ IOH = –0.6 mA

VOH > VDD –1.0 V @ IOH = –4.0 mA

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Electrical Specifications

Output Hig h-Vol tag e Charac teris ti cs

MC68HC908GR8 — Rev 4.0 Technical Data

MOTOROLA Electrical Specifications 371

Figure 23-3. Typical High- Side Driver Characteristics –

Port PT C1–PTC0 (VDD = 4.5 Vdc)

Figure 23-4. Typical High- Side Driver Characteristics –

Port PT C1–PTC0 (VDD = 2.7 Vdc)

–35

–30

–25

–20

–15

–10

–5

–40

(mA)

–40

VOH (V)

3 3.4 3.6 3.8 4.0 4.23.2

VOH > VDD –0.8 V @ IOH = –10.0 mA

–25

–20

–15

–10

–5

–40

(mA)

1.3 1.7 1.9 2.1 2.3 2.51.5

VOH (V)

VOH > VDD –0.5 V @ IOH = –4.0 mA

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Electrical Specification s

Technical Data MC68HC908GR8 — Rev 4.0

372 Electrical Specific ations MOTOROLA

Figure 23-5. Typical High- Side Driver Characteristics –

Ports PTB5–PTB0, PTD6–PTD0, and

PTE1–PTE0 (VDD = 5.5 Vdc)

Figure 23-6. Typical High- Side Driver Characteristics –

Ports PTB5–PTB0, PTD6–PTD0, and

PTE1–PTE0 (VDD = 2.7 Vdc)

–70

–60

–50

–40

–30

–20

–10

–40

(mA)

–90

VOH (V)

3 3.4 3.6 3.8 4.0 4.23.2

–80

4.64.4

OH > VDD –0.8 V @ IOH = –2.0 mA

OH > VDD –1.5 V @ IOH = –10.0 mA

–25

–20

–15

–10

–5

–40

(mA)

1.3 1.7 1.9 2.1 2.3 2.51.5

VOH (V)

VOH > VDD –0.3 V @ IOH = –0.6 mA

VOH > VDD –1.0 V @ IOH = –4.0 mA

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Electrical Specifications

Output Low-Voltage Characteristics

MC68HC908GR8 — Rev 4.0 Technical Data

MOTOROLA Electrical Specifications 373

23.10 Output Low-Voltage Characteristics

Figure 23-7. Typical Low-Side D river Characteristics –

Port PT A3–PTA0 (VDD = 5.5 Vdc)

Figure 23-8. Typical Low-Side D river Characteristics –

Port PT A3–PTA0 (VDD = 2.7 Vdc)

–40

(mA)

VOL (V)

0 0.4 0.6 0.8 1.0 1.20.2

1.4 1.6

VOL < 0.4 V @ IOL = 1.6 mA

VOL < 1.5 V @ IOL = 10.0 mA

–40

(mA)

VOL (V)

0.4 0.6 0.8 1.0 1.20.2

1.4 1.6

VOL < 0.3 V @ IOL = 0.5 mA

VOL < 1.0 V @ IOL = 6.0 mA

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Electrical Specification s

Technical Data MC68HC908GR8 — Rev 4.0

374 Electrical Specific ations MOTOROLA

Figure 23-9. Typical Low-Side D river Characteristics –

Port PT C1–PTC0 (VDD = 4.5 Vdc)

Figure 23-10. Typical Low-Side Driver Characteristics –

Port PT C1–PTC0 (VDD = 2.7 Vdc)

(mA)

VOL (V)

0.4 0.6 0.8 1.0 1.2 1.4 1.6

–40

VOL < 1.0 V @ IOL = 15 mA

–40

(mA)

VOL (V)

0.4 0.6 0.8 1.0 1.20.2

1.4 1.6

VOL < 0.8 V @ IOL = 10 mA

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Electrical Specifications

Output Low-Voltage Characteristics

MC68HC908GR8 — Rev 4.0 Technical Data

MOTOROLA Electrical Specifications 375

Figure 23-11. Typical Low-Side Driver Characteristics –

Ports PTB5–PTB0, PTD6–PTD0, and

PTE1–PTE0 (VDD = 5.5 Vdc)

Figure 23-12. Typical Low-Side Driver Characteristics –

Ports PTB5–PTB0, PTD6–PTD0, and

PTE1–PTE0 (VDD = 2.7 Vdc)

–40

(mA)

VOL (V)

0 0.4 0.6 0.8 1.0 1.20.2

1.4 1.6

VOL < 0.4 V @ IOL = 1.6 mA

VOL < 1.5 V @ IOL = 10.0 mA

–40

(mA)

VOL (V)

0.2 0.4 0.6 0.8 1.00

1.2 1.6

1.4

VOL < 0.3 V @ IOL = 0.5 mA

VOL < 1.0 V @ IOL = 6.0 mA

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Electrical Specification s

Technical Data MC68HC908GR8 — Rev 4.0

376 Electrical Specific ations MOTOROLA

23.11 Typical Supply Currents

Figure 23-13. Typical Operating IDD, with All Modules

Turned On (–40 °C to 125 °C)

Figure 23-14. Typical Wait Mode IDD, with all Modules Disabled

(–40 °C to 125 °C)

0123456789

5.5 V

3.6 V

fbus (M Hz)

(mA)

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

012345678

5.5 V

3.6 V

(mA)

fbus (M Hz)

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Electrical Specifications

Typical Supply Currents

MC68HC908GR8 — Rev 4.0 Technical Data

MOTOROLA Electrical Specifications 377

Figure 23-15. Typical Stop Mode IDD, with all Modules Disabled

(–40 °C to 125 °C)

1.05

1.10

1.15

1.20

1.25

1.30

0123456789

5.5 V

3.6 V

fbus (MHz)

(

1.35

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Electrical Specification s

Technical Data MC68HC908GR8 — Rev 4.0

378 Electrical Specific ations MOTOROLA

23.12 ADC Characteri stics

Characteristic(1) Symbol Min Max Unit Comments

Supply voltage VDDAD

2.7

(VDD

min)

5.5

(VDD

max) V

VDDAD should be tied

to the same potential

as VDD via separate

traces.

Input voltages VADIN 0VDDAD VVADIN <= VREFH

Resolution BAD 88Bits

Absolute accuracy

(VREFL = 0 V, VDDAD = VREFH =

5 V ± 10%) AAD −− ± 1 LSB Includes quantization

ADC internal clock fADIC 0.5 1.048 MHz tAIC = 1/fADIC, tested

only at 1 MHz

Conversion range RAD VREFL VREFH VVREFH = VDDAD

VREFL = VSSAD

Power-up time tADPU 16 tAIC cycles

Conversion time tADC 16 17 tAIC cycles

Sample time(2) tADS 5 — tAIC

cycles

Zero input reading(3) ZADI 00 01 Hex VIN = VREFL

Full-s cale reading(3) FADI FE FF Hex VIN = VREFH

Input capacitance CADI —(20) 8 pF Not tested

Input leakage(4)

Port B ——

± 1 µA

Notes:

1. VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, VDDAD = 5.0 Vdc ± 10%, VSSAD = 0 Vdc, VREFH = 5.0 Vdc ± 10%, VREFL = 0

2. Source impedances greater than 10 kΩ adversely affect internal RC charging time during input sampli ng.

3. Zero-inpu t/fu ll-scale reading requi res suffi c ient decoupling measu res for accurate conversions.

4. The external system error caused by input leakage current is approximately equal to the product of R source and in put

current.

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Electrical Specifications

5.0 V SPI Characteristics

MC68HC908GR8 — Rev 4.0 Technical Data

MOTOROLA Electrical Specifications 379

23.13 5.0 V SPI Characteristics

Diagram

Number(1)

1. Numbers refer to dimensions in Figure 23-16 and Figure 23 -17.

Characteristic(2)

2. All timing is shown wi th respec t to 20% VDD and 70% VDD, unless noted; 100 pF load on all SPI pins.

Symbol Min Max Unit

Operating frequency

Master

Slave fOP(M)

fOP(S)

fOP/128

DC fOP/2

fOP

MHz

1Cycle time

Master

Slave tCYC(M)

tCYC(S)

1128

—tcyc

tcyc

2 Enable lead time tLead(S) 1 — tcyc

3 Enable lag time tLag(S) 1 — tcyc

4Clock (SPSCK) high time

Master

Slave tSCKH(M)

tSCKH(S)

tcyc –25

1/2 tcyc –25 64 tcyc

—ns

5Clock (SPSCK) low time

Master

Slave tSCKL(M)

tSCKL(S)

tcyc –25

1/2 tcyc –25 64 tcyc

—ns

6Data setup time (inputs)

Master

Slave tSU(M)

tSU(S)

30 —

—ns

7Data hold t ime (inputs)

Master

Slave tH(M)

tH(S)

30 —

—ns

8Access time, slave(3)

CPHA = 0

CPHA = 1

3. Time to data active from high-impedance state

tA(CP0)

tA(CP1)

040

40 ns

9Disable time, slave(4)

4. Hold time to high-impedance state

tDIS(S) —40 ns

10 Data valid time, after enable edge

Master

Slave(5)

5. With 100 pF on all SPI pins

tV(M)

tV(S)

—

—50

50 ns

11 Data hold time, outputs, after enable edge

Master

Slave tHO(M)

tHO(S)

0—

—ns

Notes:

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Electrical Specification s

Technical Data MC68HC908GR8 — Rev 4.0

380 Electrical Specific ations MOTOROLA

23.14 3.0 V SPI Characteristics

Diagram

Number(1)

1. Numbers refer to dimensions in Figure 23-16 and Figure 23 -17.

Characteristic(2)

2. All timing is shown wi th respec t to 20% VDD and 70% VDD, unless noted; 100 pF load on all SPI pins.

Symbol Min Max Unit

Operating fre que ncy

Master

Slave fOP(M)

fOP(S)

fOP/128

DC fOP/2

fOP MHz

MHz

1Cycle time

Master

Slave tCYC(M)

tCYC(S)

1128

—tcyc

tcyc

2 Enable lead time tLead(s) 1 — tcyc

3 Enable lag time tLag(s) 1 — tcyc

4Clock (SPSCK) high t ime

Master

Slave tSCKH(M)

tSCKH(S)

tcyc –35

1/2 tcyc –35 64 tcyc

—ns

5Clock (SPSCK) low time

Master

Slave tSCKL(M)

tSCKL(S)

tcyc –35

1/2 tcyc –35

64 tcyc

—ns

6Data setup time (inputs)

Master

Slave tSU(M)

tSU(S)

40 —

—ns

7Data hold time (inputs)

Master

Slave tH(M)

tH(S)

40 —

—ns

8Access time, slave(3)

CPHA = 0

CPHA = 1

3. Time to data active from high-impedance state

tA(CP0)

tA(CP1)

050

50 ns

9Disable time, slave(4)

4. Hold time to high-impedance state

tDIS(S) —50 ns

10 Data valid time, after enable edge

Master

Slave(5)

5. With 100 pF on all SPI pins

tV(M)

tV(S)

—

—60

60 ns

11 Data hold time, outputs, after enable edge

Master

Slave tHO(M)

tHO(S)

0—

—ns

Notes:

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Electrical Specifications

3.0 V SPI Characteristics

MC68HC908GR8 — Rev 4.0 Technical Data

MOTOROLA Electrical Specifications 381

Figure 23-16. SPI Master Timing

NOTE

Note: This first clock edge is generated internally, but is n ot seen at the SPSCK pin.

SS PIN OF MASTER HELD HIGH

MSB IN

INPUT

SPSCK OUTPUT

MISO

INPUT

MOSI

OUTPUT

NOTE

BITS 6–1LSB IN

MASTER MSB OUT BITS 6 –1MASTER LSB OUT

11 10 11

NOTE

Note: This last clock edge is generated internally, but is not seen at the SPSCK pin.

SS PIN OF MASTER HELD HIGH

MSB IN

INPUT

SPSCK OUTPUT

MISO

INPUT

MOSI

OUTPUT

NOTE

BITS 6–1LSB IN

MASTER MSB OUT BITS 6–1MASTER LSB OUT

10 11 10

a) SPI Master Timing (CPHA = 0)

b) SPI Master Timing (CPHA = 1)

CPOL = 0

CPOL = 1

CPOL = 0

CPOL = 1

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Electrical Specification s

Technical Data MC68HC908GR8 — Rev 4.0

382 Electrical Specific ations MOTOROLA

Figure 23-17. SPI Slave Timing

Note: Not defined but normally MSB of character just received

SLAVE

INPUT

SPSCK INP UT

MISO

INPUT

MOSI

OUTPUT

MSB IN

BITS 6–1

610

NOTESLAVE LSB OUT

LSB IN

BITS 6–1

MSB OUT

Note: Not defined but normally LSB of character previously transmitted

SLAVE

INPUT

SPSCK INPUT

MISO

OUTPUT

MOSI

INPUT

MSB IN

BITS 6–1

610

NOTE SLAVE LSB OUT

LSB IN

BITS 6–1

MSB OUT

a) SPI Slave Timing (CPHA = 0)

b) SPI Slave Timing (CPHA = 1)

CPOL = 0

CPOL = 1

CPOL = 0

CPOL = 1

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Electrical Specifications

Timer Interface Module Characteristics

MC68HC908GR8 — Rev 4.0 Technical Data

MOTOROLA Electrical Specifications 383

23.15 Timer Inter face Module Characteristics

23.16 Clock Generati on Module Characteristics

23.16.1 CGM Component Specifications

Table 23-8. Timer Interface Module Characteristics

Characteristic Symbol Min Max Unit

Input capture pulse width tTIH, tTIL 1 — tcyc

Table 23-9. CGM Component Specifications

Characteristic Symbol Min Typ Max Unit

Crystal reference frequency(1)

1. Fundamental mode crystals only

fXCLK 30 32.768 100 kHz

Crystal load capacitance(2)

2. Consult crystal manufacturer’s data.

CL———pF

Crystal fixed capacitance(2) C162 × CL40 pF

Crystal tuning capacitance(2) C262 × CL40 pF

Feedback bias resistor RB10 10 22 MΩ

Series resistor RS330 330 470 kΩ

Notes:

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Electrical Specification s

Technical Data MC68HC908GR8 — Rev 4.0

384 Electrical Specific ations MOTOROLA

23.16.2 CGM Electrical Specifications

Description Symbol Min Typ Max Unit

Operating voltage VDD 2.7 —5.5 V

Operating temperature T –40 25 125 oC

Crystal reference frequency fRCLK 30 32.768 100 kHz

Range nominal multiplier fNOM —38.4 —kHz

VCO center-of-range frequency(1)

1. 5.0 V ± 10% VDD

fVRS 38.4 k —40.0 M Hz

Medium-voltage VCO center-of-range frequency(2)

2. 3.0 V ± 10% VDD

fVRS 38.4 k —40.0 M Hz

VCO ran ge li near ran ge mul tiplier L 1 —255

VCO power-of-two range multiplier 2E1 — 4

VCO m ul tip ly factor N 1 —4095

VCO prescale multiplier 2P118

Reference divider factor R 1 1 15

VCO oper at ing frequency fVCLK 38.4 k —40.0 M Hz

Bus o perat ing frequency(1) fBUS ——8.2 MHz

Bus frequency @ medium voltage(2) fBUS ——4.1 MHz

Manual acquisition time tLock ——50 ms

Automatic lock time tLock ——50 ms

PLL jitter(3)

3. Deviation of average bus frequency over 2 ms. N = VCO multiplier.

fJ0 — fRCLK x

0.025%

x 2P N/4 Hz

External clock input frequency

PLL disabled fOSC dc —32.8 M Hz

External clock input frequency

PLL enabled fOSC 30 k —1.5 M Hz

Notes:

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Electrical Specifications

Memory Characteristics

MC68HC908GR8 — Rev 4.0 Technical Data

MOTOROLA Electrical Specifications 385

23.17 Memory Character istics

Characteristic Symbol Min Typ Max Unit

RAM data retention voltage VRDR 1.3 ——V

FLASH program bus clock frequency — 1 ——MHz

FLASH read bus clock frequency fRead(1)

1. fRead is defined as the frequency range for which the FLASH memory can be read.

32k —8.4M Hz

FLASH page erase time tErase(2)

2. If the page erase time is longer than tErase (Min), there is no erase-disturb, but it reduces the endurance of the FLASH

memory.

1——ms

FLASH mass erase time tMErase(3)

3. If the mass erase time is longer than tMErase (Min), there is no erase-disturb, but it reduces the endurance of the FLASH

memory.

4——ms

FLASH PGM/ERASE to HVEN set up time tnvs 10 ——µs

FLASH high-voltage hold time tnvh 5——µs

FLASH high-voltage hold time (mass erase) tnvhl 100 ——µs

FLASH program hold time tpgs 5——µs

FLASH program time tPROG 30 —40 µs

FLASH return to read time trcv(4)

4. trcv is defined as t he time it need s before the FLA SH can be read after turning off the high volta ge charge pum p, by clearing

HVEN to logic 0.

1——µs

FLASH cumulative program HV period tHV(5)

5. tHV is defined as the cumulative high voltage programming time to the same row before next erase.

tHV must satisfy this condition: tnvs + tnvh + tpgs + (tPROG × 64) ≤ tHV max.

—— 4ms

FLASH row erase endurance(6)

6. The minimum row endu rance value specifies each row of the FLASH memory is guaranteed to work for at

least this many erase / program cycles.

—10k 100k(7)

7. FLASH endurance is a function of the temperature at which erasure occurs. Typical endurance degrades when the tem-

perature whi le erasing is less than 25°C.

—Cycles

FLASH row program endurance(8)

8. The minimum row endu rance value specifies each row of the FLASH memory is guaranteed to work for at

least this many erase / program cycles.

—10k 100k(7) —Cycles

FLASH data retention time(9)

9. The FLASH is guaranteed to retain data over the entire operating temperature range for at least the minimum

time specified.

—10 100(10)

10. Motorola performs reliability te sting for data retenti on. These tests are based on samples tested at elevated temperat ures.

Due to the higher activation energy of the elevated test temperature, calculated life tests correspond to more than 100

years of operation/storage at 55°C

—Years

Notes:

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Electrical Specification s

Technical Data MC68HC908GR8 — Rev 4.0

386 Electrical Specific ations MOTOROLA

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MC68HC908GR8 — Rev 4.0 Technical Data

MOTOROLA Mechanical Specifications 387

Technical Data — MC68HC908GR8

Section 24. Mechanical Specifications

24.1 Contents

24.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .387

24.3 32-Pin LQFP (Case #873A) . . . . . . . . . . . . . . . . . . . . . . . . . .3 88

24.4 28-Pin PDIP (Case #710). . . . . . . . . . . . . . . . . . . . . . . . . . . .389

24.5 28-Pin SOIC (Case #751F). . . . . . . . . . . . . . . . . . . . . . . . . . .390

24.2 Introduction

The MC68HC908GR8 is available in these packages:

•32-pin low-profile quad fl at pack (LQFP)

•28-pin dual in-line package (PD IP)

•28-pin small outline package (SOIC)

The pa ckage informati on cont ained in this sectio n is the latest avai lable

at the time of this publication. To make sure that you have the latest

package specifications, contact one of the following:

•Local Motorola Sales Office

•World Wide Web at http://www.motoro la.com/semiconductors/

Follow World Wide Web on-line instructions to retriev e the cu rrent

mechanical specifications.

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Mechanical Specifications

Technical Data MC68HC908GR8 — Rev 4.0

388 Mechanical Specifications MOTOROLA

24.3 32-Pin LQFP (Case #873A)

- U -

- Z -

- T -

DETAIL Y

Section AE–AE

-AC-

DETAIL AD

Seating

plane

8x M °

Q °

0.20 (0.008) MAC T – U Z

0.20 (0.008) AC T-U Z

0.20 (0.008) AB T-U Z

-AB-

0.10 (0.004) AC

0.25 (0.010)

Gauge Pla ne

DETAIL AD

Base Metal

DETAIL Y

–

NOTES:

1. DIMENSIONS AND TOLERANCING AS PER ANSI

Y14.5M, 1982

2. CONTROLLING DIMENSION: MILLIMETER

3. DATUM PLANE -AB- IS LOCATED AT BOTTOM OF

LEAD AND IS CONSISTENT WITH THE LEAD

WHERE THE LEAD EXITS THE PLASTIC BODY AT

THE BOTTOM OF THE PARTING LINE

4. DA TUMS -T -, -U-, AND -Z- TO BE DETERMINED A T

DATUM PL ANE -AB-

5. DIMENSIONS S AND V TO BE DETERMINED AT

SEATING PLANE -AC-

6. DIMENSIONS A AND B DO NOT INCLUDE MOLD

PROTRUSION. ALLOWABLE PROTRUSION IS

0.250 (0.010) PER SIDE. DIMENSIONS A AND B DO

INCLUDE MOLD MISMATCH AND ARE

DETERMINED AT DATUM PLANE -AB-

7. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. DAMBAR PROTRUSION SHALL

NOT CAUSE THE D DIMENSION TO EXCEED

0.520 (0.020)

8. MINIMUM SOLDER PLA TE THICKNESS SHALL BE

0.0076 (0.00 03)

9. EXACT SHAPE OF EACH CORNER MAY VARY

FROM DEPICTION

DIM MILLIMETERS INCHES

MIN MAX MIN MAX

A7.000 BSC 0.276 BSC

A1 3.500 BSC 0.138 BSC

B7.000 BSC 0.276 BSC

B1 3.500 BSC 0.138 BSC

C1.400 1.600 0.055 0.063

D0.300 0.450 0.012 0.018

E1.350 1.450 0.053 0.057

F0.300 0.400 0.012 0.016

G0.800 BSC 0.031 BSC

H0.050 0.150 0.002 0.006

J0.090 0.200 0.004 0.008

K0.500 0.700 0.020 0.028

M12° REF 12° RE F

N0.090 0.160 0.004 0.006

P0.400 BSC 0.016 BSC

Q1°5°1°5°

R0.150 0.250 0.006 0.010

S9.000 BSC 0.354 BSC

S1 4.500 BSC 0.177 BSC

V9.000 BSC 0.354 BSC

V1 4.500 BSC 0.177 BSC

W0.200 RE F 0.008 REF

X1.000 RE F 0.039 REF

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Mechanical Specifications

28-Pin PDIP (Case #710)

MC68HC908GR8 — Rev 4.0 Technical Data

MOTOROLA Mechanical Specifications 389

24.4 28-Pin PDIP (Case #710)

Dim. Min. Max. Notes Dim. Min. Max.

A 36.45 37.21 1. All dimensions in mm.

2. Positional tolerance of leads (‘D’) shall be within 0.25 mm at

maximum material condition, in relation to seating plane and to

each ot her.

3. Dimension ‘L’ is to centre of leads when formed parallel.

4. Dimension ‘B’ does not include mou l d protrusion.

H1.652.16

B 13.72 14.22 J 0.20 0.38

C 3.94 5.08 K 2.92 3.43

D 0.36 0.56 L 15.24 BSC

F 1.02 1.52 M 0°15°

G 2.54 BSC N 0.51 1.02

F D

Seating

Plane

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Mechanical Specifications

Technical Data MC68HC908GR8 — Rev 4.0

390 Mechanical Specifications MOTOROLA

24.5 28-Pin SOIC (Case #751F)

D 28 PL

– T –

Seating

Plane MF

0.25 MBM

0.25 MBSAS

14 PL

R x 45°

Dim. Min. Max. Notes Dim. Min. Max.

A 17.80 18.05 1. Dimensions ‘A’ and ‘B’ are datums and ‘T’ is a datum surfa c e.

2. Dimensioning and tolerancing per AN SI Y14.5M, 1982.

3. All dimensions in mm.

4. Dimensions ‘A’ and ‘B’ do not inc l ude mould protrusion.

5. Maximum mould protrusion is 0.15 mm per side.

J 0.229 0.317

B 7.40 7.60 K 0.127 0.292

C 2.35 2.65 M 0°8°

D 0.35 0.49 P 10.05 10.55

F 0.41 0.90 R 0.25 0.75

G1.27 BSC ———

– A –

– B –P

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MC68HC908GR8 — Rev 4.0 Technical Data
MOTOROLA Ordering Information 391
 
Technical Data — MC68HC908GR8
Section 25. Ordering Information
25.1  Contents
25.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .391
25.3 MC Order Numbers  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .392
25.4 Development Tools. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .393
25.2  Introduction
This section contains instructions for ordering the MC68HC908GR8 and 
MC68HC908GR4.
    
  
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Orderi ng Info r ma tion

Technical Data MC68HC908GR8 — Rev 4.0

392 Ordering Information MOTOROLA

25.3 MC Orde r Numbers

Table 25-1. MC Order Numbers

MC Or der Number(1)

1. FA = quad flat pack

P = plastic dual in line package

DW = Small outline integrated circuit (SOIC) package

Operating

Temperature Range

(°C)

Production Parts

MC68HC908GR8CP

MC68HC908GR8CFA

MC68HC908GR8CDW

MC68HC908GR8VFA

MC68HC908GR8VP

MC68HC908GR8VDW

MC68HC908GR8MFA

MC68HC908GR8MP

MC68HC908GR8MDW

– 40 to + 85

– 40 to + 105

– 40 to + 125

MC68HC908GR4CP

MC68HC908GR4CFA

MC68HC908GR4CDW

MC68HC908GR4VFA

MC68HC908GR4VP

MC68HC908GR4VDW

MC68HC908GR4MFA

MC68HC908GR4MP

MC68HC908GR4MDW

– 40 to + 85

– 40 to + 105

– 40 to + 125

Tape and Reel

MC908GR8CFAR2

MC908GR8CDWR2

MC908GR8VFAR2

MC908GR8VDWR2

MC908GR8MFAR2

MC908GR8MDWR2

– 40 to + 85

– 40 to + 105

– 40 to + 125

MC908GR4CFAR2

MC908GR4CDWR2

MC908GR4VFAR2

MC908GR4VDWR2

MC908GR4MFAR2

MC908GR4MDWR2

– 40 to + 85

– 40 to + 105

– 40 to + 125

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Ordering Information

Development Tools

MC68HC908GR8 — Rev 4.0 Technical Data

MOTOROLA Ordering Information 393

25.4 Development Tools

Table 25-2. Development Tool Kits

Ordering Part Number Description

M68ICS08GR HC908GR8 ICS KIT includes: M68ICS08GR programmer board, Windows-

based IDE, 68HC908GR8 sample, ICS Board & IDE documentation, Universal

Power Supply, Serial cable

KITMMEVS08GR HC908GR8 EVS KIT includes: M68MMPFB0508, M68EML08GP32,

M68C BL0 5C, M68 TC08G R8P 28 , M68TC08 GR 8FA 32, M68 TQS 032 SA G1,

M68TQP032SA1, M68ICS08GR Kit

KITMMDS08GR HC908GR8 MMDS KIT includes: M68MMDS0508, M68EML08GP32,

M68C BL0 5C, M68 TC08G R8P 28 , M68TC08 GR 8FA 32, M68 TQS 032 SAG 1,

M68TQP032SA1, M68ICS08GR Kit

Table 25-3. Development Tool Components

Ordering Part Number Description Comments

M68MMDS0508 High performance emulator

M68MMPFB0508 MMEVS Platform Board

M68EML08GP32 HC908GP32 Emulator Board Used for HC908GR8/GR4 emulation

M68CBL05C Low noise flex-cable

M68TC08GR8P28 28-pin DIP target head adapter

M68TC0 8GR8FA 32 32-pin QFP target hea d adapte r

M68TQS032SAG1 32-pin TQ socket with guides

M68TQP032SA1 32-pin TQPACK

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Orderi ng Info r ma tion

Technical Data MC68HC908GR8 — Rev 4.0

394 Ordering Information MOTOROLA

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MC68HC908GR8 — Rev 4.0 Technical Data

MOTOROLA Glossary 395

Technical Data — MC68HC908GR8

Glossary

A — See “accu mulator (A ). ”

accu mulator (A) — An 8-bit general-purpose register in the CPU08. The CPU08 uses the

accumulator to hold op erands and results of arithm etic and l ogic operatio ns.

acquisition mode — A mode of PLL operation du ring startup before the PLL locks on a

frequency. Also see "tracking mode."

address bus — The set of wires that the CPU or DMA uses to read and write memory locations.

addressing mode — The way th at the CPU dete rmine s the op erand address for an i nstruction.

The M68HC08 CPU has 16 addressing modes.

ALU — See “arithmetic logic unit (ALU).”

arithmetic logic unit (ALU) — The portion of the CPU that contains the logic circuitry to perform

arithmetic, logic, and manipulation operations on operands.

asynchronous — Refers to logic circuits and operations that are not synchronized by a common

reference signal.

baud rate — The total number of bits transmitted per unit of time.

BCD — See “binary-coded decim al (BCD).”

binary — Relating to the base 2 number system.

binary number system — The base 2 number system, having two digits, 0 and 1. Binary

arithmetic is convenient in digital circuit design because digital circuits have two

permi ssible voltage levels, low and h i gh. The binary digits 0 and 1 can be interprete d to

correspond to the two digital voltage levels.

binary-coded decimal (BCD) — A nota ti on tha t uses 4-bit binary nu m bers to represent the 1 0

decimal digits and that retains the same positional structure of a decimal number. Fo r

example,

234 (decimal) = 0010 0011 0100 (BCD)

bit — A binary digit. A bit has a value of either logic 0 or logic 1.

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Glossary

Technical Data MC68HC908GR8 — Rev 4.0

396 Glossary MOTOROLA

branch instruction — An instruction that ca uses the CPU to continu e proce ssing at a memory

location other than the next sequential address.

break module — A module in the M68HC08 Family. Th e break module a llows soft w are to halt

program execution at a programmable point in order to ent er a backgroun d routine.

breakpoint — A number written into the brea k address registers of the brea k module. When a

numbe r appe ars o n the inter nal ad dress bus th at i s the same as th e number in th e br eak

address registers, the CPU executes the software interrupt instruction (SWI).

break interrupt — A software interrupt caused by the appearance on the internal address bus

of the same value that is written in the break address registers.

bus — A set of wires that transfers logic signals.

bus clock — The bus clock is derived from th e CGMOUT o utput from the CGM. The bus clock

frequency, fop, is equal to the frequen c y of the oscillator output, CGMXCLK, divided by

four.

byte — A set of eight bits.

C — The carry/borrow bit in the condition code r egister. The CP U08 sets the carry/borrow bit

when an addition operation produces a carry out of bit 7 of the accumulator or when a

subtraction operation requires a borrow. Some logical operations and da ta manipulati on

instructions also clear or set the carry/borrow bit (as in bit test and branch instructions and

shifts and rotates).

CCR — See “co ndition code reg ist er .”

central processor unit (CPU) — The primary functioning unit of any computer system. The

CPU controls the execution of instructions.

CGM — See “clock generator module (CGM).”

clear — To change a bit from logic 1 to logic 0; the opposite of set.

clock — A square wave signal used to synchronize events in a computer.

clock generator module (CGM) — A module in the M68HC08 Family. The CGM generates a

base clock signal fr om which the system clocks are derived. The CGM may include a

crystal oscillator circuit and or phase-locked loop (PLL) circuit.

comparator — A device that compares the magnitude of two inputs. A digital comparator defines

the equality or rela tive differences between two binary nu mbers.

computer operating properly module (COP) — A counter module in the M68HC08 Family that

resets the MCU if allowed to overflow.

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Glossary

MC68HC908GR8 — Rev 4.0 Technical Data

MOTOROLA Glossary 397

condition code register (CCR) — An 8-bit register in the CPU08 that contains the interrupt

mask bit and five bits that indicate th e results of the instruction just executed.

control bit — One bit of a register manipulated by software to control the operation of the

module.

control unit — One of two majo r units of the CPU. The con trol unit contains lo gic function s that

synchronize the machine and direct v arious operat ions. The control unit decodes

instr uctions and ge nerates the i nternal control signals that perform the requested

operations. The outputs of the control unit drive the execution unit, which contains the

arithmetic logic unit (ALU), CPU registers, and bu s interfac e.

COP — See "computer operating properly module (COP)."

counter clock — The input clock to the TIM counter. This clock is the output of the TIM

prescaler.

CPU — See “central processor unit (CPU).”

CPU08 — The central processor unit of the M68HC08 Family.

CPU clock — The CPU clock is derived from the CGMOUT output from the CGM. The CPU

clock frequency is equal to the frequency of the oscillator output, CGMXCLK, divided by

four.

CPU cycles — A CPU cycle is one period of the in ternal bus clock, normally derived by dividing

a crystal oscillator sou rce by two or more so the high and low times will be equal. The

length of time required to execute an instruction is measured in CPU clock cycles.

CPU registers — Memory locations that are wired directly into the CPU logic instead of being

part of the ad dressable memory map. The CPU always has direct access to the

information in these registers. The CPU registers in an M68HC08 are:

•A (8-bit accumulator)

•H:X (16-bit index register)

•SP (16-bit st ack pointer)

•PC (16- bi t pr og ram counter)

•CCR (condition code registe r con taining the V, H, I, N, Z, and C

bits)

CSIC — customer-specified integrated circuit

cycle time — The period of the operating frequency: tCYC =1/f

OP.

decimal number system — Base 10 numbering system that uses the digits zero through nine.

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Glossary

Technical Data MC68HC908GR8 — Rev 4.0

398 Glossary MOTOROLA

direct memory access module (DMA) — A M68HC08 Family module that can perform data

transfers between any two CPU-addressable locations without CPU intervention. For

transmitting or receiving blocks of data to or from peripherals, DMA transfers are faster

and more code-efficient than CPU interrupts.

DMA — See "dire c t memory access mod ule (DMA)."

DMA service request — A sign al from a peripheral to the DMA module that enables the DMA

module to transf er data.

duty cycl e — A ratio of the amount o f time the signal is on versus the time it is off. Duty cycle is

usually represented by a percentage.

EEPROM — Electrically erasable, programmable, read-only memory. A nonvolatile type of

memory that can be el ectrica lly repr ogramme d.

EPROM — Era sable, pr ogram mable, read-onl y memo ry. A nonvol atile type of mem ory that can

be erased by exposure to an ultraviolet light source and then reprogramm ed.

exception — An even t such as an inter rupt or a reset tha t stops the seque ntial execut ion of the

instructions in the main program.

external interrupt module (IRQ) — A module in the M68HC08 Family with both dedicated

external int errupt pi ns and port pi ns that can be enable d as interrupt pins.

fetch — To copy data from a memory location into the accumulator.

firmware — Instructions and data programmed into nonvolatile memory.

free-running counter — A device that co un ts fr om zero to a predetermi ned nu mb er , th en r o ll s

over to zero and begins counting again.

full-duplex transmission — Communication on a channel in which data can be sent and

received simultaneously.

H — The upper byte of the 16-bit index register (H:X) in the CPU08.

H — The half-carry bit in the condition code register of the CPU08. This bit indicates a carry from

the lo w-ord er fo ur bits o f the accu mulato r value to the high -or der four bits. The half- carr y

bit is required for binary-coded decimal arithmetic operations. The decimal adjust

accumulator (DAA) instruction uses the state of the H and C bits to determine the

appr opriat e correction factor.

hexadecimal — Base 16 numbering system that uses the digits 0 through 9 and the letters A

through F.

high byte — The most significant eight bits of a word.

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Glossary

MC68HC908GR8 — Rev 4.0 Technical Data

MOTOROLA Glossary 399

illegal address — An address not within the memory map

illegal opcode — A nonexistent opcode.

I — The interrupt mask bit in the condition code register of the CPU08. When I is set, all interrupts

are disabled.

index regist er (H: X) — A 16-bit register in the CPU08. The upper byte of H:X is called H. The

lower byte is called X. In the indexed addressing modes, the CPU uses the conten ts of

H:X to determine the effective address of the operand. H:X can also serve as a temporary

data storage location .

input/output (I/O) — Input/output interfaces between a computer system and the external world.

A CPU reads an input to sense the level of an external signal and writes to an output to

change the leve l on an external sig na l.

instructions — Operations that a CPU can perform. Instructions are expressed by programmers

as ass embly language mnemonics. A CPU int erpre ts an opcode and its associate d

oper and(s) and instru ction .

interrupt — A temporary break in the sequential execution of a prog ram to respond to signals

from peripheral dev ices by execut ing a subrouti ne.

interrupt request — A signal from a peri ph er al to the CP U inte nd ed to cause the CP U to

execute a subroutine.

I/O — See “input/outpu t (I/0).”

IRQ — See "external interrupt module (IRQ)."

jitter — Short-term signal instability.

latch — A circuit that retains the voltage level (logic 1 or logic 0) written to it for as long as power

is applied to the circuit.

latency — The time lag between instruction completion and data movement.

least significant bit (LSB) — The rightmost digit of a binary number.

logic 1 — A voltage level approximately equal to the input power voltage (VDD).

logic 0 — A voltage level approximately equal to the ground voltage (VSS).

low byte — The least significant eight bits of a word.

low voltage inhibit module (LVI) — A module in the M68HC08 Family that monitors power

supply vol tag e.

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Glossary

Technical Data MC68HC908GR8 — Rev 4.0

400 Glossary MOTOROLA

LVI — See "low voltage inhibit module (LVI)."

M68HC08 — A Motorola family of 8-bit MCUs.

mark/space — The logic 1/logic 0 convention used in formatting data in serial communication.

mask — 1. A logic circuit that forces a bit or group of bits to a desired state. 2. A photomask used

in integrated circuit fabrication to transfer an image onto silicon.

mask option — A optional microcontroller feature that the customer chooses to enable or

disable.

mask option register (MOR) — An EPROM location containing bits that enable or disable

certain MCU features.

MCU — Microcontroller unit. See “microcontroller.”

memory location — Each M68H C08 memory lo cation hol ds one byte of data an d has a unique

address. To store information in a memory location, the CPU places the address of the

location on the address bus, the data information on the data bus, and asserts the write

signal. To read information from a memory location, the CPU places the address of the

location on the address bus and asserts the read signal. In response to the read signal,

the selected memory location places its data onto the data bus.

memory map — A pictorial representation of all memory locations in a computer system.

microcontroller — Microcontroller unit (MCU). A complete computer sy stem, including a CPU,

memory, a clock oscillator, and input/output (I/O) on a single integrated circuit.

modulo counter — A counter that can be programmed to count to any number from zero to its

maximum po ssible modu lus.

monitor ROM — A section of ROM that can execute commands from a host computer for testing

purposes.

MOR — See "mask option register (MOR)."

most significant bit (MSB) — The leftmost digit of a binary number.

multiplexer — A device that can select one of a nu mber of inputs and pass the logic level of that

input on to the output.

N — The negative bit in the condition code register of the CPU08. The CPU sets the negative bit

when an arithmetic operation, logical operation, or data manipulation produces a negative

result.

nibble — A set of four bits (half of a byte).

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Glossary

MC68HC908GR8 — Rev 4.0 Technical Data

MOTOROLA Glossary 401

object code — The output from an assembler or compiler that is itself executable machine code,

or is suitable for processing to produce executable machine code.

opcode — A b i nary co de that instruc ts the CPU to perform an operation.

open-drain — An outpu t that has no pullup tr ansi stor. An external p ullup device c an be

connected to the power supply to provide the logic 1 output voltage.

operand — Data on which an operation is performed. Usually a statement consists of an

operator and an operand. For example, the operator may be an add instruction, and the

operand may be the qu antity to be added.

oscillator — A circuit that produces a constant frequency square wave that is used by the

computer as a timing and sequencing reference.

OTPROM — One-time programmable read-only memory. A nonvolatile type of memory that

cannot be reprogrammed.

overflow — A quantity that is too large to be contained in one byte or one word.

page zero — The first 256 bytes of memory (a ddresses $0000–$00FF).

parity — An error -checking sche me that cou nts the number of logic 1 s in each by te transmitt ed.

In a system that uses odd parity, every byte is expected to have an odd number of logic

1s. In an even parity system, every byte should have an even number of logic 1s. In the

transmitter, a parity generator appends an extra bit to each byte to make the number of

logic 1s odd for odd parity or even for even parity. A parity checker in the receiver counts

the number of logic 1s in each byte. The parity checker generates an error signal if it finds

a byte with an incorre ct number of logic 1s.

PC — See “program counter (PC).”

peripheral — A circuit not under direct CPU control.

phase-locked loop (PLL) — A oscillator circuit in which the frequency of the oscillator is

synchronized to a reference signal.

PLL — See "phase-locked loop (PLL)."

pointer — Poi nte r re gi ste r. An ind ex r e gi ster i s som eti mes cal l ed a pointer regi ster b eca use i ts

contents a re used in the calcu lation of the ad dress of an oper and, and therefo re points to

the oper and .

polarity — The two opposite logic levels, logic 1 and logic 0, which correspond to two different

voltage levels, VDD and VSS.

polling — Periodically read ing a stat us bit to monitor the condition of a periph eral device.

port — A set of wi res for communicating with off-chip devices.

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Glossary

Technical Data MC68HC908GR8 — Rev 4.0

402 Glossary MOTOROLA

prescaler — A circuit that generates an output signal related to the input signal by a fractional

scale factor such as 1/2, 1/8, 1/10 etc.

program — A set of computer instructions that cause a computer to perform a desired operation

or operati on s.

program counter (PC) — A 16-bit register in the CPU08. The PC register holds the address of

the next instruction or opera nd that the CPU will use.

pull — An instruction that copies into the accumulator the contents of a stack RAM location. The

stack RAM address is in th e stack pointer.

pullup — A transist or in the ou tput of a log ic gate that connects the output to the lo gic 1 voltag e

of the power supply.

pulse-width — The amount of time a signal is on as opposed to being in its off state.

pulse-width modulation (PWM) — Controlled variation (modulation) of the pulse width of a

signal with a constant frequency.

push — A n instruct ion tha t copies the con tents o f the accu mulator to the stack RAM. The sta ck

RAM address is in the stack point er.

PWM period — The time required for one complete cycle of a PWM waveform.

RAM — Random access memory. All RAM location s can be read or written by the CPU. The

contents of a RAM memory location remain valid until the CPU writes a different value or

until power is turned off.

RC circuit — A circuit consisting of capacitors and resistors having a defined time constant.

read — To copy the contents of a memory location to the accumulator.

reserved memory location — A memory location that is used only in special factory test modes.

Writing to a reserved location has no effect. Reading a reserv ed location returns an

unpredictable value.

reset — To force a de vice to a known condition.

ROM — Read-only memory. A type of memory that can be read but cannot be changed (written).

The contents of ROM must be specified before manufacturing the MCU.

SCI — See "serial com mu ni ca t ion interface mo du le (SC I) ."

serial — Pertaining to sequential transmission over a single line.

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Glossary

MC68HC908GR8 — Rev 4.0 Technical Data

MOTOROLA Glossary 403

serial communications interface module (SCI) — A module in the M68HC08 Family that

supports asynchronous communication.

serial peripheral interface module (SPI) — A module in the M68HC08 Family that supports

synchronous communication.

set — To change a bit from logic 0 to logic 1; opposite of clear.

shift register — A chain of circuits that can retain the logic levels (logic 1 or logic 0) written to

them and that can shift the logic levels to the right or left through adjacent circuits in the

chain.

signed — A binary number notation that accommodates both positive an d negative numbers.

The most significant bit is used to indicate whether the number is positive or negative,

normally logic 0 for positive and logic 1 for negative. The other seven bits indicate the

magnitude of the number.

software — Instructions and data that control the operation of a microcontroller.

software interrupt (SWI) — An instruction that causes an interrupt and its associated vector

fetch.

SPI — See "serial peripheral interface module (SPI)."

stack — A po rtion of RAM re ser v ed for st or ag e o f C PU r e gister co ntents and subr ou ti ne r etu rn

addresses.

stack pointer (SP) — A 16-bit register in the CPU08 containing the address of the next available

storage location on the stack.

start bi t — A bit that signals the beginning of an asynchronous serial transmission.

status bit — A register bit that indicates the condition of a device.

stop bit — A bit that signals the e nd of an async hronous seri al transmissi on.

subroutine — A sequence of instructions to be used more than once in the course of a program.

The la st inst ruction in a subr ou ti ne i s a re tur n fr om su br ou tine ( RTS ) in str uctio n. At each

place in the main program where the subroutine instructions are needed, a jump or branch

to subr outine (JSR o r BSR) inst ruction is us ed to call t he subroutine. The CPU lea ves the

flow of the main program to execute the instructions in the subroutine. When the RTS

instruction is executed, the CPU returns to the main program where it left off.

synchronous — Refers to logic circuits a nd operations that are synchronized by a common

reference signal.

TIM — See "timer interface module (TIM)."

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Glossary

Technical Data MC68HC908GR8 — Rev 4.0

404 Glossary MOTOROLA

timer interface module (TIM) — A module used to relate events in a system to a point in time.

timer — A module used to relate events in a system to a point in time.

toggle — To change the state of an output from a logic 0 to a logic 1 or from a lo gic 1 to a logic 0.

tracki ng mode — Mode of low- jitter PLL operation during which the PLL is lock ed on a

frequency. Also see "acqu isition mode."

two’s complement — A means of performing binary subtraction using addition techniques. The

most significant bit of a two’s complement number indicates the sign of the number (1

indicate s negative). The two’s complement negative of a number is obtained by inverting

each bit in the number and then adding 1 to the result.

unbuffered — Utilizes only one register for data; new data overwrites current data.

unimplemented memory location — A memory location that is not used. Writing to an

unimplemented location has no effect. Reading an unimplemented location returns an

unpredictable value. Executing an opcode at an unimplemented location causes an illegal

addr ess reset.

V —The overflow bit in the condition code register of the CPU08. The CPU08 sets the V bit when

a two' s complement overfl ow occurs. The signed branch instructions BGT, BGE, BLE,

and BLT use the overflow bit.

variable — A value that changes during the course of program execution.

VCO — See "voltage-controlled oscillator."

vector — A memory l oca ti on that con tai n s the ad dr ess of the begi nn in g of a sub r outine written

to service an interrupt or reset.

voltage-cont roll ed os cill at or (VC O) — A circuit that produces an oscillating output signal of a

frequency that is controlled by a dc voltage applied to a control input.

waveform — A g raphical representation in which the amplitud e of a wa ve is plotted against time.

wired-OR — Connection of circuit outputs so that if any output is high, the connection point is

high.

word — A set of two byte s (16 bits).

write — The transfer of a byte of data from the CPU to a memory location.

X — The lower byte o f the inde x register (H:X) in t he CPU08.

Z — The ze ro bit in t he condition code reg ister of the CP U08. The CPU0 8 sets the zero bit wh en

an arithmetic operation, logical operation, or data manipulation produces a result of $00.

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MC68HC908GR8 — Rev 4.0 Technical Data
MOTORO LA Revisi on Histor y 405
 
Technical Data — MC68HC908GR8
Revision History
Contents
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .405
Changes from Rev 3.0 published in Febru ary 2002 to Rev 4.0 
published i n June 2002. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 05
Changes f rom Rev 2.0 published in January 2002 to Rev 3.0 pub-
lished in February 2002 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .406
Changes fr om Rev 1.0 published in April 2001 to Rev 2.0 pub-
lished in December 2001 . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 06
Introduction
This section contains the revision history for the MC68HC908GR8 
technical data book.
Changes from Rev 3.0 published in February 2002 to Rev 4.0 published in 
June 2002
Section Page (in Rev 3.0) Description of change
All references to the ROM MC68HC08GR8 removed. Appendix A removed.
Electrical 
Specifications
363 Maximum junction temperature increased to 140°C
364 Input High Voltage for OSC1 changed
Stop IDD for temperatures >85°C added
366 Input High Voltage for OSC1 changed
Input Low Voltage for OSC1 changed
Stop IDD for temperatures >85°C added
    
  
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Revision Hist ory

Technical Data MC68HC908GR8 — Rev 4.0

406 Revision Histor y MOTOR OLA

Changes from Rev 2.0 published in January 2002 to Rev 3.0 published in

February 2002

Changes from Rev 1.0 published in April 2001 to Rev 2.0 published in

December 2001

Section Page (in Rev 3.0) Description of change

All references to the ROM MC68HC08GR8 removed. Appendix A removed.

Electrical

Specifications

363 Maximum operating temperature increased to 125°C

376-377 Maximum temperature increased to 125°C in titles of figures 23-

13, 23-14 and 23-15

383 Maximum operating temperature increaed to 125°C

Ordering

Information 391 New section added

Section Page (in Rev 2.0) Description of change

Monitor ROM

(MON)

The blank state of the reset vectors, $FFFE and $FFFF, was incorrectly defined as $00

and is now $FF. This affects several places in the Monitor ROM (MON) section. The

information was previously described in an addendum. See details below:

190 Penultimate bullet of features list

192 Final sentence of first paragraph

Each list item in Entering Monitor Mode section

193 Third column of Table 15-1

Timebase Module

(TBM) 329 Sever al ch ange s for clari f icati o n

Timer Interface

Module (TIM) 335 Several changes for clari fic ati on

Electrical

Specifications 385 Typical column added to table. Typical values added for FLASH

row program endurance and FLASH data retention time

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