DESCRIPTION
The DAC7800, DAC7801 and DAC7802 are members of a
new family of monolithic dual 12-bit CMOS multiplying Digi-
tal-to-Analog Converters (DACs). The digital interface speed
and the AC multiplying performance are achieved by using
an advanced CMOS process optimized for data conversion
circuits. High stability on-chip resistors provide true 12-bit
integral and differential linearity over the wide industrial
temperature range of –40°C to +85°C.
The DAC7800 features a serial interface capable of clocking-
in data at a rate of at least 10MHz. Serial data is clocked
(edge triggered) MSB first into a 24-bit shift register and then
latched into each DAC separately or simultaneously as
required by the application. An asynchronous CLEAR control
is provided for power-on reset or system calibration func-
tions. It is packaged in a 16-pin 0.3" wide plastic DIP.
The DAC7801 has a 2-byte (8 + 4) double-buffered interface.
Data is first loaded (level transferred) into the input registers
in two steps for each DAC. Then both DACs are updated
simultaneously. The DAC7801 features an asynchronous
CLEAR control. The DAC7801 is packaged in a 24-pin 0.3"
wide plastic DIP. The DAC7802 has a single-buffered 12-bit
data word interface. Parallel data is loaded (edge triggered)
into the single DAC register for each DAC. The DAC7802 is
packaged in a 24-pin 0.3" wide plastic DIP.
FEATURES
●TWO DACs IN A 0.3" WIDE PACKAGE
●SINGLE +5V SUPPLY
●HIGH-SPEED DIGITAL INTERFACE:
Serial—DAC7800
8 + 4-Bit Parallel—DAC7801
12-Bit Parallel—DAC7802
●MONOTONIC OVER TEMPERATURE
●LOW CROSSTALK: –94dB min
●FULLY SPECIFIED OVER –40OC TO +85OC
APPLICATIONS
●PROCESS CONTROL OUTPUTS
●ATE PIN ELECTRONICS LEVEL SETTING
●PROGRAMMABLE FILTERS
●PROGRAMMABLE GAIN CIRCUITS
●AUTO-CALIBRATION CIRCUITS
Dual Monolithic CMOS 12-Bit Multiplying
DIGITAL-TO-ANALOG CONVERTERS
Serial Interface
8-Bit Interface
8 Bits + 4 Bits
Serial
DAC7801
DAC7800
12-Bit MDAC
DAC A
FB B
I
OUT B
CLR
WR
A0
CS
A1
UPD
UPD A
UPD B
CS
CLK
CLR
12-Bit MDAC
DAC B
R
12-Bit Interface
DAC7802
CSA
WR
12
8
CSB
12
12 AGND B
REF B
V
FB A
I
OUT A
R
AGND A
REF A
V
DAC7800
DAC7801
DAC7802
SBAS005B – JANUARY 1990 – REVISED FEBRUARY 2004
www.ti.com
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright © 1990-2004, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
DAC7800, 7801, 7802
2SBAS005A
www.ti.com
SPECIFIED
RELATIVE GAIN PACKAGE TEMPERATURE PACKAGE ORDERING TRANSPORT
PRODUCT ACCURACY ERROR PACKAGE-LEAD DESIGNATOR(1) RANGE MARKING NUMBER MEDIA, QUANTITY
DAC7800KP ±1LSB ±3LSB DIP-16 N –40°C to +85°C DAC7800KP DAC7800KP Rails, 25
DAC7800LP ±1/2 LSB ±1LSB DIP-16 N DAC7800LP DAC7800LP Rails, 25
DAC7800KU ——SO-16 DW –40°C to +85°C DAC7800KU DAC7800KU/1K Tape and Reel, 1000
DAC7800LU ——SO-16 DW DAC7800LU DAC7800LU/1K Tape and Reel, 1000
DAC7801KP ±1LSB ±3LSB DIP-24 NTG –40°C to +85°C DAC7801KP DAC7801KP Rails, 15
DAC7801LP ±1/2 LSB ±1LSB DIP-24 NTG DAC7801LP DAC7801LP Rails, 15
DAC7801KU ——SO-24 DW –40°C to +85°C DAC7801KU DAC7801KU/1K Tape and Reel, 1000
DAC7801LU ——SO-24 DW DAC7801LU DAC7801LU/1K Tape and Reel, 1000
DAC7802KP ±1LSB ±3LSB DIP-24 NTG –40°C to +85°C DAC7802KP DAC7802KP Rails, 15
DAC7802LP ±1/2 LSB ±1LSB DIP-24 NTG DAC7802LP DAC7802LP Rails, 15
DAC7802KU ——SO-24 DW –40°C to +85°C DAC7802KU DAC7802KU/1K Tape and Reel, 1000
DAC7802LU ——SO-24 DW DAC7802LU DAC7802LU/1K Tape and Reel, 1000
NOTE: (1 ) For the most current specifications and package information, see the package option addendum located at the end of this data sheet.
ELECTRICAL CHARACTERISTICS
At VDD = +5VDC, VREF A = VREF B = +10V, TA = –40°C to +85°C, unless otherwise noted.
DAC7800, 7801, 7802K DAC7800, 7801, 7802L
PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS
ACCURACY
Resolution 12 ✻Bits
Relative Accuracy ±1±1/2 LSB
Differential Nonlinearity ±1✻LSB
Gain Error Measured Using RFB A and RFB B.±3±1 LSB
All Registers Loaded with All 1s.
Gain Temperature Coefficient(1) 25 ✻✻ppm/°C
Output Leakage Current TA = +25°C 0.005 10 ✻✻ nA
TA = –40°C to +85°C 3 150 ✻✻ nA
REFERENCE INPUT
Input Resistance 6 10 14 ✻✻✻ kΩ
Input Resistance Match 0.5 3 ✻2%
DIGITAL INPUTS
VIH (Input HIGH Voltage) 2 ✻V
VIL (Input LOW Voltage) 0.8 ✻V
IIN (Input Current) TA = +25°C±1✻µA
TA = –40°C to +85°C±10 ✻µA
CIN (Input Capacitance) 0.8 10 ✻✻ pF
POWER SUPPLY
VDD 4.5 5.5 ✻✻V
IDD 0.2 2 ✻✻ mA
Power-Supply Rejection VDD from 4.5V to 5.5V 0.002 ✻%/%
✻ Same specification as for DAC7800, 7801, 7802K.
VDD to AGND ...............................................................................0V, +7V
VDD to DGND...............................................................................0V, +7V
AGND to DGND ....................................................................... –0.3, VDD
Digital Input to DGND .....................................................–0.3, VDD + 0.3
VREF A, VREF B to AGND .................................................................. ±16V
VREF A, VREF B to DGND .................................................................. ±16V
IOUT A, IOUT B to AGND ............................................................. –0.3, VDD
Storage Temperature Range ....................................... –55°C to +125°C
Operating Temperature Range ...................................... –40°C to +85°C
Lead Temperature (soldering, 10s)..............................................+300°C
Junction Temperature...................................................................+175°C
NOTE: (1) Stresses above those listed under “Absolute Maximum Ratings”
may cause permanent damage to the device. Exposure to absolute maximum
conditions for extended periods may affect device reliaiblity.
ABSOLUTE MAXIMUM RATINGS(1)
At TA = +25°C, unless otherwise noted. ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Texas Instru-
ments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
PACKAGE/ORDERING INFORMATION
DAC7800, 7801, 7802 3
SBAS005A www.ti.com
AC PERFORMANCE
OUTPUT OP AMP IS OPA602.
At VDD = +5VDC, VREF A = VREF B = +10V, TA = +25°C, unless otherwise noted. These specifications are fully characterized but not subject to test.
NOTE: (1) Ensured but not tested.
DAC7800, 7801, 7802K DAC7800, 7801, 7802L
PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS
OUTPUT CURRENT SETTLING TIME To 0.01% of Full-Scale 0.4 0.8 ✻✻ µs
RL = 100Ω, CL = 13pF
DIGITAL-TO-ANALOG GLITCH IMPULSE VREF A = VREF B = 0V 0.9 ✻nV-s
RL = 100Ω, CL = 13pF
AC FEEDTHROUGH fVREF = 10kHz –75 –72 ✻✻ dB
OUTPUT CAPACITANCE DAC Loaded with All 0s 30 50 ✻✻ pF
DAC Loaded with All 1s 70 100 ✻✻ pF
CHANNEL-TO-CHANNEL ISOLATION
VREF A to IOUT B fVREF A = 10kHz –90 –94 ✻✻ dB
VREF B = 0V,
Both DACs Loaded with 1s
VREF B to IOUT A fVREF B = 10kHz –90 –101 ✻✻ dB
VREF A = 0V,
Both DACs Loaded with 1s
DIGITAL CROSSTALK Full-Scale Transition 0.9 ✻nV-s
RL = 100Ω, CL = 13pF
✻ Same specification as for DAC7800, 7801, and 7802K.
DAC7800
BLOCK DIAGRAM
DAC A
DAC B
DAC A Register
12
12
12 UPD B
I
AGND B
R
V
V
R
I
AGND A
UPD A
OUT B
FB B
REF B
REF A
FB A
OUT A
12
VDD
9
DGND
10
15
16
14
13
4
3
2
1
6
DAC B Register
Bit 0
Bit 11
Bit 12
Bit 23
Control Logic and Shift Register
711
CLR
12
DAC7800
Data
In
5
CLK
8
CS
PIN CONFIGURATION
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
AGND A
CLK
UPD A
Data In
CS
AGND B
I
R
V
V
CLR
UPD B
DGND
OUT A
FB A
REF A
OUT B
DAC7800
I
R
V
FB B
REF B
DD
CLK UPD A UPD B CS CLR FUNCTION
XXXX0All register contents set to 0’s (asynchronous).
X X X 1 X No data transfer.
X X 0 1 Input data is clocked into input register (location Bit 23) and previous data shifts.
X0101Input register bits 23 (LSB) - 12 (MSB) are loaded into DAC A.
X1001Input register bits 11 (LSB) - 0 (MSB) are loaded into DAC B.
X0001Input register bits 23 (LSB) - 12 (MSB) are loaded into DAC A, and input register bits 11 (LSB) - 0 (MSB)
are loaded into DAC B.
X = Don’t care. means falling edge triggered.
LOGIC TRUTH TABLE
Top View DIP
DAC7800, 7801, 7802
4SBAS005A
www.ti.com
DATA
CS
CLK t
1
t
5
UPD A
UPD B
t
3
t
7
CLR
t
6
t
8
t
4
0V
5V
5V
5V
5V
0V
NOTES: (1) All input signal rise and fall times are measured from 10% to 90% of +5V. t = t = 5ns.
(2) Timing measurement reference level is V + V
2
FR
IH IL
.
t
2
PARAMETER
MINIMUM
t1 — Data Setup Time 15ns
t2 — Data Hold Time 15ns
t3 — Chip Select to CLK, 15ns
Update, Data Setup Time
t4 — Chip Select to CLK, 40ns
Update, Data Hold Time
t5 — CLK Pulse Width 40ns
t6 — Clear Pulse Width 40ns
t7 — Update Pulse Width 40ns
t8 — CLK Edge to UPD A 15ns
or UPD B
TIMING CHARACTERISTICS
VDD = +5V, VREF A = VREF B = +10V, TA = –40°C to +85°C.
Data In
Bit 0 Bit 23Bit 22Bit 21Bit 20Bit 19Bit 18Bit 17Bit 16Bit 15Bit 14Bit 13Bit 12Bit 11Bit 10Bit 9Bit 8Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1
LSB
DAC A
MSB
DAC A
LSB
DAC B
MSB
DAC B
DAC7800 Data Input Sequence
DAC7800 Digital Interface Block Diagram
24-Bit
Shift Register
DAC A Register
UPD A
Data In
CLK
UPD B
LSB MSB DAC B Register
LSB MSB
Bit
23 Bit
12 Bit
11 Bit
0
CLK
DATA INPUT FORMAT
DAC7800 (Cont.)
DAC7800, 7801, 7802 5
SBAS005A www.ti.com
LOGIC TRUTH TABLE
BLOCK DIAGRAM PIN CONFIGURATION
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
AGND A
CS
DB0
DB1
DB2
DB3
DB4
DB5
DGND
AGND B
I
R
V
V
UPD
WR
CLR
A1
A0
DB7
DB6
OUT A
FB A
REF A
FB B
REF B
DD
OUT B
DAC7801
I
R
V
DAC7801
CLR UPD CS WR A1 A0 FUNCTION
1 1 1 X X X No Data Transfer
1 1 X 1 X X No Data Transfer
0 X X X X X All Registers Cleared
1 1 0 0 0 0 DAC A LS Input Register Loaded with DB7 - DB0 (LSB)
1 1 0 0 0 1 DAC A MS Input Register Loaded with DB3 (MSB) - DB0
1 1 0 0 1 0 DAC B LS Input Register Loaded with DB7 - DB0 (LSB)
1 1 0 0 1 1 DAC B MS Input Register Loaded with DB3 (MSB) - DB0
1 0 1 0 X X DAC A, DAC B Registers Updated Simultaneously from Input Registers
1 0 0 0 X X DAC A, DAC B Registers are Transparent
X = Don’t care.
TIMING CHARACTERISTICS
VDD = +5V, VREF A = VREF B = +10V, TA = –40°C to +85°C.
PARAMETER MINIMUM
t1 — Address Valid to Write Setup Time 10ns
t2 — Address Valid to Write Hold Time 10ns
t3 — Data Setup Time 30ns
t4 — Data Hold Time 10ns
t5 — Chip Select or Update to Write Setup Time 0ns
t6 — Chip Select or Update to Write Hold Time 0ns
t7 — Write Pulse Width 40ns
t8 — Clear Pulse Width 40ns
A0–A1
CLR
t
2
t
1
t
8
WR
t
7
CS, UPD
t
6
t
4
t
3
DATA
t
5
5V
0V
5V
0V
5V
0V
5V
0V
5V
0V
NOTES: (1) All input signal rise and fall times are measured from 10% to 90%
of +5V. t
R
= t
F
= 5ns. (2) Timing measurement reference level is .
V
IH
+ V
IL
2
DAC A
I
AGND A
R
V
V
R
I
AGND B
OUT A
FB A
REF A
REF B
FB B
OUT B
20
VDD
2
1
3
4
21
22
23
24
DAC A Register
48
DAC A
LS
Input
Reg
DAC A
MS
Input
Reg
Control Logic
DAC B
DAC B Register
48
12
DGND
DAC B
LS
Input
Reg
DAC B
MS
Input
Reg
19
16
15
5
18
17
UPD
A1
A0
CS
WR
CLR
DAC7801
14 6
DB7–DB0
12
12
Top View DIP
DAC7800, 7801, 7802
6SBAS005A
www.ti.com
BLOCK DIAGRAM
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
AGND
I
R
V
CS A
(LSB) DB0
DB1
DB2
DB3
DB4
DB5
DGND
I
R
V
V
CS B
WR
DB11 (MSB)
DB10
DB9
DB8
DB7
DB6
OUT A
FB A
REF A
FB B
REF B
DD
OUT B
DAC7802
TIMING CHARACTERISTICS
At VDD = +5V, and TA = –40oC to +85oC.
PARAMETER MINIMUM
t1 - Data Setup Time 20ns
t2 - Data Hold Time 15ns
t3 - Chip Select to Write Setup Time 30ns
t4 - Chip Select to Write Hold Time 0ns
t5 - Write Pulse Width 30ns
LOGIC TRUTH TABLE
CSA CSB WR FUNCTION
X X 1 No Data Transfer
1 1 X No Data Transfer
0 A Rising Edge on CSA or CSB Loads
Data to the Respective DAC
01 DAC A Register Loaded from Data Bus
10 DAC B Register Loaded from Data Bus
00 DAC A and DAC B Registers Loaded
from Data Bus
X = Don’t care. means rising edge triggered.
PIN CONFIGURATION
DAC7802
DATA 5V
0V
5V
5V
CSA, CSB
WR
t
2
t
1
t
3
t
4
t
5
NOTES: (1) All input signal rise and fall times are measured from 10%
to 90% of +5V. t
R
= t
R
= 5ns. (2) Timing measurement reference level
is V
IH
+ V
IL
2.
CK
DAC B
DAC A
12
12
12
12
12
DGND
18
CS A 5
CS B 20
WR 19
21
V
DD
DAC7802
6
2 I
3 R
OUT A
FB A
23 R
24 I
1 AGND
FB B
OUT B
DAC A Register
CK DAC B Register
DB11–DB0
4
22
V
V
REF A
REF B
Top View DIP
DAC7800, 7801, 7802 7
SBAS005A www.ti.com
TYPICAL CHARACTERISTICS
OUTPUT OP AMP IS OPA602.
TA = +25°C, VDD = +5V.
Output Leakage Current (A)
OUTPUT LEAKAGE CURRENT
vs TEMPERATURE
1µ
100n
10n
1n
100p
10p
1p–75 –50 –25 0 +25 +50 +75 +100 +125
Temperature (°C)
–60
–65
–70
–75
–80
–85
–90
–95
–100
THD + Noise (dB)
THD + NOISE vs FREQUENCY
Frequency (Hz)
1k10 100 10k 100k
1Vrms
3Vrms
6Vrms
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
Crosstalk (dB)
CHANNEL-TO-CHANNEL ISOLATION
vs FREQUENCY
Frequency (Hz)
100k1k 10k 1M 10M
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
Feedthrough (dB)
FEEDTHROUGH vs FREQUENCY
Frequency (Hz)
100k1k 10k 1M 10M
+30
+20
+10
0
–10
–20
–30
–40
–50
Gain (dB)
FREQUENCY RESPONSE
Frequency (Hz)
100k1k 10k 1M 10M
CF= 5pF
CF= 10pF
CF= 0pF
Frequency (Hz)
PSRR (dB)
PSRR vs FREQUENCY
70
60
50
40
30
20
10
0
–10 1k 10k 100k 1M
DAC Loaded w/0s
DAC Loaded w/1s
DAC7800, 7801, 7802
8SBAS005A
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DISCUSSION OF
SPECIFICATIONS
RELATIVE ACCURACY
This term, also known as end point linearity or integral
linearity, describes the transfer function of analog output to
digital input code. Relative accuracy describes the deviation
from a straight line, after zero and full-scale errors have been
adjusted to zero.
DIFFERENTIAL NONLINEARITY
Differential nonlinearity is the deviation from an ideal 1LSB
change in the output when the input code changes by 1LSB.
A differential nonlinearity specification of 1LSB maximum
ensures monotonicity.
GAIN ERROR
Gain error is the difference between the full-scale DAC output
and the ideal value. The ideal full scale output value for the
DAC780x is –(4095/4096)VREF. Gain error may be adjusted
to zero using external trims, see Figures 5 and 7.
OUTPUT LEAKAGE CURRENT
The current which appears at IOUT A and IOUT B with the DAC
loaded with all zeros.
OUTPUT CAPACITANCE
The parasitic capacitance measured from IOUT A or IOUT B to
AGND.
CHANNEL-TO-CHANNEL ISOLATION
The AC output error due to capacitive coupling from DAC A
to DAC B or DAC B to DAC A.
MULTIPLYING FEEDTHROUGH ERROR
The AC output error due to capacitive coupling from VREF to
IOUT with the DAC loaded with all zeros.
OUTPUT CURRENT SETTLING TIME
The time required for the output current to settle to within
+0.01% of final value for a full-scale step.
DIGITAL-TO-ANALOG GLITCH ENERGY
The integrated area of the glitch pulse measured in nanovolt-
seconds. The key contributor to DAC glitch is charge injected
by digital logic switching transients.
DIGITAL CROSSTALK
Glitch impulse measured at the output of one DAC but caused
by a full-scale transition on the other DAC. The integrated
area of the glitch pulse is measured in nanovolt-seconds.
CIRCUIT DESCRIPTION
Figure 1 shows a simplified schematic of one half of a DAC780x.
The current from the VREF A pin is switched between IOUT A and
AGND by 12 single-pole double-throw CMOS switches. This
maintains a constant current in each leg of the ladder regard-
less of the input code. The input resistance at VREF is therefore
A CMOS switch transistor, included in series with the ladder
terminating resistor and in series with the feedback resistor,
RFB A, compensates for the temperature drift of the ON resis-
tance of the ladder switches.
Figure 2 shows an equivalent circuit for DAC A. COUT is the
output capacitance due to the N-channel switches and varies
from about 30pF to 70pF with digital input code. The current
source ILKG is the combination of surface and junction leak-
ages to the substrate. ILKG approximately doubles every 10°C.
RO is the equivalent output resistance of the DAC and it varies
with input code.
constant and can be driven by either a voltage or current, AC
or DC, positive or negative polarity, and have a voltage range
up to ±20V.
OUT A
I
AGND
FB A
R
2R
2R2R2R2R
RRR
VREF A
DB11
(MSB) DB10 DB9 DB0
(LSB)
R
FIGURE 1. Simplified Circuit Diagram for DAC A.
FIGURE 2. Equivalent Circuit for DAC A.
FB A
R
OUT A
I
VREF A
ILKG
ROUT
C
O
R
AGND A
DIN
4096 xVREF
R
R
INSTALLATION
ESD PROTECTION
All digital inputs of the DAC780x incorporate on-chip ESD
protection circuitry. This protection is designed to withstand
2.5kV (using the Human Body Model, 100pF and 1500Ω).
However, industry standard ESD protection methods should
be used when handling or storing these components. When
not in use, devices should be stored in conductive foam or
rails. The foam or rails should be discharged to the destina-
tion socket potential before devices are removed.
POWER-SUPPLY CONNECTIONS
The DAC780x are designed to operate on VDD = +5V +10%.
For optimum performance and noise rejection, power-supply
decoupling capacitors CD should be added as shown in the
application circuits. These capacitors (1µF tantalum recom-
mended) should be located close to the DAC. AGND and
DAC7800, 7801, 7802 9
SBAS005A www.ti.com
DGND should be connected together at one point only,
preferably at the power-supply ground point. Separate re-
turns minimize current flow in low-level signal paths if properly
connected. Output op amp analog common (+ input) should
be connected as near to the AGND pins of the DAC780x as
possible.
WIRING PRECAUTIONS
To minimize AC feedthrough when designing a PC board,
care should be taken to minimize capacitive coupling be-
tween the VREF lines and the IOUT lines. Similarly, capacitive
coupling between DACs may compromise the channel-to-
channel isolation. Coupling from any of the digital control or
data lines might degrade the glitch and digital crosstalk
performance. Solder the DAC780x directly into the PC board
without a socket. Sockets add parasitic capacitance (which
can degrade AC performance).
AMPLIFIER OFFSET VOLTAGE
The output amplifier used with the DAC780x should have low
input offset voltage to preserve the transfer function linearity.
The voltage output of the amplifier has an error component
which is the offset voltage of the op amp multiplied by
the “noise gain” of the circuit. This “noise gain” is equal to
(RF/RO + 1) where RO is the output impedance of the DAC
IOUT terminal and RF is the feedback network impedance. The
nonlinearity occurs due to the output impedance varying with
code. If the 0 code case is excluded (where RO = infinity), the
RO will vary from R-3R providing a “noise gain” variation
between 4/3 and 2. In addition, the variation of RO is nonlinear
with code, and the largest steps in RO occur at major code
transitions where the worst differential nonlinearity is also
likely to be experienced. The nonlinearity seen at the amplifier
output is 2VOS – 4VOS/3 = 2VOS/3. Thus, to maintain good
nonlinearity the op amp offset should be much less than
1/2 LSB.
UNIPOLAR CONFIGURATION
Figure 3 shows DAC780x in a typical unipolar (two-quadrant)
multiplying configuration. The analog output values versus
digital input code are listed in Table II. The operational
amplifiers used in this circuit can be single amplifiers such as
the OPA602, or a dual amplifier such as the OPA2107. C1
and C2 provide phase compensation to minimize settling time
and overshoot when using a high speed operational amplifier.
If an application requires the DAC to have zero gain error, the
circuit shown in Figure 4 may be used. Resistors R2 and R4
induce a positive gain error greater than worst-case initial
negative gain error. Trim resistors R1 and R3 provide a
variable negative gain error and have sufficient trim range to
correct for the worst-case initial positive gain error plus the
error produced by R2 and R4.
BIPOLAR CONFIGURATION
See Figure 5 for the DAC780x in a typical bipolar (four-
quadrant) multiplying configuration. See Table III for the
listing of the analog output values versus digital input code.
DATA INPUT ANALOG OUTPUT
MSB ↓↓ LSB
1111 1111 1111 –VREF (4095/4096)
1000 0000 0000 –VREF (2048/4096) = –1/2VREF
0000 0000 0001 –VREF (1/4096)
0000 0000 0000 0 Volts
TABLE II. Unipolar Output Code.
The operational amplifiers used in this circuit can be single
amplifiers such as the OPA602, a dual amplifier such as the
OPA2107, or a quad amplifier like the OPA404. C1 and C2
provide phase compensation to minimize settling time and
overshoot when using a high speed operational amplifier. The
bipolar offset resistors R5–R7 and R8–R10 should be ratio-
matched to 0.01% to ensure the specified gain error perfor-
mance.
DAC A
IOUT A
DAC B
AGND A
IOUT B
RFB B
RFB A
C1
10pF
C2
10pF
DAC780X
VOUT A
VOUT B
–
+
–
+
A1
A2
DGND VREF B
VREF A
VDD
+5V
CD
A1, A2 OPA602 or 1/2 OPA2107.
DAC7802 has a single analog
common, AGND.
+
1µF
AGND B
R
100
3
Ω
REF B
R
2
Ω
47
R
4
Ω
47
DAC A
I
OUT A
DAC B
AGND A
I
OUT B
R
FB B
R
FB A
C1 10pF
C2 10pF
DAC780X
V
OUT A
V
OUT B
–
+
–
+
A1
A2
DGND
V
DD
+5V
C
D
A1, A2 OPA602 or 1/2 OPA2107.
DAC7802 has a single analog
common, AGND.
+
1µF
AGND B
V
IN A
R
100
1
Ω
REF A
V
V
IN B
V
FIGURE 4. Unipolar Configuration with Gain Trim.
FIGURE 3. Unipolar Configuration.
DAC7800, 7801, 7802
10 SBAS005A
www.ti.com
If an application requires the DAC to have zero gain error, the
circuit may be used, see Figure 6. Resistors R2 and R4 induce
a positive gain error greater than worst-case initial negative
gain error. Trim resistors R1 and R3 provide a variable
negative gain error and have sufficient trim range to correct
for the worst-case initial positive gain error plus the error
produced by R2 and R4.
DATA INPUT ANALOG OUTPUT
MSB ↓↓ LSB
1111 1111 1111 +VREF (2047/2048)
1000 0000 0001 +VREF (1/2048)
1000 0000 0000 0 Volts
0111 1111 1111 –VREF (1/2048)
0000 0000 0000 –VREF (2048/2048)
TABLE III. Bipolar Output Code.
FIGURE 5. Bipolar Configuration.
R3
10k
1
C
10pF
DAC A
DAC B
R
10k
5Ω
DAC780X
DGND
VREF A
VDD
+5V
CD
2
R6Ω
20k
R2Ω
20k
R
10k
C
10pF
VOUT A
VOUT B
A1
A3
DAC7802 has a single analog common, AGND.
A1–A4, OPA602 or 1/2 OPA2107.
–
+
A2
–
+
A4
5
Ω
Ω
R1Ω
20k
R4Ω
20k
REF B
V
IOUT B
RFB B
–
+
AGND B
IOUT A
RFB A
–
+
AGND A
1µF
+
APPLICATIONS
12-BIT PLUS SIGN DACS
For a bipolar DAC with 13 bits of resolution, two solutions are
possible. The addition of a precision difference amplifier and
a high speed JFET switch provides a 12-bit plus sign voltage-
output DAC, see Figure 7. When the switch selects the op
amp output, the difference amplifier serves as a noninverting
output buffer. If the analog ground side of the switch is
selected, the output of the difference amplifier is inverted.
Another option, see Figure 8, also produces a 12-bit plus sign
output without the additional switch and digital control line.
DIGITALLY PROGRAMMABLE ACTIVE FILTER
See Figure 9 for the DAC780x in a digitally programmable
active filter application. The design is based on the state-
variable filter, Texas Instruments UAF42, an active filter topol-
ogy that offers stable and repeatable filter characteristics.
DAC1 and DAC2 can be updated in parallel with a single word
to set the center frequency of the filter. DAC 4, which makes
use of the uncommitted op amp in UAF42, sets the Q of the
filter. DAC3 sets the gain of the filter transfer function without
changing the Q of the filter. The reverse is also true.
The center frequency is determined by fC = 1/2πRC where R is
the ladder resistance of the DAC (typical value, 10kΩ) and C
the internal capacitor value (1000pF) of the UAF42. External
capacitors can be added to lower the center frequency of the
filter. But the highest center frequency for this circuit will be
about 16kHz because the effective series resistance of the
DAC cannot be less than 10kΩ.
Note that the ladder resistance of the DAC may vary from
device to device. Thus, for best tracking, DAC2 and DAC3
should be in the same package. Some calibration may be
necessary from one filter to another.
DAC7800, 7801, 7802 11
SBAS005A www.ti.com
FIGURE 6. Bipolar Configuration with Gain Trim.
R
100
1
R
7
10k
1
C
10pF
DAC A
DAC B
R
10kΩ
DAC7802
DGND
V
IN A
V
DD
+5V
C
D
2
R
10
Ω
20k
R
6
Ω
20k
R
10k
C
10pF
V
OUT A
V
OUT B
A1
A3
DAC7802 has a single analog common, AGND.
A1–A4, OPA602 or 1/2 OPA2107.
–
+
A2
–
+
A4
9
Ω
Ω
R
5
Ω
20k
R
8
Ω
20k
V
I
OUT B
R
FB B
–
+
AGND B
I
OUT A
R
FB A
–
+
AGND A
Ω
R
100
3
Ω
R
2
Ω
47
R
4
Ω
47
IN B
+
1µF V
REF A
V
REF B
FIGURE 7. 12-Bit Plus Sign DAC.
1
C
10pF
I
OUT A
DAC A
DAC B
R
FB A
DAC780X
DGND
V
DD
+5V
C
D
A1
DAC7802 has a single analog common, AGND.
A1 OPA602 or 1/2 OPA2107.
INA105
DG188
Sign Control
REF102
±10V
13 Bits
V
REF B
+15V
V
REF A
R
R
R
R
AGND B
+10V
AGND A
2
4
6
1µF
2
3
1
6
DAC7800, 7801, 7802
12 SBAS005A
www.ti.com
FIGURE 8. 13-Bit Bipolar DAC.
1
C
10pF
I
OUT A
DAC A
DAC B
R
FB A
DAC780X
DGND
V
DD
+5V
A1
DAC7802 has a single analog common, AGND.
A1 OPA602 or 1/2 OPA2107.
REF102
±10V
13 Bits
V
REF B
+15V
V
REF A
R
R
R
AGND B
AGND A
+10V
I
OUT B
R
FB B
2
C
10pF
A2
R
C
D
INA105
2
4
6
1µF
2
36
1
V
REF 2
DAC 2
DAC 1
DAC 3
Gain Adjust
Filter Input
V
REF 3
I
OUT 3
AGND 3
High-Pass Out Band-Pass
Out
Low-Pass
Out
UAF 42
C
C
RR
R
R
DAC780X
V
REF 1
I
OUT 1
AGND 1
I
OUT 2
AGND 2 DAC 4
Q Adjust
V
REF 4
I
OUT 4
AGND 4
R
FB 4
C
Adjustf
R = 50k
C = 1000pF ±0.5%
Ω±0.5%
1/2 DAC780X
1/2 DAC780X
15
13
12
3
14
7
211
8
4
6
FIGURE 9. Digitally Programmable Universal Active Filter.
PACKAGE OPTION ADDENDUM
www.ti.com 16-Aug-2012
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
DAC7800KP NRND PDIP N 16 25 Green (RoHS
& no Sb/Br) CU NIPDAU N / A for Pkg Type
DAC7800KPG4 NRND PDIP N 16 25 Green (RoHS
& no Sb/Br) CU NIPDAU N / A for Pkg Type
DAC7800KU ACTIVE SOIC DW 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
DAC7800KU/1K ACTIVE SOIC DW 16 1000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
DAC7800KU/1KG4 ACTIVE SOIC DW 16 1000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
DAC7800KUG4 ACTIVE SOIC DW 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
DAC7800LP NRND PDIP N 16 25 Green (RoHS
& no Sb/Br) CU NIPDAU N / A for Pkg Type
DAC7800LPG4 NRND PDIP N 16 25 Green (RoHS
& no Sb/Br) CU NIPDAU N / A for Pkg Type
DAC7800LU NRND SOIC DW 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
DAC7800LU/1K OBSOLETE SOIC DW 16 TBD Call TI Call TI
DAC7800LUG4 NRND SOIC DW 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
DAC7801KP NRND PDIP NT 24 15 Green (RoHS
& no Sb/Br) CU NIPDAU N / A for Pkg Type
DAC7801KPG4 NRND PDIP NT 24 15 Green (RoHS
& no Sb/Br) CU NIPDAU N / A for Pkg Type
DAC7801KU ACTIVE SOIC DW 24 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
DAC7801KU/1K ACTIVE SOIC DW 24 1000 TBD Call TI Call TI
DAC7801KU/1KG4 ACTIVE SOIC DW 24 1000 TBD Call TI Call TI
DAC7801KUG4 ACTIVE SOIC DW 24 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
DAC7801LP NRND PDIP NT 24 15 Green (RoHS
& no Sb/Br) CU NIPDAU N / A for Pkg Type
PACKAGE OPTION ADDENDUM
www.ti.com 16-Aug-2012
Addendum-Page 2
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
DAC7801LPG4 NRND PDIP NT 24 15 Green (RoHS
& no Sb/Br) CU NIPDAU N / A for Pkg Type
DAC7801LU ACTIVE SOIC DW 24 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
DAC7801LU/1K ACTIVE SOIC DW 24 TBD Call TI Call TI
DAC7801LU/1KG4 ACTIVE SOIC DW 24 TBD Call TI Call TI
DAC7801LUG4 ACTIVE SOIC DW 24 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
DAC7802KP NRND PDIP NTG 24 15 Green (RoHS
& no Sb/Br) CU NIPDAU N / A for Pkg Type
DAC7802KU ACTIVE SOIC DW 24 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
DAC7802KU/1K ACTIVE SOIC DW 24 1000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
DAC7802KU/1KG4 ACTIVE SOIC DW 24 1000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
DAC7802KUG4 ACTIVE SOIC DW 24 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
DAC7802LP NRND PDIP NTG 24 15 Green (RoHS
& no Sb/Br) CU NIPDAU N / A for Pkg Type
DAC7802LU ACTIVE SOIC DW 24 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
DAC7802LUG4 ACTIVE SOIC DW 24 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
PACKAGE OPTION ADDENDUM
www.ti.com 16-Aug-2012
Addendum-Page 3
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
DAC7800KU/1K SOIC DW 16 1000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1
DAC7802KU/1K SOIC DW 24 1000 330.0 24.4 10.75 15.7 2.7 12.0 24.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
DAC7800KU/1K SOIC DW 16 1000 367.0 367.0 38.0
DAC7802KU/1K SOIC DW 24 1000 367.0 367.0 45.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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