Intel® Atom™ Processor E6xx
Series
Specification Update
July 2014
Revision 017
Documen t Number: 3242 09 -017US
Intel® Atom™ Processor E6xx Series
Spec ific ation Update July 20 14
2 Document Number: 324209-017US
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Copyright © 2014, Intel Corporation. All rights reserved.
Intel® Atom™ Processor E6xx Series
July 20 14 Spec ific ation Update
Document Number: 324209-017US 3
Contents
Preface ..................................................................................................................................5
Summary Tables of Changes ....................................................................................................7
Iden tificati on Inf or m ation ...................................................................................................... 13
Errata ................................................................................................................................. 17
Specification Changes ........................................................................................................... 41
Specif ication Clarifications ..................................................................................................... 46
Documentation Changes ........................................................................................................ 49
Intel® Atom™ Processor E6xx Series
Spec ific ation Update July 20 14
4 Document Number: 324209-017US
Revision History
Date Revision Description
September 2010 001 Initial release.
December 2010 002 • Added errata BI41 and BI44 and Specification Changes 1 though 4
February 2011 003 • Added Specification Chang e 2, and Document Chang es 1 and 2
March 2011 004 • Added Specification Change 3, added section
April 2011 005 • Added Specification Changes 5, 7 and 8
• Correct ed T a ble Number 4 and Specification Chang e 2
• Document Changes 3 through 6, 11, 14, and 15
May 2011 006 • Removed Speci fication Chang es referri ng to Da t asheet Rev. 002 and TMDG Rev. 001
• Added Specification Changes 9 and 10
• Document Changes 17 through 27, and 29
June 2011 007 • Added column “Stepping “to Table 5 through 7
• Added erratum BI45 and BI46
• Specification Changes 11 through 13
• Document only changes 30 and 32
August 2011 008 • Removed Sp ecificati on Changes and Document Changes throug h Revisio n 007.
• Added errata BI48, BI49, BI50.
• Added Specification Change 1
• Specification Clarification 13,
• Document-Only Chang es 2 through 5.
November 2011 009 • Added erratum BI51
• Updated Table 10
February 2012 010 • Added Errata BI52, and BI53.
• Specific a tion Changes 2 through 4
• Documentation Chang es 7 and 8.
• Added B1 PRQ stepping to the Component Markings table.
April 2012 011 • Added Errata BI54 and BI55
May 2012 012 • Added Errata BI56
January 2013 013 • Added Errata BI57 and BI58
March 2013 014 • Added Errata BI59. Added Documentation Change 8
March 2013 015 • Out of cycle release to add Documentation Change 9.
May 2013 016 • Updated Erratum BI57.
July 2014 017 • Updated link to access Intel® 64 and IA-32 Architectures Software Developer’s Manual.
§
Preface
Intel® Atom™ Processor E6xx Series
July 20 14 Spec ific ation Update
Document Number: 324209-017US 5
Preface
This doc ument is an upda te to the specifica tions c ontaine d in the doc uments listed in
the following A ffected D ocum e nts/Re la ted Docu m ents table. It is a compilat ion of
device and document errata and specification clarifications and changes, and is
intended for hardware system manufacturers and for software developers of
application s, opera ting sys te m , and tools .
Information types d efined in the Nom enclatu r e s e c tion of this document a r e
consolid ated into this upda te document and a r e no longer publish ed in other
docume nts. T his document m a y also contain information that has not been pr eviously
published.
Related Documents
Document Title Document
Number/Location
Intel® 64 and IA-32 Architectures Software Developer’s
Manuals http://www.intel.com/conte
nt/www/us/en/processors/a
rchitectures-software-
developer-manuals.html
Intel® Atom™ Processor E6xx Series Datasheet http://download.intel.com/e
mbedded/processor/datashe
et/324208.pdf
Intel® Atom™ Processor E6xx Series Thermal and Mechanical
Design Guidelines
http://download.intel.com/e
mbedded/processors/therm
alguide/ 324 21 0.pdf
Nomenclature
Errata are design defects or err or s . Errata ma y c au se the Intel® Atom™ P r oc e s sor
E6xx Series’ be havior to deviate from pu blished specif ic ations. Ha r dware and sof tware
designed to be u s ed with any given stepping mu s t a s s ume that all erra ta doc umented
for that stepping are pres ent on a ll dev ices .
Speci ficat ion Chan ges are modifications to the current published s pec if ic atio ns.
These changes will be inc orporated in the next relea s e of the specifications.
Specification Clarifications describe a specif ic ation in greater de tail or f urther
highlig ht a spec ificat ion’s impact to a c omplex de s ig n situation. Thes e c larifica tions will
be incorporated in the next release of th e s pec ificati ons.
Docume nt a t ion Changes inclu d e typos, er r ors, or omiss ions from th e curre nt
published spec ificati ons. These c hanges will be incorporated in the nex t relea s e of the
specifications.
Preface
Intel® Atom™ Processor E6xx Series
Spec ific ation Update July 20 14
6 Document Number: 324209-017US
Note: Errata rem a in in th e specification u pd a te throughout the pr od uct’s lifecycle, or until a
particular stepping is no longer commercially available. Under these circumstances,
errata remov ed from the specification update ar e a r chiv ed a nd avai lable upon reques t.
Specification changes, specification clarifications and documentation changes are
removed fr om the specification update when th e a ppr opriate cha nges are made to th e
appropriate product specification or user doc umentation ( datash eets, ma nuals, etc.).
§
Summary Tables of Changes
Intel® Atom™ Processor E6xx Series
July 20 14 Spec ific ation Update
Document Number: 324209-017US 7
Summary Table s of Changes
The following table in d ic a tes th e Specification Cha nges, Errata, Specification
Clarificati ons or Doc umenta tion Ch a nges, wh ich apply to the listed MC H steppin gs.
Inte l intends to fix som e of the er r a ta in a fu ture stepping of th e c om p onent, a nd to
account for the other outstanding iss ues th r ough docum e ntation or Specific atio n
Cha nges as n oted . This table uses th e following notations:
Codes Used in Summary Table
Stepping
X: Erratum, S p ecification Ch an g e or Clarif ic ation that applies
to this ste pping.
(No mark) or (Blank Box): This erratum is fixed in listed stepping or s pe c ifica tion
chan ge does not apply to listed stepping.
Status
Doc: Documen t change or u pdate tha t w ill be implemen ted.
Plan Fix: This erratum may be f ix ed in a future s teppin g of the
product.
Fixed: This err a tu m has been previou s ly fixed.
No Fix: Ther e are no pla ns to fix this erra tum.
Row
Shaded: This item is either new or m od ified f r om the prev ious
version of th e d oc ument.
Summary Tables of Changes
Intel® Atom™ Processor E6xx Series
Spec ific ation Update July 20 14
8 Document Number: 324209-017US
Errata (Sheet 1 of 4)
Number Steppings Plans ERRATA
BI1 X X No Fix IO_SMI Indication in SMRAM State Save Area May Be Set Incor rec tly
BI2 X X No Fix Writes to IA32_DEBUGCTL MSR May Fail When FREEZE_LBRS_ON_PMI Set
BI3 X X No Fix Address Reported by Machine-Check Architecture (MCA) on L2 Cache Errors May Be
Incorrect
BI4 X X No Fix Pending x87 FPU Exceptions (#MF) Following STI May Be Ser viced before Hig he r
Priority Interrupts
BI5 X X No Fix Benign Exception After Double Fault May Not Cause Triple Fault Shutdown
BI6 X X No Fix IA32_MC1_STATUS MSR Bit [60] Does No t Reflect Machine Check Error R epo r ti n g
Enable Correctly
BI7 X X No Fix If Two Logical Processors Use Same CR3 Value but Configure APIC Virtualization
Differently, Either May Operate as if APIC Virtualization Were Disabled
BI8 X X No Fix VM Exit Due to Fault While Delivering Software Interrupt May Save Incorrect Data Into
VMCS
BI9 X X No Fix VM Exit Occurring in IA-32e Mode May Not Produce VMX Abort When Expected
BI10 X X No Fix Perform ance Moni toring Event for Outstandi ng B us Requests Ignores AnyThread Bi t
BI11 X X No Fix Thermal Interrup ts Dropped Duri ng and While Exiting Deep Power- Down State
BI12 X X No Fix Corruption of CS Segment Register Duri ng RSM While Transitioning From Real Mode to
Protected Mode
BI13 X X No Fix Perform ance Moni toring Counter With AnyThrea d Bit Set May Not Count on Non-Active
Thread
BI14 X X No Fix GP and Fixed Performance Monitoring Counters With AnyThread Bit Set May Not
Accurately Count Only OS or Only USR Events
BI15 X X No Fix PMI Requ es t Not G ener a t ed on Count er O verflow if Its OVF Bit Already Set in
IA32_PERF_GLOBAL_STATUS
BI16 X X No Fix Processor May Use Incorrect Translation if TLBs Contain Two Different Translations for
Linear Address
BI17 X X No Fix Write to AP IC Register Sometimes May Ap p ea r to Have Not Occurred
BI18 X X No Fix xTPR Update Transaction Cycle, if Enabled, May Be Issued to FSB After Processor
Issued Stop-Grant Special Cycle
BI19 X X No Fix Processor Ma y Report #TS Inste a d of #GP Fault
BI20 X X No Fix Writing Local Vector Tabl e (LVT) When Interrupt Pending May Cause Unexpected
Interrupt
BI21 X X No Fix MOV To/Fr om D eb ug Regi sters Causes Debug Exception
BI22 X X No Fix
Usin g 2M/4 M Pag es W h en A2 0M# Ass ert ed May Result i n Incorrect Addr ess Transla tions
BI23 X X No Fix Values for LBR/BTS/BTM Will Be Incorrect After Exit From SMM
Summary Tables of Changes
Intel® Atom™ Processor E6xx Series
July 20 14 Spec ific ation Update
Document Number: 324209-017US 9
Errata (Sheet 2 of 4)
Number Steppings Plans ERRATA
BI24 X X No Fix
Incorrect Addr ess Compute d f or Last Byte o f FXSAVE /FXRSTOR Image Leads
to Partial Me mory Upd ate
BI25 X X No Fix Therm al Inte rrupt Not Generated W he n Curre nt Temp era ture Invalid
BI26 X X No Fix Progr a mm ing Di g ital Therm al Sens or (DTS ) Thre s hold May Cause
Unexpected Thermal Interrupts
BI27 X X No Fix Returning to Real Mode From SMM With EFLAG S .V M Set May Res ult in
Unpredictable System Behavior
BI28 X X No Fix Fault o n ENT ER Ins truction May Result in Unexpec te d Val ue s on Stack Fr ame
BI29 X X No Fix With TF (Trap Flag) Asserted, FP Instruction That Triggers Unmasked FP
Excep tion May Take Single Step Trap Before Retirement of Instruction
BI30 X X No Fix Enabled Debug Breakpoint or Sing le S tep Trap May Be Taken After MOV
SS/POP SS Instr uc tion if Followed by Flo a ting Point Ex cep ti o n S ignaling
Instruction
BI31 X X No Fix Code Segment L
imit/Canonical Faults on RSM May Be Serviced Before Higher
Priority Interrupts/Exceptions and May Push Wrong Address Onto Stack
BI32 X X No Fix BTS (Branc h Trac e Store) and PEBS (Precise Event Ba s ed Sampling ) May
Update Memo r y Out si de BTS/PEBS Bu ffer
BI33 X X No Fix Single S tep Interrupts With Floating Point Excepti o n Pending May Be
Mishandled
BI34 X X No Fix Unsync hronized Cross-Modifying Code Operations Can Cause Unexpected
Instr uc tion Execution Results
BI35 X X No Fix LBR Stack May No t Be Frozen on PMI Req uest Whe n FREEZ E_LB RS _O N_PMI
Set
BI36 X X No Fix
PMI Request Not Gene r a ted on Counter Ov erflow if Its OVF Bit Already S e t in
IA32_PERF_GLOBAL_STATUS
BI37 X X No Fix Sync hro nous Reset of IA32_MPERF on IA32_ A PERF Ove rf low May Not Work
BI38 X Fixed Processor May Not Recognize Signal PWROK on Its Initial Assertion
BI39 X Fixed Image on SDVO Display Clip ped When Multiple Displ ay Pla nes and SDVO
Port Enab led
BI40 X X No Fix Larg e Amounts of LPC Bus Memory Re ads and Writes May Temp or arily
Starve Other I/O Devices
BI41 X X No Fix Delayed I/O Device Memory Transactions Can Cause System Hang
BI42 X Fixed Sof tware Can Inadvertently Change SDVO Base Class Code Register
BI43 X Fixed Voltage Supplied to Internal RTC Logic Violates Design Specification
BI44 X Fixed Flickering May be Observed on Display while Running Intensive Graphics and
Video Decoding Activities
BI45 X X No Fix C6 Reque s t May Cause a Machine Che ck if the Other Logic al Processor is in
C4 or C6
Summary Tables of Changes
Intel® Atom™ Processor E6xx Series
Spec ific ation Update July 20 14
10 Document Number: 324209-017US
Errata (Sheet 3 of 4)
Number Steppings Plans ERRATA
BI46 x X No Fix EOI Tr a ns actio n May No t be Sent if Softw are Ente rs Core C6 During an
Interrupt Service Routine
BI47 X X No Fix PCNT Thro ttling May Cause System Hang During TM1 Thermal Eve nt
BI48 X X No Fix VMX Transiti o ns May Set Bi ts 63 :32 of the IA32_F M ASK MSR
BI49 X X No Fix Writing the Local Vec tor Table (LVT) w he n an Interr up t is Pending May
Cause an Unexpected Interrupt
BI50 X X No Fix Clearing PCIe* Root Port' s BME Bit With Pend ing Upstream Traffic Will C a use
Inter na l Bus to Hang
BI51 X X No Fix CPUID Instruction Returns Incorrect Brand String
BI52 X No Fix The APIC Time r May Drift When Bus Ratios Less Than 6 Are Used
BI53 X X No Fix Extende d Tags Ar e Alway s Used But Not Repor ted on PCIe* Root Ports
BI54 X X No Fix Outbound MSI From The PMU Can Result in Live Lock And/or Sys tem Hang
When Simultaneously Occur ring With an Inbound I/O Read
BI55 x X No Fix SMBus Timing Violation
BI56 X X No Fix RTC Does No t Detect a Coin Cell Ba tte r y Low Vo ltage Condition
BI57 x X No Fix Comple x Conditions Asso c iated Wi th Ins truction Page Remapping or
Self/Cross-Modify ing Code Execution May Lead to Unpre dictable Sys te m
Behavior
BI58 No Fix REP MOVS/STOS Executing With Fast S tring s Enable d and Crossing Pa ge
Boundaries with Incons is te nt Memory Types May Use an Incorre c t Data Size
or Le a d to M e m ory-Ordering Violations
BI59 x x No Fix Paging S tructure Entry May be Used Before Acce s sed And Dir ty F lags Are
Updated
Summary Tables of Changes
Intel® Atom™ Processor E6xx Series
July 20 14 Spec ific ation Update
Document Number: 324209-017US 11
Specification Changes
No. Stepping Document Title Rev. Specification Changes
B0 B1
1 X X Intel® Atom™ Processor E6xx
Series
Thermal and Mechanical
Design
Guidelines 003 Heatsink Height Change
2 X X Intel® Atom™ Processor E6xx
Series
Datasheet 004 C hang e d VCC3 3R TC Spe c ific ation in
“Oper ating Condition Powe r Supp ly and
Reference DC Characteristics ” Tab le
3 X Intel® Atom™ Processor E6xx
Series
Datasheet 004 C hang e d VCCR TC E X T Specification fro m
“Oper ating Condition Powe r Supp ly and
Reference DC Characteristics” Table
4 X X Intel® Atom™ Processor E6xx
Series
Datasheet 004 C hang e d VI H and VIL Specif i cations fo r
RTCRST#, PWROK, and RSMRST# in
“Activ e Si g nal DC Charac ter is tic s ” T able
Specification Clarifications
No. Stepping Document Title Rev. Specification Clarifications
B0 B1
1 X X Intel® Atom™ Processor E6xx
Series
Datasheet 003 A d d Info rmation Related to Memory -
Mapped Accesses
Document Changes (Sheet 1 of 2)
No. Stepping Document Title Rev. Document-Only Changes
B0 B1
1. X X Intel® Atom™ Processor E6xx Series
Datasheet 003
2. X X Intel® Atom™ Processor E6xx Series
Datasheet 003 Missing 06 h (Hos t Data 0 ) Register
Description for SMBus Contr o ller
3. X X Intel® Atom™ Processor E6xx Series
Datasheet 003 Missing 07 h (HoD esc riptio n for SMBus
Controllerst Data1) Register
4. X X Intel® Atom™ Processor E6xx Series
Datasheet 003 Changi ng BAR1 to WDTBA for
WatchDog Timer Base Address
Variable.
5. X X Intel® Atom™ Processor E6xx Series
Datasheet 003 Added VIH, VIL and ILEAK Specification
and Remove VOH and
IOH Specific a tio n
to CMOS 1. 05 Open Drain
Summary Tables of Changes
Intel® Atom™ Processor E6xx Series
Spec ific ation Update July 20 14
12 Document Number: 324209-017US
Document Changes (Sheet 2 of 2)
No. Stepping Document Title Rev. Document-Only Changes
B0 B1
6. X Intel® Atom™ Processor E6xx Series
Datasheet 003 Updated GVD.FD Register Bit 0
Description
7. X X Intel® Atom™ Processor E6xx Series
Datasheet 003 Upd ated Note Tex t in the Operating
Conditi o n Pow er Supply and
Reference DC Cha ract eristics Tabl e
8. X Intel® Atom™ Processor E6xx Series
Datasheet 003 Corrected Bus 0, Device 3 PCI
Configuration Register Default
9. X Intel® Atom™ Processor E6xx Series
Datasheet 003
Update to Specification Change 4.
Updated Note s for “Op er ating
Condition
Power Supply and Referen ce DC
Charac teris tic s ” Table
§
Identifica tio n Informatio n
Intel® Atom™ Processor E6xx Series
July 20 14 Spec ific ation Update
Document Number: 324209-017US 13
Identification Information
Component Identification Using Programming Interface
The Intel® Atom™ Processor E6xx Series stepp ing can be iden tif ied by the following
register contents:
Part Number Stepping CPUID Vendor
ID
1
Device ID2
Rev
Number
3
Intel® Atom™ Processor E620 0.6
GHz (Commercial Temperature)
B0 0020661h 8086 4115 01
Intel® Atom™ Processor E620T
0.6 GHz (Extended Temperature)
B0 0020661h 8086 4115 01
Intel® Atom™ Processor E640
1.0 GHz (Commercial Temperature)
B0 0020661h 8086 4114 01
Intel® Atom™ Processor E640T
1.0 GHz (Extended Temperature)
B0 0020661h 8086 4114 01
Intel® Atom™ Processor E660
1.3 GHz (Commercial Temperature)
B0 0020661h 8086 4114 01
Intel® Atom™ Processor E660T
1.3 GHz (Industrial Temperature)
B0 0020661h 8086 4114 01
Intel® Atom™ Processor E680
1.6 GHz (Commercial Temperature)
B0 0020661h 8086 4114 01
Intel® Atom™ Processor E680T
1.6 GHz (Extended Temperature)
B0 0020661h 8086 4114 01
Intel® Atom™ Processor E620
0.6 GHz (Commercial Temperature)
B1 0020661h 8086 4115 02
Intel® Atom™ Processor E620T
0.6 GHz (Extended Temperature)
B1 0020661h 8086 4115 02
Intel® Atom™ Processor E640
1.0 GHz (Commercial Temperature)
B1 0020661h 8086 4114 02
Intel® Atom™ Processor E640T
1.0 GHz (Extended Temperature)
B1 0020661h 8086 4114 02
Intel® Atom™ Processor E660
1.3 GHz (Commercial Temperature)
B1 0020661h 8086 4114 02
Intel® Atom™ Processor E660T
1.3 GHz (Industrial Temperature)
B1 0020661h 8086 4114 02
Intel® Atom™ Processor E680
1.6 GHz (Commercial Temperature)
B1 0020661h 8086 4114 02
Intel® Atom™ Processor E680T
1.6 GHz (Extended Temperature)
B1 0020661h 8086 4114 02
Identifica tio n Informatio n
Intel® Atom™ Processor E6xx Series
Spec ific ation Update July 20 14
14 Document Number: 324209-017US
NOTES:
1. The Vendor ID corresponds to bits [15:0] of the VID - Vendor Identification Register
located at Offset 00–01h in the PCI Bus 0 Device 0 Functio n 0 conf i g uration space.
2. The Device ID corresponds to bits [15:0] of the DID - Device Identification Register
located at Offset 02–03h in the PCI Bus 0 Device 0 Function 0 configuration space.
3. The Revision Numb er corresponds to bits [7:0] of the RID - Revision Identification
Regis ter loca te d at Offse t 08h in the PCI Bus 0 Device 31 Function 0 config uration
space.
Component Marking Information
The Intel® Atom™ Processor E6xx Series can be identif ied b y the f ollowin g c ompon ent
markings:
Stepping S-Spec Top
Marking Notes
B0 PRQ
909841
1.6 GHz (Commer c ial T emperatur e )
B0 PRQ
905523
1.3 GHz (Commer c ial T emperatur e )
B0 PRQ
905528
1.0 GHz (Commer c ial T emperatur e )
B0 PRQ
905531
0.6 GHz (Commer c ial T emperatur e )
B0 PRQ
909839
1.6 GHz (Exte nde d Tempera tur e )
B0 PRQ
905804
1.3 GHz (Exte nde d Tempera tur e )
B0 PRQ
905805
1.0 GHz (Exte nde d Tempera tur e )
B0 PRQ
905806
0.6 GHz (Exte nde d Tempera tur e )
B1 ES
913796
0.6 GHz (Commer c ial T emperatur e )
B1 ES
913784
1.0 GHz (Commer c ial T emperatur e )
B1 ES
913750
1.3 GHz (Commer c ial T emperatur e )
B1 ES
914597
1.6 GHz (Commer c ial T emperatur e )
B1 QS
915059
0.6 GHz (Exte nde d Tempera tur e )
B1 QS
915058
1.0 GHz (Exte nde d Tempera tur e )
B1 QS
915057
1.3 GHz (Exte nde d Tempera tur e )
B1 QS
915056
1.6 GHz (Exte nde d Tempera tur e )
B1 PRQ
913706
1.6 GHz (Commer c ial T emperatur e )
B1 PRQ
913720
1.3 GHz (Commer c ial Temperature)
B1 PRQ
913761
1.0 GHz (Commer c ial T emperatur e )
B1 PRQ
913773
0.6 GHz (Commer c ial T emperatur e )
B1 PRQ
913549
1.6 GHz (Exte nde d Tempera tur e )
B1 PRQ
913571
1.3 GHz (Exte nde d Tempera tur e )
B1 PRQ
913650
1.0 GHz (Extended Temperature)
B1 PRQ
913695
0.6 GHz (Exte nde d Tempera tur e )
Identifica tio n Informatio n
Intel® Atom™ Processor E6xx Series
July 20 14 Spec ific ation Update
Document Number: 324209-017US 15
Legen d for
Figure 1 Mark Text Notes
GRP1INE1 INTEL {M } {C}’09 {e 1} 1, 2, 3
GRP2LINE1 {FPO} {SPEC C ode} 4
Legen d for
Figure 2 Mark Text Notes
GRP1INE1 {FPO} {SPEC C ode} 4
GRP2LINE1 INTEL {M } {C}’09 {e 1} 1, 2, 3
NOTES:
1. M = Manufacturing copyright
2. NOTES: C = Copyright line
3. e1 = ROHS marking
4. FPO = Wafer lot #
Figure 1 Top-Side Marking Exa mple for Intel® Atom™ Processor E6x x Series B0
Stepping.
Identifica tio n Informatio n
Intel® Atom™ Processor E6xx Series
Spec ific ation Update July 20 14
16 Document Number: 324209-017US
Figure 2. Top-Side M a rkin g Ex am ple for Intel® Atom™ Processor E6xx Seri es B1
Stepping
Errata
Intel® Atom™ Processor E6xx Series
July 20 14 Spec ific ation Update
Document Number: 324209-017US 17
Errata
BI1. IO_SMI Indication in SMRAM State Save Area May Be Set Incorrectly
Problem: The IO_SMI bit in SM RAM’s loc a tion 7F A4h is s e t to “1” by the proces sor to indicate
that a System Management Interrupt (SMI) occurred as the result of executing an
instruction that read s from a n I/O por t. Due to th is erratum, th e IO_SMI bit may be
incorr e c tly set by:
• An SMI that is pending while a lower priority event is executing
• A REP I/O read
• A I/O read that redirects to MWAIT
Implication: SMM handlers may get a false IO_SMI indication.
Workaround: The SMM handler has to evaluate the saved context to determine if the SMI was
triggered by an instruction that read from an I/O port. The SMM handler must not
restart an I/O instruction if the platform has not been configured to generate a
synchronous SMI for the recorded I/O port address.
Status: No Fix.
BI2. Writes to IA32_DEBUGCTL MSR May Fail When FREEZE_LBRS_ON_PMI
Set
Problem: When the FREEZE_LBRS_ON_PMI, IA32_DEBUGCTL MSR (1D9h) bit [11], is set, future
writes to the IA32_DEBUGCTL MSR may not occur in certain rare corner cases. Writes
to this r eg ister by software or during certain processor operations are affected.
Implication: Under certain circumstances, the IA32_DEBUGCTL MSR value may not be updated
properly and will retain the old value. Intel has not observed this erratum with any
commercially available software.
Workaround: Do not set the FREEZE_LBRS_ON_PMI bit of IA32_DEBUGCTL MSR.
Status: No Fix.
Errata
Intel® Atom™ Processor E6xx Series
Spec ific ation Update July 20 14
18 Document Number: 324209-017US
BI3. Address Reported by Machine-Check Architecture (MCA) on L2 Cache
Errors May Be Incorrect
Problem: When an L2 Cache error occurs (error code 010Ah or 110Ah reported in
IA32_MCi_STAT U S MSR bits [15:0]), the address is logged in th e M CA address register
(IA32_M Ci_ADDR MSR). Under s om e s cenarios, th e a ddr es s r eported may be incorrec t.
Implication: Software sh ould not rely on the value r eported in IA32_MCi_ADD R M SR for L2 C a c he
errors.
Workaround: None identified.
Status: No Fix.
BI4. Pending x87 FPU Exceptions (#MF) Following STI May Be Serviced
before Higher Priority Interrupts
Problem: Interrupts tha t a re pending prior t o the exec ution of the STI ( Set Interrup t F lag)
instruction a r e normally serv ic e d im m e diate ly after the instr uction followin g the S TI. An
exception to th is is if the follow ing instr uction tr iggers a # MF. In this s ituation, the
interrupt should be ser viced b efore the #MF. Becau s e of this e r r a tum, if following STI,
an in struction that tr ig gers a #MF is exe c uted wh ile ST PCLK#, Enha nc ed Intel
SpeedStep® Technology transitions or Intel® Thermal Mon itor e vents oc c ur, the
pending #MF may be serv ic ed before higher pr iority in ter r upts.
Implication: Software may observe # MF bein g s er viced before higher priority interrup ts .
Workaround: None identified.
Status: No Fix.
BI5. Benign Exception After Double Fault May Not Cause Triple Fault
Shutdown
Problem: According to the Intel® 64 and IA-32 Architectures S of tware Develo per ’ s Manual,
Volume 3A, “Exception a nd Inter rupt Reference,” if another exception occ urs while
attemp ting to c a ll the double fault handler, the proces sor enter s shutd own mode. Due
to this erratum, any benign faults while attem pting to call the doubl e fault handler w ill
not cause a sh utdown . However , Contributory Exceptions and Page Faults will c ontinu e
to cause a triple f ault sh utdown.
Implication: If a benign exception occurs while attempting to call the double fa ult ha ndler, the
processor ma y hang or may handle the benign exception. Intel has not observed this
erratum with a ny commer cially a vailabl e s oftwar e.
Workaround: None identified.
Status: No Fix.
Errata
Intel® Atom™ Processor E6xx Series
July 20 14 Spec ific ation Update
Document Number: 324209-017US 19
BI6. IA32_MC1_STATUS MSR Bit [60] Does Not Reflect Machine Check
Error Reporting Enable Correctly
Problem: IA32_MC1_STATUS MS R (405h) bit [60] ( EN - Er ror En a bled) is s upposed to indic a te
whether the enable bit in t he IA32_M C1_CTL MSR ( 404h) was set at the time of the
last update t o th e IA32_MC 1_STATUS MSR. Due to this er r a tu m , IA32_MC1_S TATUS
MSR b it [ 60] in s tea d r eports the current va lue of the IA32_MC 1_CTL MSR ena ble bit.
Implication: IA32_MC1_S T ATUS MSR bit [60] may not reflect th e correct s tate of the en a ble bit in
the IA 32_M C1_CTL MSR at the time of the las t u pda te.
Workaround: None identified.
Status: No Fix.
BI7. If Two Logical Proc e s sors Use Same CR3 Val ue but Configure AP IC
Virtualization Differ ently, Eith er May Op er ate a s if APIC Virt u al i zation
Were Disabled
Problem: If a logical process or is in VM X non-root op er ati on with the “v ir tual APIC acces ses ” VM-
execution control se t to 1, it ma y inc orrectly op er ate as if th e “virtual APIC a ccesses”
VM-execution control was cleared to 0 if another logical pr oc essor h a s the sam e value
in CR 3 an d one of th e following is true:
• The other logic al proce s s or is not in VMX non-r oot ope r a tion.
• Th e other logical processor has the “virtual APIC accesses” VM-execu tion contr ol
cleared to 0.
• Th e other logical processor ’s value of th e “A PIC-access address” VM-execution
control field is different th an that of the fir s t log ic al proc essor.
Implication: A logical processor may fail to sup port the API C-virtualization f e a tures pr operly if a
virtual-machine monitor (VMM) uses the same page tables as a virtual machine (VM)
using the APIC-virtualization features, or if two VMs (or two vir tual CPUs within a VM )
use the s a me pa ge ta bles but operate with diff er ent settings of the APIC -virtualization
features.
Workaround: A VMM s hould n ot use for itself the same page ta bles as a VM using the APIC -
virtu a lization features, and it should configure two virtu al CPUs to use the same page
tables on ly if the y use the same settings of the API C-virtu alizati on fea tures.
Status: No Fix.
Errata
Intel® Atom™ Processor E6xx Series
Spec ific ation Update July 20 14
20 Document Number: 324209-017US
BI8. VM Exit Due to Fault While Delivering Software Interrupt May Save
Incorrect Data Into VMCS
Problem: If a fault occ urs during delivery of a software inter r upt (I N Tn) in virtual-8086 mode
when vir t ual mode extensions are in effect and that fault causes a VM exit, incorrect
data ma y be sav e d into the V MCS. S p ec ifically , information about th e s oftwar e
interrupt ma y not be repor ted in the IDT-vectoring information field. In a dd ition, the
interruptibility-state f ield may indicate blocking b y STI or by MOV SS if su ch blocking
were in effect before execu tion of the INTn in struction or bef or e e xecution of the VM-
entry instru ction tha t injected the software in terrupt.
Implication: In gen er al, VMM softwa r e tha t follows the guidelines given in the s ection “Handling VM
Exits D ue to Exceptions” of th e Intel® 64 and IA-32 Architectures S of tware Develop er ' s
Manu a l Volume 3B: Sy s tem Progra m m in g Guide shou ld not be affec ted. If the erratu m
improp erly causes indicati on of blocking by STI or b y M O V SS, the ability of a VMM to
inject a n interr upt may be delay ed b y one in s tr uction.
Workaround: VMM s oftwar e sh ould follow the g uidelines given in the section “Handlin g VM Exits Du e
to Exc ep tions” of the Intel® 64 an d IA -32 Architectu r es Software Dev eloper's Manual
Volume 3B : S ystem Progra mm ing Guide.
Status: No Fix.
BI9. VM Exit Occurring in IA-32e Mode May Not Produce VMX Abort When
Expected
Problem: If a VM exit occurs while th e pr ocessor is in IA-32e mode and th e “host address-space
size” VM-exit con tr ol is 0 , a VMX abort sh ould occur. Due to this erra tum, the expec ted
VMX a b or ts may not occ ur an d instead the VM Exit will occur normally. The conditions
requir ed to observe this erra tum are a VM entry that returns fr om SMM with the “IA-
32e guest” V M-entry control set to 1 in the SMM VMCS a nd the “host addres s-space
size” VM-exit con tr ol c le a red to 0 in the exec utive V MCS.
Implication: A VM exit will occur when a V MX abort was expected.
Workaround: An SMM VMM should always set the “IA-32e guest” VM-entry control in the SMM VMCS
to be the v a lue tha t w a s in th e LMA bit (IA 32_EFER.LMA.LMA[ bit 10]) in the IA 32_EF E R
MSR (C0000080h) at th e time of the las t S M M VM exit. If this guideline is followed,
that v a lue will be 1 only if the “host a d dr e s s-space size” VM-exit control is 1 in the
executive VMCS.
Status: No Fix.
Errata
Intel® Atom™ Processor E6xx Series
July 20 14 Spec ific ation Update
Document Number: 324209-017US 21
BI10. Performance Monitoring Event for Outstanding Bus Requests Ignores
AnyThread Bit
Problem: The Performance Monitoring Event of Outstanding Bus Requests will ignore the
AnyTh r ea d bit (IA32_PE R FEVTSEL0 MS R ( 186h)/IA32_PERFEVTSEL1 MSR (187h) bit
[21]) and will instead always count all transactions across all logical processors, even
when AnyThread is clear.
Implication: The perf or m ance m onitor cou nt may be incorrec t when countin g only th e current
logica l processor’s outstandin g b us requ e s ts on a pr oc essor supporting Intel® Hyper-
Threading Technology.
Workaround: None identified.
Status: No Fix.
BI11. Thermal Interrupts Dropped During and While Exiting Deep Power-
Down State
Problem: Thermal interrupts are ignored while the processor is in the Deep Power-Down State as
well as d uring a small window of time while exit ing from the D eep P ow er-Down Sta te .
During this window, if the PRO CHOT signal is driven or the interna l value of the se nsor
reaches th e pr ogr a mm ed therma l trip po int, the ass oc ia ted th er mal interrupt may be
lost.
Implication: In the eve nt of a thermal event wh ile a proc es s or is waking up from the Deep Pow er-
Down State, the proces s or will initiate a n appropr iate throttle r e s p onse. H owever, the
assoc ia ted ther m al interrupt ge nerated may b e lost.
Workaround: None identified.
Status: No Fix.
Errata
Intel® Atom™ Processor E6xx Series
Spec ific ation Update July 20 14
22 Document Number: 324209-017US
BI12. Corrupti o n of CS Seg ment Register Dur ing RSM While Transitioning
From Real Mode to Protected Mode
Problem: During the transition from real mode to protected mode, if an SMI (System
Man a ge m ent Interrup t) occurs between the MO V to CR0 tha t s e ts PE (Protec tion
Enable, bit 0) a nd the firs t f a r J MP, the subsequent RSM (Resume from Sy s tem
Managem ent Mode) may cau s e the lower two bits of CS segmen t regis ter to be
corrupted.
Implication: The corr uption of the bottom two bits of the CS segment register will have no impact
unless s of tw a r e explicitly ex a m in es the CS segment register between ena bling
protected mode and the f ir s t f a r J M P. The Intel® 64 an d IA-32 Arch itectures Software
Developer' s M a nual Volu me 3A: System Pr ogra m m in g G uide, Par t 1, in the section
titled “ Switch ing to Protect ed Mode,” r e c om m e nds the far JMP immediately follows the
write to C R0 to enable pro tected mod e. In tel has n ot ob s e r ved this e r r a tum with any
commercially available softw a r e .
Workaround: None identified.
Status: No Fix.
BI13. Performance Monitoring Counter With AnyThread Bit Set May Not
Count on Non-Active Th read
Problem: A performance counter with the AnyThread bit (IA32_PERFEVTSEL0 MSR
(186h)/IA32_PE R F EVTSEL1 MSR ( 187h) bit [21], IA32_FIXED_CTR_CTRL MSR (38Dh)
bit [2] for IA32_FIXED_CTR0, bit [6] for IA32_FIXED_CTR1, bit [10] for
IA32_FIXED_CTR2) set should cou nt that event on all logical pr ocess or s on that core.
Due to this erratum, a performance counter on a logical processor which has requested
to be placed in the Deep Pow er-Down State may not count ev ents tha t occur on
anoth e r logical pr oc e s sor.
Implication: The perf or m ance m onitor cou nt may b e incorrect when the logical proces s or is a s le ep
but still attem pting to c ount another logical pr oc e s sor’ s events . This will only occ ur on
processors s upporting Intel® Hyper-Threading Technolo gy (Intel® HT Technology).
Workaround: None identified.
Status: No Fix.
Errata
Intel® Atom™ Processor E6xx Series
July 20 14 Spec ific ation Update
Document Number: 324209-017US 23
BI14. GP and Fixed Performance Monitoring Counters With AnyThread Bit
Set May Not Accurately Count Only OS or Only USR Events
Problem: A fixed or GP (general purpose) performance counter with the AnyThread bit
(IA32_F IXED_CT R _CTRL MSR ( 38Dh) bit [2] for IA32_FIX E D _CTR0, bit [6] for
IA32_FIXED_CTR1, bit [10] for IA32_FIXED_CTR2; IA32_PERFEVTSEL0 MSR
(186h)/IA32_PE R F EVTSEL1 MSR ( 187h) bit [21]) set ma y not count corr ec tly when
coun ting only O S (rin g 0 ) even ts or only U SR (ring > 0) events. The c ounters will c ount
correctly if they ar e counting both O S and USR even ts or if the AnyThread bit is clea r .
Implication: A perform a nce monitor counter m a y be inc or r ect when it is coun ting for all logica l
process or s on that core and not countin g at all privilege le vels. T his err a tum will only
occur on proc essors s upporting multip le logical processors pe r c ore.
Workaround: None identified.
Status: No Fix.
BI15. PMI Request Not Generated on Counter Overflow if Its OVF Bit Already
Set in IA32_PERF_GLOBAL_STATUS
Problem: If a perfor m a nce counter overflow s and s oftwar e doe s not clear the corr es pon ding OVF
(overflow) bit in IA 32 _PERF _GLOBAL_STATUS MS R (38Eh), futur e overflows of tha t
coun te r will not trigger PM I (Pe r formance Monitoring Interr upt) requests.
Implication: If sof tware does not clear the OVF bit corres p onding t o a perfor m a nce counter, future
counter overflows may not cause PMI requests.
Workaround: Software s hould clear th e IA 32_PERF_G LO BAL_STATUS.OVF bit in the PMI ha ndler.
Status: No Fix.
Errata
Intel® Atom™ Processor E6xx Series
Spec ific ation Update July 20 14
24 Document Number: 324209-017US
BI16. Processo r M ay U se Incorrect Translation if TLBs Co ntain T wo D if f erent
Translations for Linear Address
Problem: The TLBs may contain both ordinary and large-page translations for a 4 kByte range of
linear addresses. This may occur if software modifies a PDE (page-directory entry) tha t
is marked pr es ent to set the PS bit (this c hanges the page s iz e used for the a ddr es s
range). If the two translations d iffer with res pe c t to page f r ame, per m issions, or
memory type, the processor may use a page frame, permissions , or m emor y type that
corres ponds to neither tr anslation.
Implication: Due to this er r atum, s oftwar e may n ot function properly if it sets the PS flag in a PDE
and also changes th e pa ge frame, per m iss ion s , or memory ty pe for the linear
addresses m a pped through tha t P DE.
Workaround: Softw a r e c a n avoid this problem b y ensuring that the TLBs never contain both ord inary
and large-page translations for a linear address that differ with respect to page frame,
permissions, or memor y type.
Status: No Fix.
BI17. Write to APIC Register Sometimes May Appear to Have Not Occurred
Problem: With respec t to the retire m ent of in structions, s tor es to th e unca cheable memory b a s e d
APIC regis ter s pa ce are handled in a non-synchronized way. For example, if an
instruction that mas ks the inte r r upt flag, for example, CLI, is executed soon after an
unc acheable w r ite to the T a s k Prior ity Register ( TPR) that lowers the APIC pr ior ity, the
interrupt mas king opera tion m a y tak e effect before the actual priority has been
lowered. This m a y cau se interru pts whos e pr iority is lower than the initial TP R , but
highe r than the final T PR, to not be serviced u ntil the interru p t enable d flag is f inally
set, in other wor d s , by an ST I instru c tion. I nterru p ts will r emain pending a nd are n ot
lost.
Implication: In this example, the processor m a y allow interru pts to be accepted but may de la y their
service.
Workaround: This non-synchroniza tion c a n be avoided by iss uing an APIC regis ter r ea d a fter the
APIC register write. This will force the store to th e APIC register b efore an y subsequent
instructions are exec uted. N o c om m e r c ial operating system is know n to be im p acted by
this erratum.
Status: No Fix.
Errata
Intel® Atom™ Processor E6xx Series
July 20 14 Spec ific ation Update
Document Number: 324209-017US 25
BI18. xTPR Update Transaction Cycle, if Enabled, May Be Issued to FSB Aft er
Processor Issued Stop-Grant Special Cycle
Problem: According to the FSB (Front Side Bu s ) protoco l s p ecific ation, no FSB cycles s hould be
issued by the processor once a Stop-Grant special cycle has been issued to the bus. If
xTPR update transactions are enabled by clearing th e IA32_MI SC_ENAB LES [ bit 23] a t
the time of Stop-Clock assertion, an xTPR update transaction cycle may be issued to
the FSB after the processor has issued a Stop Grant Acknowledge transaction.
Implication: When this erratum occurs in systems using C-states C2 (Stop-Grant State) and higher,
the result c ou ld be a s ystem hang.
Workaround: The BIOS must leave the xTPR update transactions disabled (default).
Status: No Fix.
BI19. Processo r May Rep ort #TS Inste ad of #GP Fault
Problem: A jump to a busy TSS (Task-State Segment) may cause a #TS (invalid TSS exc epti on)
instea d of a #G P fault (g eneral pr otection exce ption).
Implication: Operation systems that access a busy TSS may get an invalid TSS fault instead of a
#GP fault. Intel h a s not obser ved this er r atum w ith any comm ercially availab le
software.
Workaround: None identified.
Status: No Fix.
BI20. Writing Local Vector Table (LVT) When Interrupt Pending May Cause
Unexpected Interrupt
Problem: If a local inte r r upt is pen d ing w hen the LVT entry is written, a n interrupt ma y be taken
on the new in te r r upt vector even if the ma sk bit is set.
Implication: An interrupt may immediately be generated w ith the new v ec tor when a LVT entry is
written , even if the n e w LVT entry ha s the mask b it s e t. If there is no Interr upt Servic e
Routin e ( ISR) set up for tha t vector, the sys te m will GP f au lt. If th e ISR does not do an
End of Interr upt (EOI), th e bit f or the vector will be left set in the in-serv ic e register
and mask all interrupts at the same or lowe r pr iority.
Workaround: Any vec tor p r ogrammed into an LVT e ntry mus t have an ISR associated with it, ev en if
that v ector was programm ed as masked. This ISR routine must do an EOI to clear any
unexpected in te r r upts that ma y occu r. The ISR a s sociated wi th the sp urious vector
does not generate an E O I; therefore, the spuriou s vector shou ld n ot be used when
writin g the LVT .
Status: No Fix.
Errata
Intel® Atom™ Processor E6xx Series
Spec ific ation Update July 20 14
26 Document Number: 324209-017US
BI21. MOV To/From Debug Regi ster s Caus es Deb ug Except ion
Problem: When in V86 mode, if a MOV in s tr uction is exec uted to/from debug r egisters , a
general- pr otection ex c eption ( #GP) shou ld be gen er a ted. However, in the case wh en
the general detect enable flag (GD) bit is s et, the observ ed behavior is th a t a debug
exception ( #DB) is generated instead.
Implication: With debug-r eg ister pr otection enabled (in other words, the GD bit set), when
attempting to execute a M O V on debug register s in V86 mode, a debu g ex c eption will
be generate d instead of the expected gen era l -p rotection fault.
Workaround: In gen era l, operating sy s tems do not set the GD bit wh en they ar e in V 86 m ode. T he
GD bit is generally set an d used by debugger s . The debug exc eption handler should
chec k that the exception did not occu r in V86 m ode bef or e c on tinuing. If the exception
did occur in V 86 m ode, the exception ma y be directe d to th e general-protection
exception handler.
Status: No Fix.
BI22. Using 2M/4M Pages When A20M# Asserted May Result in Incorrect
Address Translations
Problem: An external A 20M# pin if enabled f orc es a ddr es s bit 20 to be masked (forced to zero)
to emulate r ea l-a ddress mode addr es s wraparou nd at 1 megabyte. H owever, if a ll of
the following c ondition s a r e m et, a ddr es s bit 20 may n ot be ma s k ed.
• Paging is enabled.
• A linear address has bit 20 set.
• The a ddr es s references a large page.
• A20M# is enabled.
Implication: When A20M# is enabled an d a n address references a large pa ge, the resu lting
translated physical addr ess may be incorrect. This erratu m has not been observ ed with
any c ommercia lly ava ila ble operating system.
Workaround: Operating sy s tems s hould not allow A 20M# to be enabled if the mas king of addres s bit
20 could be app lied to an address that references a large pa ge. A20M# is n or m a lly on ly
used with the first megabyte of memory.
Status: No Fix.
Errata
Intel® Atom™ Processor E6xx Series
July 20 14 Spec ific ation Update
Document Number: 324209-017US 27
BI23. Values for LBR/BTS/BTM Will Be Incorrect After Exit From SMM
Problem: After a return fr om SMM (Sys tem Mana ge m ent Mode), the processor will incor rectly
update the LBR (Last Branch Record) and the BTS (Branch Trace Store), hence,
rendering their data inv a lid. The c or res ponding data if sent out as a BTM on the system
bus w ill also be inc orrect. Note: This is s ue wou ld only occ ur when one of th e thr e e
above mention ed debug su ppor t f a c ili ties is used.
Implication: The value of the LBR, BT S, and BTM im mediately a fter an RSM op er ation should n ot be
used.
Workaround: None identified.
Status: No Fix.
BI24. Incorrect Address Computed for Last Byte of FXSAVE/FXRSTOR Image
Leads to Partial Memory Update
Problem: A partial memory state save of the 512-byte F XSAVE im age or a pa r tia l m e m ory s ta te
restore of th e FXRS TOR image may occur if a mem ory addr es s ex c eeds the 64 kB limit
while the proces sor is op erating in 16-bit mode or if a m em ory address ex c eeds the 4
GB limit while th e pr ocess or is opera ting in 32 -bit mode.
Implication: FXSAVE/FXRS TOR will incur a #GP fault due to the memory limit violation as e xpected,
but the m em ory state m a y be only p a r tially sa ved or restored.
Workaround: Software s hould avoid mem ory access es th a t wrap around the respective 16-bit and
32-bit mode m e mory lim its.
Status: No Fix.
BI25. Thermal Inte r rupt Not G enerated Wh en Current Temperature Invalid
Problem: When the DTS (Digital Th e r m al Sens or) cros s es one of its programmed thr e s holds it
generates an interru pt and logs the event (IA32_T HERM_STATUS MSR (019C h) bits
[9,7]). D ue to this erratu m , if the DTS reaches an invalid temperature (a s indicated
IA32_THERM_ STATUS MSR bit [31]) it d oes not generate a n interrupt ev en if one of
the programmed thresholds is cr os s ed a nd the corresponding log bits become set.
Implication: When the tempera ture reach es a n in valid temperature the proces s or does not g enerate
a thermal inter r upt even if a progra m m ed th r es hold is cros s ed.
Workaround: None identified.
Status: No Fix.
Errata
Intel® Atom™ Processor E6xx Series
Spec ific ation Update July 20 14
28 Document Number: 324209-017US
BI26. Programming Digital Thermal Sensor (DTS) Threshold May Cause
Unexpected Thermal Interrupts
Problem: Software can enable DTS therm a l in terr upts by programming the thermal th r es hold
and setting th e r es pec tive ther ma l interrupt ena ble bit. W hen programm ing the DTS
value, the previous DTS threshold ma y be crossed. This will gen era te a n unex pected
thermal interrupt.
Implication: Software may observe an unexpected th er ma l interru pt oc c ur after repr ogra mming th e
thermal thres hold.
Workaround: In the ACPI/ O S, implement a worka r ound by tem porarily disabling th e D T S thresh old
interrupt bef ore updatin g the DTS threshold v a lu e.
Workaround: No Fix.
BI27. Returning to Real Mode From SMM With EFLAGS.VM Set May Result in
Unpredic tabl e System Beha vior
Problem: Returning back from SMM mode into r e a l m ode while E FLAGS. VM is set in SMRAM may
result in unpredictable system beh a vior.
Implication: If SMM software changes the values of EFLAGS.VM in SMRAM, it may result in
unpr e dictable s ystem behavior . In tel has not obs er ved this behavior in c ommercially
available software.
Workaround: SMM s oftwar e sh ould not c hange the value of EFL AGS.VM in SMRAM.
Status: No Fix.
BI28. Fault on ENTER Instruction May Result in Unexpected Values on Stack
Frame
Problem: The ENTER instruction is used to create a procedure stack frame. Due to this erratum,
if execution of the E N TE R instru c tion resu lts in a f ault, the dynam ic storage area of the
resultant stack frame may contain unexpected values (in other words, residual stack
data as a result of processing the fault).
Implication: Data in the created stack frame may be a lter e d follo wing a fault on the ENTE R
instruction. Please r efer to “Proced ure Ca lls For Bloc k-Structured Languages” in the
Intel® 64 and IA-32 Architectures Software Developer's Manual Volume 1: Basic
Architectur e for information on the usage of the ENTE R instr uctions . This err atum is not
expected to occur in ring 3. Faults are usually processed in ring 0, and stack switch
occur s when tr ansf e r r ing to ring 0. Intel h as not observed this e r r a tum on any
commercially available softw a r e .
Workaround: None identified.
Status: No Fix.
Errata
Intel® Atom™ Processor E6xx Series
July 20 14 Spec ific ation Update
Document Number: 324209-017US 29
BI29. With TF (Trap Flag) Asserted, FP Instruction That Triggers Unmasked
FP Exception May Take Single Step Trap Before Retirement of
Instruction
Problem: If an FP in s tr uction ge nerates a n un m asked exc ep tion w ith the EFLAGS.T F =1, it is
possib le for exter nal eve nts to oc cur, including a tra ns ition to a lower power sta te.
When r es uming from the low er pow er s ta te, it may be possible to take the single s tep
trap bef or e the execution of the orig inal FP instru c tion com p letes.
Implication: A single step trap will be taken when not expected.
Workaround: None identified.
Status: No Fix.
BI30. Ena bled Debug Breakpoint or Single Step Tr ap Ma y Be Taken After
MOV SS/POP SS Instruction if Followed by Floating Point Exception
Signal ing Instruction
Problem: A MOV SS/ POP SS ins tr uction sh ould inhibit all interr upts in c luding debu g br eakpoints
until a fter exe c ution of the follow ing instr uction. This is inten d ed to allow the seq uential
execution of MOV S S/POP SS and MOV [ r/e]SP, [r/e]BP instru ctions w ithout h av ing an
invalid stac k during interrupt ha ndling. However, an enabled de bu g breakpoint or
single s tep trap may be taken after MOV SS/POP SS if this ins tr uction is followed by a n
instruction that sign als a f loa ting point exception ra ther th a n a MOV [ r /e]SP, [r/e]BP
instruc tion . This results in a debug exception being signaled on a n unexpected
instruction boundary sin ce the MOV SS/POP SS an d the following instru c tion should be
executed autom atica lly.
Implication: This ca n r es ult in in correct s ignaling of a debug excepti on and possibly a m ismatched
Stack Segment and Stack Pointer. If MOV SS/POP SS is not followed by a MOV [r/e]S P ,
[r/e]BP, there may be a mismatched Stack Segment and Stack Pointer on any
exception. Intel has not obse r ved this e r r a tum with any commer c ially av ailable
software or system.
Workaround: As recommended in the I ntel® 64 a nd IA-32 Archite c tures S oftwar e D eveloper 's
Man ual, th e u s e of MOV SS/P O P SS in conj unction with MO V [r/e] SP, [r/ e]BP will avoid
the fa ilure since the MOV [r/e]SP, [r/e]BP will not generate a floating p oint ex c e ption.
Developers of debug tools s hould be awar e of the poten tia l incorre ct debu g e ven t
signa ling created by this erratum.
Status: No Fix.
Errata
Intel® Atom™ Processor E6xx Series
Spec ific ation Update July 20 14
30 Document Number: 324209-017US
BI31. Code Segment Limit/Canonical Faults on RSM May Be Serviced Before
Higher Priority Interrupts/Exceptions and May Push Wrong Address
Onto Stack
Problem: Normally, when the proces s or encounters a Segmen t Limit or C anonical Fault due to
code execution, a #GP (Gener a l Protect ion Ex c e ption) fault is g enerated a fter all high er
prior ity In ter r upts and excepti ons are servic ed. Due to this erra tum, if RSM (R esume
from Sy s tem M a nagement M ode) r eturns to the execution flow that resu lts in a Code
Segment Limit or Canonical Fault, the #GP f ault may be ser viced bef ore a higher
prior ity interr upt or exc e ption (for example, NMI (Non-Mas kable Interru pt) , D ebug
break (#DB), Machine Check (#MC), etc.). If the RSM attempts to retur n to a non-
canonical address, the address pushed onto the stack for this #GP fault may not match
the non-canonical address that caused the fault.
Implication: Operating systems m a y observ e a #GP fault being serviced bef or e higher pri ority
interrupts and exceptions. Intel h as not observed this erra tum on a ny commer c ially
available software.
Workaround: None identified.
Status: No Fix.
BI32. BTS (Branch Trace Store) and PEBS (Precise Event Based Sampling)
May Update Mem ory Out sid e BTS /P EBS Bu ff er
Problem: If the BTS/PEBS buffer is defined such that:
• The dif ference betw een the BTS/PEBS buff er ba s e a nd th e BTS/PEBS absolute
maxim um is n ot a n integer multiple of the correspon ding r ecord siz es .
• Th e BTS/PEBS abs olute max imum is le s s than a re c or d s ize from the end of the
virtual address space.
• Th e r e c or d that would cross the BT S/PEBS a b s olute max im um will a lso continue
past the end of the virtu a l addr es s s pa c e.
A BTS/PEBS r e c or d c an be written that will wrap a t the 4G bou ndary (lega cy mode) or
264 boundary (IA-32e mode, including both 64-bit mode and c ompa tibility m ode), and
write memory outside of the BTS/PEBS buffer.
Implication: Software tha t uses BTS/ PEBS nea r the 4G bounda r y (legacy m ode) or 264 bounda r y
(IA-32e mode, includin g both 64-bit mode and compatibili ty mode) and defines the
buffer such that it does not hold a n integer m ultiple of rec or d s can u p date memory
outside the BTS/PE BS buffer.
Workaround: Define the BTS/PEBS buffer such that the BTS/PEBS absolute maximum minus the
BTS/ PE BS buffer base is an integer multiple of the corresponding record s izes as
recommended in the I ntel® 64 and IA -32 Architectu r es S oftware Dev eloper’s Ma nual
Volume 3B .
Status: No Fix.
Errata
Intel® Atom™ Processor E6xx Series
July 20 14 Spec ific ation Update
Document Number: 324209-017US 31
BI33. Single Step Interrupts With Floating Point Exception Pending May Be
Mishandled
Problem: In certa in circumstanc e s , when a f loa ting point exception (#MF) is p ending during
single step exec ution, pr ocessing of the single step debug exc eption (#DB) may be
mishandled.
Implication: When th is erratum occurs, #DB will be incorrectly handle d a s follows :
• #DB is s ignaled before the pending higher priori ty #M F ( in ter r upt 16).
• #DB is generated twice on th e s ame ins tr uction.
Workaround: None identified.
Status: No Fix.
BI34. Unsynchronized Cross-Modifying Code Operations Can Cause
Unexpected Instruction Execution Results
Problem: The act of one proces sor, or s ystem bus mas ter , writing data in to a cur r ently ex ecuting
code segment of a s e c ond processor with th e intent of hav ing the s ec ond processor
execute that data as code is called cross-modif ying cod e ( XMC). XMC that does not
force the second proces s or to ex ecute a s ynchronizing in struction, prior to exec ution of
the new c ode, is ca lled unsynchr onized XMC. Software using unsynchr onized XMC to
modify the instruction by te stream of a pr oces s or c a n see unexpected or un pr edicta ble
execution beh a vior fr om the proces sor that is executin g the modif ied code.
Implication: In this case, the phrase “unexpected or unpredictable execution behavior”
encomp a sses th e g eneration of m ost of the e xceptions listed in the In te l ® 64 an d IA -32
Architectur es Software D eveloper’s Manual Volu m e 3A: System Programming Guide,
inclu d ing a General Pr ote c tion F a ult (#G P) or other un expected behav iors .
Workaround: In or der to avoid this erra tum, program m e r s should use the XMC syn c hroniza tion
algor ithm as de ta iled in the Intel® 64 and IA-32 Ar c hitectur es Software Developer’ s
Man ual Volu m e 3A: System Program m ing Gu ide , section “Handling Self- and Cross-
Modifyin g Code.”
Status: No Fix.
Errata
Intel® Atom™ Processor E6xx Series
Spec ific ation Update July 20 14
32 Document Number: 324209-017US
BI35. LBR Stack May Not Be Frozen on PMI Request When
FREEZE_LBRS_ON_PMI Set
Problem: When the FREEZ E _L BRS_ON_PMI flag (IA 32_DEBUGCTL MSR (1D9h) bit [11] ) is s et on
an Intel® Atom™ Processor E6xx Series, a PMI (performance monitor interru pt) r eque st
should ca use the LB R an d TR flags (IA32_DE BUGCT L MS R ( 1D9h) bit [1:0]) to be
cleared and the LBR (la s t bra nch recor d) s tac k to stop being updated by
branches/interrupts/exceptions. Due to this erratum, the processor may clear the LBR
and TR flags but not stop the LBR stack from being updated when
FREEZE_LBRS_ON_PMI is set and a PMI request occurs.
Implication: Following a PMI request, the LBRs may continue to be updated by
branches/interrupts/exceptions even when FREEZE_LBR S _O N _P MI is set. Th e LBRs
may con ta in values rec or ded a f ter th e PMI request.
Workaround: None identified.
Status: No Fix.
BI36. PMI Request Not Generated on Counter Overflow if Its OVF Bit Already
Set in IA32_PERF_GLOBAL_STATUS
Problem: If a perfor m a nce counter overflow s and s oftwar e doe s not clear the corresponding OVF
(overflow) bit in IA 32 _PERF _GLOBAL_STATUS MS R (38Eh), futur e overflows of tha t
coun te r will not trigger PM I (Pe r formance Monitoring Interr upt) requests.
Implication: If sof tware does not clear the OVF bit corres p onding t o a perfor m a nce counter, futur e
counter overflows may not cause PMI requests.
Workaround: Software s hould clear th e IA 32_PERF_G LO BAL_STATUS.OVF bit in the PMI ha ndler.
Status: No Fix.
BI37. Synchronous Reset of IA32_MPERF on IA32_APERF Overflow May Not
Work
Problem: When either the IA32_MP ERF or IA32_APERF MSR (E7h , E8h) incr ements to its
maximum value of FFFF_FFFF_FFFF_FFFFh, both MSRs are supposed to synchronously
reset to 0h on the nex t cloc k . Due to this err a tum, IA32_MPE R F may not be reset w hen
IA32 _APER F overf lows. Instead , IA32 _MPER F may con tinue to increment with out being
reset.
Implication: Due to this erratum, software cannot reply on the synchronous reset of the
IA32_MPERF regis ter. The typical u s a ge of IA32_MP ERF/IA32_APERF is to initialize
them w ith a va lue of 0; in this case, the ov er flow of the cou nter would not h a p pen for
ten years.
Workaround: None identified.
Status: No Fix.
Errata
Intel® Atom™ Processor E6xx Series
July 20 14 Spec ific ation Update
Document Number: 324209-017US 33
BI38. Processor May Not Recognize Signal PWROK on Its Initial Assertion
Problem: During any sy s tem pow er -on event in wh ich power had been r em ov ed from the
process or (including S3 ) , th e p r oc e s sor may fail to recognize the PWROK input signal
during pow er -up. Th is m issed obser v a tion is dependent upon the processor
temperature and ca n cause the s ystem n ot to b oot.
Implication: The system m a y f a il to boot. Each proc es s or m a y be affec ted a t dif f er ent tempera tu r e
ranges.
Workaround: An external hardware workaround has been identified. Please r efer to Intel ® Atom™
Processor E6xx S er ies -based – Platform Des ign G uide for de ta ils .
Status: Plan Fix.
BI39. Image on SDVO Display Clipped When Multiple Display Planes and
SDVO Port Enabled
Problem: An interna l tim ing genera tor and th e SDVO (Serial Digital Video Output) timing
genera tor may bec ome out of synch with each oth er . T his condition on ly manifests
when any combination of multiple disp lay planes an d the SDVO port ar e concurr e ntly
enabled an d c a n result in a clipped im a ge.
Implication: A clipped image will be observ ed on the SDV O displa y.
Workaround: A software w or karou nd has been ide ntifie d and may be implemented a s a workaroun d
for th is e r r a tum.
Status: Plan Fix.
BI40. Large Amounts of LPC Bus Memory Reads and Writes May Temporarily
Starve Other I/O Devices
Problem: During heavy memory read and mem or y write tr a ffic to the LPC ( L ow Pin Count) Bus,
downstream transactions to I/O devices may be blocked for periods of 3.2 μs.
Implication: I/O devices may suffer a performance impact (for example, audio glitches). None
identified.
Status: No Fix.
Errata
Intel® Atom™ Processor E6xx Series
Spec ific ation Update July 20 14
34 Document Number: 324209-017US
BI41. Delayed I/O Device Memory Transactions Can Cause System Hang
Problem: Back-to-back uncacheable write transactions issued by the processor to downstream
I/O devices can cause indeterminate delays to completions of upstream memory
transactions from I/O devices.
Implication: Long bursts of downstream transactions may cause system hangs and/or au d io
glitches.
Workaround: A BIOS workaround to increase the priority of the affec te d tr ansa c tions has been
identified.
Status: No Fix.
BI42. Software Can Inadvertently Change SDVO Base Class Code Register
Problem: Software that programs the unused SDVO (Serial Digital Video Out) base address
register at of fset 1Ch ( Bus 0; Device 3; Function 0) inadverten tly modif ies the SD V O
base class code register (Bus 0; Device 3; Function 0; Offset 9h) to an incorrect value.
Implication: Softwar e that relies on the base c la s s code cou ld fail to function p r ope r ly or will repor t
the SDVO device incorrec tly.
Workaround: A BIOS workaround has been identified.
Status: Plan Fix.
BI43. Voltage Supplied to Internal RTC Logic Violates Design Specification
Problem: An internal voltage regulator for the RTC (Real Time Clock) logic produces an
overv oltage condition and pot e ntial dama ge to the inter nal log ic .
Implication: The processor is not guaranteed to meet a 10 yea r relia bility lifetime. Th e s ystem may
fail to boot over a p eriod o f time or ex hibit inaccurate RTC clock opera tion.
Workaround: A worka r ou nd has been identified. P lea s e refer to the Intel® Atom™ Process or E6xx
Series Erratum: “ Voltage Supplied to Inter nal RT C (Real Tim e Clock) Logic V iolates
Design Spec if ic a tion” FA Q , document number 324702, for f urther deta ils .
Status: Plan Fix.
Errata
Intel® Atom™ Processor E6xx Series
July 20 14 Spec ific ation Update
Document Number: 324209-017US 35
BI44. Flickering M ay be O bserved on Display w hil e Running Intensive
Graphics and Video Decoding Activities
Problem: During intensive graphics a nd video playbac k activities , a nd with large numbers of
display read r equests, the display ma y experienc e flicker in g.
Implication: Flickering may be obs er ved on displa y s c onnected to the integrate d displa y engine.
Workaround: A worka r ou nd has been identified in BIOS and Intel® Embedded M edia G r a phics Dr iv er .
Status: Plan Fix.
BI45. C6 Request May Cause a Machine Check if the Other Logical Processor
is in C4 or C6
Problem: A machine chec k may be generated if a log ic a l processor requests the C 6 C-state and
the othe r logical proces s or is in either the C4 or C6 C-states.
Implication: This erratum may result in unexpected machine-check exceptions .
Workaround: It is possible for the BI O S to contain a workaround for this erratum.
Status: No Fix.
BI46. EOI Transaction May Not be Sent if Software Enters Core C6 During an
Interrupt Service Routine
Problem: If core C6 is entered a fter the start of an interrupt s er vice rou tine but be fore a w r ite to
the APIC EOI (End of Interrupt) register, and the c ore is woken up by an even t other
than a fixed inte r r upt sour ce the cor e m a y drop th e EOI tr a nsaction the next time AP IC
EOI r e gister is written and fu r ther inter rupts from the same or lower priority level will
be blocked.
Implication: EOI transactions may be los t and interru pts m a y be blocked wh en core C6 is used
during in terr upt service routines.
Workaround: Software s hould chec k the ISR register and if any in terr upts are in s ervice only enter
C1.
Status: No Fix.
Errata
Intel® Atom™ Processor E6xx Series
Spec ific ation Update July 20 14
36 Document Number: 324209-017US
BI47. PCNT Throttling May Cause System Hang During TM1 Thermal Event
Problem: The TM1 (Therma l M onitor 1 ) therma l event and PCNT (Process or Control) m e cha nism
can e a c h independ ently control pr ocess or throttling and sh ould work at the same time
without issu es. Due to this erratum, if PCNT throttling is enabled durin g a TM1 thermal
event, the tw o throttling mechanis m s m ay conf lic t with each othe r a nd leadin g to a
system hang.
Implication: When this erratum occurs, the system may hang.
Workaround: A BIOS workar ound has been identified and may be implemented as a w orkaroun d for
this erratum.
Status: No fix.
BI48. VMX Transitions May Set Bits 63:32 of the IA32_FMASK MSR
Problem: Bits 63:32 of the IA32_FMAS K M SR ( C0000084H) are r es er ved and attempts to set
them should f ail. Du e to this erratum, loa d s of this MSR as part of a VMX transition
(from either the VM-exit MSR-load area or the VM-entry MSR-load area) may set any of
these bits withou t c ausing the tra nsition to fail.
Implication: Subsequen t rea ds of the IA32_FM A SK MSR (e.g. by RDMSR ) w ill return a non -zero
valu e for bits 63: 3 2. In tel has not observ ed this erra tum with any comme rcially
available software.
Workaround: Software s hould ensure that bits 63:32 a r e a ll 0 in a ny entry f or the IA32_FMASK M SR
in any VM-exit MSR-load area or VM-entry MSR-load area.
Status: No Fix
BI49. Wri ting t he Lo cal Ve ctor Table (LVT) when an I nterrup t is Pending
May Ca use an Une x pe c te d Interrupt
Problem: If a local inte r r upt is pen d ing w hen the LVT entry is written, a n interrupt ma y be taken
on the new in te r r upt vector even if the ma sk bit is set.
Implication: An interru pt ma y immediately be generated w ith the new v ec tor when a LVT entry is
written, even if the new LVT entry has th e m a sk bit set. If there is no Inter rupt Service
Routin e ( ISR) set up for tha t vector th e s ystem w ill GP fault. If th e ISR does not do an
End of Interr upt (EOI) the bit for the vector will be left set in the in-serv ic e register an d
mask all interrupts at the same or lower pri ority.
Workaround: Any vec tor p r ogrammed into an LVT e ntry mus t have an ISR associated with it, ev en if
that vector was programmed as masked. This ISR routine must do an EOI to clear any
unex pec ted in terr upts that may oc c ur. The IS R associated w ith th e s purious vector
does not generate an E O I, therefore the spur iou s vector s hould not be us ed w hen
writin g the LVT .
Status: No Fix.
Errata
Intel® Atom™ Processor E6xx Series
July 20 14 Spec ific ation Update
Document Number: 324209-017US 37
BI50. Clearing PCIe* Root Port's BME Bit With Pending Upstream Traffic Will
Cause Internal Bus to Hang
Problem: When there are upstream transactions in any of the PCIe* root port's bu ffers a nd the
BME (B us Master Enable) bit of that r oot por t is c le ared to dis able th e port as b us
master , the com pletion from the BM E c lea r conf ig uration c ycle becom e s blocke d by th e
pendin g upstrea m transactions. G iven th es e c onditions, th e pr ocessor will time out
waitin g for the b loc ked configuration c ycle.
Implication: Due to this er r atum an internal bu s will hang leadin g to: IERR, NMI, Reset, etc .
Workaround: During OS ru ntime, BI OS and device drivers c a n on ly c lear the root p ort or en d point
BME s a fter the a ttached end point devices a r e p ut into id le s tate with no pending
upstream transactions. BIOS and OS must make sure there are no upstream
transac tion s before clear ing the BME a nd before BIOS h an ds of f the boot process to the
OS.
Status: No Fix.
BI51. CPUID Instruction Returns Incorrect Brand String Problem:
Problem: When a CPUID instruction is ex ec uted with EAX = 80000002H , 80000003H a nd
80000004H on an Intel® Atom™ processor, the return value conta ins the bra nd s tring
Genuine Intel (R) CPU when it should have Intel( R) Atom(TM) CPU w ith the
corresponding SKU ( e. g.,: E620 or E660) .
Implication: When th is erratum occurs, the proc essor will r eport the incorrec t b r a nd string.
Workaround: It is possible for BIOS to contain a workarou nd for this err atum.
Status: No Fix.
BI52. The APIC Timer May Drift When Bus Ratios Less Than 6 Are Used
Problem: The APIC T im e r m ay not decr em e nt correctly when usin g b us ratios lower tha n 6. T his
may c ause lim ited amoun ts of drift.
Implication: Due to this er r atum, in the w or st case of a nomin a l bus fr e quency of 100 MHz, a DCR
(Divide Con figuration Register) of 128 and a bus ratio of 4, th e c ounter can drift by up
to ~60 μs per timer countdown.
Workaround: It is possible for the BI O S to contain a worka r ound f or th is e r r atum. This workaroun d
will disable bus ratios less th an 6.
Status: No fix for B0. Ultra Low Frequency Mode is de -featured in B1.
Errata
Intel® Atom™ Processor E6xx Series
Spec ific ation Update July 20 14
38 Document Number: 324209-017US
BI53. Extended Tags A re Al ways U sed But Not Reported on PCI e* Ro ot Ports
Problem: Although the dev ic e' s P CIe* root p or ts d o not report 8-bit Extended Tag support in the
DCAP.EFTS register a nd don' t allow the en a blin g of Extended Ta gs in the DCT L.E T F E
regist er, they will still gener a te transactions with Extended Tags.
Implication: PCIe* end points that do not su pport extended tags as requ ir ed by the PCI e* Base
Specif ication may fail.
Workaround: None identified.
Status: No fix
BI54. Outbound MSI Fro m The PM U Ca n Result in Live Loc k An d /or System
Hang When Simultaneously Occurring With an Inbound I/O Read
Problem: The Power Management Unit (PMU) is capable of generating Message Signaled
Interrupts (MSI) to the processor. In specific corner cases, an outbou nd MSI fr om th e
PMU m a y occur s im ultane ously with an in b ound I/O rea d r e s ulting in live loc k and/ or a
system hang.
Implication: When th is erratum occurs, the proc essor ma y live lock and/or res ult in a sy stem ha ng.
The P MU will not be a ble to supp or t MSI for display power up and thermal trip events.
Workaround: PMU MSIs ha ve been disabled in firmware. Softwa r e is r equired to not enable the MSIs
for therma l events an d Dis pla y power up.
Status: No Fix.
BI55. SMBus Timing Violation
Problem: Due to this erratum, there is a violation of the specified requirem ent for SMB Hold
Time. The processor hold time from th e falling e dge of SMB Data to the falling edge of
SMB CLK is 1/ 4 th e pr ogr a mm ed SMB C LK period. In the case of a 100 kHz bus, this
becomes 10 μs / 4 = 2.5 μs, which violates the 4.0 μs specification.
Implication: Intel has not observed any fun c tional fa ilures w ith any c om m e r c ially av ailable systems.
Workaround: Custom e r s have the option to progra m for slow er SMB CLK.
Status: No Fix.
BI56. RTC Does Not Detect a Coin Cell Battery Low Voltage Condition
Problem: The RTC's (Real Time Clock) TRC.RTCIO bit in the GPE0BLK (Offset 34H; b it 2) is not
set to 1 when th e c oin cell battery voltage is below th e r ep la c e ment threshold.
Implication: Softwar e is unable to r ep ort when th e RT C battery voltage is below th e r ep la c emen t
threshold.
Workaround: None identified.
Status: No Fix.
Errata
Intel® Atom™ Processor E6xx Series
July 20 14 Spec ific ation Update
Document Number: 324209-017US 39
BI57. Complex Conditions Associated With Instruction Page Remapping or
Self/Cross-Modifying Code Execution May Lead to Unpredictable
System Behavior
Problem: Under a com ple x set of internal con ditions, instr uction page remapping, or self / cross
modifying c ode events may lead to u npredictab le system behavior
Implication: Due to this Erratum, unpredic table system behavior m a y be observed.
Workaround: None identified.
Status: No Fix.
BI58. REP MOVS/STOS Executing With Fast Strings Enabled and Crossing
Page Boundaries with Inconsistent Memory Types May Use an
Incorrect Data Size or Lead to Memory-Ordering Violations
Problem: Under the c ondition s describ ed in the S oftwar e D e velopers Man ual sec tion "Fa st Strin g
Operation," the pr oc essor performs R EP MO VS or REP STOS a s fast strings. D ue to this
erratum, fast string REP MOVS/REP STOS instruc tions tha t cross pa ge bounda r ies from
WB/WC memory types to UC/WP/WT memory types, may start using an incorrect data
size or m ay obser ve memory orde r ing violations.
Implication: Upon crossing th e pa ge bounda r y , th e following may occu r , dependent on th e new
page memory ty pe:
• UC: T he data size of eac h read and write ma y be different tha n the original da ta
size.
• WP: Th e da ta s ize of each read and write may be dif ferent than the original dat a
size and there may be a memory ordering v iolation.
• WT: T here may be a memory or de r ing vio lation.
Workaround: Softw a r e s hould avoid crossing pag e bounda r ies from WB or WC memory type to UC,
WP or W T memory type w ithin a sin gle R EP MOVS or RE P STOS instruction that will
execute w ith fast strings enabled.
Status: No Fix.
Errata
Intel® Atom™ Processor E6xx Series
Spec ific ation Update July 20 14
40 Document Number: 324209-017US
BI59. Paging Structure Entry May be Used Before Accessed And Dirty Flags
Are Updated
Problem: If software modifies a pa g ing stru cture entry wh ile the processor is using the entry for
linear address tr a nslation, the proces s or may erroneously use the old value of the
entry to form a tr a nslation in a TLB (or an entry in a paging structure cache) and then
update the entry's new valu e to s e t the acce s s e d flag or dir ty flag. This will occur only
if both the old an d new v a lues of the entry r esu lt in valid translations.
Implication: Incorrect behavior may occur with algorithms that atomically check that the accessed
flag or the dirty flag of a paging structure en tr y is clear and m odify oth er p a r ts of tha t
paging s tructu re entry in a manner that results in a differ e nt valid tr a nslation.
Workaround: Affected a lgorithms must ensu r e that appr opriate TLB invalidation is done befor e
assuming that futu r e a c cesses do n ot use translations ba s e d on the old value of the
paging stru c ture entry.
Status: No Fix.
§
Specification Changes
Intel® Atom™ Processor E6xx Series
July 20 14 Spec ific ation Update
Document Number: 324209-017US 41
Specification Changes
1. Heatsink Height Change
Issue: Heatsink height on Figu r e 10 “1U N a tural Convec tion Heats ink Mechanical Drawin g” has
chan ged from 13.5 ±0.2 mm to 29 ±0.2 mm.
Old Text:
Figure 10. 1U Natural Convection Heatsink Mechanical Drawing
Specification Changes
Intel® Atom™ Processor E6xx Series
Spec ific ation Update July 20 14
42 Document Number: 324209-017US
New Text:
Figure 10. 1U Natural Convection Heatsink Mechanical Drawing
Affected Docs:Figure 10 “1U Natural Convection Heatsink Mechanical Drawing” of Intel® Atom™
Processor E6xx Series Thermal and Mechanical Design Guidelines, Rev 003.
Specification Changes
Intel® Atom™ Processor E6xx Series
July 20 14 Spec ific ation Update
Document Number: 324209-017US 43
2. Changed VCC33RTC Specification in “Operating Condition Power
Supply and Reference DC Characteristics” Table
Issue: As erratum of Voltage Supplied to Internal RTC Logic Violates Design Specification
(Errata No. BI43) has been fixed in Intel® Atom™ Processor E6xx Series B1 stepping,
the VCCRTCEXT specification is changed to reflect B0 and B1 stepping characteristics.
Old Text:
Table 405. Opera t ing Conditio n Power Supply a n d Reference DC Charac t e r istics [i n
Datasheet]
Symbol
Parameter
Min.
Typ.
Max.
Unit
Notes
VCCP33,
VCCP33SUS,
VCCPSUS,
3.3 V Supply Voltage (Legacy IO, SDVO
pads, Suspend Power supply, RTC
suspend, RTC well)
3.135
3.3
3.465
V
VCC33RTC
2.9 V Supply Voltage (RTC well) 2.0
(battery
mode)
2.9
3.045
V
New Text:
Table 405. Opera t ing Conditio n Power Supply a n d Reference DC Charac t e r istics [i n
Datasheet]
Symbol
Parameter
Min.
Typ.
Max.
Unit
Notes
VCCP33,
VCCP33SUS,
VCCPSUS
3.3 V Supply Voltage (Legacy IO,
SDVO pads, Suspend Power supply,
RTC suspend)
3.135
3.3
3.465
V
VCC33RTC
3.3 V Supply Voltage (RTC well) 3.135
3.3
3.465
V
B1
Stepping
2.0
(battery
mode)
2.9 V Supply Voltage (RTC well) 2.755
2.9
3.045
V
B0
Stepping
2.17
(battery
mode)
Affec ted Doc s : T a ble 405 “Opera tin g Condition P ower S upply and Refer ence DC Cha r a c teris tics ” of
Intel® Atom™ Processor E6xx Series Datasheet, revision 004.
Specification Changes
Intel® Atom™ Processor E6xx Series
Spec ific ation Update July 20 14
44 Document Number: 324209-017US
3. Changed VCCRTCE XT Speci fic atio n from “O per ating Cond iti on Po wer
Supply and Reference DC Characteristics” Table
Issue: As erratum of Voltage Supplied to Internal RTC Logic Violates Design Specification
(Errata No. BI43) has been fixed in Intel® Atom™ Processor E6xx Series B1 stepping.
The VCCRTCEXT specification is changed to apply only to the B0 stepping.
Old Text:
Table 405. Opera t ing Conditio n Power Supply a n d Reference DC
Symbol
Parameter
Min.
Typ.
Max.
Unit
Notes
VCCRTCEXT
1.24 V Supply Voltage (RTC well)
1.178
1.24
1.302
V
New Text:
Table 405. Opera t ing Conditio n Power Supply a n d Reference DC Charac t e r istics
Symbol
Parameter
Min.
Typ.
Max.
Unit
Notes
VCCRTCEXT
1.24 V Supply Voltage (RTC well)
1.178
1.24
1.302
V B0 Stepping
only; does
not apply to
B1 stepping
Affec ted Doc s : T a ble 405 “Opera tin g Condition P ower S upply and Refer ence DC Cha r a c teris tics ” of
Intel® At om™ Processor E6xx Series Datasheet, revision 004.
Specification Changes
Intel® Atom™ Processor E6xx Series
July 20 14 Spec ific ation Update
Document Number: 324209-017US 45
4. Change d VIH and VIL Specifications for RTCRST#, PWROK, and
RSMRST# in “Active Signal DC Characteristics” Table
Issue: The VIH and VIL specifica ti ons are ch an ged to reflect B0 a nd B1 stepping
characteristics.
Old Text:
Table 406. Active Signal DC Chara cteri stics
Symbol
Parameter
Min
Nom
Max
Unit
Notes
RTCRST#,PWROK,RSMRST#
VIH Input high voltage 2.17
VCC33RTC +
0.5 V
VIL
Input low voltage
-0.5
0.68
V
New Text:
Table 406. Active Signal DC Chara cteri stics
Symbol
Parameter
Min
Nom
Max
Unit
Notes
RTCRST#,PWROK,RSMRST#
VIH
Input high voltage 2.0
VCC33RTC +
0.1
V
B1
Stepping
2.17
B0
Stepping
VIL
Input low voltage
-0.5
0.78
V
B1
Stepping
0.68
B0
Stepping
Affected Docs: Table 406 “Active Signal DC Characteristics” of Intel® Atom™ Processor E6xx Series
Datasheet, revision 004.
Specification Clarifications
Intel® Atom™ Processor E6xx Series
Spec ific ation Update July 20 14
46 Document Number: 324209-017US
Specification Clarifications
1. Add Information Related to Memory-Mapp e d Acc esses
Issue: New information is added to Section 5.2 “ Introd uction” related to mem ory-mapped
accesses which cross DWORD boundary and lead to unpredictable process or behav ior.
Old Text:
5.2 Introduction
The Intel® Atom™ Processor E6xx Series contains two sets of software accessible
registers accessed via the host processor I/O address space: Control registers and
intern al conf ig uration r eg isters .
• Control registers are I/O mapped into the processor I/O space that controls access
to PCI and PCI Express* configuration s pa c e.
• Interna l c onfigu r ation regis te r s r e s iding within the processor ar e partitioned in to
nine logical device register sets, one for eac h PCI device listed in T a ble 39. (Thes e
are “logical” devices because they reside w ith in a single phys ica l device.)
The proces s or’ s internal registers (I / O M a pped, Conf igu r a tion a nd PCI Expres s *
Extended Configu ra tion r egis ters ) a r e a c c es s ible by th e host processor. The register s
that reside with in the low er 256 bytes of each device can be accessed as Byte, Word
(16-bit), or DWord (32-bit) qu a ntities, with th e excepti on of CONFIG_ADDRE SS, whic h
can only be accessed as a DWord. All multi-byte n umeric fields u s e little-endian
ordering (i.e., lower address es c ontain the leas t signi fican t parts of the field) . Registers
which r es ide in bytes 256 through 4095 of each device may only be acces s ed using
memory mapped transactions in DWord (32-bit) quantiti e s . Some of the registers
described in this section contain r e s e r ved bits. Thes e bits a r e labeled Res er ved.
Software must deal correctly with fields that are reserved. On reads, software must use
appropria te ma s ks to extr a c t th e defined bits and not rely on res erved bits being a ny
particular value. O n writes, sof tware must ensu r e that the valu es of reserved bit
positions a re pr es er ved. T hat is, the values of reser ved bit p ositions mu s t f ir s t be rea d,
merged w ith the n e w values for other bit posit ions an d then w r itten back.
Note: Softwar e does not need to perf orm r ea d, merge, an d write operations for the
conf iguration address r egister.
In addition to res e r ved bits within a r eg is ter, the processor c ontains addres s location s
in the configuration space of the Host Bridge en tity th a t are mar ked either Reserv ed or
Intel Res er v ed. The processor responds to accesses to reserved address locations by
completing th e host cycle. W hen a Reserv ed r egis ter location is rea d, a zero v a lue is
returned. (Reserv ed r egis ters can be 8, 16, or 32 bits in size). Writes to R es erved
registers have n o effec t on the processor . R egis ters that are mar k ed a s Intel Reserved
must not be modif ied by sy s tem s oftware. W r ites to Intel R es er v ed r egis ters may
cause s ystem failu r e. R ea ds f rom In tel R es er v ed r egisters may return a non-zero
value.
Specification Clarifications
Intel® Atom™ Processor E6xx Series
July 20 14 Spec ific ation Update
Document Number: 324209-017US 47
Upon a Cold Res et, the proc es s or sets all configu r atio n register s to predetermined
default sta tes. Some default register v a lues are determined by ex ter nal strapping
options. The default state r epresents the minim um functionality featur e s e t r equir ed to
successfully bring up the system; it does n ot represen t the optimal syste m
conf iguration . It is the responsibi lity of the system initia lization softw are (u s ually BIOS)
to proper ly deter m ine the DRAM configura tions, oper ating par ameter s and opti onal
system features that are applicable configurati ons, oper ating par a meters and o ptional
system f ea tures that ar e applicable and to pr ogr a m the registers the registers the
system memory accordingly.
New Text:
5.2 Introduction
The Intel® Atom™ Process or E6xx Series contains two sets of s oftwar e accessible
registers accessed via the host processor I/O address space: Control registers and
intern al conf ig uration r eg isters .
• Control registers are I/O mapped into the processor I/O space that controls access
to PCI and PCI Express* configuration s pa c e.
• Internal configu r ation regis ters residing within the proces sor are pa rtitioned into
nine logical device register sets, one for eac h PCI device listed in T a ble 39. (Thes e
are “logical” devices bec a use they r es ide w ith in a single phys ic a l dev ic e. )
The processor’s internal re gister s ( I/O Mapped, Configu r a tion a nd PCI Expr es s *
Extended Configu ra tion r egis ters ) a r e a c c es s ible by th e host processor. The register s
that reside within the lower 256 bytes of ea c h device can be access ed a s By te, Word
(16-bit) , or DWord (32-bit) qua ntities, with the excepti on of CONFIG_ADDRE SS, whic h
can only be accessed as a DWord. All multi-byte n umeric fields u s e little-endian
orderin g ( i.e., lower addre s ses con ta in the lea s t signi fican t parts of the field) . Registers
which r es ide in bytes 256 throu gh 4095 of each device may on ly be accessed using
memory mapped transactions in DWord (32-bit) quantiti e s . Some of the registers
described in this section c ontain r es er ved bits. Th es e bits a r e labeled Res er ved.
Softw are mu s t de a l correctly with fields that a r e r es erved. On r ea ds , sof tware mus t use
appropria te ma s ks to extr a c t th e defined bits and not rely on res erved bits being a ny
particular value. O n writes, sof tware must ensu r e that the va lues of r e s e r ved bit
positions a re pr es er ved. T hat is, the values of rese r ved b it positions mu st first b e r e a d ,
merged w ith the n e w values for other bit posit ions an d then w r itten back.
Note: Softwar e does not need to perf or m rea d, merge, and write opera tion s for the
conf iguration address r egister.
Software must n ot ge nerate configu ration re quests from memory-mapped accesses
that cr oss DWORD boundary , as this w ill result in unpredictable beha vior.
Specification Clarifications
Intel® Atom™ Processor E6xx Series
Spec ific ation Update July 20 14
48 Document Number: 324209-017US
In addition to res e r ved bits within a r eg is ter, the processor c ontains addres s location s
in the configuration s pa c e of the Host B r idge en tity that are m a r k ed either Reserv ed or
Intel Res er v ed. The proces s or r es pon ds to ac c es s es to reserved address locations by
completing th e host cycle. W hen a Reserv ed r egis ter location is rea d, a zero v a lue is
returned. (Reserv ed registers c a n be 8, 16, or 32 bits in s iz e) . Writes to Reserved
registers have n o effec t on the processor . R egis ters that are mar k ed a s Intel Reserved
must not be modif ied by sy s tem s oftware. W r ites to Intel R es er v ed r egis ters may
cause system failure. Reads from Intel Reserved registers may return a non-zero
value.
Upon a Cold Res et, the proc es s or s ets a ll configuration r egis ters to predetermined
default sta tes. Some default register v a lues are determined by ex ter nal strapping
options. The default state r e pr e s ents the m inimum functionality feature set required to
successf ully bring up the sys te m ; it d oes not represent the optim al system
conf iguration . It is the responsibi lity of the system initia lization softw are (u s ually BIOS)
to properly determine the DRA M config uration s , operatin g parameters and optional
system features th a t a re applica ble c onfigu r ations, opera ting para m eters a nd optional
system f ea tures that ar e applicable and to pr ogr a m the registers the registers the
system memory accordingly.
Affected Docs: Intel® Atom™ Processor E6xx Series Da ta s heet Rev003.
§
Documentation Changes
Intel® Atom™ Processor E6xx Series
July 20 14 Spec ific ation Update
Document Number: 324209-017US 49
Documentation Changes
Ther e are no doc umenta tion c hanges in this Spe c ification Update revision.
§