DG534A/538A
Vishay Siliconix
Document Number: 70069
S-05734—Rev. G, 29-Jan-02 www.vishay.com
1
4-/8-Channel W ideband Video Multiplexers
FEATURES BENEFITS APPLICATIONS
DWide Bandwidth: 500 MHz
DVery Low Crosstalk: –97 dB @ 5 MHz
DOn-Board TTL-Compatible Latches with
Readback
DOptional Negative Supply
DLow rDS(on): 45
DSingle-Ended or Differential Operation
DLatch-up Proof
DImproved System Bandwidth
DImproved Channel Off-Isolation
DSimplified Logic Interfacing
DHigh-Speed Readback
DAllows Bipolar Signal Swings
DReduced Insertion Loss
DAllows Differential Signal Switching
DWideband Signal Routing and
Multiplexing
DVideo Switchers
DATE Systems
DInfrared Imaging
DUltrasound Imaging
DESCRIPTION
The DG534A is a digitally selectable 4-channel or dual
2-channel multiplexer. The DG538A is an 8-channel or dual
4-channel multiplexer. On-chip TTL-compatible address
decoding logic and latches with data readback are included to
simplify the interface to a microprocessor data bus. The low
on-resistance and low capacitance of the these devices make
them ideal for wideband data multiplexing and video and audio
signal routing in channel selectors and crosspoint arrays. An
optional negative supply pin allows the handling of bipolar
signals without dc biasing.
The DG534A/DG538A are built on a D/CMOS process that
combines n-channel DMOS switching FETs with low-power
CMOS control logic, drivers and latches. The low-capacitance
DMOS FETs are connected in a “T” configuration to achieve
extremely high levels of off isolation. Crosstalk is reduced to
–97 dB at 5 MHz by including a ground line between adjacent
signal paths. An epitaxial layer prevents latch-up.
For more information refer to Vishay Siliconix applications
note AN502.
FUNCTIONAL BLOCK DIAGRAM AND PIN CONFIGURATION
1
2
3
4
5
6
7
8
20
19
18
17
16
15
14
13
GND NC
DADB
V+ V–
SA1 SB1
GND GND
SA2 SB2
4/2 VL
RS I/O
Dual-In-Line
Top View
912
WR EN
10 11
A1A0
Latches/Drivers
PLCC
14
15
16
17
18
8
7
6
5
4
1231920
111091312
Top View
SA1 SB1
GND GND
SA2 SB2
4/2 VL
RS NC
1
0
EN
I/O
V+
D
GND
D
V–
Latch/Drivers
A
A
A
B
WR
DG534ADN
DG534ADJ
DG534A/538A
Vishay Siliconix
www.vishay.com
2Document Number: 70069
S-05734—Rev. G, 29-Jan-02
FUNCTIONAL BLOCK DIAGRAM AND PIN CONFIGURATION
Latch/Drivers
1
2
3
4
5
6
7
8
28
27
26
25
24
23
22
21
Top View
GND DB
DAV–
V+ SB1
SA1 GND
GND SB2
SA2 GND
GND SB3
SA3 GND
920
GND SB4
Dual-In-Line
10 19
SA4 VL
11
12
18
17
8/4
RS EN
13 16
WR A0
14 15
A2A1
I/O
SA1
SB1
D
D
A
B
RS
0
A1
2
I/O
A
A
WR
Latch/Drivers
PLCC
7
8
9
5
20
19
21
22
23
24
25
1234
10
11
12 13 14 15 16 17 18
262728
Top View
6
GND GND
SA2 SB2
GND GND
SA3 SB3
GND GND
SA4 SB4
8/4 VL
V+
GND
V–EN
DG538ADJ
DG538ADN
TRUTH TABLE Ċ DG534A
I/O A1A0EN WR RS 4/2aOn Switch
X X X X 1 1 Maintains previous state
X X X X X 0 X None (latches cleared)
X X X 0 0 1 X None
0 0 0 1 0 1 0 SA1
0 0 1 1 0 1 0 SA2 DA and DB may be
0 1 0 1 0 1 0 SB1
DA and DB may be
connected externally Latches Transparent
0 1 1 1 0 1 0 SB2
0 X 0 1 0 1 1 SA1 and SB1
0 X 1 1 0 1 1 SA2 and SB2
1Note b 1 1 Note c
Logic “0” = VAL v 0.8 V
Logic “1” = VAH w 2.4 V
X = Don’t Care
DG534A/538A
Vishay Siliconix
Document Number: 70069
S-05734—Rev. G, 29-Jan-02 www.vishay.com
3
TRUTH TABLE Ċ DG538A
I/O A2A1A0EN WR RS 8/4aOn Switch
X X X X X 1 1 Maintains previous state
X X X X X X 0 X None (latches cleared)
X X X X 0 0 1 X None
0 0 0 0 1 0 1 0 SA1
0 0 0 1 1 0 1 0 SA2
0 0 1 0 1 0 1 0 SA3
0 0 1 1 1 0 1 0 SA4 DA and DB should be
0 1 0 0 1 0 1 0 SB1
DA and DB should be
connected externally
0 1 0 1 1 0 1 0 SB2 Latches Transparent
0 1 1 0 1 0 1 0 SB3
0 1 1 1 1 0 1 0 SB4
0 X 0 0 1 0 1 1 SA1 and SB1
0 X 0 1 1 0 1 1 SA2 and SB2
0 X 1 0 1 0 1 1 SA3 and SB3
0 X 1 1 1 0 1 1 SA4 and SB4
1Note b 1 1 Note c
Logic “0” = VAL v 0.8 V
Logic “1” = VAH w 2 V
X = Don’t Care
Notes:
a. Connect DA and DB together externally for single-ended operation.
b. With I/O high, An and EN pins become outputs and reflect latch contents. See timing diagrams for more detail.
c. 8/4 can be either “1” or “0” but should not change during these operations.
ORDERING INFORMATION
Temperature Range Package Part Number
DG534A
_20-Pin Plastic DIP DG534ADJ
–40 to 85_C20-Pin PLCC DG534ADN
–55 to 125_C20-Pin Sidebraze DG534AAP/883, 5962-906021MRC
DG538A
_28-Pin Plastic DIP DG538ADJ
–40 to 85_C28-Pin PLCC DG538ADN
–55 to 125_C28-Pin Sidebraze DG538AAP/883, 5962-8976001MXA
DG534A/538A
Vishay Siliconix
www.vishay.com
4Document Number: 70069
S-05734—Rev. G, 29-Jan-02
ABSOLUTE MAXIMUM RATINGS
V+ to GND –0.3 V to +21 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
V+ to V––0.3 V to +21 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
V– to GND –10 V to +0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VL0 V to (V+) + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Digital Inputs (V–) –0.3 V to (VL) + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
or 20 mA, whichever occurs first
VS, VD(V–) –0.3 V to (V–) + 14 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
or 20 mA, whichever occurs first
Current (any terminal) Continuous 20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current(S or D) Pulsed l ms 10% Duty 40 mA. . . . . . . . . . . . . . . . . . . . . . . . . .
Storage Temperature (A Suffix) –65 to 150_C. . . . . . . . . . . . . . . . . . .
(D Suffix) –65 to 125_C. . . . . . . . . . . . . . . . . . .
Power Dissipation (Package)a
Plastic DIPb625 mW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PLCCc450 mW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Sidebrazed1200 mW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Notes:
a. All leads soldered or welded to PC board.
b. Derate 8.3 mW/_C above 75_C.
c. Derate 6 mW/_C above 75_C.
d. Derate 16 mW/_C above 75_C.
SPECIFICATIONSa
Test Conditions
Unless Otherwise Specified A Suffix
–55 to 125_CD Suffix
–40 to 85_C
Parameter Symbol V+ = 15 V, V– = –3 V, VL = 5 V
WR = 0.8 V, RS, EN= 2 V TempbTypcMindMaxdMindMaxdUnit
Analog Switch
Analog Signal RangegVANALOG V– = –5 V Full –5 8 –5 8 V
Drain-Source
On-Resistance rDS(on) IS = –10 mA, VS = 0 V Room
Full 45 90
120 90
120
Resistance Match
Between Channels rDS(on)
VAIL = 0.8 V, VAIH = 2 V
Sequence Each Switch On Room 9 9
Source Off
Leakage Current IS(off) VS = 8 V, VD = 0 V, EN = 0.8 V Room
Full 0.05 –5
–50 5
50 –5
–50 5
50
Drain Off
Leakage Current ID(off) VS = 0 V, VD = 8 V, EN = 0.8 V Room
Full 0.1 –20
–500 20
500 –20
–100 20
100 nA
Drain On
Leakage Current ID(on) VS = VD = 8 V Room
Full 0.1 –20
–1000 20
1000 –20
–200 20
200
Digital Control
Input Voltage High VAIH Full 2 2
Input Voltage Low VAIL Full 0.8 0.8 V
Address Input Current IAI VAI = 0 V, or 2 V or 5 V Room
Full –0.1 –1
–10 1
10 –1
–10 1
10 A
VAO = 2.7 V Room –21 –2.5 –2.5
Address Output Current IAO VAO = 0.4 V Room 3.5 2.5 2.5 mA
Dynamic Characteristics
On State Input PLCC Room 28 40 40
On State Input
CapacitancegCS(on) See Figure 11 DIP Room 31 45 45
Off State Input PLCC Room 3 5 4
Off State Input
CapacitancegCS(off) DIP Room 4 5 pF
Off State Output See Figure 12 PLCC Room 6 10 8
Off State Output
CapacitancegCD(off) DIP Room 8 10
Transition Time tTRANS Room
Full 160 300
500 300
500
Break-Before-Make
Interval tOPEN
See Figure 4 Room
Full 80 50
25 50
25
EN, WR Turn On Time tON See Figure 2 and 3 Room
Full 150 300
500 300
500
ns
EN, Turn Off Time tOFF See Figure 2 Room
Full 105 175
300 175
300
Charge Injection Qi See Figure 5 Room –70 pC
DG534A/538A
Vishay Siliconix
Document Number: 70069
S-05734—Rev. G, 29-Jan-02 www.vishay.com
5
SPECIFICATIONSa
Test Conditions
Unless Otherwise Specified A Suffix
–55 to 125_CD Suffix
–40 to 85_C
Parameter Symbol V+ = 15 V, V– = –3 V, VL = 5 V
WR = 0.8 V, RS, EN= 2 V TempbTypcMindMaxdMindMaxdUnit
Dynamic Characteristics (Cont’d)
RL = 75 f = 5 MHz PLCC Room –75
Chip Disabled CrosstalkfXTALK(CD) EN = 0.8 V
See Figure 8 DIP Room –65
RIN = 10
RL = 10 kPLCC Room –97
Adjacent Input CrosstalkfXTALK(AI)
RL = 10 k
f = 5 MHz
SeeFigure 9 DIP Room –87
Adjacent Input Crosstalk XTALK(AI) RIN = 75 , RL = 75 PLCC Room –80
f = 5 MHz
See Figure 7 DIP Room –70
RIN = 10
RL = 10 kPLCC Room –77 dB
All Hostile Crosstalk XTALK(AH)
RL = 10 k
f = 5 MHz
See Figure 7 DIP Room –72
All Hostile Crosstalk XTALK(AH) RIN = 75 , RL = 75 PLCC Room –77
f = 5 MHz
See Figure 7 DIP Room –72
RIN = 10 , RL = 10 k
f = 5 MHz, See Figure 10 Room –84
Differential Crosstalk XTALK(DIFF) RIN = RL = 75
f = 5 MHz, See Figure 10 Room –84
Bandwidth BW RL = 50 , See Figure 6 Room 500 MHz
Power Supplies
Positive Supply Current I+ Any One Channel Selected with Ad- Room
Full 0.6 2
52
5
Negative Supply Current I–
Any One Channel Selected with Ad-
dress Inputs at GND or 5 V Room
Full 0.6 –1.8
–2–1.8
–2
mA
V+ to V–Full 10 21 10 21
Functional Check of
Maximum Operating V– to GND Functional Test Only Full –5.5 0 –5.5 0 V
Supply Voltage Range V+ to GND Full 10 21 10 21
Logic Supply Current ILFull 150 500 500 A
Timing
Reset to Write tRW Room
Full –22 50 50
WR, RS
Minimum Pulse Width tMPW Room
Full 60 200 200
A0, A1, EN
Data Valid to Strobe tDW Room
Full 20 100 100
A0, A1, EN
Data Valid after Strobe tWD
See Figure 1 Room
Full –20 50 50
ns
Address Bus Tri-StateetAZ Room 25
Address Bus Output tAO Room 95
Address Bus Input tAI Room 110
Notes:
a. Refer to PROCESS OPTION FLOWCHART.
b. Room = 25_C, Full = as determined by the operating temperature suffix.
c. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
d. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
e. Defined by system bus requirements.
f. Each individual pin shown as GND must be grounded.
g. Guaranteed by design, not subject to production test.
DG534A/538A
Vishay Siliconix
www.vishay.com
6Document Number: 70069
S-05734—Rev. G, 29-Jan-02
CONTROL CIRCUITRY
DADB
Decode
EN
V–
EN
SA1 SA2 SB1 SB2
SA3 SA4 SB3 SB4
WRA2
A1
A0
VL
RS
8/4
VREF
VREF VREF VREF VREF VREF VREF VREF
I/O
A2
A1
A0A2
A1
A0
SA1 – SA4
SB1 – SB4
DA, DB
Latch
I/O
Decode
Tri-State
Buffer
V–
V–
V–
V+ V–
VL
**
*Typical all Readback (AX, EN) pins
VL
DG534A/538A
Vishay Siliconix
Document Number: 70069
S-05734—Rev. G, 29-Jan-02 www.vishay.com
7
TYPICAL CHARACTERISTICS (25_C UNLESS NOTED)
Supply Currents vs. Temperature Leakage vs. Temperature
rDS(on) vs. VD and Temperature Adjacent Input Crosstalk vs. Frequency
Address, EN Output Current vs. Temperature rDS(on) vs. V–, V+
Current (mA)Current (mA)
Leakage
rDS(on)
– Drain-Source On-Resistance ( )
(dB)
TALK(AI)
X
Temperature (_C) Temperature (_C)
Temperature (_C) V– – Negative Supply (V)
VD – Drain Voltage (V) f – Frequency (MHz)
1.4
1.0
0.6
–0.2
–0.6
–1.4
70
60
50
40
30 –6–5–4–3–2–10
–40 –20 0 20 40 60 80 100 120 –40 –20 0 20 40 60 80 100 120
V+ = 15 V
V– = –3 V
VL = 5 V
I+
IS(off)
ID(on)
V+ = 10 V
V+ = 12 V
V+ = 15 V
VD = 0 V
VL = 5 V
IS = –10 mA
8
0
–8
–16
–32 –40 –20 0 20 40 60 80 100 120
0.2
–1.0
V+ = 15 V
V– = –3 V
VL = 5 V
I–
–24
(Source)
IL
1 A
100 nA
10 nA
1 nA
100 pA
10 pA
1 pA
VAO = 0.4 V
VAO = 2.7 V
V+ = 15 V
V– = –3 V
VL = 5 V
200
180
160
140
120
–20 24 6810
100
80
60
40
20
–100
–80
–60
–40
–20
1 10 100
V+ = 15 V
V– = –3 V
VL = 5 V
IS = – 10 mA
V+ = 15 V
V– = –3 V
VL = 5 V
RIN = 10
RL = 10 k
125_C
–55_C
PLCC
DIP
ID(off)
25_C
(Sink)
rDS(on)
– Drain-Source On-Resistance ( )
DG534A/538A
Vishay Siliconix
www.vishay.com
8Document Number: 70069
S-05734—Rev. G, 29-Jan-02
TYPICAL CHARACTERISTICS (25_C UNLESS NOTED)
Adjacent Input Crosstalk vs. Frequency Adjacent Input Crosstalk vs. Frequency
Differential Crosstalk vs. Frequency Differential Crosstalk vs. Frequency
All Hostile Crosstalk vs. Frequency All Hostile Crosstalk vs. Frequency
(dB)
TALK(AI)
X
(dB)
TALK(AI)
X
(dB)
TALK(AH)
X
(dB)
TALK(AH)
X
f – Frequency (MHz) f – Frequency (MHz)
f – Frequency (MHz) f – Frequency (MHz)
f – Frequency (MHz) f – Frequency (MHz)
–100
–80
–60
–40
–20
1 10 100
PLCC DIP
V+ = 15 V
V– = –3 V
VL = 5 V
RIN = RL = 75
–100
–80
–60
–40
–20
1 10 100
PLCC
DIP
V+ = 15 V
V– = –3 V
VL = 5 V
RIN = 10
RL = 10 k
–100
–80
–60
–40
–20
1 10 100
–100
–80
–60
–40
–20
1 10 100
PLCC
DIP
V+ = 15 V
V– = –3 V
VL = 5 V
RIN = 10
RL = 10 k
PLCC
DIP
V+ = 15 V
V– = –3 V
VL = 5 V
RIN = RL = 75
–100
–80
–60
–40
–20
1 10 100
PLCC
DIP
V+ = 15 V
V– = –3 V
VL = 5 V
RIN = 10
RL = 10 k
–100
–80
–60
–40
–20
1 10 100
PLCC
DIP
V+ = 15 V
V– = –3 V
VL = 5 V
RIN = 75
RL = 75
(dB)
TALK(DIFF)
X
(dB)
TALK(DIFF)
X
DG534A/538A
Vishay Siliconix
Document Number: 70069
S-05734—Rev. G, 29-Jan-02 www.vishay.com
9
TYPICAL CHARACTERISTICS (25_C UNLESS NOTED)
Switching Times vs. Temperature Transition Time vs. Temperature
Time (ns)
Time (ns)
Temperature (_C) Temperature (_C)
225
–40 40 120
250
–20 0 20 60 80 100
200
175
150
125
100
75
tTRANS
225
–40 40 120
50 –20 0 20 60 80 100
tBBM
tOFF
tON
200
175
150
125
100
75
OUTPUT TIMING REQUIREMENTS
FIGURE 1.
Don’t Care Write Data Don’t Care
Don’t Care New Data Don’t Care
Driven Bus Hi Z Device Data* Out Hi Z Driven Bus
Writing Data to Device
Delay Time Required after Reset before Write
3 V
0 V
3 V
0 V
3 V
0 V
3 V
0 V
3 V
0 V
3 V
0 V
3 V
0 V
3 V
0 V
Reading Data From Device
WR
RS
A0, A1, A2, EN
I/O
WR
WR
tWD
tMPW
tAZ tAI
tAO
A0, A1, A2, EN
A0, A1, A2, EN
tMPW
tDW
tRW
DG534A/538A
Vishay Siliconix
www.vishay.com
10 Document Number: 70069
S-05734—Rev. G, 29-Jan-02
TEST CIRCUITS
FIGURE 2. EN, CS, CS, Turn On/Off Time
FIGURE 3. WR, Turn On Time
VL
A0
A1, A2
+15 V
EN
V+
V–GND
VO
SBn
SA1 – SBn-1
8/4, 4/2
1 k
+1 V
+5 V
+
10 F100 nF
RS
I/O
+
10 F100 nF
–3 V
WR
45 pF
DA
DB
Logic Input
tr <20 ns
tf <20 ns
EN
VOUT
tOFF
tON
Switch
Output
3 V
0 V 50%
90%
V–
–3 V
VO
1 k
SA1
SA2 – SBn
8/4, 4/2
+1 V
45 pF
DA
DB
EN, VL, RS
A0
+
A1, A2
10 F100 nF
I/O
WR
+
Logic Input
tr <20 ns
tf <20 ns
10 F100 nF
Address
Logic
Logic
Input
+15 V
V+
GND
+5 V +3 V
0 V
WR
VOUT
tON(WR)
A0+3 V
0 V
90%
0 V
DG534A/538A
Vishay Siliconix
Document Number: 70069
S-05734—Rev. G, 29-Jan-02 www.vishay.com
11
TEST CIRCUITS
FIGURE 4. Transition Time and Break-Before-Make Interval
FIGURE 5. Charge Injection
Transition Time
(tTRANS)
VOUT
S1S16
Turning Off Turning On
BBM Interval
A0, A1, A2
50%
90%
3 V
0 V
VO
SB1
1 k
SA1
EN
SA2 – SBn
8/4
or
4/2
45 pF
DA
DB
VL
A0, A1, A2
+
10 F100 nF
RS
I/OWR
Logic Input
tr <20 ns
tf <20 ns
+
10 F100 nF
Logic
Input V–
–3 V
+15 V
V+
GND
+5 V +1 V
EN
VOUT VOUT
VOUT is the measured voltage error due to
charge injection. The charge injection in Cou-
lombs is Q = CL x VOUT
EN
8/4
or
4/2
VO
V+
DA
DB
I/OWR
SBn
A0, A1, A2, RS
+
10 F
+
100 nF
10 F100 nF
CL = 1000 pF
GND V–
–3 V
+15 V
VL
+5 V
DG534A/538A
Vishay Siliconix
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12 Document Number: 70069
S-05734—Rev. G, 29-Jan-02
TEST CIRCUITS
FIGURE 6. Bandwidth
FIGURE 7. All Hostile Crosstalk FIGURE 8. Chip Disabled Crosstalk
VO
DA
SA2 – SBn
A0
to
A2
VL
+
10 F
+
100 nF
10 F100 nF
RS
I/O WR
EN
8/4, 4/2
VIN SA1 50
V–
–3 V
+15 V
V+
GND
+5 V
Note: SA1 on or any other one channel on.
All Channels Off
8/4 or 4/2 = Logic “0”
RL
75
RL
VOUT
DA
DB
SA1
RIN SAn
SB1
SBn
VOUT
DA
DB
SA1
SAn
SB1
SBn
FIGURE 9. Adjacent Input Crosstalk FIGURE 10. Differential Crosstalk
Channels SA1 and SB1 On
4/2 = Logic “1”
Signal
Generator
RL
VOUT
DA
DB
SA1
RIN SAn
SB1
SBn
RIN
10 RL
10 k
RIN
10 W
Sn
Sn+1
VSn–1
VSn
VSn+1
Sn–1
XTALK(AI) +20 log10
VSn –1
VSn or 20 log10
VSn )1
VSn
VRL
XTALK(AH) +20 log10 VOUT
VXTALK(CD) +20 log10 VOUT
V
XTALK(DIFF) +20 log10 VOUT
V
DG534A/538A
Vishay Siliconix
Document Number: 70069
S-05734—Rev. G, 29-Jan-02 www.vishay.com
13
TEST CIRCUITS
Meter
HP4192A
Impedance
Analyzer
or Equivalent
FIGURE 11. On State Input Capacitance FIGURE 12. Off State Input/Output Capacitance
SB1
SA1
EN
8/4
or
4/2
DADB
VL
RS
I/O WR V–
–3 V
V+
GND
+5 V
A0
A2
A1
SAn
SBn
+15 V
SB1
SA1
EN
VL
RS
I/O WR V–
–3 V
V+
GND
+5 V
SA2
SB2
+15 V
8/4 or 4/2 DA
DB
Meter
HP4192A
Impedance
Analyzer
or Equivalent
OPERATING VOLTAGE RANGE
22
21
20
19
18
17
16
15
14
13
12
11
10
–5–4–3–2–1
–5.5 0
Notes:
a. Both V+ and V– must have decoupling capacitors mounted as close as possible to the device pins. Typical decoup-
ling capacitors would be 10-F tantalum bead in parallel with 100-nF ceramic disc.
b. Production tested with V+ = 15 V and V– = –3 V.
a. For VL = 5 V "10%, 0.8- or 2-V TTL compatibility is maintained over the entire operating voltage range.
Allowable Operating Voltage
Area
(Note b)
Positive Supply Voltage
V+ (Volts)
Negative Supply Voltage
V– (Volts)
FIGURE 13.
DG534A/538A
Vishay Siliconix
www.vishay.com
14 Document Number: 70069
S-05734—Rev. G, 29-Jan-02
PIN DESCRIPTION
Pin Number
Symbol DG534ADJ DG538A Description
DA2 2 Analog Output/Input
V+ 3 3 Positive Supply Voltage
SA1 4 4 Analog Input/Output
SA2 6 6 Analog Input/Output
SA3 –8Analog Input/Output
SA4 –10 Analog Input/Output
4/2 7 –4 x 1 or 2 x 2 Select
8/4 –11 8 x 1 or 4 x 2 Select
RS 8 12 Reset
WR 9 13 Write command that latches A, EN
A0, A1, A211, 10, –16, 15, 14 Binary address inputs that determine which channel(s) is/are connected to the out-
put(s)
EN 12 17 Enable. Input/Output, if EN = 0, all channels are open
I/O 13 18 Input/Output control. Used to write to or read from the address latches
VL14 19 Logic Supply Voltage, usually +5 V
SB4 –20 Analog Input/Output
SB3 –22 Analog Input/Output
SB2 15 24 Analog Input/Output
SB1 17 26 Analog Input/Output
V–18 27 Negative Supply Voltage
DB19 28 Analog Output/Input
GND 1, 5, 16 1, 5, 7, 9, 21, 23, 25 Analog and Digital Grounds. All grounds should be connected externally to optimize
dynamic performance
APPLICATIONS
Device Description
The DG534A/538A D/CMOS wideband multiplexers offer
single-ended or differential functions. A 8/4 or 4/2 logic input
pin selects the single-ended or differential mode.
To meet the high dynamic performance demands of video,
high definition TV, digital data routing (in excess of 100 Mbps),
etc., the DG534A/538A are fabricated with DMOS transistors
configured in ‘T’ arrangements with second level ‘L’
configurations (see Functional Block Diagram).
Use of DMOS technology yields devices with very low
capacitance and low rDS(on). This directly relates to improved
high frequency signal handling and higher switching speeds,
while maintaining low insertion loss figures. The ‘T’ and ‘L’
switch configurations further improve dynamic performance
by greatly reducing crosstalk and output node capacitances.
The DG534A/DG538A are improved pin-compatible
replacements for the non-A versions. Improvements include:
higher current readback drivers, readback of the EN bit,
latchup protection
Frequency Response
A single multiplexer on-channel exhibits both resistance
[rDS(on)] and capacitance [CS(on)]. This RC combination
causes a frequency dependent attenuation of the analog
signal. The –3-dB bandwidth of the DG534A/538A is typically
500 MHz (into 50 ). This figure of 500 MHz illustrates that the
switch-channel cannot be represented by a simple RC
combination. The on capacitance of the channel is distributed
along the on-resistance, and hence becomes a more complex
multi-stage network of R’s and C ’s making up the total rDS(on)
and CS(on).
DG534A/538A
Vishay Siliconix
Document Number: 70069
S-05734—Rev. G, 29-Jan-02 www.vishay.com
15
APPLICATIONS (CONT'D)
Power Supplies and Decoupling
A useful feature of the DG534A/538A is its power supply
flexibility. It can be operated from unipolar supplies (V–
connected to 0 V) if required. Allowable operating voltage
ranges are shown in Figure 13.
Note that the analog signal must not go below V– by more than
0.3 V (see absolute maximum ratings). However, the addition
of a V– pin has a number of advantages:
a. It allows flexibility in analog signal handling, i.e. with V– =
–5 V and V+ = 15 V, up to "5 V ac signals can be
accepted.
b. The value of on capacitance (CS(on)) may be reduced by
increasing t he reverse bias across the internal FET body to
source junction. V+ has no effect on CS(on).
It is useful to note that tests indicate that optimum video
differential phase and gain occur when V– is –3 V.
c. V– eliminates the need to bias an ac analog signal using
potential dividers and large decoupling capacitors.
It is established rf design practice to incorporate sufficient
bypass capacitors in the circuit to decouple the power supplies
to all active devices in the circuit. The dynamic performance
of the DG534/538 is adversely affected by poor decoupling of
power supply pins. Also, since the substrate of the device is
connected to the negative supply, proper decoupling of this pin
is essential.
Rules:
a. Decoupling capacitors should be incorporated on all
power supply pins (V+, V–, VL).
b. They should be mounted as close as possible to the
device pins.
c. Capacitors should have good frequency characteristics -
tantalum bead and/or ceramic disc types are suitable.
Recommended decoupling capacitors are 1- to 10-F
tantalum bead, in parallel with 100-nF ceramic or
polyester.
d. Additional high frequency protection may be provided by
51- carbon film resistors connected in series with the
power supply pins (see Figure 14).
Board Layout
PCB layout rules for good high frequency performance must
also be observed to achieve the performance boasted by the
DG534A/538A. Some tips for minimizing stray effects are:
a. Use extensive ground planes on double sided PCB
separating adjacent signal paths. Multilayer PCB is even
better.
b. Keep signal paths as short as practically possible with all
channel paths of near equal length.
c. Use strip-line layout techniques.
Improvements in performance can be obtained by using PLCC
parts instead of DIPs. The stray effects of the quad PLCC
package are lower than those of the dual-in-line packages.
Sockets for the PLCC packages usually increase crosstalk.
DG534A
+5 V +15 V
–3 V
+
++
V–
V+
GND
SA1
SA2
SB1
SB2
DA
DB
C2C1C1C2
51 W 51
51
C1C2
C1 = 1 F Tantalum
C2 = 100 nF Polyester
FIGURE 14. DG534A Power Supply Decoupling
VL
Interfacing
Logic interfacing is easily accomplished. Comprehensive
addressing and control functions are incorporated in the
design.
The V L pin permits interface to various logic types. The device
is primarily designed to be TTL or CMOS logic compatible with
+5 V applied to VL. The actual logic threshold can be raised
simply by increasing VL.
DG534A/538A
Vishay Siliconix
www.vishay.com
16 Document Number: 70069
S-05734—Rev. G, 29-Jan-02
APPLICATIONS (CONT'D)
A typical switching threshold versus VL is shown in Figure 15.
These devices feature an address readback (Tally) facility,
whereby the last address written to the device may be output
to the system. This allows improved status monitoring and
hand shaking without additional external components.
This function is controlled by the I/O pin, which directly
addresses the tri-state buffers connected to the EN and
address pin s . EN a n d address pins can be assigned to accept
data (when I/O = 0; WR = 0; RS = 1), or output data (when I/O =
1; WR = 1; RS = 1), or to reflect a high impedance and latched
state (when I/O = 0; WR = 1; RS = 1).
When I/O is high, the address output can sink or source
current. Note that VL is the logic high output condition. This
point must be respected if VL is varied for input logic threshold
shifting.
Further control pins facilitate easy microprocessor interface.
On chip address, data latches are activated by WR, which
serves as a strobe type function eliminating the need for
peripheral latch or memory I/O port devices. Also, for ease of
interface, a direct reset function (RS) allows all latches to be
cleared and switches opened. Reset should be used during
power up, etc., to avoid spurious switch action. See Figure 1 6.
Channel address data can only be entered during WR low,
when the address latches are transparent and I/O is low.
Similarly, address readback is only operational when WR and
I/O are high.
The Siliconix CLC410 Video amplifier is recommended as an
output buffer to reduce insertion loss and to drive coaxial
cables. For low power video routing applications or for unity
gain input buffers CLC111/CLC114 are recommended.
8
7
6
5
4
3
2
1
0024681012141618
Vth
(V)
VL (V)
FIGURE 15. Switching Threshold Voltage vs. VL
Reset
Address
Decoder
WR
Video
Bus Data
Bus
Address Bus
Data Bus
I/O
75
75
75
75
CLC410
AV = 2
CLC410
CLC410
CLC410
DG534A
DG534A
FIGURE 16. DG534A in a Video Matrix
WR
EN
RS
SA1
SB2
A0, A1DA
DB
EN
WR
RS
SA1
SB2
A0, A1DA
DB
Document Number: 91000 www.vishay.com
Revision: 18-Jul-08 1
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