FSF055D, FSF055R 25A, 60V, 0.020 Ohm, Rad Hard, SEGR Resistant, N-Channel Power MOSFETs June 1998 Features Description * 25A, 60V, rDS(ON) = 0.020 The Discrete Products Operation of Intersil Corporation has developed a series of Radiation Hardened MOSFETs specifically designed for commercial and military space applications. Enhanced Power MOSFET immunity to Single Event Effects (SEE), Single Event Gate Rupture (SEGR) in particular, is combined with 100K RADS of total dose hardness to provide devices which are ideally suited to harsh space environments. The dose rate and neutron tolerance necessary for military applications have not been sacrificed. * Total Dose - Meets Pre-RAD Specifications to 100K RAD (Si) * Single Event - Safe Operating Area Curve for Single Event Effects - SEE Immunity for LET of 36MeV/mg/cm2 with VDS up to 80% of Rated Breakdown and VGS of 10V Off-Bias * Dose Rate - Typically Survives 3E9 RAD (Si)/s at 80% BVDSS - Typically Survives 2E12 if Current Limited to IDM This MOSFET is an enhancement-mode silicon-gate power field-effect transistor of the vertical DMOS (VDMOS) structure. It is specially designed and processed to be radiation tolerant. The MOSFET is well suited for applications exposed to radiation environments such as switching regulation, switching converters, motor drives, relay drivers and drivers for high-power bipolar switching transistors requiring high speed and low gate drive power. This type can be operated directly from integrated circuits. * Photo Current - 6.0nA Per-RAD(Si)/s Typically * Neutron - Maintain Pre-RAD Specifications for 3E13 Neutrons/cm2 - Usable to 3E14 Neutrons/cm2 Ordering Information RAD LEVEL The Intersil portfolio of SEGR resistant radiation hardened MOSFETs includes N-Channel and P-Channel devices in a variety of voltage, current and on-resistance ratings. Numerous packaging options are also available. SCREENING LEVEL PART NUMBER/BRAND 10K Commercial FSF055D1 10K TXV FSF055D3 100K Commercial FSF055R1 100K TXV FSF055R3 100K Space FSF055R4 Reliability screening is available as either commercial, TXV equivalent of MIL-S-19500, or Space equivalent of MIL-S-19500. Contact Intersil's Semiconductor for any desired deviations from the data sheet. Symbol D G Formerly available as type TA17650. S Package TO-254AA G S D CAUTION: Beryllia Warning per MIL-S-19500 refer to package specifications. (c)2001 Fairchild Semiconductor Corporation FSF055D, FSF055R Rev. A FSF055D, FSF055R Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified Drain to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VDS Drain to Gate Voltage (RGS = 20k) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR Continuous Drain Current TC = 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID TC = 100oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM Gate to Source Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VGS Maximum Power Dissipation TC = 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PT TC = 100oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PT Linear Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Single Pulsed Avalanche Current, L = 100H, (See Test Figure). . . . . . . . . . . . . . . . . . . . . . IAS Continuous Source Current (Body Diode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IS Pulsed Source Current (Body Diode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ISM Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TJ , TSTG Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL (Distance >0.063in (1.6mm) from Case, 10s Max) FSF055D, FSF055R 60 60 UNITS V V 25 25 200 20 A A A V 125 50 1.14 200 25 200 -55 to 150 300 W W W/ oC A A A oC oC CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Electrical Specifications TC = 25oC, Unless Otherwise Specified PARAMETER Drain to Source Breakdown Voltage Gate Threshold Voltage SYMBOL BVDSS VGS(TH) TEST CONDITIONS ID = 1mA, VGS = 0V VGS = VDS, ID = 1mA Zero Gate Voltage Drain Current IDSS VDS = 48V, VGS = 0V Gate to Source Leakage Current IGSS VGS = 20V Drain to Source On-State Voltage VDS(ON) Drain to Source On Resistance Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Total Gate Charge rDS(ON)12 td(ON) tr VGS = 12V, ID = 25A ID = 25A, VGS = 12V td(OFF) tf VGS = 0V to 20V Gate Charge at 12V Qg(12) VGS = 0V to 12V Threshold Gate Charge Qg(TH) VGS = 0V to 2V Gate Charge Drain Plateau Voltage TC = 25oC TC = 125oC VDD = 30V, ID = 25A, RL = 1.2, VGS 12V, RGS = 2.35 Qg(TOT) Gate Charge Source TC = -55oC TC = 25oC TC = 125oC TC = 25oC TC = 125oC TC = 25oC TC = 125oC VDD = 30V, ID = 25A Qgs Qgd MIN TYP MAX UNITS 60 - - V - - 5.0 V 1.5 - 4.0 V 0.5 - - V - - 25 A - - 250 A - - 100 nA - - 200 nA - - 0.525 V - 0.014 0.020 - - 0.029 - - 150 ns - - 180 ns - - 140 ns - - 60 ns - - 290 nC - 140 190 nC - - 15 nC - 32 49 nC - 61 89 nC V(PLATEAU) ID = 25A, VDS = 15V - 6 - V VDS = 25V, VGS = 0V, f = 1MHz - 4300 - pF - 2000 - pF Input Capacitance CISS Output Capacitance COSS Reverse Transfer Capacitance CRSS - 500 - pF Thermal Resistance Junction to Case RJC - - 0.88 oC/W Thermal Resistance Junction to Ambient RJA - - 40 oC/W (c)2001 Fairchild Semiconductor Corporation FSF055D, FSF055R Rev. A FSF055D, FSF055R Source to Drain Diode Specifications PARAMETER SYMBOL Forward Voltage VSD Reverse Recovery Time TEST CONDITIONS ISD = 25A MIN TYP MAX 0.6 - 1.8 V - - 290 ns ISD = 25A, dISD/dt = 100A/s trr Electrical Specifications up to 100K RAD PARAMETER UNITS TC = 25oC, Unless Otherwise Specified MIN MAX Drain to Source Breakdown Volts (Note 3) SYMBOL BVDSS VGS = 0, ID = 1mA TEST CONDITIONS 60 - UNITS V Gate to Source Threshold Volts (Note 3) VGS(TH) VGS = VDS , ID = 1mA 1.5 4.0 V Gate to Body Leakage (Notes 2, 3) IGSS VGS = 20V, VDS = 0V - 100 nA Zero Gate Leakage (Note 3) IDSS VGS = 0, VDS = 48V - 25 A Drain to Source On-State Volts (Notes 1, 3) VDS(ON) VGS = 12V, ID = 25A - 0.525 V Drain to Source On Resistance (Notes 1, 3) rDS(ON)12 VGS = 12V, ID = 25A - 0.020 NOTES: 1. Pulse test, 300s Max. 2. Absolute value. 3. Insitu Gamma bias must be sampled for both VGS = 12V, VDS = 0V and VGS = 0V, VDS = 80% BVDSS . Single Event Effects (SEB, SEGR) (Note 4) ENVIRONMENT (NOTE 5) TEST Single Event Effects Safe Operating Area SYMBOL SEESOA ION SPECIES TYPICAL LET (MeV/mg/cm) TYPICAL RANGE () APPLIED VGS BIAS (V) (NOTE 6) MAXIMUM VDS BIAS (V) Ni 26 43 -20 60 Br 37 36 -10 60 Br 37 36 -15 48 Br 37 36 -20 36 I 60 31 0 60 I 60 31 -5 48 I 60 31 -10 36 I 60 31 -15 24 I 60 31 -20 12 NOTES: 4. Testing conducted at Brookhaven National Labs; sponsored by Naval Surface Warfare Center (NSWC), Crane, IN. 5. Fluence = 1E5 ions/cm2 (typical), T = 25oC. 6. Does not exhibit Single Event Burnout (SEB) or Single Event Gate Rupture (SEGR). (c)2001 Fairchild Semiconductor Corporation FSF055D, FSF055R Rev. A FSF055D, FSF055R Typical Performance Curves LET = 26MeV/mg/cm2, RANGE = 43 LET = 37MeV/mg/cm2, RANGE = 36 LET = 60MeV/mg/cm2, RANGE = 31 1E-3 FLUENCE = 1E5 IONS/cm2 (TYPICAL) 60 VDS (V) 50 1 40 30 2 20 3 10 LIMITING INDUCTANCE (HENRY) 12370 Unless Otherwise Specified TEMP = 25oC -10 -5 -15 VGS (V) -20 30A 1E-5 100A 300A 1E-6 -25 30 10 100 1000 300 DRAIN SUPPLY (V) FIGURE 1. SINGLE EVENT EFFECTS SAFE OPERATING AREA FIGURE 2. DRAIN INDUCTANCE REQUIRED TO LIMIT GAMMA DOT CURRENT TO IAS 40 300 TC = 25oC 100 ID , DRAIN CURRENT (A) 30 ID , DRAIN (A) ILM = 10A 1E-7 0 0 1E-4 20 10 0 -50 0 50 100 100s 1ms 10 10ms OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) 1 0.1 150 TC , CASE TEMPERATURE (oC) 100ms 1 100 200 10 VDS , DRAIN TO SOURCE VOLTAGE (V) FIGURE 3. MAXIMUM CONTINUOUS DRAIN CURRENT vs TEMPERATURE FIGURE 4. FORWARD BIAS SAFE OPERATING AREA 2.5 PULSE DURATION = 250ms, VGS = 12V, ID = 25A QGD QGS VG NORMALIZED rDS(ON) 2.0 QG 12V 1.5 1.0 0.5 CHARGE 0.0 -80 -40 0 40 80 120 160 TJ , JUNCTION TEMPERATURE (oC) FIGURE 5. BASIC GATE CHARGE WAVEFORM (c)2001 Fairchild Semiconductor Corporation FIGURE 6. NORMALIZED rDS(ON) vs JUNCTION TEMPERATURE FSF055D, FSF055R Rev. A FSF055D, FSF055R Typical Performance Curves Unless Otherwise Specified (Continued) NORMALIZED THERMAL RESPONSE (ZJC) 10 1 0.5 0.1 0.01 0.2 0.1 0.05 0.02 0.01 PDM SINGLE PULSE 0.001 10-5 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZJC + TC 10-4 10-3 10-2 10-1 t1 t2 100 101 t, RECTANGULAR PULSE DURATION (s) FIGURE 7. NORMALIZED MAXIMUM TRANSIENT THERMAL RESPONSE IAS , AVALANCHE CURRENT (A) 500 STARTING TJ = 25oC 100 STARTING TJ = 150oC IF R = 0 tAV = (L) (IAS) / (1.3 RATED BVDSS - VDD) IF R 0 tAV = (L/R) ln [(IAS*R) / (1.3 RATED BVDSS - VDD) + 1] 10 0.01 0.1 1 tAV , TIME IN AVALANCHE (ms) 10 FIGURE 8. UNCLAMPED INDUCTIVE SWITCHING (c)2001 Fairchild Semiconductor Corporation FSF055D, FSF055R Rev. A FSF055D, FSF055R Test Circuits and Waveforms ELECTRONIC SWITCH OPENS WHEN IAS IS REACHED VDS L BVDSS + CURRENT I TRANSFORMER AS tP - VARY tP TO OBTAIN REQUIRED PEAK IAS VDD 50V-150V DUT tP VDD + 50 VGS 20V 0V VDS IAS 50 tAV FIGURE 9. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 10. UNCLAMPED ENERGY WAVEFORMS tON VDD tOFF td(ON) td(OFF) tr RL VDS tf 90% 90% VDS VGS = 12V 10% DUT 10% 0V 90% RGS 50% VGS 50% PULSE WIDTH 10% FIGURE 11. RESISTIVE SWITCHING TEST CIRCUIT (c)2001 Fairchild Semiconductor Corporation FIGURE 12. RESISTIVE SWITCHING WAVEFORMS FSF055D, FSF055R Rev. A FSF055D, FSF055R Screening Information Screening is performed in accordance with the latest revision in effect of MIL-S-19500, (Screening Information Table). Delta Tests and Limits (JANTXV Equivalent, JANS Equivalent) TC = 25oC, Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS MAX UNITS Gate to Source Leakage Current IGSS VGS = 20V 20 (Note 7) nA Zero Gate Voltage Drain Current IDSS VDS = 80% Rated Value Drain to Source On Resistance rDS(ON) TC = 25oC at Rated ID Gate Threshold Voltage VGS(TH) ID = 1.0mA 25 (Note 7) A 20% (Note 8) 20% (Note 8) V NOTES: 7. Or 100% of Initial Reading (whichever is greater). 8. Of Initial Reading. Screening Information TEST JANTXV EQUIVALENT JANS EQUIVALENT Gate Stress VGS = 30V, t = 250s VGS = 30V, t = 250s Pind Optional Required Pre Burn-In Tests (Note 9) MIL-S-19500 Group A, Subgroup 2 (All Static Tests at 25oC) MIL-S-19500 Group A, Subgroup 2 (All Static Tests at 25oC) Steady State Gate Bias (Gate Stress) MIL-STD-750, Method 1042, Condition B VGS = 80% of Rated Value, TA = 150oC, Time = 48 hours MIL-STD-750, Method 1042, Condition B VGS = 80% of Rated Value, TA = 150oC, Time = 48 hours Interim Electrical Tests (Note 9) All Delta Parameters Listed in the Delta Tests and Limits Table All Delta Parameters Listed in the Delta Tests and Limits Table Steady State Reverse Bias (Drain Stress) MIL-STD-750, Method 1042, Condition A VDS = 80% of Rated Value, TA = 150oC, Time = 160 hours MIL-STD-750, Method 1042, Condition A VDS = 80% of Rated Value, TA = 150oC, Time = 240 hours PDA 10% 5% Final Electrical Tests (Note 9) MIL-S-19500, Group A, Subgroup 2 MIL-S-19500, Group A, Subgroups 2 and 3 NOTE: 9. Test limits are identical pre and post burn-in. Additional Screening Tests PARAMETER Safe Operating Area Unclamped Inductive Switching SYMBOL SOA IAS TEST CONDITIONS MAX UNITS VDS = 48V, t = 10ms 6.8 A VGS(PEAK) = 15V, L = 0.1mH 200 A Thermal Response VSD tH = 100ms; VH = 25V; IH = 4A 130 mV Thermal Impedance VSD tH = 500ms; VH = 25V; IH = 4A 240 mV (c)2001 Fairchild Semiconductor Corporation FSF055D, FSF055R Rev. A FSF055D, FSF055R Rad Hard Data Packages - Intersil Power Transistors TXV Equivalent 1. Rad Hard TXV Equivalent - Standard Data Package A. Certificate of Compliance B. Assembly Flow Chart C. Preconditioning - Attributes Data Sheet E. Preconditioning Attributes Data Sheet Hi-Rel Lot Traveler HTRB - Hi Temp Gate Stress Post Reverse Bias Data and Delta Data HTRB - Hi Temp Drain Stress Post Reverse Bias Delta Data - Attributes Data Sheet F. Group A - Attributes Data Sheet E. Group B - Attributes Data Sheet G. Group B - Attributes Data Sheet F. Group C - Attributes Data Sheet H. Group C - Attributes Data Sheet G. Group D - Attributes Data Sheet I. Group D - Attributes Data Sheet D. Group A 2. Rad Hard TXV Equivalent - Optional Data Package A. Certificate of Compliance 2. Rad Hard Max. "S" Equivalent - Optional Data Package A. Certificate of Compliance B. Assembly Flow Chart B. Serialization Records C. Preconditioning - Attributes Data Sheet - Precondition Lot Traveler - Pre and Post Burn-In Read and Record Data C. Assembly Flow Chart D. Group A - Attributes Data Sheet - Group A Lot Traveler E. Group B - Attributes Data Sheet - Group B Lot Traveler - Pre and Post Read and Record Data for Intermittent Operating Life (Subgroup B3) - Bond Strength Data (Subgroup B3) - Pre and Post High Temperature Operating Life Read and Record Data (Subgroup B6) F. Group C G. Group D - Attributes Data Sheet - Group C Lot Traveler - Pre and Post Read and Record Data for Intermittent Operating Life (Subgroup C6) - Bond Strength Data (Subgroup C6) - Attributes Data Sheet - Group D Lot Traveler - Pre and Post RAD Read and Record Data D. SEM Photos and Report E. Preconditioning - Attributes Data Sheet - Hi-Rel Lot Traveler - HTRB - Hi Temp Gate Stress Post Reverse Bias Data and Delta Data - HTRB - Hi Temp Drain Stress Post Reverse Bias Delta Data - X-Ray and X-Ray Report F. Group A - Attributes Data Sheet - Hi-Rel Lot Traveler - Subgroups A2, A3, A4, A5 and A7 Data G. Group B - Attributes Data Sheet - Hi-Rel Lot Traveler - Subgroups B1, B3, B4, B5 and B6 Data H. Group C - Attributes Data Sheet - Hi-Rel Lot Traveler - Subgroups C1, C2, C3 and C6 Data I. Group D - Attributes Data Sheet - Hi-Rel Lot Traveler - Pre and Post Radiation Data Class S - Equivalents 1. Rad Hard "S" Equivalent - Standard Data Package A. Certificate of Compliance B. Serialization Records C. Assembly Flow Chart D. SEM Photos and Report (c)2001 Fairchild Semiconductor Corporation FSF055D, FSF055R Rev. A FSF055D, FSF055R TO-254AA 3 LEAD JEDEC TO-254AA HERMETIC METAL PACKAGE INCHES A OP E A1 Q H1 D 0.065 R MAX. TYP. L Ob MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A 0.249 0.260 6.33 6.60 - A1 0.040 0.050 1.02 1.27 - Ob 0.035 0.045 0.89 1.14 2, 3 D 0.790 0.800 20.07 20.32 - E 0.535 0.545 13.59 13.84 - e 0.150 TYP 3.81 TYP 4 e1 0.300 BSC 7.62 BSC 4 H1 0.245 0.265 6.23 6.73 - J1 0.140 0.160 3.56 4.06 4 L 0.520 0.560 13.21 14.22 - OP 0.139 0.149 3.54 3.78 - Q 0.110 0.130 2.80 3.30 - NOTES: 1 2 3 e e1 J1 1. These dimensions are within allowable dimensions of Rev. A of JEDEC outline TO-254AA dated 11-86. 2. Add typically 0.002 inches (0.05mm) for solder coating. 3. Lead dimension (without solder). 4. Position of lead to be measured 0.250 inches (6.35mm) from bottom of dimension D. 5. Die to base BeO isolated, terminals to case ceramic isolated. 6. Controlling dimension: Inch. 7. Revision 1 dated 1-93. WARNING! BERYLLIA WARNING PER MIL-S-19500 Packages containing beryllium oxide (BeO) shall not be ground, machined, sandblasted, or subject to any mechanical operation which will produce dust containing any beryllium compound. Packages containing any beryllium compound shall not be subjected to any chemical process (etching, etc.) which will produce fumes containing beryllium or its' compounds. (c)2001 Fairchild Semiconductor Corporation FSF055D, FSF055R Rev. A TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ACExTM BottomlessTM CoolFETTM CROSSVOLTTM DenseTrenchTM DOMETM EcoSPARKTM E2CMOSTM EnSignaTM FACTTM FACT Quiet SeriesTM FAST FASTrTM GlobalOptoisolatorTM GTOTM HiSeCTM ISOPLANARTM LittleFETTM MicroFETTM MICROWIRETM OPTOLOGICTM OPTOPLANARTM PACMANTM POPTM PowerTrench QFETTM QSTM QT OptoelectronicsTM Quiet SeriesTM SILENT SWITCHER SMART STARTTM Star* PowerTM StealthTM SuperSOTTM-3 SuperSOTTM-6 SuperSOTTM-8 SyncFETTM TinyLogicTM UHCTM UltraFETTM VCXTM DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or 2. A critical component is any component of a life support device or system whose failure to perform can systems which, (a) are intended for surgical implant into be reasonably expected to cause the failure of the life the body, or (b) support or sustain life, or (c) whose support device or system, or to affect its safety or failure to perform when properly used in accordance with instructions for use provided in the labeling, can be effectiveness. reasonably expected to result in significant injury to the user. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Product Status Definition Advance Information Formative or In Design This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. Preliminary First Production This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. No Identification Needed Full Production This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only. Rev. H