18-Mbit (512K x 36/1M x 18) Pipelined SRAM
CY7C1380D, CY7C1380F
CY7C1382D, CY7C1382F
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document #: 38-05543 Rev. *E Revised Feburary 07, 2007
Features
• Supports bus operation up to 250 MHz
• Available speed grades are 250, 200, and 167 MHz
• Registered inputs and outputs for pipelined operation
• 3.3V core power supply
• 2.5V or 3.3V IO power supply
• Fast clock-to-output times
— 2.6 ns (for 250 MHz device)
• Provides high-performance 3-1-1-1 access rate
• User selectable burst counter supporting Intel® Pentium®
interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self-timed write
• Asynchronous output enable
• Single cycle chip deselect
• CY7C1380D/CY7C1382D available in JEDEC-standard
Pb-free 100-pin TQFP, Pb-free and non Pb-free 165-ball
FBGA package. CY7C1380F/CY7C1382F available in
Pb-free and non Pb-free 119-ball BGA package
• IEEE 1149.1 JTAG-Compatible Boundary Scan
• ZZ sleep mode option
Functional Description [1]
The CY7C1380D/CY7C1382D/CY7C1380F/CY7C1382F
SRAM integrates 524,288 x 36 and 1,048,576 x 18 SRAM
cells with advanced synchronous peripheral circuitry and a
two-bit counter for internal burst operation. All synchronous
inputs are gated by registers controlled by a positive edge
triggered clock input (CLK). The synchronous inputs include
all addresses, all data inputs, address-pipelining chip enable
(CE1), depth-expansion chip enables (CE2 and CE3 [2]), burst
control inputs (ADSC, ADSP, and ADV), write enables (BWX,
and BWE), and global write (GW). Asynchronous inputs
include the output enable (OE) and the ZZ pin.
Addresses and chip enables are registered at rising edge of
clock when address strobe processor (ADSP) or address
strobe controller (ADSC) are active. Subsequent burst
addresses can be internally generated as they are controlled
by the advance pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate a self-timed write cycle.This part supports byte write
operations (see Pin Definitions on page 6 and Truth Table [4,
5, 6, 7, 8] on page 9 for further details). Write cycles can be one
to two or four bytes wide as controlled by the byte write control
inputs. GW when active LOW causes all bytes to be written.
The CY7C1380D/CY7C1382D/CY7C1380F/CY7C1382F
operates from a +3.3V core power supply while all outputs
operate with a +2.5 or +3.3V power supply. All inputs and
outputs are JEDEC-standard and JESD8-5-compatible.
Selection Guide
250 MHz 200 MHz 167 MHz Unit
Maximum Access Time 2.6 3.0 3.4 ns
Maximum Operating Current 350 300 275 mA
Maximum CMOS Standby Current 70 70 70 mA
Notes:
1. For best practices or recommendations, please refer to the Cypress application note AN1064, SRAM System Design Guidelines on www.cypress.com.
2. CE3, CE2 are for TQFP and 165 FBGA packages only. 119 BGA is offered only in 1 chip enable.
CY7C1380D, CY7C1380F
CY7C1382D, CY7C1382F
Document #: 38-05543 Rev. *E Page 2 of 30
Logic Block Diagram – CY7C1380D/CY7C1380F [3] (512K x 36)
Logic Block Diagram – CY7C1382D/CY7C1382F [3] (1M x 18)
ADDRESS
REGISTER
ADV
CLK BURST
COUNTER
AND
LOGIC
CLR
Q1
Q0
ADSP
ADSC
MODE
BWE
GW
CE
1
CE
2
CE
3
OE
ENABLE
REGISTER
OUTPUT
REGISTERS
SENSE
AMPS
OUTPUT
BUFFERS
E
PIPELINED
ENABLE
INPUT
REGISTERS
A0, A1, A
BW B
BW
C
BW
D
BW
A
MEMORY
ARRAY
DQs
DQP
A
DQP
B
DQP
C
DQP
D
SLEEP
CONTROL
ZZ
A
[1:0]
2
DQ A , DQP
A
BYTE
WRITE REGISTER
DQ B , DQP
B
BYTE
WRITE REGISTER
DQ C , DQP
C
BYTE
WRITE REGISTER
DQ D , DQP D
BYTE
WRITE REGISTER
DQ A , DQP
A
BYTE
WRITE DRIVER
DQ B , DQP
B
BYTE
WRITE DRIVER
DQ C , DQP
C
BYTE
WRITE DRIVER
DQ D ,DQP
D
BYTE
WRITE DRIVER
A0, A1, A ADDRESS
REGISTER
ADV
CLK
BURST
COUNTER AND
LOGIC
Q1
ADSC
BW
B
BW
A
CE
1
DQ
B,
DQP
B
WRITE REGISTER
DQ
A,
DQP
A
WRITE REGISTER
ENABLE
REGISTER
OE
SENSE
MEMORY
ARRAY
2
CE2
CE3
GW
BWE
PIPELINED
ENABLE
DQs
DQP
A
DQP
B
OUTPUT
INPUT
DQ
A,
DQP
A
WRITE DRIVER
OUTPUT
BUFFERS
DQ
B,
DQP
B
WRITE DRIVER
ZZ SLEEP
CONTROL
Note:
3. CY7C1380F and CY7C1382F have only 1 chip enable (CE1).
CY7C1380D, CY7C1380F
CY7C1382D, CY7C1382F
Document #: 38-05543 Rev. *E Page 3 of 30
Pin Configurations
A
A
A
A
A
1
A
0
NC/72M
NC/36M
V
SS
V
DD
A
A
A
A
A
A
A
A
DQP
B
DQ
B
DQ
B
V
DDQ
V
SSQ
DQ
B
DQ
B
DQ
B
DQ
B
V
SSQ
V
DDQ
DQ
B
DQ
B
V
SS
NC
V
DD
ZZ
DQ
A
DQ
A
V
DDQ
V
SSQ
DQ
A
DQ
A
DQ
A
DQ
A
V
SSQ
V
DDQ
DQ
A
DQ
A
DQP
A
DQP
C
DQ
C
DQc
V
DDQ
V
SSQ
DQ
C
DQ
C
DQ
C
DQ
C
V
SSQ
V
DDQ
DQ
C
DQ
C
V
DD
NC
V
SS
DQ
D
DQ
D
V
DDQ
V
SSQ
DQ
D
DQ
D
DQ
D
DQ
D
V
SSQ
V
DDQ
DQ
D
DQ
D
DQP
D
A
A
CE
1
CE
2
BW
D
BW
C
BW
B
BW
A
CE
3
V
DD
V
SS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
MODE
CY7C1380D
(512K X 36)
NC
A
A
A
A
A
1
A
0
NC/72M
NC/36M
V
SS
V
DD
A
A
A
A
A
A
A
A
A
NC
NC
V
DDQ
V
SSQ
NC
DQP
A
DQ
A
DQ
A
V
SSQ
V
DDQ
DQ
A
DQ
A
V
SS
NC
V
DD
ZZ
DQ
A
DQ
A
V
DDQ
V
SSQ
DQ
A
DQ
A
NC
NC
V
SSQ
V
DDQ
NC
NC
NC
NC
NC
NC
V
DDQ
V
SSQ
NC
NC
DQ
B
DQ
B
V
SSQ
V
DDQ
DQ
B
DQ
B
V
DD
NC
V
SS
DQ
B
DQ
B
V
DDQ
V
SSQ
DQ
B
DQ
B
DQP
B
NC
V
SSQ
V
DDQ
NC
NC
NC
A
A
CE
1
CE
2
NC
NC
BW
B
BW
A
CE
3
V
DD
V
SS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
MODE
CY7C1382D
(1 Mbit x 18)
NC
100-pin TQFP Pinout (3 Chip Enable)
A
A
CY7C1380D, CY7C1380F
CY7C1382D, CY7C1382F
Document #: 38-05543 Rev. *E Page 4 of 30
Pin Configurations (continued)
2345671
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
VDDQ
NC/288M
NC/144M
DQPC
DQC
DQD
DQC
DQD
AA AA
ADSP VDDQ
AA
DQC
VDDQ
DQC
VDDQ
VDDQ
VDDQ
DQD
DQD
NC
NC
VDDQ
VDD
CLK
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC/576M
NC/1G
NC
NC
TDOTCKTDITMS
NC/36MNC/72M
NC
VDDQ
VDDQ
VDDQ
AAA
A
A
AA
A
AA
A
A0
A1
DQA
DQC
DQA
DQA
DQA
DQB
DQB
DQB
DQB
DQB
DQB
DQB
DQA
DQA
DQA
DQA
DQB
VDD
DQC
DQC
DQC
VDD
DQD
DQD
DQD
DQD
ADSC
NC
CE1
OE
ADV
GW
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS DQPA
MODE
DQPD
DQPB
BWB
BWC
NC VDD NC
BWA
NC
BWE
BWD
ZZ
2345671
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
VDDQ
NC/288M
NC/144M
NCDQB
DQB
DQB
DQB
AA AA
ADSP VDDQ
AA
NC
VDDQ
NC
VDDQ
VDDQ
VDDQ
NC
NC
NC
NC/72M
VDDQ
VDD
CLK
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC/576M
NC/1G
NC
NC
TDOTCKTDITMS
AA
NC
VDDQ
VDDQ
VDDQ
A NC/36M A
A
A
AA
A
AA
A
A0
A1
DQA
DQB
NC
NC
DQA
NC
DQA
DQA
NC
NC
DQA
NC
DQA
NC
DQA
NC
DQA
VDD
NC
DQB
NC
VDD
DQB
NC
DQB
NC
ADSC
NC
CE1
OE
ADV
GW
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS NC
MODE
DQPB
DQPA
NC
BWB
NC VDD NC
BWA
NC
BWE
NC
ZZ
CY7C1382F (1M x 18)
CY7C1380F (512K x 36)
119-Ball BGA Pinout
CY7C1380D, CY7C1380F
CY7C1382D, CY7C1382F
Document #: 38-05543 Rev. *E Page 5 of 30
Pin Configurations (continued)
165-Ball FBGA Pinout (3 Chip Enable)
CY7C1380D (512K x 36)
234 5671
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
TDO
NC/288M
NC/144M
DQPC
DQC
DQPD
NC
DQD
CE1BWB CE3
BWCBWE
ACE2
DQC
DQD
DQD
MODE
NC
DQC
DQC
DQD
DQD
DQD
NC/36M
NC/72M
VDDQ
BWDBWACLK GW
VSS VSS VSS VSS
VDDQ VSS
VDD VSS
VSS
VSS
A
VSS
VSS
VSS
VDDQ
VDDQ
NC
VDDQ
VDDQ
VDDQ
VDDQ
A
A
VDD VSS
VDD VSS VSS
VDDQ VDD
VSS
VDD
VSS
VDD VSS VSS
VSS
VDD
VDD VSS
VDD VSS VSS
NC
TCK
VSS
TDI
A
A
DQCVSS
DQCVSS
DQC
DQC
NC
VSS
VSS
VSS
VSS
NC
VSS
A1
DQD
DQD
NC
NC
VDDQ
VSS
TMS
891011
A
ADV A
ADSC NC
OE ADSP ANC/576M
VSS VDDQ NC/1G DQPB
VDDQ
VDD DQB
DQB
DQB
NC
DQB
NC
DQA
DQA
VDD VDDQ
VDD VDDQ DQB
VDD
NC
VDD
DQA
VDD VDDQ DQA
VDDQ
VDD
VDD VDDQ
VDD VDDQ DQA
VDDQ
AA
VSS
A
A
A
DQB
DQB
DQB
ZZ
DQA
DQA
DQPA
DQA
A
VDDQ
A
CY7C1382D (1M x 18)
A0
A
VSS
234 5671
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
TDO
NC/288M
NC/144M
NC
NC
DQPB
NC
DQB
ACE1NC CE3
BWBBWE
ACE2
NC
DQB
DQB
MODE
NC
DQB
DQB
NC
NC
NC
NC/36M
NC/72M
VDDQ
NC BWACLK GW
VSS VSS VSS VSS
VDDQ VSS
VDD VSS
VSS
VSS
A
VSS
VSS
VSS
VSS
VDDQ
VDDQ
NC
VDDQ
VDDQ
VDDQ
VDDQ
A
A
VDD VSS
VDD VSS VSS
VDDQ VDD
VSS
VDD
VSS
VDD VSS VSS
VSS
VDD
VDD VSS
VDD VSS VSS
NC
TCKA0
VSS
TDI
A
A
DQBVSS
NC VSS
DQB
NC
NC
VSS
VSS
VSS
VSS
NC
VSS
A1
DQB
NC
NC
NC
VDDQ
VSS
TMS
891011
A
ADV A
ADSC A
OE ADSP ANC/576M
VSS VDDQ NC/1G DQPA
VDDQ
VDD NC
DQA
DQA
NC
NC
NC
DQA
NC
VDD VDDQ
VDD VDDQ DQA
VDD
NC
VDD
NCVDD VDDQ DQA
VDDQ
VDD
VDD VDDQ
VDD VDDQ NC
VDDQ
AA
VSS
A
A
A
DQA
NC
NC
ZZ
DQA
NC
NC
DQA
A
VDDQ
A
CY7C1380D, CY7C1380F
CY7C1382D, CY7C1382F
Document #: 38-05543 Rev. *E Page 6 of 30
Pin Definitions
Name IO Description
A0, A1, A Input-
Synchronous
Address inputs used to select one of the address locations. Sampled at the rising edge of
the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 [2]are sampled active. A1: A0
are fed to the two-bit counter..
BWA, BWB
BWC, BWD
Input-
Synchronous
Byte write select inputs, active LOW. Qualified with BWE to conduct byte writes to the SRAM.
Sampled on the rising edge of CLK.
GW Input-
Synchronous
Global write enable input, active LOW. When asserted LOW on the rising edge of CLK, a
global write is conducted (all bytes are written, regardless of the values on BWX and BWE).
BWE Input-
Synchronous
Byte write enable input, active LOW. Sampled on the rising edge of CLK. This signal must be
asserted LOW to conduct a byte write.
CLK Input-
Clock
Clock input. Used to capture all synchronous inputs to the device. Also used to increment the
burst counter when ADV is asserted LOW, during a burst operation.
CE1Input-
Synchronous
Chip enable 1 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
CE2 and CE3 to select or deselect the device. ADSP is ignored if CE1 is HIGH. CE1 is sampled
only when a new external address is loaded.
CE2 [2] Input-
Synchronous
Chip enable 2 input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction
with CE1 and CE3 to select or deselect the device. CE2 is sampled only when a new external
address is loaded.
CE3 [2] Input-
Synchronous
Chip enable 3 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
CE1 and CE2 to select or deselect the device. CE3 is sampled only when a new external address
is loaded.
OE Input-
Asynchronous
Output enable, asynchronous input, active LOW. Controls the direction of the IO pins. When
LOW, the IO pins behave as outputs. When deasserted HIGH, IO pins are tri-stated, and act as
input data pins. OE is masked during the first clock of a read cycle when emerging from a
deselected state.
ADV Input-
Synchronous
Advance input signal, sampled on the rising edge of CLK, active LOW. When asserted, it
automatically increments the address in a burst cycle.
ADSP Input-
Synchronous
Address strobe from processor, sampled on the rising edge of CLK, active LOW. When
asserted LOW, addresses presented to the device are captured in the address registers. A1: A0
are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is
recognized. ASDP is ignored when CE1 is deasserted HIGH.
ADSC Input-
Synchronous
Address strobe from controller, sampled on the rising edge of CLK, active LOW. When
asserted LOW, addresses presented to the device are captured in the address registers. A1: A0
are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is
recognized.
ZZ Input-
Asynchronous
ZZ sleep input. This active HIGH input places the device in a non-time critical sleep condition
with data integrity preserved. For normal operation, this pin has to be LOW or left floating. ZZ
pin has an internal pull down.
DQs, DQPXIO-
Synchronous
Bidirectional data IO lines. As inputs, they feed into an on-chip data register that is triggered
by the rising edge of CLK. As outputs, they deliver the data contained in the memory location
specified by the addresses presented during the previous clock rise of the read cycle. The
direction of the pins is controlled by OE. When OE is asserted LOW, the pins behave as outputs.
When HIGH, DQs and DQPX are placed in a tri-state condition.
VDD Power Supply Power supply inputs to the core of the device.
CY7C1380D, CY7C1380F
CY7C1382D, CY7C1382F
Document #: 38-05543 Rev. *E Page 7 of 30
Functional Overview
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock.
Maximum access delay from the clock rise (tCO) is 2.6 ns (250
MHz device).
The CY7C1380D/CY7C1382D/CY7C1380F/CY7C1382F
supports secondary cache in systems utilizing a linear or
interleaved burst sequence. The interleaved burst order
supports Pentium® and i486™ processors. The linear burst
sequence is suited for processors that utilize a linear burst
sequence. The burst order is user selectable, and is
determined by sampling the MODE input. Accesses can be
initiated with either the processor address strobe (ADSP) or
the controller address strobe (ADSC). Address advancement
through the burst sequence is controlled by the ADV input. A
two-bit on-chip wraparound burst counter captures the first
address in a burst sequence and automatically increments the
address for the rest of the burst access.
Byte write operations are qualified with the byte write enable
(BWE) and byte write select (BWX) inputs. A global write
enable (GW) overrides all byte write inputs and writes data to
all four bytes. All writes are simplified with on-chip
synchronous self-timed write circuitry.
Three synchronous chip selects (CE1, CE2, CE3) and an
asynchronous output enable (OE) provide for easy bank
selection and output tri-state control. ADSP is ignored if CE1
is HIGH.
Single Read Accesses
This access is initiated when the following conditions are
satisfied at clock rise: (1) ADSP or ADSC is asserted LOW,
(2) CE1, CE2, CE3 are all asserted active, and (3) the write
signals (GW, BWE) are all deserted HIGH. ADSP is ignored if
CE1 is HIGH. The address presented to the address inputs (A)
is stored into the address advancement logic and the address
register while being presented to the memory array. The
corresponding data is allowed to propagate to the input of the
output registers. At the rising edge of the next clock the data
is allowed to propagate through the output register and onto
the data bus within 2.6 ns (250 MHz device) if OE is active
LOW. The only exception occurs when the SRAM is emerging
from a deselected state to a selected state, its outputs are
always tri-stated during the first cycle of the access. After the
first cycle of the access, the outputs are controlled by the OE
signal. Consecutive single read cycles are supported. Once
the SRAM is deselected at clock rise by the chip select and
either ADSP or ADSC signals, its output will tri-state
immediately.
Single Write Accesses Initiated by ADSP
This access is initiated when both of the following conditions
are satisfied at clock rise: (1) ADSP is asserted LOW, and
(2) CE1, CE2, CE3 are all asserted active. The address
VSS Ground Ground for the core of the device.
VSSQ IO Ground Ground for the IO circuitry.
VDDQ IO Power
Supply
Power supply for the IO circuitry.
MODE Input-Static Selects burst order. When tied to GND selects linear burst sequence. When tied to VDD or left
floating selects interleaved burst sequence. This is a strap pin and must remain static during
device operation. Mode pin has an internal pull up.
TDO JTAG serial
output
Synchronous
Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If the JTAG
feature is not being utilized, this pin must be disconnected. This pin is not available on TQFP
packages.
TDI JTAG serial
input
Synchronous
Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature is
not being utilized, this pin can be disconnected or connected to VDD. This pin is not available on
TQFP packages.
TMS JTAG serial
input
Synchronous
Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature is
not being utilized, this pin can be disconnected or connected to VDD. This pin is not available on
TQFP packages.
TCK JTAG-
Clock
Clock input to the JTAG circuitry. If the JTAG feature is not being utilized, this pin must be
connected to VSS. This pin is not available on TQFP packages.
NC – No Connects. 36M, 72M, 144M, 288M, 576M and 1G are address expansion pins and are not
internally connected to the die.
Pin Definitions (continued)
Name IO Description
CY7C1380D, CY7C1380F
CY7C1382D, CY7C1382F
Document #: 38-05543 Rev. *E Page 8 of 30
presented to A is loaded into the address register and the
address advancement logic while being delivered to the
memory array. The write signals (GW, BWE, and BWX) and
ADV inputs are ignored during this first cycle.
ADSP triggered write accesses require two clock cycles to
complete. If GW is asserted LOW on the second clock rise, the
data presented to the DQs inputs is written into the
corresponding address location in the memory array. If GW is
HIGH, then the write operation is controlled by BWE and BWX
signals.
The CY7C1380D/CY7C1382D/CY7C1380F/CY7C1382F
provides byte write capability that is described in the write
cycle descriptions table. Asserting the byte write enable input
(BWE) with the selected byte write (BWX) input, will selectively
write to only the desired bytes. Bytes not selected during a
byte write operation will remain unaltered. A synchronous
self-timed write mechanism has been provided to simplify the
write operations.
The CY7C1380D/CY7C1382D/CY7C1380F/CY7C1382F is a
common IO device, the output enable (OE) must be deserted
HIGH before presenting data to the DQs inputs. Doing so will
tri-state the output drivers. As a safety precaution, DQs are
automatically tri-stated whenever a write cycle is detected,
regardless of the state of OE.
Single Write Accesses Initiated by ADSC
ADSC write accesses are initiated when the following
conditions are satisfied: (1) ADSC is asserted LOW, (2) ADSP
is deserted HIGH, (3) CE1, CE2, CE3 are all asserted active,
and (4) the appropriate combination of the write inputs (GW,
BWE, and BWX) are asserted active to conduct a write to the
desired byte(s). ADSC-triggered Write accesses require a
single clock cycle to complete. The address presented to A is
loaded into the address register and the address
advancement logic while being delivered to the memory array.
The ADV input is ignored during this cycle. If a global write is
conducted, the data presented to the DQs is written into the
corresponding address location in the memory core. If a byte
write is conducted, only the selected bytes are written. Bytes
not selected during a byte write operation will remain
unaltered. A synchronous self-timed write mechanism has
been provided to simplify the write operations.
The CY7C1380D/CY7C1382D/CY7C1380F/CY7C1382F is a
common IO device, the output enable (OE) must be deserted
HIGH before presenting data to the DQs inputs. Doing so will
tri-state the output drivers. As a safety precaution, DQs are
automatically tri-stated whenever a write cycle is detected,
regardless of the state of OE.
Burst Sequences
The CY7C1380D/CY7C1382D/CY7C1380F/CY7C1382F
provides a two-bit wraparound counter, fed by A1: A0, that
implements an interleaved or a linear burst sequence. The
interleaved burst sequence is designed specifically to support
Intel Pentium applications. The linear burst sequence is
designed to support processors that follow a linear burst
sequence. The burst sequence is user selectable through the
MODE input.
Asserting ADV LOW at clock rise will automatically increment
the burst counter to the next address in the burst sequence.
Both read and write burst operations are supported.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation sleep mode. Two
clock cycles are required to enter into or exit from this sleep
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the sleep mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the sleep mode. CE1, CE2, CE3, ADSP, and ADSC must
remain inactive for the duration of tZZREC after the ZZ input
returns LOW.
Interleaved Burst Address Table
(MODE = Floating or VDD)
First
Address
A1: A0
Second
Address
A1: A0
Third
Address
A1: A0
Fourth
Address
A1: A0
00 01 10 11
01 00 11 10
10 11 00 01
11 10 01 00
Linear Burst Address Table (MODE = GND)
First
Address
A1: A0
Second
Address
A1: A0
Third
Address
A1: A0
Fourth
Address
A1: A0
00 01 10 11
01 10 11 00
10 11 00 01
11 00 01 10
ZZ Mode Electrical Characteristics
Parameter Description Test Conditions Min. Max. Unit
IDDZZ Sleep mode standby current ZZ > VDD – 0.2V 80 mA
tZZS Device operation to ZZ ZZ > VDD – 0.2V 2tCYC ns
tZZREC ZZ recovery time ZZ < 0.2V 2tCYC ns
tZZI ZZ Active to sleep current This parameter is sampled 2tCYC ns
tRZZI ZZ Inactive to exit sleep current This parameter is sampled 0 ns
CY7C1380D, CY7C1380F
CY7C1382D, CY7C1382F
Document #: 38-05543 Rev. *E Page 9 of 30
Truth Table [4, 5, 6, 7, 8]
Operation Add. Used CE1CE2CE3ZZ ADSP ADSC ADV WRITE OE CLK DQ
Deselect Cycle, Power Down None H X X L X L X X X L-H Tri-State
Deselect Cycle, Power Down None L L X L L X X X X L-H Tri-State
Deselect Cycle, Power Down None L X H L L X X X X L-H Tri-State
Deselect Cycle, Power Down None L L X L H L X X X L-H Tri-State
Deselect Cycle, Power Down None L X H L H L X X X L-H Tri-State
Sleep Mode, Power Down None X X X H X X X X X X Tri-State
READ Cycle, Begin Burst External L H L L L X X X L L-H Q
READ Cycle, Begin Burst External L H L L L X X X H L-H Tri-State
WRITE Cycle, Begin Burst External L H L L H L X L X L-H D
READ Cycle, Begin Burst External L H L L H L X H L L-H Q
READ Cycle, Begin Burst External L H L L H L X H H L-H Tri-State
READ Cycle, Continue Burst Next X X X L H H L H L L-H Q
READ Cycle, Continue Burst Next X X X L H H L H H L-H Tri-State
READ Cycle, Continue Burst Next H X X L X H L H L L-H Q
READ Cycle, Continue Burst Next H X X L X H L H H L-H Tri-State
WRITE Cycle, Continue Burst Next X X X L H H L L X L-H D
WRITE Cycle, Continue Burst Next H X X L X H L L X L-H D
READ Cycle, Suspend Burst Current X X X L H H H H L L-H Q
READ Cycle, Suspend Burst Current X X X L H H H H H L-H Tri-State
READ Cycle, Suspend Burst Current H X X L X H H H L L-H Q
READ Cycle, Suspend Burst Current H X X L X H H H H L-H Tri-State
WRITE Cycle, Suspend Burst Current X X X L H H H L X L-H D
WRITE Cycle, Suspend Burst Current H X X L X H H L X L-H D
Notes:
4. X = Don't Care, H = Logic HIGH, L = Logic LOW.
5. WRITE = L when any one or more byte write enable signals, and BWE = L or GW = L. WRITE = H when all byte write enable signals, BWE, GW = H.
6. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
7. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BWX. Writes may occur only on subsequent clocks
after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to tri-state. OE is a
don't care for the remainder of the write cycle.
8. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tri-state when OE is
inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW).
CY7C1380D, CY7C1380F
CY7C1382D, CY7C1382F
Document #: 38-05543 Rev. *E Page 10 of 30
Truth Table for Read/Write [4, 9]
Function (CY7C1380D/CY7C1380F) GW BWE BWDBWCBWBBWA
Read HHXXXX
Read HLHHHH
Write Byte A – (DQA and DQPA) HLHHHL
Write Byte B – (DQB and DQPB)HLHHLH
Write Bytes B, A H L H H L L
Write Byte C – (DQC and DQPC) HLHLHH
Write Bytes C, A H L H L H L
Write Bytes C, B H L H L L H
Write Bytes C, B, A H L H L L L
Write Byte D – (DQD and DQPD) HL LHHH
Write Bytes D, A H L L H H L
Write Bytes D, B H L L H L H
Write Bytes D, B, A H L L H L L
Write Bytes D, C H L L L H H
Write Bytes D, C, A H L L L H L
Write Bytes D, C, B HLLLLH
Write All Bytes HLLLLL
Write All Bytes LXXXXX
Truth Table for Read/Write [4, 9]
Function (CY7C1382D/CY7C1382F) GW BWE BWBBWA
Read H H X X
Read H L H H
Write Byte A – (DQA and DQPA)HLHL
Write Byte B – (DQB and DQPB) HLLH
Write Bytes B, A H L L L
Write All Bytes H L L L
Write All Bytes L X X X
Note:
9. Table only lists a partial listing of the byte write combinations. Any combination of BWX is valid. Appropriate write will be done based on which byte write is active.
CY7C1380D, CY7C1380F
CY7C1382D, CY7C1382F
Document #: 38-05543 Rev. *E Page 11 of 30
IEEE 1149.1 Serial Boundary Scan (JTAG)
The CY7C1380D/CY7C1382D incorporates a serial boundary
scan test access port (TAP).This part is fully compliant with
1149.1. The TAP operates using JEDEC-standard 3.3V or
2.5V IO logic levels.
The CY7C1380D/CY7C1382D contains a TAP controller,
instruction register, boundary scan register, bypass register,
and ID register.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(VSS) to prevent clocking of the device. TDI and TMS are
internally pulled up and may be unconnected. They may
alternately be connected to VDD through a pull up resistor.
TDO must be left unconnected. Upon power up, the device will
come up in a reset state which will not interfere with the
operation of the device.
TAP Controller State Diagram
The 0 or 1 next to each state represents the value of TMS at
the rising edge of TCK.
Test Access Port (TAP)
Test Clock (TCK)
The test clock is used only with the TAP controller. All inputs
are captured on the rising edge of TCK. All outputs are driven
from the falling edge of TCK.
Test MODE SELECT (TMS)
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. This pin may be left
unconnected if the TAP is not used. The ball is pulled up
internally, resulting in a logic HIGH level.
Test Data-In (TDI)
The TDI ball is used to serially input information into the
registers and can be connected to the input of any of the
registers. The register between TDI and TDO is chosen by the
instruction that is loaded into the TAP instruction register. TDI
is internally pulled up and can be unconnected if the TAP is
unused in an application. TDI is connected to the most
significant bit (MSB) of any register. (See TAP Controller Block
Diagram.)
Test Data-Out (TDO)
The TDO output ball is used to serially clock data-out from the
registers. The output is active depending upon the current
state of the TAP state machine. The output changes on the
falling edge of TCK. TDO is connected to the least significant
bit (LSB) of any register. (See TAP Controller State Diagram.)
TAP Controller Block Diagram
Performing a TAP Reset
A Reset is performed by forcing TMS HIGH (VDD) for five rising
edges of TCK. This Reset does not affect the operation of the
SRAM and may be performed while the SRAM is operating.
At power up, the TAP is reset internally to ensure that TDO
comes up in a High-Z state.
TAP Registers
Registers are connected between the TDI and TDO balls and
allow data to be scanned in and out of the SRAM test circuitry.
Only one register can be selected at a time through the
instruction register. Data is serially loaded into the TDI ball on
the rising edge of TCK. Data is output on the TDO ball on the
falling edge of TCK.
Instruction Register
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the
TDI and TDO balls as shown in the TAP Controller Block
Diagram. Upon power up, the instruction register is loaded
with the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as
described in the previous section.
TEST-LOGIC
RESET
RUN-TEST/
IDLE
SELECT
DR-SCAN
SELECT
IR-SCAN
CAPTURE-DR
SHIFT-DR
CAPTURE-IR
SHIFT-IR
EXIT1-DR
PAUSE-DR
EXIT1-IR
PAUSE-IR
EXIT2-DR
UPDATE-DR
EXIT2-IR
UPDATE-IR
1
1
1
0
1 1
0 0
1 1
1
0
0
0
0 0
0
0
0 0
1
0
1
1
0
1
0
1
1
1
1 0
Bypass Register
0
Instruction Register
012
Identification Register
012293031 ...
Boundary Scan Register
012..x ...
Selection
Circuitry
Selection
Circuitry
TCK
TMS TAP CONTROLLER
TDI TDO
CY7C1380D, CY7C1380F
CY7C1382D, CY7C1382F
Document #: 38-05543 Rev. *E Page 12 of 30
When the TAP controller is in the Capture-IR state, the two
least significant bits are loaded with a binary ‘01’ pattern to
allow for fault isolation of the board-level serial test data path.
Bypass Register
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between the
TDI and TDO balls. This allows data to be shifted through the
SRAM with minimal delay. The bypass register is set LOW
(VSS) when the BYPASS instruction is executed.
Boundary Scan Register
The boundary scan register is connected to all the input and
bidirectional balls on the SRAM.
The boundary scan register is loaded with the contents of the
RAM input and output ring when the TAP controller is in the
Capture-DR state and is then placed between the TDI and
TDO balls when the controller is moved to the Shift-DR state.
The EXTEST, SAMPLE/PRELOAD, and SAMPLE Z
instructions can be used to capture the contents of the input
and output ring.
The boundary scan order tables show the order in which the
bits are connected. Each bit corresponds to one of the bumps
on the SRAM package. The MSB of the register is connected
to TDI, and the LSB is connected to TDO.
Identification (ID) Register
The ID register is loaded with a vendor-specific 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired
into the SRAM and can be shifted out when the TAP controller
is in the Shift-DR state. The ID register has a vendor code and
other information described in the Identification Register
Definitions on page 15.
TAP Instruction Set
Overview
Eight different instructions are possible with the three bit
instruction register. All combinations are listed in Identification
Codes on page 15. Three of these instructions are listed as
RESERVED and must not be used. The other five instructions
are described in detail below.
Instructions are loaded into the TAP controller during the
Shift-IR state when the instruction register is placed between
TDI and TDO. During this state, instructions are shifted
through the instruction register through the TDI and TDO balls.
To execute the instruction once it is shifted in, the TAP
controller needs to be moved into the Update-IR state.
EXTEST
The EXTEST instruction enables the preloaded data to be
driven out through the system output pins. This instruction also
selects the boundary scan register to be connected for serial
access between the TDI and TDO in the Shift-DR controller
state.
IDCODE
The IDCODE instruction causes a vendor-specific 32-bit code
to be loaded into the instruction register. It also places the
instruction register between the TDI and TDO balls and allows
the IDCODE to be shifted out of the device when the TAP
controller enters the Shift-DR state.
The IDCODE instruction is loaded into the instruction register
upon power up or whenever the TAP controller is given a test
logic reset state.
SAMPLE Z
The SAMPLE Z instruction causes the boundary scan register
to be connected between the TDI and TDO balls when the TAP
controller is in a Shift-DR state. The SAMPLE Z command
places all SRAM outputs into a High-Z state.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When
the SAMPLE/PRELOAD instructions are loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the input and output pins is
captured in the boundary scan register.
The user must be aware that the TAP controller clock can only
operate at a frequency up to 20 MHz, while the SRAM clock
operates more than an order of magnitude faster. As there is
a large difference in the clock frequencies, it is possible that
during the Capture-DR state, an input or output will undergo a
transition. The TAP may then try to capture a signal while in
transition (metastable state). This will not harm the device, but
there is no guarantee as to the value that will be captured.
Repeatable results may not be possible.
To guarantee that the boundary scan register will capture the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller's capture setup plus
hold times (tCS and tCH). The SRAM clock input might not be
captured correctly if there is no way in a design to stop (or
slow) the clock during a SAMPLE/PRELOAD instruction. If this
is an issue, it is still possible to capture all other signals and
simply ignore the value of the CK and CK# captured in the
boundary scan register.
Once the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the
boundary scan register between the TDI and TDO pins.
PRELOAD allows an initial data pattern to be placed at the
latched parallel outputs of the boundary scan register cells
prior to the selection of another boundary scan test operation.
The shifting of data for the SAMPLE and PRELOAD phases
can occur concurrently when required; that is, while data
captured is shifted out, the preloaded data is shifted in.
BYPASS
When the BYPASS instruction is loaded in the instruction
register and the TAP is placed in a Shift-DR state, the bypass
register is placed between the TDI and TDO balls. The
advantage of the BYPASS instruction is that it shortens the
boundary scan path when multiple devices are connected
together on a board.
EXTEST Output Bus Tri-State
IEEE Standard 1149.1 mandates that the TAP controller be
able to put the output bus into a tri-state mode.
The boundary scan register has a special bit located at bit #85
(for 119-BGA package) or bit #89 (for 165-fBGA package).
CY7C1380D, CY7C1380F
CY7C1382D, CY7C1382F
Document #: 38-05543 Rev. *E Page 13 of 30
When this scan cell, called the “extest output bus tri-state,” is
latched into the preload register during the Update-DR state in
the TAP controller, it will directly control the state of the output
(Q-bus) pins, when the EXTEST is entered as the current
instruction. When HIGH, it will enable the output buffers to
drive the output bus. When LOW, this bit will place the output
bus into a High-Z condition.
This bit can be set by entering the SAMPLE/PRELOAD or
EXTEST command, and then shifting the desired bit into that
cell, during the Shift-DR state. During Update-DR, the value
loaded into that shift-register cell will latch into the preload
register. When the EXTEST instruction is entered, this bit will
directly control the output Q-bus pins. Note that this bit is
preset HIGH to enable the output when the device is powered
up, and also when the TAP controller is in the Test-Logic-Reset
state.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
TAP Timing
TAP AC Switching Characteristics Over the Operating Range [10, 11]
Parameter Description Min. Max. Unit
Clock
tTCYC TCK Clock Cycle Time 50 ns
tTF TCK Clock Frequency 20 MHz
tTH TCK Clock HIGH time 20 ns
tTL TCK Clock LOW time 20 ns
Output Times
tTDOV TCK Clock LOW to TDO Valid 10 ns
tTDOX TCK Clock LOW to TDO Invalid 0 ns
Setup Times
tTMSS TMS Setup to TCK Clock Rise 5 ns
tTDIS TDI Setup to TCK Clock Rise 5 ns
tCS Capture Setup to TCK Rise 5 ns
Hold Times
tTMSH TMS Hold after TCK Clock Rise 5 ns
tTDIH TDI Hold after Clock Rise 5 ns
tCH Capture Hold after Clock Rise 5 ns
tTL
Test Clock
(TCK)
Test Mode Select
(TMS)
tTH
Test Data-Out
(TDO)
tCYC
Test Data-In
(TDI)
tTMSH
tTMSS
tTDIH
tTDIS
tTDOX
tTDOV
DON’T CARE UNDEFINED
Notes:
10. tCS and tCH refer to the setup and hold time requirements of latching data from the boundary scan register.
11. Test conditions are specified using the load in TAP AC test conditions. tR/tF = 1ns.
CY7C1380D, CY7C1380F
CY7C1382D, CY7C1382F
Document #: 38-05543 Rev. *E Page 14 of 30
3.3V TAP AC Test Conditions
Input pulse levels .................................................VSS to 3.3V
Input rise and fall times ..................... ..............................1 ns
Input timing reference levels...........................................1.5V
Output reference levels...................................................1.5V
Test load termination supply voltage...............................1.5V
3.3V TAP AC Output Load Equivalent
2.5V TAP AC Test Conditions
Input pulse levels................................................. VSS to 2.5V
Input rise and fall time .....................................................1 ns
Input timing reference levels .................. ......................1.25V
Output reference levels .................. ..............................1.25V
Test load termination supply voltage .................... ........1.25V
2.5V TAP AC Output Load Equivalent
TDO
1.5V
20pF
Z = 50 Ω
O
50Ω
TDO
1.25V
20pF
Z = 50 Ω
O
50Ω
TAP DC Electrical Characteristics And Operating Conditions
(0°C < TA < +70°C; VDD = 3.3V ±0.165V unless otherwise noted) [12]
Parameter Description Test Conditions Min. Max. Unit
VOH1 Output HIGH Voltage IOH = –4.0 mA, VDDQ = 3.3V 2.4 V
IOH = –1.0 mA, VDDQ = 2.5V 2.0 V
VOH2 Output HIGH Voltage IOH = –100 µA VDDQ = 3.3V 2.9 V
VDDQ = 2.5V 2.1 V
VOL1 Output LOW Voltage IOL = 8.0 mA VDDQ = 3.3V 0.4 V
VDDQ = 2.5V 0.4 V
VOL2 Output LOW Voltage IOL = 100 µA VDDQ = 3.3V 0.2 V
VDDQ = 2.5V 0.2 V
VIH Input HIGH Voltage VDDQ = 3.3V 2.0 VDD + 0.3 V
VDDQ = 2.5V 1.7 VDD + 0.3 V
VIL Input LOW Voltage VDDQ = 3.3V –0.3 0.8 V
VDDQ = 2.5V –0.3 0.7 V
IXInput Load Current GND < VIN < VDDQ –5 5 µA
Note:
12. All voltages referenced to VSS (GND).
CY7C1380D, CY7C1380F
CY7C1382D, CY7C1382F
Document #: 38-05543 Rev. *E Page 15 of 30
Identification Register Definitions
Instruction Field
CY7C1380D/CY7C1380F
(512K x 36)
CY7C1382D/CY7C1382F
(1 Mbit x 18) Description
Revision Number (31:29) 000 000 Describes the version number.
Device Depth (28:24) [13] 01011 01011 Reserved for internal use.
Device Width (23:18) 119-BGA 101000 101000 Defines the memory type and
architecture.
Device Width (23:18) 165-FBGA 000000 000000 Defines the memory type and
architecture.
Cypress Device ID (17:12) 100101 010101 Defines the width and density.
Cypress JEDEC ID Code (11:1) 00000110100 00000110100 Allows unique identification of
SRAM vendor.
ID Register Presence Indicator (0) 1 1 Indicates the presence of an ID
register.
Scan Register Sizes
Register Name Bit Size (x36) Bit Size (x18)
Instruction 3 3
Bypass 1 1
ID 32 32
Boundary Scan Order (119-ball BGA package) 85 85
Boundary Scan Order (165-ball FBGA package) 89 89
Identification Codes
Instruction Code Description
EXTEST 000 Captures IO ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM outputs to High-Z state.
IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI and TDO.
This operation does not affect SRAM operations.
SAMPLE Z 010 Captures IO ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM output drivers to a High-Z state.
RESERVED 011 Do Not Use. This instruction is reserved for future use.
SAMPLE/PRELOAD 100 Captures IO ring contents. Places the boundary scan register between TDI and TDO.
Does not affect SRAM operation.
RESERVED 101 Do Not Use. This instruction is reserved for future use.
RESERVED 110 Do Not Use. This instruction is reserved for future use.
BYPASS 111 Places the bypass register between TDI and TDO. This operation does not affect SRAM
operations.
Note:
13. Bit #24 is 1 in the register definitions for both 2.5v and 3.3v versions of this device.
CY7C1380D, CY7C1380F
CY7C1382D, CY7C1382F
Document #: 38-05543 Rev. *E Page 16 of 30
119-Ball BGA Boundary Scan Order [14, 15]
Bit # Ball ID Bit # Ball ID Bit # Ball ID Bit # Ball ID
1H4 23 F6 45 G4 67 L1
2T424E746A468M2
3T5 25 D7 47 G3 69 N1
4T626H748C370P1
5R5 27 G6 49 B2 71 K1
6L528E650B372L2
7R6 29 D6 51 A3 73 N2
8U630C752C274P2
9R731B753A275R3
10 T7 32 C6 54 B1 76 T1
11 P6 33 A6 55 C1 77 R1
12 N7 34 C5 56 D2 78 T2
13 M6 35 B5 57 E1 79 L3
14 L7 36 G5 58 F2 80 R2
15 K6 37 B6 59 G1 81 T3
16 P7 38 D4 60 H2 82 L4
17 N6 39 B4 61 D1 83 N4
18 L6 40 F4 62 E2 84 P4
19 K7 41 M4 63 G2 85 Internal
20 J5 42 A5 64 H1
21 H6 43 K4 65 J3
22 G7 44 E4 66 2K
Notes:
14. Balls which are NC (No Connect) are pre-set LOW.
15. Bit# 85 is pre-set HIGH.
CY7C1380D, CY7C1380F
CY7C1382D, CY7C1382F
Document #: 38-05543 Rev. *E Page 17 of 30
165-Ball BGA Boundary Scan Order [14, 16]
Bit # Ball ID Bit # Ball ID Bit # Ball ID
1 N6 31 D10 61 G1
2N7 32C11 62 D2
3 N10 33 A11 63 E2
4P11 34B11 64 F2
5 P8 35 A10 65 G2
6 R8 36 B10 66 H1
7R9 37A9 67 H3
8P9 38B9 68 J1
9P10 39C10 69 K1
10 R10 40 A8 70 L1
11 R11 41 B8 71 M1
12 H11 42 A7 72 J2
13 N11 43 B7 73 K2
14 M11 44 B6 74 L2
15 L11 45 A6 75 M2
16 K11 46 B5 76 N1
17 J11 47 A5 77 N2
18 M10 48 A4 78 P1
19 L10 49 B4 79 R1
20 K10 50 B3 80 R2
21 J10 51 A3 81 P3
22 H9 52 A2 82 R3
23 H10 53 B2 83 P2
24 G11 54 C2 84 R4
25 F11 55 B1 85 P4
26 E11 56 A1 86 N5
27 D11 57 C1 87 P6
28 G10 58 D1 88 R6
29 F10 59 E1 89 Internal
30 E10 60 F1
Note:
16. Bit# 89 is pre-set HIGH.
CY7C1380D, CY7C1380F
CY7C1382D, CY7C1382F
Document #: 38-05543 Rev. *E Page 18 of 30
Maximum Ratings
Exceeding the maximum ratings may impair the useful life of
the device. For user guidelines, not tested.
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Supply Voltage on VDD Relative to GND ....... –0.3V to +4.6V
Supply Voltage on VDDQ Relative to GND ...... –0.3V to +VDD
DC Voltage Applied to Outputs
in Tri-State........................................... –0.5V to VDDQ + 0.5V
DC Input Voltage ................................... –0.5V to VDD + 0.5V
Current into Outputs (LOW) ........................................ 20 mA
Static Discharge Voltage........................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-up Current .................................................... >200 mA
Operating Range
Range
Ambient
Temperature VDD VDDQ
Commercial 0°C to +70°C 3.3V –5%/+10% 2.5V – 5%
to VDD
Industrial –40°C to +85°C
Electrical Characteristics Over the Operating Range [17, 18]
Parameter Description Test Conditions Min. Max. Unit
VDD Power Supply Voltage 3.135 3.6 V
VDDQ IO Supply Voltage for 3.3V IO 3.135 VDD V
for 2.5V IO 2.375 2.625 V
VOH Output HIGH Voltage for 3.3V IO, IOH = –4.0 mA 2.4 V
for 2.5V IO, IOH = –1.0 mA 2.0 V
VOL Output LOW Voltage for 3.3V IO, IOL = 8.0 mA 0.4 V
for 2.5V IO, IOL = 1.0 mA 0.4 V
VIH Input HIGH Voltage [17] for 3.3V IO 2.0 VDD + 0.3V V
for 2.5V IO 1.7 VDD + 0.3V V
VIL Input LOW Voltage [17] for 3.3V IO –0.3 0.8 V
for 2.5V IO –0.3 0.7 V
IXInput Leakage Current
except ZZ and MODE
GND ≤ VI ≤ VDDQ –5 5 µA
Input Current of MODE Input = VSS –30 µA
Input = VDD 5µA
Input Current of ZZ Input = VSS –5 µA
Input = VDD 30 µA
IOZ Output Leakage Current GND ≤ VI ≤ VDDQ, Output Disabled –5 5 µA
IDD VDD Operating Supply
Current
VDD = Max., IOUT = 0 mA,
f = fMAX = 1/tCYC
4.0-ns cycle, 250 MHz 350 mA
5.0-ns cycle, 200 MHz 300 mA
6.0-ns cycle, 167 MHz 275 mA
ISB1 Automatic CE
Power Down
Current—TTL Inputs
VDD = Max, Device Deselected,
VIN ≥ VIH or VIN ≤ VIL
f = fMAX = 1/tCYC
4.0-ns cycle, 250 MHz 160 mA
5.0-ns cycle, 200 MHz 150 mA
6.0-ns cycle, 167 MHz 140 mA
ISB2 Automatic CE Power
Down Current-CMOS
Inputs
VDD = Max, Device Deselected,
VIN ≤ 0.3V or VIN > VDDQ – 0.3V, f = 0
All speeds 70 mA
ISB3 Automatic CE
Power Down
Current—CMOS Inputs
VDD = Max, Device Deselected, or
VIN ≤ 0.3V or VIN > VDDQ – 0.3V
f = fMAX = 1/tCYC
4.0-ns cycle, 250 MHz 135 mA
5.0-ns cycle, 200 MHz 130 mA
6.0-ns cycle, 167 MHz 125 mA
ISB4 Automatic CE
Power Down
Current—TTL Inputs
VDD = Max, Device Deselected,
VIN ≥ VIH or VIN ≤ VIL, f = 0
All speeds 80 mA
Notes:
17. Overshoot: VIH(AC) < VDD +1.5V (pulse width less than tCYC/2), undershoot: VIL(AC) > –2V (pulse width less than tCYC/2).
18. TPower up: Assumes a linear ramp from 0v to VDD(min.) within 200 ms. During this time VIH < VDD and VDDQ < VDD.
CY7C1380D, CY7C1380F
CY7C1382D, CY7C1382F
Document #: 38-05543 Rev. *E Page 19 of 30
Capacitance [19]
Parameter Description Test Conditions
100 TQFP
Package
119 BGA
Package
165 FBGA
Package Unit
CIN Input Capacitance TA = 25°C, f = 1 MHz,
VDD = 3.3V.
VDDQ = 2.5V
589pF
CCLK Clock Input Capacitance 5 8 9 pF
CIO Input/Output Capacitance 5 8 9 pF
Thermal Resistance [19]
Parameter Description Test Conditions
100 TQFP
Package
119 BGA
Package
165 FBGA
Package Unit
ΘJA Thermal Resistance
(Junction to Ambient)
Test conditions follow standard
test methods and procedures
for measuring thermal
impedance, in accordance with
EIA/JESD51.
28.66 23.8 20.7 °C/W
ΘJC Thermal Resistance
(Junction to Case)
4.08 6.2 4.0 °C/W
AC Test Loads and Waveforms
OUTPUT
R = 317Ω
R = 351Ω
5pF
INCLUDING
JIG AND
SCOPE
(a) (b)
OUTPUT
RL= 50Ω
Z0= 50Ω
V
T
= 1.5V
3.3V ALL INPUT PULSES
VDDQ
GND
90%
10%
90%
10%
≤1 ns ≤1 ns
(c)
OUTPUT
R = 1667Ω
R = 1538Ω
5pF
INCLUDING
JIG AND
SCOPE
(a) (b)
OUTPUT
RL= 50Ω
Z0= 50Ω
VT= 1.25V
2.5V ALL INPUT PULSES
VDDQ
GND
90%
10%
90%
10%
≤1 ns ≤1 ns
(c)
3.3V IO Test Load
2.5V IO Test Load
Note:
19. Tested initially and after any design or process change that may affect these parameters.
CY7C1380D, CY7C1380F
CY7C1382D, CY7C1382F
Document #: 38-05543 Rev. *E Page 20 of 30
Switching Characteristics Over the Operating Range [20, 21]
Parameter Description
250 MHz 200 MHz 167 MHz
UnitMin. Max. Min. Max. Min. Max.
tPOWER VDD(Typical) to the first Access [22] 111 ms
Clock
tCYC Clock Cycle Time 4.0 56 ns
tCH Clock HIGH 1.7 2.0 2.2 ns
tCL Clock LOW 1.7 2.0 2.2 ns
Output Times
tCO Data Output Valid After CLK Rise 2.6 3.0 3.4 ns
tDOH Data Output Hold After CLK Rise 1.0 1.3 1.3 ns
tCLZ Clock to Low-Z [23, 24, 25] 1.0 1.3 1.3 ns
tCHZ Clock to High-Z [23, 24, 25] 2.6 3.0 3.4 ns
tOEV OE LOW to Output Valid 2.6 3.0 3.4 ns
tOELZ OE LOW to Output Low-Z [23, 24, 25] 000 ns
tOEHZ OE HIGH to Output High-Z [23, 24, 25] 2.6 3.0 3.4 ns
Setup Times
tAS Address Setup Before CLK Rise 1.2 1.4 1.5 ns
tADS ADSC, ADSP Setup Before CLK Rise 1.2 1.4 1.5 ns
tADVS ADV Setup Before CLK Rise 1.2 1.4 1.5 ns
tWES GW, BWE, BWX Setup Before CLK Rise 1.2 1.4 1.5 ns
tDS Data Input Setup Before CLK Rise 1.2 1.4 1.5 ns
tCES Chip Enable SetUp Before CLK Rise 1.2 1.4 1.5 ns
Hold Times
tAH Address Hold After CLK Rise 0.3 0.4 0.5 ns
tADH ADSP, ADSC Hold After CLK Rise 0.3 0.4 0.5 ns
tADVH ADV Hold After CLK Rise 0.3 0.4 0.5 ns
tWEH GW, BWE, BWX Hold After CLK Rise 0.3 0.4 0.5 ns
tDH Data Input Hold After CLK Rise 0.3 0.4 0.5 ns
tCEH Chip Enable Hold After CLK Rise 0.3 0.4 0.5 ns
Notes:
20. Timing reference level is 1.5V when VDDQ = 3.3V and is 1.25V when VDDQ = 2.5V.
21. Test conditions shown in (a) of AC Test Loads unless otherwise noted.
22. This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD(minimum) initially before a read or write operation
can be initiated.
23. tCHZ, tCLZ,tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of AC Test Loads and Waveforms on page 19. Transition is measured ± 200
mV from steady-state voltage.
24. At any given voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions.
25. This parameter is sampled and not 100% tested.
CY7C1380D, CY7C1380F
CY7C1382D, CY7C1382F
Document #: 38-05543 Rev. *E Page 21 of 30
Switching Waveforms
Read Cycle Timing [26]
tCYC
tCL
CLK
ADSP
tADH
tADS
ADDRESS
tCH
OE
ADSC
CE
tAH
tAS
A1
tCEH
tCES
GW, BWE,
BWx
Data Out (Q) High-Z
tCLZ
tDOH
tCO
ADV
tOEHZ
tCO
Single READ BURST READ
tOEV
tOELZ tCHZ
ADV
suspends
burst.
Burst wraps around
to its initial state
tADVH
tADVS
tWEH
tWES
tADH
tADS
Q(A2) Q(A2 + 1) Q(A2 + 2)
Q(A1) Q(A2) Q(A2 + 1)Q(A2 + 3)
A2 A3
Deselect
cycle
Burst continued with
new base address
DON’T CARE UNDEFINED
Note:
26. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
CY7C1380D, CY7C1380F
CY7C1382D, CY7C1382F
Document #: 38-05543 Rev. *E Page 22 of 30
Write Cycle Timing [26, 27]
Switching Waveforms (continued)
tCYC
tCL
CLK
ADSP
tADH
tADS
ADDRESS
tCH
OE
ADSC
CE
tAH
tAS
A1
tCEH
tCES
BWE,
BW X
a
ta Out (Q)
High-Z
ADV
BURST READ BURST WRITE
D(A2) D(A2 + 1) D(A2 + 1)
D(A1) D(A3) D(A3 + 1) D(A3 + 2)D(A2 + 3)
A2 A3
Data In (D)
Extended BURST WRITE
D(A2 + 2)
Single WRITE
tADH
tADS
tADH
tADS
tOEHZ
tADVH
t
ADVS
tWEH
tWES
tDH
tDS
GW
tWEH
tWES
Byte write signals are
ignored for first cycle when
ADSP initiates burst
ADSC extends burst
ADV suspends burst
DON’T CARE UNDEFINED
Note:
27. Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BWX LOW.
CY7C1380D, CY7C1380F
CY7C1382D, CY7C1382F
Document #: 38-05543 Rev. *E Page 23 of 30
Read/Write Cycle Timing [26, 28, 29]
Switching Waveforms (continued)
tCYC
tCL
CLK
ADSP
tADH
tADS
ADDRESS
tCH
OE
ADSC
CE
tAH
tAS
A2
tCEH
tCES
BWE,
BW
X
Data Out (Q) High-Z
ADV
Single WRITE
D(A3)
A4 A5 A6
D(A5) D(A6)
Data In (D)
BURST READBack-to-Back READs
High-Z
Q(A2)Q(A1) Q(A4) Q(A4+1) Q(A4+2)
tWEH
tWES
Q(A4+3)
tOEHZ
tDH
tDS
tOELZ
tCLZ
tCO
Back-to-Back
WRITEs
A1
DON’T CARE UNDEFINED
A3
Notes:
28. The data bus (Q) remains in high-Z following a WRITE cycle, unless a new read access is initiated by ADSP or ADSC.
29. GW is HIGH.
CY7C1380D, CY7C1380F
CY7C1382D, CY7C1382F
Document #: 38-05543 Rev. *E Page 24 of 30
ZZ Mode Timing [30, 31]
Switching Waveforms (continued)
tZZ
I
SUPPLY
CLK
ZZ
tZZREC
ALL INPUTS
(except ZZ)
DON’T CARE
IDDZZ
tZZI
tRZZI
Outputs (Q)
High-Z
DESELECT or READ Only
Notes:
30. Device must be deselected when entering ZZ mode. See Truth Table [4, 5, 6, 7, 8] on page 9 for all possible signal conditions to deselect the device.
31. DQs are in high-Z when exiting ZZ sleep mode.
CY7C1380D, CY7C1380F
CY7C1382D, CY7C1382F
Document #: 38-05543 Rev. *E Page 25 of 30
Ordering Information
Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit
www.cypress.com for actual products offered.
Speed
(MHz) Ordering Code
Package
Diagram Part and Package Type
Operating
Range
167 CY7C1380D-167AXC 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free Commercial
CY7C1382D-167AXC
CY7C1380F-167BGC 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)
CY7C1382F-167BGC
CY7C1380F-167BGXC 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Pb-Free
CY7C1382F-167BGXC
CY7C1380D-167BZC 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)
CY7C1382D-167BZC
CY7C1380D-167BZXC 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free
CY7C1382D-167BZXC
CY7C1380D-167AXI 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free Industrial
CY7C1382D-167AXI
CY7C1380F-167BGI 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)
CY7C1382F-167BGI
CY7C1380F-167BGXI 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Pb-Free
CY7C1382F-167BGXI
CY7C1380D-167BZI 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)
CY7C1382D-167BZI
CY7C1380D-167BZXI 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free
CY7C1382D-167BZXI
200 CY7C1380D-200AXC 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free Commercial
CY7C1382D-200AXC
CY7C1380F-200BGC 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)
CY7C1382F-200BGC
CY7C1380F-200BGXC 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Pb-Free
CY7C1382F-200BGXC
CY7C1380D-200BZC 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)
CY7C1382D-200BZC
CY7C1380D-200BZXC 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free
CY7C1382D-200BZXC
CY7C1380D-200AXI 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free Industrial
CY7C1382D-200AXI
CY7C1380F-200BGI 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)
CY7C1382F-200BGI
CY7C1380F-200BGXI 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Pb-Free
CY7C1382F-200BGXI
CY7C1380D-200BZI 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)
CY7C1382D-200BZI
CY7C1380D-200BZXI 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free
CY7C1382D-200BZXI
CY7C1380D, CY7C1380F
CY7C1382D, CY7C1382F
Document #: 38-05543 Rev. *E Page 26 of 30
250 CY7C1380D-250AXC 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free Commercial
CY7C1382D-250AXC
CY7C1380F-250BGC 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)
CY7C1382F-250BGC
CY7C1380F-250BGXC 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Pb-Free
CY7C1382F-250BGXC
CY7C1380D-250BZC 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)
CY7C1382D-250BZC
CY7C1380D-250BZXC 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free
CY7C1382D-250BZXC
CY7C1380D-250AXI 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free Industrial
CY7C1382D-250AXI
CY7C1380F-250BGI 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)
CY7C1382F-250BGI
CY7C1380F-250BGXI 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Pb-Free
CY7C1382F-250BGXI
CY7C1380D-250BZI 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)
CY7C1382D-250BZI
CY7C1380D-250BZXI 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free
CY7C1382D-250BZXI
Ordering Information (continued)
Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit
www.cypress.com for actual products offered.
CY7C1380D, CY7C1380F
CY7C1382D, CY7C1382F
Document #: 38-05543 Rev. *E Page 27 of 30
Package Diagrams
Figure 1. 100-Pin Thin Plastic Quad Flat pack (14 x 20 x 1.4 mm) (51-85050)
NOTE:
1. JEDEC STD REF MS-026
2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH
MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE
3. DIMENSIONS IN MILLIMETERS
BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH
0.30±0.08
0.65
20.00±0.10
22.00±0.20
1.40±0.05
12°±1°
1.60 MAX.
0.05 MIN.
0.60±0.15
0° MIN.
0.25
0°-7°
(8X)
STAND-OFF
R 0.08 MIN.
TYP.
0.20 MAX.
0.15 MAX.
0.20 MAX.
R 0.08 MIN.
0.20 MAX.
14.00±0.10
16.00±0.20
0.10
SEE DETAIL A
DETAIL
A
1
100
30
31 50
51
80
81
GAUGE PLANE
1.00 REF.
0.20 MIN.
SEATING PLANE
51-85050-*B
CY7C1380D, CY7C1380F
CY7C1382D, CY7C1382F
Document #: 38-05543 Rev. *E Page 28 of 30
Figure 2. 119-ball BGA (14 x 22 x 2.4 mm) (51-85115)
Package Diagrams (continued)
51-85115-*B
CY7C1380D, CY7C1380F
CY7C1382D, CY7C1382F
Document #: 38-05543 Rev. *E Page 29 of 30
© Cypress Semiconductor Corporation, 2006-2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for
the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended
to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Intel and Pentium are registered trademarks, and i486 is a trademark of Intel Corporation. All product and company names
mentioned in this document are the trademarks of their respective holders.
Figure 3. 165-ball FBGA (13 x 15 x 1.4 mm) (51-85180)
Package Diagrams (continued)
A
1
PIN 1 CORNER
15.00±0.10
13.00±0.10
7.00
1.00
Ø0.50 (165X)
Ø0.25MCAB
Ø0.05 M C
B
A
0.15(4X)
0.35±0.06
SEATING PLANE
0.53±0.05
0.25 C
0.15 C
PIN 1 CORNER
TOP VIEW
BOTTOM VIEW
2345678910
10.00
14.00
B
C
D
E
F
G
H
J
K
L
M
N
11
1110986754321
P
R
P
R
K
M
N
L
J
H
G
F
E
D
C
B
A
A
15.00±0.10
13.00±0.10
B
C
1.00
5.00
0.36
-0.06
+0.14
1.40 MAX.
SOLDER PAD TYPE : NON-SOLDER MASK DEFINED (NSMD)
NOTES :
PACKAGE WEIGHT : 0.475g
JEDEC REFERENCE : MO-216 / DESIGN 4.6C
PACKAGE CODE : BB0AC
51-85180-*A
165 FBGA 13 x 15 x 1.40 MM BB165D/BW165D
A
1
PIN 1 CORNER
15.00±0.10
13.00±0.10
7.00
1.00
Ø0.50 (165X)
Ø0.25 M C A B
Ø0.05 M C
B
A
0.15(4X)
0.35±0.06
SEATING PLANE
0.53±0.05
0.25 C
0.15 C
PIN 1 CORNER
TOP VIEW
BOTTOM VIEW
2345678910
10.00
14.00
B
C
D
E
F
G
H
J
K
L
M
N
11
1110986754321
P
R
P
R
K
M
N
L
J
H
G
F
E
D
C
B
A
A
15.00±0.10
13.00±0.10
B
C
1.00
5.00
0.36
-0.06
+0.14
1.40 MAX.
SOLDER PAD TYPE : NON-SOLDER MASK DEFINED (NSMD)
NOTES :
PACKAGE WEIGHT : 0.475g
JEDEC REFERENCE : MO-216 / DESIGN 4.6C
PACKAGE CODE : BB0AC
51-85180-*A
CY7C1380D, CY7C1380F
CY7C1382D, CY7C1382F
Document #: 38-05543 Rev. *E Page 30 of 30
Document History Page
Document Title: CY7C1380D/CY7C1382D/CY7C1380F/CY7C1382F, 18-Mbit (512K x 36/1M x 18) Pipelined SRAM
Document Number: 38-05543
REV. ECN NO. Issue Date
Orig. of
Change Description of Change
** 254515 See ECN RKF New data sheet
*A 288531 See ECN SYT Edited description under “IEEE 1149.1 Serial Boundary Scan (JTAG)” for
non-compliance with 1149.1
Removed 225MHz and 133 MHz Speed Bins
Added Pb-free information for 100-Pin TQFP, 119 BGA and 165 FBGA Packages
Added comment of ‘Pb-free BG packages availability’ below the Ordering Infor-
mation
*B 326078 See ECN PCI Address expansion pins/balls in the pinouts for all packages are modified as per
JEDEC standard
Added description on EXTEST Output Bus Tri-State
Changed description on the Tap Instruction Set Overview and Extest
Changed Device Width (23:18) for 119-BGA from 000000 to 101000
Added separate row for 165 -FBGA Device Width (23:18)
Changed ΘJA and ΘJC for TQFP Package from 31 and 6 °C/W to 28.66 and 4.08
°C/W respectively
Changed ΘJA and ΘJC for BGA Package from 45 and 7 °C/W to 23.8 and 6.2 °C/W
respectively
Changed ΘJA and ΘJC for FBGA Package from 46 and 3 °C/W to 20.7 and 4.0 °C/W
respectively
Modified VOL, VOH test conditions
Removed comment of ‘Pb-free BG packages availability’ below the Ordering Infor-
mation
Updated Ordering Information Table
*C 416321 See ECN NXR Converted from Preliminary to Final
Changed address of Cypress Semiconductor Corporation on Page# 1 from “3901
North First Street” to “198 Champion Court”
Changed the description of IX from Input Load Current to Input Leakage Current
on page# 18
Changed the IX current values of MODE on page # 18 from –5 µA and 30 µA
to –30 µA and 5 µA
Changed the IX current values of ZZ on page # 18 from –30 µA and 5 µA
to –5 µA and 30 µA
Changed VIH < VDD to VIH < VDDon page # 18
Replaced Package Name column with Package Diagram in the Ordering
Information table
Updated Ordering Information Table
*D 475009 See ECN VKN Added the Maximum Rating for Supply Voltage on VDDQ Relative to GND
Changed tTH, tTL from 25 ns to 20 ns and tTDOV from 5 ns to 10 ns in TAP AC
Switching Characteristics table.
Updated the Ordering Information table.
*E 776456 See ECN VKN Added Part numbers CY7C1380F and CY7C1382F and its related information
Added footnote# 3 regarding Chip Enable
Updated Ordering Information table
