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LM3150

VCC

PGND

SGND

BST

ILIM

CIN

CSS

VIN VIN

RON

COUT

VOUT

CBST

CVCC VIN

RLIM RFB2

RFB1

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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

LM3150

SNVS561G –SEPTEMBER 2008–REVISED SEPTEMBER 2015

LM3150 Wide-VIN Synchronous Buck Controller

1 Features

1• PowerWise™ Step-Down Controller

• 6-V to 42-V Wide Input Voltage Range

• Adjustable Output Voltage Down to 0.6 V

• Programmable Switching Frequency up to 1 MHz

• No Loop Compensation Required

• Fully WEBENCH®Enabled

• Low External Component Count

• Constant On-Time (COT) Control

• Ultra-Fast Transient Response

• Stable With Low ESR Capacitors

• Output Voltage PreBias Startup

• Valley Current Limit

• Programmable Soft-Start

• Create a Custom Design Using the LM3150 with

the WEBENCH Power Designer

2 Applications

• Telecom

• Networking Equipment

• Routers

• Security Surveillance

• Power Modules

3 Description

The LM3150 SIMPLE SWITCHER®controller is an

easy-to-use and simplified step-down power

controller capable of providing up to 12 A of output

current in a typical application. Operating with an

input voltage range of 6 V to 42 V, the LM3150

controller features an adjustable output voltage down

to 0.6 V. The switching frequency is adjustable up to

1 MHz and the synchronous architecture provides for

highly efficient designs. The LM3150 controller

employs a constant on-time (COT) architecture with a

proprietary emulated ripple mode (ERM) control that

allows for the use of low ESR output capacitors,

which reduces overall solution size and output

voltage ripple. The COT regulation architecture allows

for fast transient response and requires no loop

compensation, which reduces external component

count and reduces design complexity.

Fault protection features such as thermal shutdown,

undervoltage lockout, overvoltage protection, short-

circuit protection, current limit, and output voltage

prebias start-up allow for a reliable and robust

solution.

The LM3150 concept provides for an easy-to-use

complete design using a minimum number of external

components and TI’s WEBENCH online design tool.

WEBENCH provides design support for every step of

the design process and includes features such as

external component calculation with a new MOSFET

selector, electrical simulation, thermal simulation, and

Build-It boards for prototyping.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)

LM3150 HTSSOP (14) 5.00 mm × 4.40 mm

(1) For all available packages, see the orderable addendum at

the end of the datasheet.

4 Typical Application Schematic

LM3150

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Table of Contents

1 Features.................................................................. 1

2 Applications ........................................................... 1

3 Description............................................................. 1

4 Typical Application Schematic............................. 1

5 Revision History..................................................... 2

6 Pin Configuration and Functions......................... 3

7 Specifications......................................................... 4

7.1 Absolute Maximum Ratings ...................................... 4

7.2 ESD Ratings.............................................................. 4

7.3 Recommended Operating Ratings............................ 4

7.4 Thermal Information.................................................. 4

7.5 Electrical Characteristics........................................... 5

7.6 Typical Characteristics.............................................. 7

8 Detailed Description.............................................. 9

8.1 Overview................................................................... 9

8.2 Functional Block Diagram....................................... 10

8.3 Feature Description................................................. 10

8.4 Device Functional Modes........................................ 13

9 Application and Implementation ........................ 14

9.1 Application Information............................................ 14

9.2 Typical Application.................................................. 14

10 Power Supply Recommendations ..................... 25

11 Layout................................................................... 25

11.1 Layout Guidelines ................................................. 25

11.2 Layout Example .................................................... 26

12 Device and Documentation Support................. 27

12.1 Documentation Support ....................................... 27

12.2 Community Resources.......................................... 27

12.3 Trademarks........................................................... 27

12.4 Electrostatic Discharge Caution............................ 27

12.5 Glossary................................................................ 28

13 Mechanical, Packaging, and Orderable

Information........................................................... 28

5 Revision History

Changes from Revision F (December 2014) to Revision G Page

• Changed graphic Inductor Current to Current Limit section. ............................................................................................... 11

Changes from Revision E (November 2012) to Revision F Page

• Added ESD Ratings table, Feature Description section, Device Functional Modes,Application and Implementation

section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and

Mechanical, Packaging, and Orderable Information section ................................................................................................. 4

411

VCC

SGND

PGND

RON

SGND

ILIM

BST

VIN

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6 Pin Configuration and Functions

HTSSOP PWP

14 PINS

Top View

Pin Functions

PIN I/O DESCRIPTION FUNCTION

NAME NO.

VCC 1 O Supply Voltage for FET

Drivers Nominally regulated to 5.95 V. Connect a 1.0-µF to 4.7-µF decoupling

capacitor from this pin to ground.

VIN 2 I Input Supply Voltage Supply pin to the device. Nominal input range is 6 V to 42 V.

EN 3 I Enable To enable the IC, apply a logic high signal to this pin greater than 1.26-V

typical or leave floating. To disable the part, ground the EN pin.

FB 4 I Feedback Internally connected to the regulation, overvoltage, and short-circuit

comparators. The regulation setting is 0.6 V at this pin. Connect to feedback

resistor divider between the output and ground to set the output voltage.

SGND 5,9 — Signal Ground Ground for all internal bias and reference circuitry. Should be connected to

PGND at a single point.

SS 6 I Soft-Start An internal 7.7-µA current source charges an external capacitor to provide the

soft-start function.

RON 7 I On-time Control An external resistor from VIN to this pin sets the high-side switch on-time.

ILIM 8 I Current Limit Monitors current through the low-side switch and triggers current limit

operation if the inductor valley current exceeds a user defined value that is set

by RLIM and the Sense current, ILIM-TH, sourced out of this pin during operation.

SW 10 O Switch Node Switch pin of controller and high-gate driver lower supply rail. A boost

capacitor is also connected between this pin and BST pin

HG 11 O High-Side Gate Drive Gate drive signal to the high-side NMOS switch. The high-side gate driver

voltage is supplied by the differential voltage between the BST pin and SW

pin.

BST 12 I Connection for Bootstrap

Capacitor High-gate driver upper supply rail. Connect a 0.33 to 0.47-µF capacitor from

SW pin to this pin. An internal diode charges the capacitor during the high-side

switch off-time. Do not connect to an external supply rail.

LG 13 O Low-Side Gate Drive Gate drive signal to the low-side NMOS switch. The low-side gate driver

voltage is supplied by VCC.

PGND 14 G Power Ground Synchronous rectifier MOSFET source connection. Tie to power ground plane.

Should be tied to SGND at a single point.

EP — — Exposed Pad Exposed die attach pad should be connected directly to SGND. Also used to

help dissipate heat out of the IC.

LM3150

SNVS561G –SEPTEMBER 2008–REVISED SEPTEMBER 2015

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(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Ratings. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and

specifications.

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) (1)(2)

MIN MAX UNIT

VIN, RON to GND –0.3 47 V

SW to GND –3 47 V

BST to SW –0.3 7 V

BST to GND –0.3 52 V

All Other Inputs to GND –0.3 7 V

Tstg Storage temperature –65 150 °C

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

7.2 ESD Ratings VALUE UNIT

V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) ±2000 V

7.3 Recommended Operating Ratings

over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT

VIN 6 42 V

Junction Temperature Range (TJ)−40 125 °C

EN 0 5 V

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

7.4 Thermal Information

THERMAL METRIC(1) LM3150

UNITPWP

14 PINS

RθJA Junction-to-ambient thermal resistance 42.5

°C/W

RθJC(top) Junction-to-case (top) thermal resistance 28.7

RθJB Junction-to-board thermal resistance 24.2

ψJT Junction-to-top characterization parameter 0.9

ψJB Junction-to-board characterization parameter 23.9

RθJC(bot) Junction-to-case (bottom) thermal resistance 4.4

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(1) VCC provides self bias for the internal gate drive and control circuits. Device thermal limitations limit external loading.

(2) See Detailed Description section for minimum on-time when using MOSFETs connected to gate drivers.

7.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS TJ= 25°C TJ= -40°C to 125°C UNIT

MIN TYP MAX MIN TYP MAX

START-UP; REGULATOR, VCC

VCC CVCC = 1 µF, 0 mA to 40

mA 5.95 5.65 6.25 V

VIN - VCC VIN - VCC Dropout Voltage IVCC = 2 mA, VIN = 5.5 V 40 mV

IVCC = 30 mA, VIN = 5.5 V 330

IVCCL VCC Current Limit(1) VCC = 0V 100 65 mA

VCCUVLO VCC Undervoltage Lockout

Threshold (UVLO) VCC Increasing 5.1 4.75 5.40 V

VCCUVLO-HYS VCC UVLO Hysteresis VCC Decreasing 475 mV

tCC-UVLO-D VCC UVLO Filter Delay 3 µs

IIN Input Operating Current No Switching, VFB = 1 V 3.5 5 mA

IIN-SD Input Operating Current,

Device Shutdown VEN = 0 V 32 55 µA

GATE DRIVE

IQ-BST Boost Pin Leakage VBST – VSW = 6 V 2 nA

RDS-HG-Pull-Up HG Drive Pullip On-

Resistance IHG Source = 200 mA 5 Ω

RDS-HG-Pull-

Down HG Drive Pulldown On-

Resistance IHG Sink = 200 mA 3.4 Ω

RDS-LG-Pull-Up LG Drive Pullup On-

Resistance ILG Source = 200 mA 3.4 Ω

RDS-LG-Pull-

Down LG Drive Pulldown On-

Resistance ILG Sink = 200 mA 2 Ω

SOFT-START

ISS SS Pin Source Current VSS = 0 V 7.7 5.9 9.5 µA

ISS-DIS SS Pin Discharge Current Current Limit 200 µA

ILIM-TH Current Limit Sense Pin

Source Current 75 85 95 µA

ON/OFF TIMER

tON ON Timer Pulse Width

VIN = 10V, RON = 100 kΩ,

VFB = 0.6V 1.02

µs

VIN = 18V, RON = 100 kΩ,

VFB = 0.6 V 0.62

VIN = 42 V, RON = 100 kΩ,

VFB = 0.6 V 0.36

tON-MIN ON Timer Minimum Pulse

Width See(2) 200 ns

tOFF OFF Timer Minimum Pulse

Width 370 525 ns

ENABLE INPUT

VEN EN Pin Input Threshold Trip

Point VEN Rising 1.20 1.14 1.26 V

VEN-HYS EN Pin Threshold Hysteresis VEN Falling 120 mV

REGULATION AND OVERVOLTAGE COMPARATOR

VFB In-Regulation Feedback

Voltage VSS > 0.6 V 0.600 0.588 0.612 V

VFB-OV Feedback Overvoltage

Threshold 0.720 0.690 0.748 V

IFB Feedback Bias Current 20 nA

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Electrical Characteristics (continued)

over operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS TJ= 25°C TJ= -40°C to 125°C UNIT

MIN TYP MAX MIN TYP MAX

BOOST DIODE

VfForward Voltage IBST = 2 mA 0.7 V

IBST = 30 mA 1

THERMAL CHARACTERISTICS

TSD Thermal Shutdown Rising 165 °C

Thermal Shutdown Hysteresis Falling 15 °C

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7.6 Typical Characteristics

Figure 1. 500-kHz Full Load Transient Figure 2. 500-kHz Partial Load Transient

Figure 3. Boost Diode Forward Voltage vs Temperature Figure 4. ILIM-TH vs Temperature

Figure 5. Quiescent Current vs Temperature Figure 6. Soft-Start Current vs Temperature

LM3150

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Typical Characteristics (continued)

Figure 7. tON vs Temperature Figure 8. tON vs Temperature

Figure 9. tON vs Temperature Figure 10. VCC Current Limit vs Temperature

Figure 11. VCC Dropout vs Temperature Figure 12. VCC vs Temperature

fS = VOUT

K x RON

D = tON

tON + tOFF = tON x fS |VOUT

VIN

RON = K x fS

VOUT

tON = K x RON

VIN

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8 Detailed Description

8.1 Overview

The LM3150 synchronous step-down controller uses a COT architecture which is a derivative of the hysteretic

control scheme. COT relies on a fixed switch on-time to regulate the output. The on-time of the high-side switch

can be set manually by adjusting the size of an external resistor (RON). To maintain a relatively constant

switching frequency as VIN varies, the LM3150 controller automatically adjusts the on-time inversely with the

input voltage. Assuming an ideal system and VIN is much greater than 1 V, the following approximations can be

made:

The on-time, tON:

where

• constant K = 100 pC (1)

The RON resistance value can be calculated as follows:

where

• fsis the desired switching frequency (2)

Control is based on a comparator and the on-timer, with the output voltage feedback (FB) compared with an

internal reference of 0.6 V. If the FB level is below the reference, the high-side switch is turned on for a fixed

time, tON, which is determined by the input voltage and the resistor RON. Following this on-time, the switch

remains off for a minimum off-time, tOFF, as specified in the Electrical Characteristics table or until the FB pin

voltage is below the reference, then the switch turns on again for another on-time period. The switching will

continue in this fashion to maintain regulation. During continuous conduction mode (CCM), the switching

frequency ideally depends on duty-cycle and on-time only. In a practical application however, there is a small

delay in the time that the HG goes low and the SW node goes low that also affects the switching frequency that

is accounted for in the typical application curves. The duty-cycle and frequency can be approximated as:

(3)

(4)

Typical COT hysteretic controllers need a significant amount of output capacitor ESR to maintain a minimum

amount of ripple at the FB pin in order to switch properly and maintain efficient regulation. The LM3150

controller, however, uses a proprietary Emulated Ripple Mode control scheme (ERM) that allows the use of low

ESR output capacitors. Not only does this reduce the need for high output capacitor ESR, but also significantly

reduces the amount of output voltage ripple seen in a typical hysteretic control scheme. The output ripple voltage

can become so low that it is comparable to voltage-mode and current-mode control schemes.

VOUT = VFB x (RFB1 + RFB2)

RFB1

CBST

BST

ON TIMER

Ron START

COMPLETE

UVLO THERMAL

SHUTDOWN

LEVEL

SHIFT L

LM3150

AVDD

DRIVER

REGULATION

COMPARATOR

VDD

LOGIC DrvH

DrvL

CURRENT LIMIT

COMPARATOR

DRIVER

GND

Vbias

VDD

toff

OFF TIMER

PMOS

input

VIN

RON

VIN

CVCC

VCC

PGND

CIN

RON

VCC

CSS

SGND

VDD

ILIM

ERM CONTROL

Zero

Current

Detect

VCC

1.20V

6V LDO 0.72V

0.6V

VIN

VOUT

COUT

RFB1

RFB2

RLIM

ILIM-TH

START

COMPLETE

0.72V

ISS

VFB-OV and

SHORT

CIRCUIT

PROTECTION

1.20V

GND

0.36V

1 M5

Vref = 0.6V

LM3150

SNVS561G –SEPTEMBER 2008–REVISED SEPTEMBER 2015

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8.2 Functional Block Diagram

8.3 Feature Description

8.3.1 Programming the Output Voltage

The output voltage is set by two external resistors (RFB1,RFB2). The regulated output voltage is calculated as

follows:

where

• RFB2 is the top resistor connected between VOUT and FB

• RFB1 is the bottom resistor connected between FB and GND (5)

8.3.2 Regulation Comparator

The feedback voltage at FB is compared to the internal reference voltage of 0.6 V. In normal operation (the

output voltage is regulated), an on-time period is initiated when the voltage at FB falls below 0.6 V. The high-side

switch stays on for the on-time, causing the FB voltage to rise above 0.6 V. After the on-time period, the high-

side switch stays off until the FB voltage falls below 0.6 V.

8.3.3 Overvoltage Comparator

The overvoltage comparator is provided to protect the output from overvoltage conditions due to sudden input

line voltage changes or output loading changes. The overvoltage comparator continuously monitors the voltage

at the FB pin and compares it to a 0.72 V internal reference. If the voltage at FB rises above 0.72 V, the on-time

pulse is immediately terminated. This condition can occur if the input or the output load changes suddenly. Once

the overvoltage protection is activated, the HG and LG signals remain off until the voltage at FB pin falls below

0.72 V.

8.3.4 Current Limit

Current limit detection occurs during the off-time by monitoring the current through the low-side switch using an

external resistor, RLIM. If during the off-time the current in the low-side switch exceeds the user defined current

limit value, the next on-time cycle is immediately terminated. Current sensing is achieved by comparing the

voltage across the low side FET with the voltage across the current limit set resistor RLIM. If the voltage across

RLIM and the voltage across the low-side FET are equal then the current limit comparator will terminate the next

on-time cycle.

'IL = (VIN - VOUT) x tON

Ivalley = IOUT - 'IL

RLIM = ICL x RDS(ON)max

ILIM-TH

ICL = IOCL - 'IL

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Feature Description (continued)

The RLIM value can be approximated as follows:

(6)

where

• IOCL is the user-defined average output current limit value

• RDS(ON)max is the resistance value of the low-side FET at the expected maximum FET junction temperature

• ILIM-TH is an internal current supply of 85 µA typical (7)

Figure 13 illustrates the inductor current waveform. During normal operation, the output current ripple is dictated

by the switching of the FETs. The current through the low-side switch, Ivalley, is sampled at the end of each

switching cycle and compared to the current limit, ICL, current. The valley current can be calculated as follows:

where

• IOUT is the average output current

•ΔILis the peak-to-peak inductor ripple current (8)

If an overload condition occurs, the current through the low-side switch will increase which will cause the current

limit comparator to trigger the logic to skip the next on-time cycle. The IC will then try to recover by checking the

valley current during each off-time. If the valley current is greater than or equal to ICL, then the IC will keep the

low-side FET on and allow the inductor current to further decay.

Throughout the whole process, regardless of the load current, the on-time of the controller will stay constant and

thereby the positive ripple current slope will remain constant. During each on-time the current ramps-up an

amount equal to:

(9)

The valley current limit feature prevents current runaway conditions due to propagation delays or inductor

saturation because the inductor current is forced to decay following any overload conditions.

Current sensing is achieved by either a low value sense resistor in series with the low-side FET or by utilizing the

RDS(ON) of the low-side FET. The RDS(ON) sensing method is the preferred choice for a more simplified design and

lower costs. The RDS(ON) value of a FET has a positive temperature coefficient and will increase in value as the

temperature of the FET increases. The LM3150 controller will maintain a more stable current limit that is closer to

the original value that was set by the user, by positively adjusting the ILIM-TH value as the IC temperature

increases. This does not provide an exact temperature compensation but allows for a more tightly controlled

current limit when compared to traditional RDS(ON) sensing methods when the RDS(ON) value can change typically

140% from room to maximum temperature and cause other components to be over-designed. The temperature

compensated ILIM-TH is shown below where TJis the die temperature of the LM3150 controller in Celsius:

ILIM-TH(TJ)=ILIM-TH x [1 + 3.3 x 10-3 x (TJ- 27)] (10)

To calculate the RLIM value with temperature compensation, substitute Equation 10 into ILIM-TH in Equation 7.

tSS = Vref x CSS

ISS

ICL

IPK

IOCL

IOUT

Inductor Current

Load Current

Increases

Normal Operation Current Limited

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Feature Description (continued)

Figure 13. Inductor Current - Current Limit Operation

8.3.5 Short-Circuit Protection

The LM3150 controller will sense a short-circuit on the output by monitoring the output voltage. When the

feedback voltage has fallen below 60% of the reference voltage, Vref x 0.6 (≈0.36 V), short-circuit mode of

operation will start. During short-circuit operation, the SS pin is discharged and the output voltage will fall to 0 V.

The SS pin voltage, VSS, is then ramped back up at the rate determined by the SS capacitor and ISS until VSS

reaches 0.7 V. During this re-ramp phase, if the short-circuit fault is still present the output current will be equal

to the set current limit. Once the soft-start voltage reaches 0.7 V, the output voltage is sensed again and if the

VFB is still below Vref x 0.6 then the SS pin is discharged again and the cycle repeats until the short-circuit fault is

removed.

8.3.6 Soft-Start

The soft-start (SS) feature allows the regulator to gradually reach a steady-state operating point, which reduces

start-up stresses and current surges. At turnon, while VCC is below the undervoltage threshold, the SS pin is

internally grounded and VOUT is held at 0 V. The SS capacitor is used to slowly ramp VFB from 0 V to 0.6 V. By

changing the capacitor value, the duration of start-up can be changed accordingly. The start-up time can be

calculated using the following equation:

where

• tSS is measured in seconds

• Vref = 0.6 V

• ISS is the soft-start pin source current, which is typically 7.7 µA (refer to Electrical Characteristics) (11)

An internal switch grounds the SS pin if VCC is below the undervoltage lockout threshold, if a thermal shutdown

occurs, or if the EN pin is grounded. By using an externally controlled switch, the output voltage can be shut off

by grounding the SS pin.

During startup the LM3150 controller will operate in diode emulation mode, where the low-side gate LG will turn

off and remain off when the inductor current falls to zero. Diode emulation mode will allow start-up into a pre-

biased output voltage. When soft-start is greater than 0.7 V, the LM3150 controller will remain in continuous

conduction mode. During diode emulation mode at current limit the low-gate will remain off when the inductor

current is off.

The soft-start time should be greater than the input voltage rise time and also satisfy the following equality to

maintain a smooth transition of the output voltage to the programmed regulation voltage during start-up.

tSS ≥(VOUT x COUT) / (IOCL - IOUT) (12)

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Feature Description (continued)

8.3.7 Thermal Protection

The LM3150 controller should be operated such that the junction temperature does not exceed the maximum

operating junction temperature. An internal thermal shutdown circuit, which activates at 165°C (typical), takes the

controller to a low-power reset state by disabling the buck switch and the on-timer, and grounding the SS pin.

This feature helps prevent catastrophic failures from accidental device overheating. When the junction

temperature falls back below 150°C the SS pin is released and device operation resumes.

8.4 Device Functional Modes

The EN pin can be activated by either leaving the pin floating due to an internal pullup resistor to VIN or by

applying a logic high signal to the EN pin of 1.26 V or greater. The LM3150 controller can be remotely shut down

by taking the EN pin below 1.02 V. Low quiescent shutdown is achieved when VEN is less than 0.4 V. During

low quiescent shutdown the internal bias circuitry is turned off.

The LM3150 controller has certain fault conditions that can trigger shutdown, such as short circuit, undervoltage

lockout, or thermal shutdown. During shutdown, the soft-start capacitor is discharged. Once the fault condition is

removed, the soft-start capacitor begins charging, allowing the part to start-up in a controlled fashion. In

conditions where there may be an open drain connection to the EN pin, it may be necessary to add a 1-nF

bypass capacitor to this pin. This will help decouple noise from the EN pin and prevent false disabling.

SW L

LM3150

VCC

PGND

SGND

BST

ILIM

CBYP

CSS

VIN VIN

RON

COUT

VOUT

CBST

CVCC

VIN

RLIM

RFB2

RFB1

CEN

CFF

CIN

LM3150

SNVS561G –SEPTEMBER 2008–REVISED SEPTEMBER 2015

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9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

9.1 Application Information

The LM3150 controller employs a COT architecture with ERM (emulated ripple mode) control. This allows for fast

transient response, reduction in output voltage ripple, and low external component count. A typical application of

this part is described in the following section.

9.2 Typical Application

Figure 14. Design Example Schematic

9.2.1 Design Requirements

To properly size the components for the application, the designer needs the following parameters: Input voltage

range, output voltage, output current range and required switching frequency. To summarize briefly, these four

main parameters will affect the choices of component available to achieve a proper system behavior.

For the power supply, the input impedance of the supply rail should be low enough that the input current

transient does not cause drop below the UVLO value. To maintain a relatively constant switching frequency as

the input voltage varies, the LM3150 controller automatically adjusts the on-time inversely with the input voltage.

The available frequency range for a given input voltage range, is determined by the duty-cycle, D = VOUT/VIN, and

the minimum tON and tOFF times. The feedback resistor values can be calculated based on the value of required

output and feedback voltage. Regarding the output capacitor, its voltage rating must be greater than or equal to

the output voltage. Similarly, the voltage rating for the input capacitor must be greater than the input voltage to

be used in the application. Also, a feed-forward capacitor may be required for improved stability, based on the

application.

The following sections describe in detail the design requirements for a typical LM3150 application.

RFB2 = 4.99 k:3.3V

0.6V-1

RFB2 = RFB1 VOUT

VFB -1

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Typical Application (continued)

9.2.2 Detailed Design Procedure

9.2.2.1 Custom Design with WEBENCH Tools

Click here to create a custom design using the LM3150 device with the WEBENCH®Power Designer.

1. Start by entering your VIN, VOUT and IOUT requirements.

2. Optimize your design for key parameters like efficiency, footprint and cost using the optimizer dial and

compare this design with other possible solutions from Texas Instruments.

3. WEBENCH Power Designer provides you with a customized schematic along with a list of materials with real

time pricing and component availability.

4. In most cases, you will also be able to:

– Run electrical simulations to see important waveforms and circuit performance,

– Run thermal simulations to understand the thermal performance of your board,

– Export your customized schematic and layout into popular CAD formats,

– Print PDF reports for the design, and share your design with colleagues.

5. Get more information about WEBENCH tools at www.ti.com/webench.

9.2.2.2 LM3150 Design Procedure

To properly size the components for the application, the designer needs the following parameters: Input voltage

range, output voltage, output current range and required switching frequency. These four main parameters will

affect the choices of component available to achieve a proper system behavior.

Table 1. Bill of Materials

DESIGNATOR VALUE PARAMETERS MANUFACTURER PART NUMBER

CBST 0.47 µF Ceramic, X7R, 16 V, 10% TDK C2012X7R1C474K

CBYP 0.1 µF Ceramic, X7R, 50 V, 10% TDK C2012X7R1H104K

CEN 1000 pF Ceramic, X7R, 50 V, 10% TDK C1608X7R1H102K

CFF 270 pF Ceramic, C0G, 50 V, 5% Vishay-Bccomponents VJ0805A271JXACW1BC

CIN1, CIN2 10 µF Ceramic, X5R, 35 V, 20% Taiyo Yuden GMK325BJ106KN-T

COUT1, COUT2 150 µF Polymer Aluminum, 6.3 V, 20% Panasonic EEF-UE0J151R

CSS 0.068 µF Ceramic, 0805, 25 V, 10% Vishay VJ0805Y683KXXA

CVCC 4.7 µF Ceramic, X7R, 16 V, 10% Murata GRM21BR71C475KA73L

L1 1.65 µH Shielded Drum Core, 2.53 mΩCoilcraft HA3778–AL

M1, M2 30 V 8 nC, RDS(ON) @4.5 V=10 mΩRenesas RJK0305DPB

RFB1 4.99 kΩ1%, 0.125 W Vishay-Dale CRCW08054k99FKEA

RFB2 22.6 kΩ1%, 0.125 W Vishay-Dale CRCW080522k6FKEA

RLIM 1.91 kΩ1%, 0.125 W Vishay-Dale CRCW08051K91FKEA

RON 56.2 kΩ1%, 0.125 W Vishay-Dale CRCW080556K2FKEA

U1 LM3150 Texas Instruments LM3150

1. Define Power Supply Operating Conditions

(a) VOUT = 3.3 V

(b) VIN-MIN =6V,VIN-TYP = 12 V, VIN-MAX = 24 V

(d) Soft-Start time tSS = 5 ms

2. Set Output Voltage with Feedback Resistors

(13)

(14)

RFB2 = 22.455 kΩ(15)

Irmsco = 12 x 12

0.3

Irmsco = IOUT x 12

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RFB2 = 22.6 kΩ, nearest 1% standard value.

3. Determine RON and fS

Dmin = VOUT/VIN-MAX (16)

Dmin = 3.3V/24V = 0.137 (17)

Dmax = 3.3V / 6V = 0.55 (18)

fsmax = 0.137/ 200 ns = 687 kHz (19)

Dmax = VOUT/VIN-MIN (20)

tOFF = (1-0.55)/687 kHz = 654 ns (21)

tOFF should meet the following criteria:

tOFF > tOFF-MIN + 200 ns (22)

tOFF > 725 ns (23)

At the maximum switching frequency of 687 kHz, which is limited by the minimum on-time, the off-time of 654

ns is less than 725 ns. Therefore the switching frequency should be reduced and meet the following criteria:

fs< (1 - D)/725 ns (24)

fS< (1 - 0.55)/725 ns = 620 kHz (25)

A switching frequency is arbitrarily chosen at 500 kHz which should allow for reasonable size components

and satisfies the requirements above.

fS= 500 kHz

Using fS= 500 kHz RON can be calculated as follows:

RON = [(VOUT x VIN)-VOUT] / (VIN x K x fS)+ROND (26)

ROND = - [(VIN - 1) x (VIN x 16.5 + 100)] - 1000 (27)

ROND = - [(12 - 1) x (12 x 16.5 + 100)] -1000 (28)

ROND = -4.3 kΩ(29)

RON = [(3.3 x 12) - 3.3] / (12 x 100 pC x 500 kHz) - 4.3 kΩ(30)

RON = 56.2 kΩ(31)

Next, check the desired minimum input voltage for RON using Figure 15. This design will meet the desired

minimum input voltage of 6 V.

4. Determine Inductor Required

(a) ET = (24-3.3) x (3.3/24) x (1000/500) = 5.7 V µs

(b) From the inductor nomograph a 12-A load and 5.7 V µs calculation corresponds to a L44 type of

inductor.

5. Determine Output Capacitance

The voltage rating on the output capacitor should be greater than or equal to the output voltage. As a rule of

thumb most capacitor manufacturers suggests not to exceed 90% of the capacitor rated voltage. In the case

of multilayer ceramics the capacitance will tend to decrease dramatically as the applied voltage is increased

towards the capacitor rated voltage. The capacitance can decrease by as much as 50% when the applied

voltage is only 30% of the rated voltage. The chosen capacitor should also be able to handle the rms current

which is equal to:

(32)

For this design the chosen ripple current ratio, r = 0.3, represents the ratio of inductor peak-to-peak current

to load current IOUT. A good starting point for ripple ratio is 0.3 but it is acceptable to choose r between 0.25

to 0.5. The nomographs in this datasheet all use 0.3 as the ripple current ratio.

(33)

Irmsco = 1A (34)

tON = (3.3V/12V)/500 kHz = 550 ns (35)

Minimum output capacitance is:

Cff = VIN-MIN x fs

VOUT xRFB1 + RFB2

RFB1 x RFB2

Cff = 6V x 500 kHz

3.3V x4.99 k: + 22.6 k:

4.99 k: x 22.6 k:= 269 pF

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COmin = 70 / (fs2x L) (36)

COmin = 70 / (500 kHz2x 1.65 µH) = 169 µF (37)

The maximum ESR allowed to prevent overvoltage protection during normal operation is:

ESRmax = (80 mV x L x Af) / ET (38)

Af= VOUT / 0.6 without a feed-forward capacitor (39)

Af= 1 with a feed-forward capacitor (40)

For this design a feed-forward capacitor will be used to help minimize output ripple.

ESRmax = (80 mV x 1.65 µH x 1) / 5.7 V µs (41)

ESRmax = 23 mΩ(42)

The minimum ESR must meet both of the following criteria:

ESRmin ≥(15 mV x L x Af) / ET (43)

ESRmin ≥[ ET / (VIN - VOUT) ] x (Af/ CO) (44)

ESRmin ≥(15 mV x 1.65 µH x 1) / 5.7 V µs = 4.3 mΩ(45)

ESRmin ≥[5.7 V µs / (12 - 3.3) ] x (1 / 169 µF) = 3.9 mΩ(46)

Based on the above criteria two 150-µF polymer aluminum capacitors with a ESR = 12 mΩeach for a

effective ESR in parallel of 6 mΩwas chosen from Panasonic. The part number is EEF-UE0J101P.

6. Determine Use of Feed-Forward Capacitor

From Step 5 the capacitor chosen in ESR is small enough that we should use a feed-forward capacitor. This

is calculated from:

(47)

Let Cff = 270 pF, which is the closest next standard value.

7. MOSFET and RLIM Selection

The LM3150 controller is designed to drive N-channel MOSFETs. For a maximum input voltage of 24 V we

should choose N-channel MOSFETs with a maximum drain-source voltage, VDS, greater than 1.2 x 24 V =

28.8 V. FETs with maximum VDS of 30 V will be the first option. The combined total gate charge Qgtotal of the

high-side and low-side FET should satisfy the following:

Qgtotal ≤IVCCL / fs(48)

Qgtotal ≤65 mA / 500 kHz (49)

Qgtotal ≤130 nC (50)

Where IVCCL is the minimum current limit of VCC, over the temperature range, specified in the Electrical

Characteristics table. The MOSFET gate charge Qgis gathered from reading the VGS vs Qgcurve of the

MOSFET datasheet at the VGS = 5 V for the high-side, M1, MOSFET and VGS = 6 V for the low-side, M2,

MOSFET.

The Renesas MOSFET RJK0305DPB has a gate charge of 10 nC at VGS = 5 V, and 12 nC at VGS = 6 V.

This combined gate charge for a high-side, M1, and low-side, M2, MOSFET 12 nC + 10 nC = 22 nC is less

than 130 nC calculated Qgtotal.

The calculated MOSFET power dissipation must be less than the max allowed power dissipation, Pdmax, as

specified in the MOSFET data sheet. An approximate calculation of the FET power dissipated Pd, of the

high-side and low-side FET is given by:

High-Side MOSFET

Pdh = 0.396 + 0.278 = 0.674W

Pcond = Iout2 x RDS(ON) x D

8.5

Vcc - Vth +6.8

Vth

2x Vin x Iout x Qgd x fs x

Psw =

Pdh = Pcond + Psw

Pcond = 122 x 0.01 x 0.275 = 0.396W

8.5

6 ± 2.5 +6.8

2.5

2x 12 x 12 x 1.5 nC x 500 kHz x

Psw = = 0.278W

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(51)

The max power dissipation of the RJK0305DPB is rated as 45 W for a junction temperature that is 125°C

higher than the case temperature and a thermal resistance from the FET junction to case, θJC, of 2.78°C/W.

When the FET is mounted onto the PCB, the PCB will have some additional thermal resistance such that the

total system thermal resistance of the FET package and the PCB, θJA, is typically in the range of 30°C/W for

this type of FET package. The max power dissipation, Pdmax, with the FET mounted onto a PCB with a

125°C junction temperature rise above ambient temperature and θJA = 30°C/W, can be estimated by:

Pdmax = 125°C / 30°C/W = 4.1 W (52)

The system calculated Pdh of 0.674 W is much less than the FET Pdmax of 4.1 W and therefore the

RJK0305DPB max allowable power dissipation criteria is met.

Low-Side MOSFET

Primary loss is conduction loss given by:

Pdl = Iout2x RDS(ON) x (1-D) = 122x 0.01 x (1-0.275) = 1 W (53)

Pdl is also less than the Pdmax specified on the RJK0305DPB MOSFET data sheet.

However, it is not always necessary to use the same MOSFET for both the high-side and low-side. For most

applications it is necessary to choose the high-side MOSFET with the lowest gate charge and the low-side

MOSFET is chosen for the lowest allowed RDS(ON). The plateau voltage of the FET VGS vs Qgcurve must be

less than VCC - 750 mV.

The current limit resistor, RLIM, is calculated by estimating the RDS(ON) of the low-side FET at the maximum

junction temperature of 100°C. By choosing to go into current limit when the average output load current is

20% higher than the output load current of 12A while the inductor ripple current ratio is 1/3 of the load current

will make ICL= 10.4 A. Then the following calculation of RLIM is:

RLIM = (10.4 x 0.014) / (75 x 10-6) = 1.9 kΩ(54)

Let RLIM = 1.91 kΩwhich is the next standard value.

8. Calculate Input Capacitance

The input capacitor should be chosen so that the voltage rating is greater than the maximum input voltage

which for this example is 24 V. Similar to the output capacitor, the voltage rating needed will depend on the

type of capacitor chosen. The input capacitor should also be able to handle the input rms current, which is a

maximum of approximately 0.5 x IOUT. For this example the rms input current is approximately 0.5 x 12 A = 6

The minimum capacitance with a maximum 5% input ripple ΔVIN-MAX = (0.05 x 12) = 0.6 V:

CIN = [12 x 0.275 x (1-0.275)] / [500 kHz x 0.6] = 8 µF (55)

To handle the large input rms current 2 ceramic capacitors are chosen at 10 µF each with a voltage rating of

50 V and case size of 1210. Each ceramic capacitor is capable of handling 3 A of rms current. A aluminum

electrolytic of 5 times the combined input capacitance, 5 x 20 µF = 100 µF, is chosen to provide input voltage

filter damping because of the low ESR ceramic input capacitors.

CBYP = 0.1µF ceramic with a voltage rating greater than maximum VIN

9. Calculate Soft-Start Capacitor

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The soft start-time should be greater than the input voltage rise time and also satisfy the following equality to

maintain a smooth transition of the output voltage to the programmed regulation voltage during startup. The

desired soft-start time, tss, of 5 ms also must satisfy the equality in Equation 12, by using the chosen

component values through the previous steps as shown below:

5 ms > (3.3V x 300 µF) / (1.2 x 12A - 12A) (56)

5 ms > 0.412 ms (57)

Because the desired soft-start time satisfies the equality in Equation 12, the soft start capacitor is calculated

as:

CSS = (7.7 µA x 5 ms) / 0.6V = 0.064 µF (58)

Let CSS = 0.068 µF, which is the next closest standard value. This should be a ceramic cap with a voltage

rating greater than 10 V.

10. CVCC, CEN, and CBST

CVCC = 4.7-µF ceramic with a voltage rating greater than 10 V

CEN = 1000-pF ceramic with a voltage rating greater than 10 V

CBST = 0.47-µF ceramic with a voltage rating greater than 10 V

ET = (Vinmax ± VOUT) x Vinmax

VOUT xfS

1000 (V x Ps)

VOUT = VFB x (RFB1 + RFB2)

RFB1

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9.2.2.3 Design Guide

The design guide provides the equations required to design with the LM3150 controller. WEBENCH design tool

can be used with or in place of this section for a more complete and simplified design process.

1. Define Power Supply Operating Conditions

(a) Required Output Voltage

(b) Maximum and Minimum DC Input Voltage

(d) Soft-Start Time

2. Set Output Voltage With Feedback Resistors

where

• RFB1 is the bottom resistor

• RFB2 is the top resistor (59)

3. Determine RON and fs

The available frequency range for a given input voltage range, is determined by the duty-cycle, D = VOUT/VIN,

and the minimum tON and tOFF times as specified in the Electrical Characteristics table. The maximum

frequency is thus, fsmax = Dmin/tON-MIN. Where Dmin=VOUT/VIN-MAX, is the minimum duty-cycle. The off-time will

need to be less than the minimum off-time tOFF as specified in the Electrical Characteristics table plus any

turnoff and turnon delays of the MOSFETs which can easily add another 200 ns. The minimum off-time will

occur at maximum duty cycle Dmax and will determine if the frequency chosen will allow for the minimum

desired input voltage. The requirement for minimum off-time is tOFF= (1–Dmax)/fs≥(tOFF-MIN + 200 ns). If tOFF

does not meet this requirement it will be necessary to choose a smaller switching frequency fS.

Choose RON so that the switching frequency at your typical input voltage matches your fSchosen above

using the following formula:

RON = [(VOUT x VIN)-VOUT] / (VIN x K x fS)+ROND (60)

ROND = - [(VIN - 1) x (VIN x 16.5 + 100)] - 1000 (61)

Use Figure 15 to determine if the calculated RON will allow for the minimum desired input voltage. If the

minimum desired input voltage is not met, recalculate RON for a lower switching frequency.

Figure 15. Minimum VIN vs. VOUT

IOUT = 10 A

4. Determine Inductor Required Using Figure 16

To use the nomograph in Figure 16, calculate the inductor volt-microsecond constant ET from the following

formula:

where

L36

L35

MAXIMUM LOAD CURRENT (A)

4 5 6 7 8 9 10 12

100 L01

L02

L03

L04

L05

L06

L07

L08

L09

L10

L11

L12

L13

L14

L15

L16

L17

L18

L19

L20

L21

L22

L23

L24

L34

L33

L32

L25

L26

L27

L28

L29

L30

L31

L48

L47

L46

L45

L44

L37

L38

L39

L40

L41

L42

L43

E À T (V À Ps)

47 PH

33 PH

22 PH

15 PH

10 PH

6.8 PH

4.7 PH

3.3 PH

2.2 PH

1.5 PH

1.0 PH

0.68 PH

0.47 PH

0.33 PH

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• fsis in kHz units (62)

The intersection of the Load Current and the Volt-microseconds lines on the chart below will determine which

inductors are capable for use in the design. Figure 16 shows a sample of parts that can be used. The offline

calculator tools and WEBENCH will fully calculate the requirements for the components needed for the

design.

Figure 16. Inductor Nomograph

Table 2. Inductor Selection Table

INDUCTOR

DESIGNATOR INDUCTANCE (µH) CURRENT (A) PART NAME VENDOR

L01 47 7-9

L02 33 7-9 SER2817H-333KL COILCRAFT

L03 22 7-9 SER2814H-223KL COILCRAFT

L04 15 7-9 7447709150 WURTH

L05 10 7-9 RLF12560T-100M7R5 TDK

L06 6.8 7-9 B82477-G4682-M EPCOS

L07 4.7 7-9 B82477-G4472-M EPCOS

L08 3.3 7-9 DR1050-3R3-R COOPER

L09 2.2 7-9 MSS1048-222 COILCRAFT

L10 1.5 7-9 SRU1048-1R5Y BOURNS

L11 1 7-9 DO3316P-102 COILCRAFT

L12 0.68 7-9 DO3316H-681 COILCRAFT

L13 33 9-12

L14 22 9-12 SER2918H-223 COILCRAFT

L15 15 9-12 SER2814H-153KL COILCRAFT

L16 10 9-12 7447709100 WURTH

L17 6.8 9-12 SPT50H-652 COILCRAFT

L18 4.7 9-12 SER1360-472 COILCRAFT

L19 3.3 9-12 MSS1260-332 COILCRAFT

L20 2.2 9-12 DR1050-2R2-R COOPER

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Table 2. Inductor Selection Table (continued)

INDUCTOR

DESIGNATOR INDUCTANCE (µH) CURRENT (A) PART NAME VENDOR

L21 1.5 9-12 DR1050-1R5-R COOPER

L22 1 9-12 DO3316H-102 COILCRAFT

L23 0.68 9-12

L24 0.47 9-12

L25 22 12-15 SER2817H-223KL COILCRAFT

L26 15 12-15

L27 10 12-15 SER2814L-103KL COILCRAFT

L28 6.8 12-15 7447709006 WURTH

L29 4.7 12-15 7447709004 WURTH

L30 3.3 12-15

L31 2.2 12-15

L32 1.5 12-15 MLC1245-152 COILCRAFT

L33 1 12-15

L34 0.68 12-15 DO3316H-681 COILCRAFT

L35 0.47 12-15

L36 0.33 12-15 DR73-R33-R COOPER

L37 22 15-

L38 15 15- SER2817H-153KL COILCRAFT

L39 10 15- SER2814H-103KL COILCRAFT

L40 6.8 15-

L41 4.7 15- SER2013-472ML COILCRAFT

L42 3.3 15- SER2013-362L COILCRAFT

L43 2.2 15-

L44 1.5 15- HA3778–AL COILCRAFT

L45 1 15- B82477-G4102-M EPCOS

L46 0.68 15-

L47 0.47 15-

L48 0.33 15-

5. Determine Output Capacitance

Typical hysteretic COT converters similar to the LM3150 controller require a certain amount of ripple that is

generated across the ESR of the output capacitor and fed back to the error comparator. Emulated Ripple

Mode control built into the LM3150 controller will recreate a similar ripple signal and thus the requirement for

output capacitor ESR will decrease compared to a typical Hysteretic COT converter. The emulated ripple is

generated by sensing the voltage signal across the low-side FET and is then compared to the FB voltage at

the error comparator input to determine when to initiate the next on-time period.

COmin = 70 / (fs2x L) (63)

The maximum ESR allowed to prevent overvoltage protection during normal operation is:

ESRmax = (80 mV x L x Af) / ETmin (64)

ETmin is calculated using VIN-MIN

Af= VOUT / 0.6 if there is no feed-forward capacitor used

Af= 1 if there is a feed-forward capacitor used

The minimum ESR must meet both of the following criteria:

ESRmin ≥(15 mV x L x Af) / ETmax (65)

ESRmin ≥[ ETmax / (VIN - VOUT) ] x (Af/ CO) (66)

ETmax is calculated using VIN-MAX.

CIN = Iomax x D x (1-D)

fs x 'VIN-MAX

RLIM (Tj) = ICL x RDS(ON)max

ILIM-TH (Tj)

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Any additional parallel capacitors should be chosen so that their effective impedance will not negatively

attenuate the output ripple voltage.

6. Determine The Use of Feed-Forward Capacitor

Certain applications may require a feed-forward capacitor for improved stability and easier selection of

available output capacitance. Use the following equation to calculate the value of Cff.

ZFB = (RFB1 x RFB2)/(RFB1 + RFB2) (67)

Cff = VOUT/(VIN-MIN x fSx ZFB) (68)

7. MOSFET and RLIM Selection

The high-side and low-side FETs must have a drain to source (VDS) rating of at least 1.2 x VIN.

Use the following equations to calculate the desired target value of the low-side FET RDS(ON) for current limit.

(69)

ILIM-TH(Tj)=ILIM-TH x [1 + 3.3 x 10-3 x (Tj- 27)] (70)

The gate drive current from VCC must not exceed the minimum current limit of VCC. The drive current from

VCC can be calculated with:

IVCCdrive = Qgtotal x fS

where

• Qgtotal is the combined total gate charge of the high-side and low-side FETs (71)

The plateau voltage of the FET VGS vs Qgcurve, as shown in Figure 17, must be less than VCC - 750 mV.

Figure 17. Typical MOSFET Gate Charge Curve

See following design example for estimated power dissipation calculation.

8. Calculate Input Capacitance

The main parameters for the input capacitor are the voltage rating, which must be greater than or equal to

the maximum DC input voltage of the power supply, and its rms current rating. The maximum rms current is

approximately 50% of the maximum load current.

where

•ΔVIN-MAX is the maximum allowable input ripple voltage. A good starting point for the input ripple voltage is 5%

of VIN (72)

CSS = ISS x tSS

Vref

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When using low ESR ceramic capacitors on the input of the LM3150 controller, a resonant circuit can be

formed with the impedance of the input power supply and parasitic impedance of long leads/PCB traces to

the LM3150 input capacitors. TI recommends using a damping capacitor under these circumstances, such as

aluminum electrolytic that will prevent ringing on the input. The damping capacitor should be chosen to be

approximately five times greater than the parallel ceramic capacitors combination. The total input

capacitance should be greater than 10 times the input inductance of the power supply leads/PCB trace. The

damping capacitor should also be chosen to handle its share of the rms input current which is shared

proportionately with the parallel impedance of the ceramic capacitors and aluminum electrolytic at the

LM3150 switching frequency.

The CBYP capacitor should be placed directly at the VIN pin. The recommended value is 0.1 µF.

9. Calculate Soft-Start Capacitor

where

• tss is the soft-start time in seconds

• Vref = 0.6V (73)

10. CVCC, CBST, and CEN

CVCC should be placed directly at the VCC pin with a recommended value of 1 µF to 4.7 µF. CBST creates a

voltage used to drive the gate of the high-side FET. It is charged during the SW off-time. The recommended

value for CBST is 0.47 µF. The EN bypass capacitor, CEN, recommended value is 1000 pF when driving the

EN pin from open-drain type of signal.

9.2.3 Application Curves

Figure 18. 250-kHz Efficiency vs Load Figure 19. 500-kHz Efficiency vs Load

Figure 20. 750-kHz Efficiency vs Load

VIN

CIN

COUT

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10 Power Supply Recommendations

The LM3150 controller is designed to operate from various DC power supplies. VIN input should be protected

from reversal voltage and voltage dump over 42 volts. The impedance of the input supply rail should be low

enough that the input current transient does not cause drop below VIN UVLO level. If the input supply is

connected by using long wires, additional bulk capacitance may be required in addition to normal input capacitor.

11 Layout

11.1 Layout Guidelines

It is good practice to layout the power components first, such as the input and output capacitors, FETs, and

inductor. The first priority is to make the loop between the input capacitors and the source of the low-side FET to

be very small and tie the grounds of the low-side FET and input capacitor directly to each other and then to the

ground plane through vias. As shown in Figure 21 when the input capacitor ground is tied directly to the source

of the low-side FET, parasitic inductance in the power path, along with noise coupled into the ground plane, are

reduced.

The switch node is the next item of importance. The switch node should be made only as large as required to

handle the load current. There are fast voltage transitions occurring in the switch node at a high frequency, and if

the switch node is made too large it may act as an antennae and couple switching noise into other parts of the

circuit. For high power designs, it is recommended to use a multilayer board. The FETs are going to be the

largest heat generating devices in the design, and as such, care should be taken to remove the heat. On

multilayer boards using exposed-pad packages for the FETs such as the power-pak SO-8, vias should be used

under the FETs to the same plane on the interior layers to help dissipate the heat and cool the FETs. For the

typical single FET Power-Pak type FETs, the high-side FET DAP is VIN. The VIN plane should be copied to the

other interior layers to the bottom layer for maximum heat dissipation. Likewise, the DAP of the low-side FET is

connected to the SW node and the SW node shape should be duplicated to the other PCB layers for maximum

heat dissipation.

See the Evaluation Board application note AN-1900 (SNVA371) for an example of a typical multilayer board

layout, and the Demonstration Board Reference Design Application Note for a typical 2-layer board layout. Each

design allows for single-sided component mounting.

Figure 21. Schematic of Parasitics

LM3150

VIN VOUT

COUT

CIN

x x

vias to

ground plane

PGND

x x

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Product Folder Links: LM3150

11.2 Layout Example

Figure 22. PCB Placement of Power Stage

LM3150

www.ti.com

SNVS561G –SEPTEMBER 2008–REVISED SEPTEMBER 2015

Product Folder Links: LM3150

12 Device and Documentation Support

12.1 Documentation Support

12.1.1 Custom Design with WEBENCH Tools

Click here to create a custom design using the LM3150 device with the WEBENCH®Power Designer.

1. Start by entering your VIN, VOUT and IOUT requirements.

2. Optimize your design for key parameters like efficiency, footprint and cost using the optimizer dial and

compare this design with other possible solutions from Texas Instruments.

3. WEBENCH Power Designer provides you with a customized schematic along with a list of materials with real

time pricing and component availability.

4. In most cases, you will also be able to:

– Run electrical simulations to see important waveforms and circuit performance,

– Run thermal simulations to understand the thermal performance of your board,

– Export your customized schematic and layout into popular CAD formats,

– Print PDF reports for the design, and share your design with colleagues.

5. Get more information about WEBENCH tools at www.ti.com/webench.

12.1.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper

right corner, click on Alert me to register and receive a weekly digest of any product information that has

changed. For change details, review the revision history included in any revised document.

12.1.3 Third-Party Products Disclaimer

TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT

CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES

OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER

ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.

12.1.4 Related Documentation

For related documentation see the following:

•AN-1900 LM3150 Evaluation Boards SNVA371

12.2 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective

contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of

Use.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration

among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help

solve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and

contact information for technical support.

12.3 Trademarks

PowerWise, E2E are trademarks of Texas Instruments.

WEBENCH, SIMPLE SWITCHER are registered trademarks of Texas Instruments.

All other trademarks are the property of their respective owners.

12.4 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

LM3150

SNVS561G –SEPTEMBER 2008–REVISED SEPTEMBER 2015

www.ti.com

Product Folder Links: LM3150

12.5 Glossary

SLYZ022 —TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

PACKAGE OPTION ADDENDUM

www.ti.com 23-Apr-2015

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead/Ball Finish

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

LM3150MH/NOPB ACTIVE HTSSOP PWP 14 94 Green (RoHS

& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LM3150

LM3150MHE/NOPB ACTIVE HTSSOP PWP 14 250 Green (RoHS

& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LM3150

LM3150MHX/NOPB ACTIVE HTSSOP PWP 14 2500 Green (RoHS

& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LM3150

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish

value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

PACKAGE OPTION ADDENDUM

www.ti.com 23-Apr-2015

Addendum-Page 2

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

LM3150MHE/NOPB HTSSOP PWP 14 250 178.0 12.4 6.95 5.6 1.6 8.0 12.0 Q1

LM3150MHX/NOPB HTSSOP PWP 14 2500 330.0 12.4 6.95 5.6 1.6 8.0 12.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 27-Jan-2016

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

LM3150MHE/NOPB HTSSOP PWP 14 250 210.0 185.0 35.0

LM3150MHX/NOPB HTSSOP PWP 14 2500 367.0 367.0 35.0

PACKAGE MATERIALS INFORMATION

www.ti.com 27-Jan-2016

Pack Materials-Page 2

MECHANICAL DATA

PWP0014A

www.ti.com

MXA14A (Rev A)

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TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms

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