ICs for Communications Single Chip ISDN USB Controller SIUC-X PSB 2154 Version 1.1 Product Overview 10.99 DS 1 * PSB 2154 Revision History: Current Version: 10.99 Previous Version: None Page Page (in previous (in current Version) Version) Subjects (major changes since last revision) ABM(R) , AOP(R) , ARCOFI(R) , ARCOFI(R) -BA, ARCOFI(R)-SP, DigiTape (R) , EPIC(R)-1, EPIC (R) -S, ELIC(R) , FALC(R) 54, FALC(R)56, FALC(R) -E1, F ALC (R) -LH, IDEC(R) , IOM(R) , IOM(R) -1, IOM(R) -2, IPAT(R)-2, ISAC (R) -P, ISAC(R)-S, ISAC (R)-S TE, ISAC(R) -P T E, ITAC(R), IWE (R) , MUSAC(R) -A, OCTAT(R)-P, QUAT (R)-S, SICAT (R) , SICOFI(R) , SICOFI(R)-2, SICOFI (R) -4, SICOFI(R) -4C, SLICOFI(R) are registered trademarks of Infineon T echnologies AG. * ACETM , ASMTM, ASP TM , POTSWIRE TM, QuadF ALC TM , SCOUTTM , SIUCTM are trademarks of Infineon Technologies AG. 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Critical components1 of the Infineon T echnologies AG, may only be used in life-support devices or systems 2 w ith the express written approval of the Infineon T echnologies AG. 1 A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that life-support device or system, or to affect its safety or effectiveness of that device or system. 2 Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain human life. If they fail, it is reasonable to assume that the health of the user may be endangered. PSB 2154 Table of Contents Page 1 1.1 1.2 1.3 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Typical Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 2 2.1 2.2 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Pin Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Pin Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 3 Functional Block Diagram Product Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 3 10.99 PSB 2154 Overview 1 Overview The Single Chip ISDN USB Controller (SIUC-X) integrates all functions on a single chip for a host based ISDN S-interface access solution through USB. It combines the basic features of the ISDN PC Adapter Circuit (IPAC PSB 2115) and the C541U 8-bit Microcontroller with USB, and adds additional features. On the ISDN side it includes the S-transceiver (Layer 1), an HDLC controller for the Dchannel and two protocol controllers for the B-channels. They can be used for HDLC protocol or transparent access. The FIFO size of the B-channel buffers is 128 bytes per channel and per direction. On the USB side it includes a full speed USB transceiver, supports bus powered operation and is compliant with USB Specification V1.1 and the Communication Device Class (CDC) Specification V1.1 for ISDN devices. The endpoints can be controlled by the microcontroller by special function registers. A boot loader in ROM allows firmware download to internal and external memory via USB according to the USB Device Class Specification for Device Firmware Upgrade (DFU) V1.0. The embedded new C800 Microcontroller core (8-bit) enables transparent or HDLCframed exchange of B-channel data between the S-interface and USB. In addition, it provides lower level D-channel access control functions. The operational firmware which is downloaded via USB is contained in internal 16K RAM. Firmware can be developed using external Flash/ROM. Emulation is supported through Enhanced Hooks Technology TM. Three sets of C ports are available for optionally connecting external memory. In applications not requiring external memory, they can be used as general purpose I/Os. Additionally, an 8 line auxiliary I/O interface has been built in. These programmable I/O lines may be used to connect other peripheral components to the SIUC-X, which need software control or have to forward status information to the C. The SPI interface for serial EEPROM communication is multiplexed on to these lines. 3 programmable LED output ports are available, one of them can indicate the activation status of the Sinterface automatically. The onchip voltage regulator supports the design of bus powered applications, i.e. the regulated 3.3V supply is generated from the USB supply by the SIUC-X itself without requiring an external voltage regulator. The SIUC-X is produced in advanced CMOS technology. Product Overview 4 10.99 Single Chip ISDN USB Controller SIUC-X PSB 2154 Version 1.1 1.1 CMOS Features General * * * * * * Single chip host based ISDN solution for USB 3.3V power supply Programmable reset sources Onchip PLL for 48 MHz clock generation 5V tolerant I/Os Onchip voltage regulator for bus-powered operation (patent pending) P-MQFP-80-1 ISDN (S-Interface, 2B+D Channels) * S/T-transceiver (ITU-T I.430) operating in TE mode * D-channel and B-channel protocol controllers (HDLC) * Different types of protocol support depending on operating mode (Non-auto mode, Transparent mode 1-3, extended transparent mode) * IOM-2 interface, single/double clock with strobe signals * Monitor and C/I-channel protocol to control peripheral devices * 128 byte FIFO buffers with programmable FIFO thresholds per B-channel per direction * 64 byte FIFO buffers per direction with programmable FIFO thresholds for D-channel * D-channel access mechanism * Transformer ratio 1:1 * 2 timers programmable between 1 ms to 14.336 s. Microcontroller & Peripherals * 8-bit C800 CPU, full software/toolset compatible to standard 80C51/80C52 microcontrollers * 48 MHz operating frequency, equivalent to 4 MIPS * 4 Kbyte onchip standard ROM program memory (boot loader), up to 64 Kbyte external program memory for firmware development * 256 byte onchip data RAM * 16 Kbyte onchip RAM (XRAM) flexibly programmable as program and/or data space * External memory extention up to 64 Kbyte program and 62 Kbyte data memory * Ports 0, 2 and 3 can be used as general purpose I/Os or as memory interface Product Overview 5 10.99 PSB 2154 Overview * Two lines can be used as external interrupt source, one of them can indicate the USB device attached status in self powered mode * Demultiplexed address/data bus allows glueless interfacing of external memory * Optimized layout for external memory connection * 14 interrupt sources to CPU (1 external, 13 internal with 2 USB, 1 SPI and 8 ISDN interrupts) selectable at 4 priority levels * 8 data pointers * Two 16-bit timers: timer 0 and timer 1 * Onchip emulation support logic using Enhanced Hooks Technology TM USB * Compliant to * * * * * * * * * * - USB Specification V1.1 - USB Communication Device Class (CDC) Specification V1.1 - USB Device Firmware Upgrade (DFU) Specification V1.0 Onchip USB transceiver 12 Mbit/s full speed operation 7 software configurable endpoints, in addition to the bi-directional Control Endpoint 0 FW supports 2 configurations by default:USB Device Firmware Upgrade (DFU) USB Communication Device Class (CDC) DFU Configuration with 1 interface and 1 endpoint (EP0) CDC Configuration with 4 additional interfaces and 2 alternate settings each, supporting 8 endpoints (EP0 - EP7) All USB transfer modes supported (bulk, isochronous, interrupt and control) Bus-powered operation possible (no external power supply necessary) Low Power Device, <100mA (operational), <500 A (suspend) Optional loading of customized configuration data (e.g. Vendor ID, Product ID, ... ) from external EEPROM Firmware * SIUC-X comes along with firmware and drivers fully supporting ISDN data access according to USB CDC V1.1 * Onchip bootloader supports DFU class: firmware can easily be downloaded via USB to internal memory (flexibility for firmware upgrades) * Customer can develop own firmware using internal/external memory Miscellaneous * * * * 8 line programmable auxiliary I/O interface with interrupt inputs SPI Interface for optional connection to an external EEPROM 3 LED output ports (one is capable to indicate S-bus activation status automatically) Strap pins for identification of different HW configurations Product Overview 6 10.99 PSB 2154 Overview 1.2 Logic Symbol The logic symbol shows all functions of the SIUC-X. It must be noted, that not all functions are available simultaneously, but depend on the selected mode. Pins which are marked with a " * " are multiplexed and not available in all modes. * USB Interface D+ 0V T EST Vo lta ge Regula tor +3.3V 0V D - VREG1 VREG2 VDD VDDA VDDAP VDDU 7.68 MHz 100 ppm VSS XTAL1 VSSA VSSAP VSSU VSSAR 8 SR1 SR2 SX1 S Interface SX2 Port 0 (Data ) 8 DU Port 2 (MSB Add re ss) DD 8 F SC AD0-7 (LSB Address) DCL 5 IO M-2 In terface BCL Port 3 (DADD, INT 0, W R, RD, PW R) Me mory Interface XT AL2 SDS / RSTO ALE / CS PSEN EA EAW External Awake RESET MMOD 2 MBIT * AUX0-7* SDI* SCK* ELD* SDO* SCS* IN T1/2* 2 8 Auxiliary In terface* Figure 1 Mu lti frame Sync. BMOD SPI Interface * External Interrupts* AUX6/7 * ACL SVN0/1 * 3 L ED O utput* System Version Number * 2154_11x Logic Symbol Product Overview 7 10.99 PSB 2154 Overview 1.3 Typical Applications The SIUC-X is suited for USB host based applications. The S interface is a 4-line 192 kbit/s interface while the 2-line USB interface works at 12 MHz. Figure 2 to figure 5 give a general overview of system integration of SIUC-X. ISDN PC Adapter for S Interface An ISDN adapter for a PC is built around the SIUC-X using the USB interface (figure 2 ). The onchip voltage regulator allows bus powered operation without the necessity of an external regulator. 3 LED ports can indicate different status information to the user. This single chip solution enables design of an embedded device cable linking USB to ISDN ("cable with a bump"). The SIUC-X also enables an optimized layout and glueless connection of external memory, to provide a small form factor even in non single chip applications. * USB USB Host Interface PC A dapt er SIUC-X PSB 2154 NT S S Interface Flash / RAM (optional) 2154_12.v sd Figure 2 ISDN PC Adapter for S Interface Product Overview 8 10.99 PSB 2154 Overview ISDN PC Adapter for U and S Interface A dual mode ISDN adapter which supports U and S interface may be realized using the SIUC-X together with the U transceiver PSB 21911 IEC-Q TE (figure 3). As a dual mode adapter it can be connected to the S interface of an NT (e.g. in Europe) whereby the U transceiver is disabled, or it is connected directly to the U interface (e.g. in North America) while the S transceiver of the SIUC-X is unused. * USB PC Adapter U CO S USB PC Adapter U NT CO S USB Host Interface IEC-Q TE PSB 21911 U Interface SIUC-X PSB 2154 S Interface F lash / RAM (optional) 2154_13.v sd Figure 3 ISDN PC Adapter for U and S Interface Product Overview 9 10.99 PSB 2154 Overview ISDN Voice/Data Terminal Figure 4 shows a voice data terminal where the SIUC-X provides its functionality as data controller and S interface whithin a two chip solution. During ISDN calls the ARCOFI-SP PSB 2163 provides speakerphone functions and includes a DTMF generator. Additionally, a DTMF receiver or keypad may be connected to the auxiliary interface of the SIUC-X. * NT USB S ARCOFI-SP PSB 2163 USB Host Interface SIUC-X PSB 2154 DTMF RX or Keypad S Interface Flash / RAM (optional) 2154_14a Figure 4 ISDN Voice/Data Terminal Product Overview 10 10.99 PSB 2154 Overview ISDN Terminal Adapter with USB Data Port The SIUC-X can be used as a microcontroller based terminal adapter (figure 5) that is connected to the communications interface of a PC. Connection of analog terminals (e.g. telephone or fax) is enabled by the DuSLIC chipset with its dual channel POTS interface. LEDs for status information and general purpose input/output control functions can directly be handled by the SIUC-X. * US B NT S TA t /r t /r DuSLIC 2 x tip/ring S LIC-X PEB 4265 S LIC-X PEB 4265 USB Host Interface SLICOFI2 PEB 3265 SIUC-X PSB 2154 Status LEDs S Interface Flash / RAM (optional) 2154_14b.vsd Figure 5 ISDN Stand-alone Terminal with POTS Interface Product Overview 11 10.99 PSB 2154 Pin Description 2 Pin Description 2.1 Pin Diagram B MOD 1 MMOD VSS BMOD0 TEST VDD AC L RESE T VDD VSS XTAL1 XTAL2 VDD AP VSSAP SX1 SX2 VSSA VDD A BC L 61 6 0 59 58 57 56 5 5 54 53 5 2 5 1 50 4 9 48 4 7 46 4 5 44 4 3 42 4 1 40 A3 DU 62 39 A4 DD FSC 63 38 A5 64 37 A6 DC L 65 36 A7 re s_ l 66 35 P2.4/A12 EA W 67 68 34 33 P2.6/A14 69 32 P3.4/PWR 31 30 P3.2/WR SDS/RSTO VDD VSS A UX0 A UX1 Figure 6 SR1 SR2 * SIUC-X PSB 2154 70 71 72 P2.7/A15 29 P2.5/A13 P2 .0 /A8 28 P2.1/A9 74 27 VSS A UX4 A UX5 75 26 P2.3/A11 76 25 P3.3/RD A UX6 77 24 P0.0/AD0 VSSAR VREG1 78 23 A0 79 22 A1 VREG2 80 21 A2 P0 .1/AD1 P0 .2/AD2 P0 .3/AD3 P0 .4/AD4 P0 .5/AD5 P0 .6/AD6 VSS VDD P0 .7/AD7 ALE / CS P2 .2 /A 10 PSEN 8 9 1 0 11 1 2 13 1 4 15 1 6 17 1 8 19 2 0 EA P3.1/INT0 AU X7 P3.0/DAD D 3 4 5 6 7 VSSU 1 2 D- 73 VDD U D+ A UX2 A UX3 2 154_ 15x.vsd Pin Diagram Product Overview 12 10.99 PSB 2154 Pin Description 2.2 Pin Definition * Table 1 Pin Definition - IOM-2 Interface Pin Symbol Input (I) Function No. Output (O) 64 FSC O Frame Sync 8-kHz frame synchronisation signal. The rising edge indicates the beginning of the IOM frame (HIGH during channel 0). 65 DCL O Data Clock IOM clock signal of twice the IOM data rate (1.536 MHz). The first rising edge is used to transmit data, the second falling edge is used to sample data. 62 DU I Data Upstream IOM data signal in upstream direction. 63 DD O(OD) Data Downstream IOM data signal in downstream direction. 61 BCL O Bit Clock Bit clock output, identical to IOM data rate , derived from the DCL output clock (BCL = DCL/2 = 768 kHz). 68 SDS / RSTO O (OD) Serial Data Strobe / Reset Output Programmable strobe signal (push pull characteristic) for time slot and/or D-channel indication on IOM-2. It can optionally be used as reset output (open drain characteristic). Table 2 Pin Definition - Auxiliary Interface Pin Symbol Input (I) Function No. Output (O) 71 72 73 AUX0 AUX1 AUX2 I/O Product Overview Auxiliary Port 0 - 2 - General input/output Ports These pins are individually programmable as general input/output. The state of the pin can be read from (input) / written to (output) a register. 13 10.99 PSB 2154 Pin Description Table 2 Pin Definition - Auxiliary Interface (cont'd) Pin Symbol Input (I) Function No. Output (O) 74 AUX3 I/O Auxiliary Port 3 Non SPI Mode: AUX3 (input/output) If not used for the SPI interface, this pin is programmable as general input/output. The state of the pin can be read from (input) / written to (output) a register. SPI Mode: ELD (input, during reset) - EEPROM Load This pin is strapped HIGH during reset to indicate the C that an EEPROM is connected (e.g. for loading USB ID values). SPI Mode: SCS (output, after reset) Serial Chip Select to EEPROM. This pin has an internal pulldown resistor, i.e. for the ELD function an external pullup resistor must be connected to indicate that an EEPROM is connected. 75 AUX4 I/O Product Overview Auxiliary Port 4 Non SPI Mode: AUX4 (input/output) If not used for the SPI interface, this pin is programmable as general input/output. The state of the pin can be read from (input) / written to (output) a register. SPI Mode: SDI (input) Serial Data Input on the SPI interface to be connected to the SO pin of the EEPROM. All modes: SVN0 - System Version Number 0 (input) During reset the state of this pin (pull up/down resistor) is latched to the internal System Version Number register. After reset this pin performs the functions described above. An internal pull down resistor is provided. MBIT - Multiframe Synchronization (output) If selected via ACFG2.A4SEL=1 the pin AUX4 is used for multiframe synchronization, i.e. it is an M-bit output. 14 10.99 PSB 2154 Pin Description Table 2 Pin Definition - Auxiliary Interface (cont'd) Pin Symbol Input (I) Function No. Output (O) 76 AUX5 I/O Auxiliary Port 5 Non SPI Mode: AUX5 (input/output) If not used for the SPI interface, this pin is programmable as general input/output. The state of the pin can be read from (input) / written to (output) a register. SPI Mode: SDO (output) Serial Data Output on the SPI interface to be connected to the SI pin of the EEPROM. All modes: SVN1 - System Version Number 1 (input) During reset the state of this pin (pull up/down resistor) is latched to the internal System Version Number register. After reset this pin performs the functions described above. An internal pull down resistor is provided. 77 AUX6 I/O Auxiliary Port 6 Non SPI Mode: AUX6 (input/output), INT1 If not used for the SPI interface, this pin is programmable as general input/output. The state of the pin can be read from (input) / written to (output) a register. In addition to that, as an input, it can generate an interrupt (ISTAA.INT1) which is maskable in MASKA. INT1. The interrupt input is either edge or level triggered (ACFG2.EL1). As an output it is able to sink higher current and so allows for direct connection of an LED in stand-alone applications. An internal pullup resistor is connected to this pin. SPI Mode: SCK (output) Serial Clock output to EEPROM 5 AUX7 I/O Auxiliary Port 7 AUX7 (input/output), INT2 This pin is programmable as general input/output. The state of the pin can be read from (input) / written to (output) a register. In addition to that, as an input, it can generate an interrupt (ISTAA.INT2) which is maskable in MASKA. INT2. The interrupt input is either edge or level triggered (ACFG2.EL2). As an output it is able to sink higher current and so allows for direct connection of an LED in standalone applications. An internal pullup resistor is connected to this pin. Product Overview 15 10.99 PSB 2154 Pin Description Table 3 Pin Definition - External Memory Interface Pin Symbol Input (I) Function No. Output (O) 41 MMOD I Memory Mode Select For memory extension MMOD is used to indicate to the C whether program and data share the same external memory device ('0') or physically separate memories for program and data are connected ('1'). This pin has no effect on the hardware functions of the device. 9 PSEN O Program Store Enable This control signal enables the external program memory to the bus during external fetch operations. It is activated every six 48 MHz clock periods except during external data memory accesses. The signal remains high during internal program execution. 11 ALE / CS I/O Address Latch Enable / Chip Select - Normal Mode: This pin is used as low active chip select signal to external program and data memory. - Emulation Mode: During reset this pin is used as an input to enter emulation mode ('0'). An internal pull-up resistor is provided. In emulation mode this output is used for latching the address into external memory during normal operation. It is activated every 6 48MHz clock periods except during an external data memory access. 8 EA I/O External Access Enable When held high, the C800 executes instructions from the internal program memory till internal program space is exceeded. When held low, the C800 fetches all instructions from the external program memory. It is used an an output during emulation. 23 22 21 40 39 38 37 36 A.0 A.7 O Address Port This is an 8-bit output port which is used to emit the loworder address byte for access to external program memory. Product Overview 16 10.99 PSB 2154 Pin Description Table 3 Pin Definition - External Memory Interface Pin Symbol Input (I) Function No. Output (O) 24 20 19 18 17 16 15 12 P0.0 P0.7 I/O Port 0 This is an 8-bit open-drain bidirectional I/O port. Port 0 pins that have 1's written to them float, and in that state can be used as high-impedance inputs. Port 0 is also the data bus during accesses to external program and data memory. In this application it uses strong internal pullup resistors when issuing 1's. For emulation Port 0 is used as the multiplexed low-order address bus and data bus. 29 28 10 26 35 30 34 33 P2.0 P2.7 I/O Port 2 This is an 8-bit quasi-bidirectional I/O port with internal pullup resistors. Port 2 pins that have 1's written to them are pulled high by the internal pullup resistors, and in that state can be used as inputs. As inputs, port 2 pins being externally pulled low will source current because of the internal pullup resistors. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @ DPTR). In this application it uses strong internal pullup resistors when issuing 1's. During accesses to external data memory that use 8-bit addresses (MOVX @ Ri), port 2 issues the contents of the XPAGE register. P3.0 P3.4 I/O Port 3 This is an 8-bit quasi-bidirectional I/O port with internal pullup resistors. Port 3 pins that have 1's written to them are pulled high by the internal pullup resistors, and in that state can be used as inputs. As inputs, port 3 pins being externally pulled low will source current because of the internal pullup resistors. Port 3 also contains the interrupt, USB attach/detach status and external memory strobe pins that are used by various options. The output latch corresponding to a secondary function must be programmed to a 1 for that function to operate. The secondary functions are assigned to the pins of port 3, as follows: Product Overview 17 10.99 PSB 2154 Pin Description Table 3 Pin Definition - External Memory Interface Pin Symbol Input (I) Function No. Output (O) 6 7 31 I I O P3.0 / DADD P3.1 / INT0 P3.2 / WR 25 O P3.3 / RD 32 O P3.4 / PWR Device Attached input External Interrupt 0 input Write control output latches the data byte from port 0 into the external data memory. Read control output enables the output of the external data memory. Program Write Signal This signal is used as write signal to external program memory during firmware download operation. The port names Port 0, Port 2 and Port 3 have been intentionally selected for compliance with the C5XX C series. Port 1 is not implemented in the SIUC-X. Table 4 Pin Definition - Miscellaneous Pin Symbol Input (I) Function No. Output (O) 2 D+ I/O USB D+ Data Line The pin D+ can directly be connected to the USB cable (Transceiver is integrated onchip). A pull up resistor (1.5K 5%) must be connected to D+ to select full speed operation according to the USB spec. 3 D- I/O USB D- Data Line The pin D- can directly be connected to the USB cable. (Transceiver is integrated onchip). 48 RESET I Reset A LOW on this input forces the SIUC-X into a reset state. The duration of this pulse must be at least 4 ms to stabilize the internal oscillator. Following the reset, the microcontroller executes a complete machine cycle to initialize indirectly resetable registers. 43 42 BMOD0 I BMOD1 Product Overview Boot Mode Select 1,0 Selects the mode for firmware operation. Pin EA determines if the firmware should start from external offchip memory. 18 10.99 PSB 2154 Pin Description Table 4 Pin Definition - Miscellaneous Pin Symbol Input (I) Function No. Output (O) 67 EAW I External Awake If a negative level on this input is detected, the SIUC-X generates an interrupt (AUXI.EAW), and if enabled, a reset pulse. 47 ACL O Activation LED This pin can either function as a programmable output or automatically indicate the activated state of the S interface by a logic 0. An LED with pre-resistance may directly be connected to ACL. 55 56 SX1 SX2 O O S-Bus Transmitter Output Differential output for the S-transmitter. positive negative 59 60 SR1 SR2 I I S-Bus Receiver Input Differential inputs for the S-receiver. 51 XTAL1 I Oscillator Input Input pin of oscillator or input from external clock source. 7.68 MHz crystal or clock required. 52 XTAL2 O Oscillator Output Output pin of oscillator. Not connected if external clock source is used. 46 TEST I TEST This pin is reserved for test purposes during manufacturing and should be connected to GND. 66 res_l I reserved, pull LOW This pin is reserved and must be connected to VSS. Table 5 Pin Definition - Power Supply Pin Symbol Input (I) Function No. Output (O) 13 45 50 69 VDD I Digital Supply Voltage, +3.3V for core logic and oscillator 58 VDDA I Analog Supply Voltage, +3.3V for S-transceiver Product Overview 19 10.99 PSB 2154 Pin Description Table 5 Pin Definition - Power Supply Pin Symbol Input (I) Function No. Output (O) 53 VDDAP I Analog Supply Voltage, +3.3V for PLL 1 VDDU I Analog Supply Voltage, +3.3V for USB module 14 27 44 49 70 VSS I Digital GND, for core logic and oscillator 57 VSSA I Analog GND, for S-transceiver 54 VSSAP I Analog GND, for PLL 4 VSSU I 79 80 VREG1 VREG2 78 VSSAR Analog GND, for USB module Voltage Regulator These two pins from the internal voltage regulator are used to connect some additional external components for regulation. The regulator uses the USB power supply (bus-powered mode) to generate the +3.3V supply for the SIUC-X which must externally be connected to the VDDx pins (the supply is not connected internally). If the voltage regulator is not used (e.g. USB self-powered mode) VREG1/2 are left not connected and the external power supply is connected to the VDDx pins. I Analog GND, for Voltage Regulator Note: Some of the pins are used to latch certain values during reset. These are ALE/CS, AUX3/ELD, AUX4/SVN0 and AUX5/SVN1. The values on these pins must be held stable for at least 600 ns after reset. Product Overview 20 10.99 PSB 2154 Functional Block Diagram 3 Functional Block Diagram The data transfer from USB to S-Interface and vice versa takes place through the C XRAM and a set of FIFOs for each channel. The IOM-2 interface allows connection of other communication devices. The C ports can be used as general I/O port and enable the optional connection of external memory and provide emulation support. A dedicated address bus allows glueless connection of external memory with optimized layout. The auxiliary interface serves as a general purpose I/O port in addition to providing external interrupt sources, LED drivers and lines for the SPI interface. Two auxiliary pins are used to latch a number for vendor specific system identification during reset. A bootloader firmware contained in 4K ROM provides the ability to download operational firmware via USB to internal/external RAM. All registers corresponding to different peripherals are available in the Special Function Register (SFR) map of the C. The ISDN specific registers are located in the external memory map of the C. Onchip PLL provide clock generation for the S-transceiver and the 48 MHz USB clock. An onchip voltage regulator allows the flexibility for bus and self powered system architectures. Figure 7 gives an overview of the functional blocks. * IOM-2 IOM-2 Interface IOM-2 Handler EEPROM SPI B-Channel HDLC B-Channel HDLC D-Channel HDLC FIFO FIFO FIFO MONITOR C/I-Channel TIC-Bus ISDN Basic Access S Interface Auxiliary Interface General Purpose I/O I/O DPLL C800 CPU USB Interface USB On Chip Emulation Support Module PORT 0 256 x 8 IRAM 16384 x 8 XRAM PORT 2 PORT 3 Memory Interface, Emulation Figure 7 4096 x 8 ROM OSC Address Bus 2154_10a Block Diagram Product Overview 21 10.99