1
®
FN7292
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 |Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2003. All Rights Reserved. Elantec is a registered trademark of Elantec Semiconductor, Inc.
All other trademarks mentioned are the property of their respective owners.
EL7556B
Integrated Adjustable 6 Amp
Synchronous Switcher
The EL7556B is an adjustable
synchronous DC:DC switching
regulator optimized for a 5V input and
1.0V-3.8V output. By combining integrated NMOS power
FETs with a fused-lead package, the EL7556B can supply
up to 6A continuous output current without the use of
ex ternal power devices or discrete heat sinks, thereby
minimizing design effort and overall system cost.
On-chip resistorless current sensing is used to achieve
stable , highly efficient, current-mode control. The EL7556B
also incorporates the VCC2DET function to directly interface
with the Intel P54 and P55 microprocessors. Depending on
the state of VCC2DET, the output voltage is internally preset
to 3.5V or a user-adjustable voltage using two external
resistors. In both internal and external feedback modes the
active-high PWRGD output indicates when the regulator
output is within ±10% of the programmed voltage. An on-
board sensor monitors die temperature (OT) for over-
temperature conditions and can be connected directly to
OUTEN to provide automatic thermal shutdown. Adjustable
oscillator frequency and slope compensation allow added
flexibility in overall system design.
The EL7556B is av ailable in a 28-pin SO package and is
specified for operation over the full -40°C to +85°C
temperature range.
Pinout EL7556B
(28-PIN SO)
TOP VIEW
Features
• EL7556/EL7556A Pin-compatible
• Improved temperature and voltage ranges
• 6A continuous load current
• Precision internal 1% reference
• 1.0V to 3.8V output voltage
• Internal power MOSFETs
• >90% efficiency
• Synchronous switching
• Adjustable slope compensation
• Over-temperature indicator
• Pulse-by-pulse current limiting
• Operates up to 1MHz
• 1.5% typical output accuracy
• Adjustable oscillator with sync
• Remote enable/disable
• Intel P54- and P55-compatible
• VCC2DET interface
• Intern al soft-start
Applications
• PC motherboards
• Local high power CPU suppli es
• 5V to 1.0V DC:DC conversion
• Portable electronics/instr uments
• P54 and P55 regulators
• GTL + Bus power supply
1
2
3
4
16
1514
13
5
6
7
12
11
9
8
10
20
19
18
17
24
23
22
21
28
27
26
25
FB1
VSS
VHI
LX
LX
LX
LX
VSSP
VSSP
VSSP
VSSP
VIN
VIN
VDD
COSC
CSLOPE
CREF
TEST
VSSP
VSSP
VCC2DET
OUTEN OT
VSSP
CP
FB2
C2V
C4
C8
C7
D1
C10
L1
C11
R1
C 6
R5 R6
C3
0.22µF
20Ω
2.5µH
1mF
39pF
220pF
0.1µF
1µF
39.2Ω
0.1µF
5.1Ω
C9
660µF
D2
D3
C 5
1µF
R4 R3
100Ω150Ω
Connect to VSSP for
external feedback
Manufactured under U.S. Patents No. 5,723,974 and No. 5,793,126
PWRGD
VIN
VIN 1µF
C3, C4, C5, C6, C7 C8 - ceramic
C5, C11 - ceramic or tantalum
C9 - Sprague 293D337X 96R3 2X3 30µF
C10 - Sprague 293D337X96R3 3X330µF
L1 - Pulse Engineering, PE-53681
D1-D4: BAT54S fast diode
D4*
D4 Required for EL7556ACM Only
C12
(Optional)
VOUT =
1V*(1+R3/R4)
C12 - 1µ F
Ordering Information
PART NUMBER PACKAGE TAPE &
REEL PKG. NO.
EL7556BCM 28-Pin SO - MDP0027
EL7556BCM-T13 28-Pin SO 13” MDP0027
Data Sheet October 5, 2001
FOR UPDATED INFORMATION SEE
EL7556D
2
Absolute Maximum Ratings (TA = 25°C)
Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C
Supply (VIN). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.0V
Ambient Operating Temperature . . . . . . . . . . . . . . . .-40°C to +85°C
Output Pins . . . . . . . . . . . . . . . -0.3V below GND, +0.3V above VDD
Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .135°C
Peak Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9A
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditi ons above those indicated in the operational sections of this specification is not implied.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests
are at the specified temperature and are pulsed tests, therefor e: TJ = TC = TA
Electrical Specifications VDD = VIN = 5V, COSC = 1nF, CSLOPE = 470pF, TA = 25°C unless otherwise specified.
PARAMETER DESCRIPTION CONDITIONS MIN TYP MAX UNIT
GENERAL
IDD VDD Supply Current OUTEN = 4V, FOSC = 120kHz 11 25 mA
IDDOFF VDD Standby Current OUTEN = 0 0.1 mA
IVIN VIN No Load Current OUTEN = 0 3 5 mA
VOUT1 Output Initial Accuracy VCC2DET = 4V, IL = 3A (See Fig. 1) 3.450 3.500 3.550 V
VOUT2 Output Initial Accuracy VCC2DET = 0V, IL = 3A R3 = 150Ω,
R4 = 100Ω 2.450 2.500 2.550 V
VOUTLINE Output line Regulation VDD = 5V, ±10% -1 1 %
VOUTLOAD Output Load Regulation 0A<ILOAD<6A, Relative to IL = 3A.
Continuous Mode of Operation -1 1 %
RSHORT Short Circuit Load Resistance IL = 6A, Prior to Continuous Application of
RSHORT. OUTEN Connected to OT. 100 mΩ
II MAX Current Limit 9A
VOUTTC Output Tempco -40°C<TA<85°C ±1 %
TOT Over Temperature Threshold 135 °C
THYS Over Temperature Hysteresis 40 °C
VPWRGD Power Good Threshold Relative to
Programmed Output Voltage VCC2SEL = 4V, VOUT = 3.50V ±6 ±10 ±14 %
VDDOFF Minimum VDD for Shutdown 3.15 V
VDDON Maximum VDD for Startup 4.15 V
VHYS Input Hysteresis VHYS = VDDON-VDDOFF 0.5 V
MSS Soft start slope 7V/mS
DMAX Maximum duty cycle 96 %
CONTROLLER - INPUTS
IPUP VCC2DET, OUTEN Pull Up Current VCC2DET, OUTEN = 0 10 14 18 µA
ICSLOPE CSLOPE Charging Current 23 28.5 34 µA
IFB1 FB1 Input Pull Up Current 2µA
ROT Over Temperature Pull Up Resistance OT = 0V 30 40 50 kΩ
VIH VCC2DET, OUTEN Input High 4 V
VIL VCC2DET, OUTEN Input Low 0.8 V
VOH PWGD Powergood Drive High ILOAD = 1mA 3.5 V
VOL PWGD Powergood Drive Low ILOAD = -1mA 1.0 V
EL7556B
3
CONTROLLER - REFERENCE
VREF Reference Accuracy IREF = 0 1.247 1.260 1.273 V
VREFTC Reference Voltage Tempco 50 ppm/°C
VREFLOAD Reference Load Regulation 0<ILOAD<100µA 0.5 0.5 %/°C
CONTROLLER - DOUBLER
VC2V Voltage Doubler Output VDD = 5V, ILOAD = 10mA 7.5 8.1 8.7 V
CONTROLLER - OSCILLATOR
FRAMP Oscillator Ramp Amplitude 1.2 V
IOSC CHG Oscillator Charge Current 0.2V<VOSC<1.4V 150 µA
IOSC DIS Oscillator Discharge Current 0.2V<VOSC<1.4V 5 mA
FOSC Oscillator initial accuracy 100 120 140 kHz
tSYNC Minimum oscillator sync width 50 ns
POWER - FET
ILEAK LX Output Leakage to VSS LX = 0V 100 µA
RDSON Composite FET Resistance 18 30 mΩ
RDSONTC RDSON Tempco 0.1 mΩ/°C
tBRM FET break before make delay 10 ns
tLEB High side FET minimum on time (LEB) 140 ns
Electrical Specifications VDD = VIN = 5V, COSC = 1nF, CSLOPE = 470pF, TA = 25°C unless otherwise specified. (Continued)
PARAMETER DESCRIPTION CONDITIONS MIN TYP MAX UNIT
EL7556B
4
Typical Performance Curves
Load Regulation (CSLOPE=100pF)
3.47
3.54
3.53
3.52
3.51
3.50
3.49
3.48
3.46
VOUT (V)
IOUT (A)
0.5 3.0 6.0
Line Regulation (CSLOPE=100pF)
3.47
3.54
3.53
3.52
3.51
3.50
3.49
3.48
3.46
VOUT (V)
VIN (V)
4.5 5.0 5.5
50 75
0.4
0.5
0.8
CSLOPE (pF)
∆VOUT (±) (%)
0.6
0.7
100 125 150 175
Line Regulation vs CSLOPE (IOUT=3A)
VDD=VIN=5.0V ±10%
0.0
0.1
0.2
0.3
0.4
0.5
0.6
∆VOUT (±) (%)
Load Regulation vs CSLOPE (VIN=5.0V)
IOUT=3A, +3A, -2.5A
0.0
0.1
0.2
0.3
88
90
96
IOUT (A)
Efficiency (%)
92
94
6.5
Efficiency vs ILOAD (VOUT =3.5V )
VDD=VIN=5.0V (±10%)
80
82
84
86
0.5 1.5 2.5 3.5 4.5 5.5 0.5 1.5
90
95
100
IOUT (A)
Efficiency (%)
2.5 3.5 4.5 6.0
Efficiency vs ILOAD (VDD=5.0V)
70
75
80
85
5.5
50 75 100 125 150 175
CSLOPE (pF)
TA=25°C
VDD=4.5V
VDD=5.5V
VCC=3.5V
VCC=2.5V
VCC=1V
TA=25°C
IOUT=0.5A
IOUT=3A
IOUT=6A TA=25°C
VIN=5.5V
VIN=4.5V
VIN=5V
TA=25°C
VOUT=3.5A
VOUT=1A
VOUT=2.5A
TA=25°C
VOUT=3.5A
VOUT=1A
VOUT=2.5A
VDD=5V
EL7556B
5
Typical Performance Curves (Continued)
FOSC (kHz)
10000
10
COSC (pF)
FOSC vs COSC
1000
100
10
1100k100 1k 20
490
510
520
Temperature (°C)
FOSC (kHz)
40 60 80 140
450
460
470
480
FOSC vs Temperature
100
500
120
50 75
-0.5
0.0
1.5
CSLOPE (pF)
∆VOUT (±) (%)
0.5
1.0
100 125 150 175
VOUT vs CSLOPE
(VIN=5.0V, ILOAD=0.5A)
-3.0
-2.0
-1.5
-1.0
-2.5
1.0 1.5
0.5
1.0
1.5
VIDEAL (V)
Deviation in VOUT (%)
2.0 2.5 3.0 4.0
VOUT Variation vs Programmed Output
Voltage [VIDEAL=(1+R3/R4)]
-1.5
-1.0
-0.5
0.0
3.5
50 75
0.4
0.5
0.8
CSLOPE (pF)
∆VOUT (±) (%)
0.6
0.7
100 125 150 175
Line Regulation vs CSLOPE
VIN=VDD=5.0V ±10%
0.0
0.1
0.2
0.3
50 75
0.4
0.5
0.8
CSLOPE (pF)
∆VOUT (±) (%)
0.6
0.7
100 125 150 175
Load Regulation vs CSLOPE
IOUT=3A, +3A, -2.5A
0.0
0.1
0.2
0.3
0
TA=25°C
IOUT=0.5A
IOUT=6A
TA=25°C
VIN=4.5V
VIN=5.5VVIN=5V
TA=25°C
VOUT=1V
VOUT=3.5V
VOUT=2.5V
TA=25°C
C
SLOPE
=100pF
C
OSC
=220pF
Loop Gain Induced Error
TA=25°C
VDD=4.5V
VDD=5.5V
VDD=5V
EL7556B
6
Typical Performance Curves (Continued)
I(VDD) + I(VIN) vs FOSC
60
50
40
30
20
10
0
IQ (mA)
FOSC (kHz)
I(VIN) vs FOSC
16
12
10
6
4
2
0
IVIN (mA)
FOSC (kHz)
14
8
50
35
30
15
10
5
0
IDD (mA)
FOSC (kHz)
45
20
40
25
1.0
1.5
FOSC (kHz)
IDD (mA) + IVIN
100 1000
IDD + IVIN vs FOSC
2.0
10
2.3
1.9
1.7
1.3
1.1
0.9
0.7
VOUT (V)
2.1
1.5
3.0
0
20
VDD(V)
IQ (mA)
3.5 4.5 5.0
Power On Reset
40
2.5
30
10
4.0
I(VDD) vs FOSC
Minimum Output Voltage vs FOSC
FOSC (kHz)
VDD=5.5V
VDD=4.5V
TA=25°C
OUTEN=VDD
VDD=5V
Continuous ModeDiscontinuous Mode
VDD=5.5V
VDD=4.5V
TA=25°C
OUTEN=VDD
VDD=5V
Continuous ModeDiscontinuous Mode
VDD=5.5V
VDD=4.5V
TA=25°C
OUTEN=VDD
VDD=5V
VDD=5.5V
VDD=4.5V
VDD=5V
FOSC=500k
TA=25°C
OUTEN=VDD
VDD=5.5V
VDD=4.5V
VDD=5V
TJ=120°C
200 1000400 600 800 200 1000400 600 800
200 1000400 600 800
EL7556B
7
Typical Performance Curves (Continued)
41
35
29
27
25
ΘJA (°C/W)
Bare Cu Area (in2)
39
31
37
33
ΘJA vs Cu Area
6.004.002.001.00 5.00
8.0
7.0
5.5
5.0
4.5
4.0
ILOAD (A)
TA (°C)
6.0
7.5
6.5
Maximum ILOAD vs Temperature
7556 Demo Board (31°C/W)
38
32
30
24
20
RDSON (m Ω)
Temperature (°C)
36
26
34
28
RDSON vs Temperature
125755025 100
0.00 3.00
22
0
Board with no
Components
Board with
Inductor
100 LFPM
Still Air
OUTEN connected to OT
70604030 65
25 50
4535 55
EL7556B
8
Pin Descriptions
I = INPUT, O = OUTPUT, S = SUPPLY
PIN
NUMBER PIN NAME PIN
TYPE FUNCTION
1 FB1 I Voltage feedback pin for the buck regulator. Active when VCC2DET is logic low. Normally connected to
external resistor divider between VOUT and GND. A 2µA pull-up current forces VOUT to VSS in the event
that FB1is floating and VCC2DET is inadvertently connected to GND.
2 CREF I Bandgap reference bypass capacitor. Typically 0.1µF to VSS.
3 CSLOPE I Slope compensation capacitor. Ramp width corresponds to LX duty cycle. CSLOPE to COSC ratio is normally
1:1.5.
4 COSC I Oscillator timing capacitor. FOSC(Hz) can be approximated by: FOSC(Hz) = 0.0001/COSC. COSC in Farads.
5 VDD S Power Supply for PWM control circuitry. Normally the same potential as VIN.
6 VIN S Power supply for the buck regulator. Connected to the drain of the high-side NMOS FET.
7 VSSP S Ground return for the buck regulator. Connected to the source of the low-side synchronous NMOS FET.
8 VIN S Same as pin 6.
9 VSSP S Same as pin 7.
10 VSSP S Same as pin 7.
11 VSSP S Same as pin 7.
12 VSSP S Same as pin 7.
13 VCC2DET I VCC2DET interface logic input. When driven to logic 1 VOUT = 3.500V. When driven to logic 0 the PWM uses
FB1 to determine VOUT: VOUT = 1.0V*(1+R3/R4).
14 OUTEN I The switching regulator output is enabled when logic 1. The reference voltage output operates whenever the
power supply is qualified (VDD>VPOR) regardless of the state of this pin.
15 OT O Over temperature indicator. Normally high. Pulls low when die temperature exceeds 135°C, returns to the
high state when die temperature has cooled to 100°C.
16 PWRGD O Power good window comparator output. Logic 1 when regulator output is within ±10% of programmed voltage.
17 TEST I Test pin. Must be connected to VSSP in normal operation.
18 VSSP S Same as pin 7.
19 VSSP S Same as pin 7.
20 LX O Inductor drive pin. High current switching output whose average voltage equals the regulator output voltage.
21 LX O Same as pin 20.
22 LX O Same as pin 20.
23 LX O Same as pin 20.
24 VHI I Gate drive to high-side driver. Bootstrapped from LX with a 0.1µF capacitor.
25 VSS S Ground return for the control circuitry.
26 C2V I Connected to voltage doubler output. Supplies gate drive to the low-side driver.
27 CP O Drives the negative side of charge pump capacitor at one-half the oscillator frequency FOSC.
28 FB2 I Voltage feedback pin. Active when VCC2DET is logic 1. Internally preset to VOUT = 3.5V.
EL7556B
9
Block Diagram
Applications Information
Circuit Description
General
The EL7556B is a fixed frequency, current mode controlled
DC:DC converter with integrated N-channel power
MOSFETs and a high precision reference. The device
incorporates all of the active circuitry required to implement
a cost effective, user-programmable 6A synchronous buck
converter suitable for use in CPU power supplies. By
combining fused-lead packaging technology with an efficient
synchronous switching architecture, high power outputs
(21W) can be realized without the use of discrete e xternal
heat sinks.
Theory of Operation
The EL7556B is composed of 7 major bloc ks:
1. PWM Controller
2. Output Voltage Mode Select
3. NMOS Power FETS and Drive Circuitry
4. Bandgap Reference
5. Oscillator
6. Temperature Sensor
7. Power Good and Power On Reset
PWM Controller
The EL7556B regulates output voltage through the use of
current-mode controlled pulse width modulation. The three
main elements in a PWM controller are the feedback loop
and reference, a pulse width modul ator whose duty cycle is
controlled by the feedback error signal, and a filter which
averages the logic level modulator output. In a step-down
(buc k) conv erter , the feedback loop f orces the time-av eraged
output of the modulator to equal the desired output voltage.
Unlike pure voltage-mode control systems current-mode
control utilizes dual feedback loops to provide both output
voltage and inductor current information to the controller.
The voltage loop minimizes DC and transient errors in the
output voltage by adjusting the PWM duty-cycle in response
to changes in line or load conditions. Since the output
voltage is equal to the time-average of the modulator output
the relatively large LC time constants found in power supply
applications generally results in low bandwidth and poor
transient response. By directly monitoring changes in
inductor current via a series sense resistor the controller’s
response time is not entirely limited by the output LC filter
-
+
-
+
-
+
-
+
-
+
-
+
-
+
-
+
Σ
-
+
FB1, Pin1
FB2, Pin 28
VCCDET, Pin 13
CSLOPE, Pi n 3
CREF, Pin 27
2-1 MUX
1.26V
4V
UVLO
V2X
RSS
PWM
Current Limit
COSC, Pin 4
VDD
VDD
CSS
Zero Cross Detect
Current Sense
LEB TDELAY
Over Temp Sensor
Q
Q
R
S
FF
RS
PWRGD, Pin 16
CP, Pin 27
C2V, Pin 26
VHI, Pin 24
VDD and VIN,
Pin 5,6,8
LX, Pin 20-23
VSSP, Pin 9-12,
18-19
OT, Pin 15
VSS, Pin 25
S
R
OUTEN, Pin 14
EL7556B
10
and can react more quickly to changes in line or load
conditions. This feed-forward characteristic also simplifies
AC loop compensation since it adds a zero to the overall
loop response. Through proper selection of the current-
f eedback to voltage-f eedback ratio , the ov erall loop response
will approach a one pole system. The resulting system offers
several advantages over traditional voltage control systems,
including simpler loop compensation, pulse by pulse current
limiting, rapid response to line variation and good load step
response.
The heart of the controller is a triple-input direct summing
comparator which sums voltage f eedback, current feedbac k
and slope compensating ramp signals together . Slope
compensation is required to prevent system instability which
occurs in current-mode topologies operating at duty-cycles
greater than 50% and is also used to define the open-loop
gain of the overall system. The compensation ramp
amplitude is user adjustable and is set using a single
externa l capacitor (CSLOPE). Each comparator input is
weighted and determines the load and line regulation
characteristics of the system. Current feedback is measured
by sensing the inductor current flowing through the high-side
switch whenever it is conducting. At the beginning of each
oscillator period the high-side NMOS switch is turned on and
CSLOPE ramps positively from its reset state (VREF
potential). The comparator inputs are gated off for a
minimum period of time (LEB) after the high-side switch is
tur ned on to allow the system to settle. The Leading Edge
Blanking (LEB) period prev ents the detection of erroneous
voltages at the comparator inputs due to switching noise.
When programming low regulator output voltages the LEB
dela y will limit the maximum operating frequency of the
circuit since the LEB will result in a minimum duty-cycle
regardless of the PWM error voltage. This relationship is
shown in the performance curves. If the inductor current
exceeds the maximum current limit (ILMAX), a secondary
over-current comparator will terminate the high-side switch.
If ILMAX has not been reached, the regulator output voltage
is then compared to the reference voltage VREF. The
resultant error voltage is summed with the current feedback
and slope compensation ramp . The high-side switch remains
on until all three comparator inputs have summed to zero, at
which time the high-side switch is turned off and the low-side
s witch is turned on. In order to eliminate cross-conduction of
the high-side and low-side switches a 10ns break-before-
make delay is incorporated in the switch driver circuitry. In
the continuous mode of operation the low-side switch will
remain on until the end of the oscillato r period. In order to
improve the low current efficiency of the EL7556B, a zero-
crossing comparator senses when the inductor transitions
through zero . Turning off the low-side switch at zero inductor
current prevents forward conduction through the intern al
clamping diodes (LX to VSSP) when the low-side switch
turns off, reducing power dissipation. The output enable
(OUTEN) input allows the regulator output to be disabled by
an external logic control signal.
Output Voltage Mode Select
The VCC2DET multiplexes the FB1 and FB2 pins to the
PWM controller. A logic 1 on VCC2DET selects the FB2
input and forces the output voltage to the internally
programmed value of 3.50V. A logic zero on VCC2DET
selects FB1 and allows the output to be programmed from
1.0 to 3.8V. In general:
However, due to the relatively low open loop gain of the
system, gain errors will occur as the output voltage and loop-
gain are changed. This is shown in the performance curves.
(The output voltage is fa ctory trimmed to minimize error at a
2.50V output). A 2uA pull-up current from FB1 to VIN fo rces
VOUT to GND in the event that FB1 is not used and the
VCC2DET is inadvertently toggled between the internal and
external feedback mode of operation.
NMOS Power FETs and Drive Circuitry
The EL7556B integrates low resistance (25mΩ) NMOS
FETs to achiev e high efficiency at 6A. Gate driv e for both the
high-side and low-side switches is derived through a charge
pump consisting of the CP pin and extern al components D1-
D3 and C5-C6. The CP output is a low resistance inverter
driven at one-half the oscillator frequency. This is used in
conjunction with D2-D3 to generate a 7.5V (typical) voltage
on the C2V pin which provides gate drive to the low-side
NMOS switch and associated lev el shifter. In order to use an
NMOS switch for the high-side drive it is necessary to drive
the gate voltage above the source voltage (LX). This is
accomplished by boot-strapping the VHI pin above the C2V
voltage with capacitor C6 and diode D1. When the low-side
switch is turned on the LX voltage is close to GND potential
and capacitor C6 is charged through diodes D1-D3 to
appro ximately 6.9V. At the beginning of the next cycle the
high side switch turns on and the LX pin begins to rise from
GND to VDD potential. As the LX pin rises the positive plate
of capacitor C6 follows and eventually reaches a value of
approximately 11.2V, for VDD=5V. This voltage is then level
shifted and used to drive the gate of the high-side FET, via
the VHI pin.
Reference
A 1% temperature compensated band gap reference is
integrated in the EL7556B. The e xternal CREF capacitor acts
as the dominant pole of the amplifier and can be increased
in size to maximize transient noise rejection. A value of
0.1uF is recommended.
Oscillator
The system clock is generated by an internal relaxation
oscillator with a maximum duty-cycle of approximately 96%.
VOUT 1V 1 R3
R4
-------+
×Volt×=
EL7556B
11
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Operating frequency can be adjusted through the COSC pin
or can be driven by an external clock source. If the oscillator
is driven by an external source, care must be taken in the
selection of CSLOPE. Since the COSC and CSLOPE values
deter mine the open loop gain of the system, changes to
COSC require corresponding changes to CSLOPE in order to
maintain a constant gain ratio. The recommended ratio of
COSC to CSLOPE is 1.5:1
Temperature Sensor
An inter nal temperature sensor continuously monitors die
temperature. In the event that die temperature exceeds the
thermal trip-point, the OT pin will output a logic 0. The upper
and lower trip points are set to 135°C and 100°C
respectively. To enable ther mal shutdown this pin should be
tied directly to OUTEN. Use of this feature is recommended
during no rmal operati on.
Power Good and Power On Reset
During power up the output regulator will be disabled until
VIN reaches a value of approximately 4.0V. Approximately
500mV of hysteresis is present to eliminate noise induced
oscillations.
Under-voltage and over-voltage conditions on the regulator
output are detected through an internal window comparator.
A logic 1 on the PWRGD output indicates that regulated
output voltage is within ±10% of the nominally programmed
output voltage. Although small, the typical values of the
PWRGD threshold will vary with changes to external
f eedback (and resultant loop gain) of the system. This
dependence is shown in the typical performance curves.
Thermal Management
The EL7556B utilizes “fused lead” packaging tech nology in
conjunction with the system board layout to achieve a lower
thermal resistance than typically found in standard 28-pin
SO packages. By fusing (or connecting) multiple exter nal
leads to the die substrate within the package, a very
conductive heat path to the outside of the package is
created. This conductive heat path MUST then be connected
to a heat sinking area on the PCB in order to dissipate heat
out and away from the device. The conductive paths for the
EL7556B package are the fused leads: # 7, 9, 10, 11, 12, 18,
and 19. If a sufficient amount of PCB metal area is
connected to the fused package leads, a junction-to-ambient
thermal resistance of approximately 31°C/W can be
achieved (compared to 78°C/W for a standard SO28
package). The general relationship between PCB heat-
sinking metal area and the thermal resistance for this
package is shown in the Performance Curves section of this
data sheet. It can be readily seen that the thermal resistance
for this package approaches an asymptotic value of
approximately 31°C/W without any airflow. Additional
information can be found in Application Note #8 (Measuri ng
the Thermal Resistance of P ower Surface-Mount Pac kages).
If the thermal shutdown pin is connected to OUTEN the IC
will enter thermal shutdown when the maximum junction
temperature is reached. For a thermal sh utdown of 135°C
and power dissipation of 2.2W the ambient temperature is
limited to a maximum value of 67°C (typical). The ambient
temperature range can be extended with the application of
air flow. For example, the addition of 100LFM reduces the
ther mal resistance by approximately 15% and can extend
the operating ambient to 77°C (typical). Since the thermal
performance of the IC is heavily dependent on the board
la yout, the system designer should exercise care during the
design phase to ensure that the IC will operate under the
worst-case environmental conditions.
EL7556B
