24AA01/SNB21 - Microchip Technology, Inc.



1998 Microchip Technology Inc. DS21052H-page 1

24AA01/02

FEATURES

• Single supply with operation down to 1.8V

• Low power CMOS technology

- 1 mA active current typical

- 10

A standby current typical at 5.5V

-3

A standby current typical at 1.8V

• Organized as a single b lock of 128 b ytes (128 x 8)

or 256 bytes (256 x 8)

• 2-wire serial interface bus, I



compatible

• Schmitt trigger, ﬁltered inputs for noise suppres-

sion

• Output slope control to eliminate ground bounce

• 100 kHz (1.8V) and 400 kHz (5V) compatibility

• Self-timed write cycle (including auto-erase)

• Page-write buffer for up to 8 bytes

• 2 ms typical write cycle time for page-write

• Hardware write protect for entire memory

• Can be operated as a serial ROM

• ESD protection > 3,000V

• 1,000,000 ERASE/WRITE cycles guaranteed

• Data retention > 200 years

• 8-pin DIP or SOIC package

• Available for extended temperature ranges

DESCRIPTION

The Microchip Technology Inc. 24AA01 and 24AA02

are 1K bit and 2K bit Electrically Erasable PR OMs. The

devices are organized as a single block of 128 x 8-bit

or 256 x 8-bit memor y with a two wire serial interface.

Low-v oltage design permits operation down to 1.8 v olts

with standby and activ e currents of only 3

A and 1 mA,

respectively. The 24AA01 and 24AA02 also hav e page-

write capability for up to 8 bytes of data. The 24AA01

and 24AA02 are available in the standard 8-pin DIP

and 8-pin surface mount SOIC packages.

PACKAGE TYPES

BLOCK DIAGRAM

- Commercial (C): 0°C to +70°C

- Industrial (I): -40°C to +85°C

24AA01/02

VSS

VCC

SCL

SDA

24AA01/02

VSS

VCC

SCL

SDA

PDIP

SOIC

HV GENERATOR

EEPROM

ARRAY

PAGE LATCHES

YDEC

XDEC

SENSE AMP

R/W CONTROL

MEMORY

CONTROL

LOGIC

I/O

CONTROL

LOGIC

SDA SCL

VCC

VSS

1K 1.8V I

™

Serial EEPROM

C is a trademark of Philips Corporation

24AA01/02

DS21052H-page 2



1998 Microchip Technology Inc.

1.0 ELECTRICAL

CHARACTERISTICS

1.1 Maximum Ratings*

...................................................................................7.0V

All inputs and outputs w.r.t. V

................-0.6V to V

+1.0V

Storage temperature.....................................-65°C to +150°C

Ambient temp. with power applied..............-65°C to +125°CC

Soldering temperature of leads (10 seconds).............+300°C

ESD protection on all pins

..................................................≥

4 kV

*Notice:

Stresses above those listed under “Maximum ratings”

may cause permanent damage to the device. This is a stress rat-

ing only and functional operation of the device at those or any

other conditions above those indicated in the operational listings

of this speciﬁcation is not implied. Exposure to maximum rating

conditions for extended periods may affect device reliability.

TABLE 1-1: PIN FUNCTION TABLE

FIGURE 1-1: BUS TIMING START/STOP

Name Function

Ground

SDA Serial Address/Data/I/O

SCL Serial Clock

WP Write Protect Input

+1.8V to 5.5V Power Supply

A0, A1, A2 No Internal Connection

TABLE 1-2: DC CHARACTERISTICS

= +1.8V to +5.5V

Commercial (C):Tamb = 0°C to +70°C

Industrial (I): Tamb = -40°C to +85°C

Parameter Symbol Min Typ Max Units Conditions

WP, SCL and SDA pins:

High level input voltage

Low level input voltage

Hysteresis of Schmitt trigger

inputs

Low level output voltage

HYS

.7 V

—

.05 V

—

.3 V

—

.40

(Note)

= 3.0 mA, V

= 1.8V

Input leakage current I

-10 — 10

= .1V to 5.5V

Output leakage current I

-10 — 10

OUT

= .1V to 5.5V

Pin capacitance

(all inputs/outputs) C

OUT

— — 10 pF Vcc = 5.0V (Note 1)

Tamb = 25˚C, F

LCK

= 1 MHz

Operating current I

Write

Read

—

0.5

—

0.05

—

= 5.5V, SCL = 400 kHz

= 1.8V, SCL = 100 kHz

= 5.5V, SCL = 400 kHz

= 1.8V, SCL = 100 kHz

Standby current I

CCS

—

100

—

= 5.5V, SDA = SCL = V

= 3.0V, SDA = SCL = V

= 1.8V, SDA = SCL = V

WP = V

Note:This parameter is periodically sampled and not 100% tested.

TSU:STA THD:STA

VHYS

TSU:STO

START STOP

SCL

SDA

24AA01/02



1998 Microchip Technology Inc. DS21052H-page 3

FIGURE 1-2: BUS TIMING DATA

TABLE 1-3: AC CHARACTERISTICS

Parameter Symbol Standard Mode V

= 4.5 - 5.5V

Fast Mode Units Remarks

Min Max Min Max

Clock frequency F

CLK

— 100 — 400 kHz

Clock high time T

HIGH

4000 — 600 — ns

Clock low time T

LOW

4700 — 1300 — ns

SDA and SCL rise time T

— 1000 — 300 ns (Note 1)

SDA and SCL fall time T

— 300 — 300 ns (Note 1)

START condition hold time T

STA

4000 — 600 — ns After this period the ﬁrst

clock pulse is generated

START condition setup

time T

STA

4700 — 600 — ns Only relevant for repeated

START condition

Data input hold time T

DAT

0—0—ns(Note 2)

Data input setup time T

DAT

250 — 100 — ns

STOP condition setup time T

STO

4000 — 600 — ns

Output valid from clock T

— 3500 — 900 ns (Note2)

Bus free time T

BUF

4700 — 1300 — ns Time the bus must be free

before a new transmis-

sion can start

Output fall time from V

min to V

max T

— 250 20 +0.1

250 ns (Note 1), C

≤

100 pF

Input ﬁlter spike suppres-

sion (SDA and SCL pins) T

— 50 — 50 ns (Note 3)

Write cycle time T

— 10 — 10 ms Byte or Page mode

Endurance — 1M — 1M — cycles 25°C, Vcc = 5.5V, Block

Mode (Note 4)

Note 1:

Not 100% tested. C

= total capacitance of one bus line in pF.

As a transmitter, the device must provide an internal minimum delay time to bridge the undeﬁned region

(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.

The combined T

and V

HYS

speciﬁcations are due to new Schmitt trigger inputs which provide improved

noise spike suppression. This eliminates the need for a T

speciﬁcation for standard operation.

This parameter is not tested b ut guaranteed b y characterization. For endur ance estimates in a speciﬁc appli-

cation, please consult the Total Endurance Model which can be obtained on our BBS or website.

SCL

TSU:STA

TLOW

THIGH

THD:DAT TSU:DAT TSU:STO

THD:STA TBUF

TAA

TSP

THD:STA

SDA

OUT

24AA01/02

DS21052H-page 4  1998 Microchip Technology Inc.

2.0 FUNCTIONAL DESCRIPTION

The 24AA01/02 supports a bi directional 2-wire bus

and data transmission protocol. A device that sends

data onto the bus is deﬁned as transmitter, and a

device receiving data as receiver. The bus has to be

controlled by a master device which generates the

serial clock (SCL), controls the bus access , and gener-

ates the START and STOP conditions, while the

24AA01/02 works as slav e. Both, master and slav e can

operate as transmitter or receiv er but the master de vice

determines which mode is activated.

3.0 BUS CHARACTERISTICS

The following bus protocol has been deﬁned:

• Data transfer may be initiated only when the bus

is not busy.

• During data transfer, the data line must remain

stable whenever the cloc k line is HIGH. Changes

in the data line while the clock line is HIGH will be

interpreted as a START or STOP condition.

Accordingly, the following bus conditions have been

deﬁned (Figure 3-1).

3.1 Bus not Busy (A)

Both data and clock lines remain HIGH.

3.2 Start Data Transfer (B)

A HIGH to LOW transition of the SDA line while the

clock (SCL) is HIGH determines a START condition.

All commands must be preceded by a START condi-

tion.

3.3 Stop Data Transfer (C)

A LOW to HIGH transition of the SDA line while the

clock (SCL) is HIGH determines a ST OP condition. All

operations must be ended with a STOP condition.

3.4 Data Valid (D)

The state of the data line represents valid data when,

after a START condition, the data line is stable for the

duration of the HIGH period of the clock signal.

The data on the line must be changed during the LOW

period of the clock signal. There is one cloc k pulse per

bit of data.

Each data transfer is initiated with a START condition

and terminated with a STOP condition. The number of

the data bytes transferred between the START and

STOP conditions is determined by the master device

and is theoretically unlimited, although only the last 16

will be stored when doing a write operation. When an

ov erwrite does occur it will replace data in a ﬁrst in ﬁrst

out fashion.

3.5 Acknowledge

Each receiving device, when addressed, is obliged to

generate an acknowledge after the reception of each

byte. The master device must generate an extra clock

pulse which is associated with this acknowledge bit.

The device that acknowledges, has to pull down the

SD A line during the ac kno wledge cloc k pulse in such a

way that the SDA line is stable LOW during the HIGH

period of the acknowledge related clock pulse. Of

course, setup and hold times must be taken into

account. A master must signal an end of data to the

slave by not generating an acknowledge bit on the last

byte that has been clocked out of the slave. In this

case, the sla ve must lea ve the data line HIGH to enable

the master to generate the STOP condition.

FIGURE 3-1: DATA TRANSFER SEQUENCE ON THE SERIAL BUS

Note: The 24AA01/02 does not generate any

acknowledge bits if an internal program-

ming cycle is in progress.

(A) (B) (D) (D) (A)(C)

DSCL

MSCL

DSCL

MSCL

START

CONDITION ADDRESS OR

ACKNOWLEDGE

VALID

DATA

ALLOWED

TO CHANGE

STOP

CONDITION

24AA01/02

 1998 Microchip Technology Inc. DS21052H-page 5

3.6 Device Address

The 24AA01/02 are software-compatible with older

devices such as 24C01A, 24C02A, 24LC01, and

24LC02. A single 24AA02 can be used in place of two

24LC01's, for example, without any modiﬁcations to

software. The “chip select” portion of the control byte

becomes a don't care.

After generating a START condition, the bus master

transmits the sla v e address consisting of a 4-bit device

code (1010) f or the 24AA01/02, follo w ed b y three don't

care bits.

The eighth bit of slav e address determines if the master

device wants to read or write to the 24AA01/02

(Figure 3-2).

The 24AA01/02 monitors the bus for its corresponding

slav e address all the time. It generates an ac knowledge

bit if the slave address was true and it is not in a pro-

gramming mode.

FIGURE 3-2: CONTROL BYTE

ALLOCATION

4.0 WRITE OPERATION

4.1 Byte Write

Following the start signal from the master, the device

code (4 bits), the don't care bits (3 bits), and the R/W

bit which is a logic low is placed onto the bus by the

master transmitter. This indicates to the addressed

slav e receiver that a byte with a w ord address will follow

after it has generated an acknowledge bit during the

ninth clock cycle . Theref ore the next byte transmitted by

the master is the word address and will be written into

the address pointer of the 24AA01/02. After receiving

another acknowledge signal from the 24AA01/02 the

master device will transmit the data word to be written

into the addressed memory location. The 24AA01/02

acknowledges again and the master generates a stop

condition. This initiates the internal write cycle, and dur-

ing this time the 24AA01/02 will not generate acknowl-

edge signals (Figure 4-1).

4.2 Page Write

The write control byte, w ord address and the ﬁrst data

byte are tr ansmitted to the 24AA01/02 in the same way

as in a byte write. But instead of generating a stop con-

dition the master transmits up to eight data b ytes to the

24AA01/02 which are temporarily stored in the on-chip

page buffer and will be written into the memory after the

master has transmitted a stop condition. After the

receipt of each word, the three lower order address

pointer bits are internally incremented by one. The

higher order ﬁve bits of the w ord address remains con-

stant. If the master should transmit more than eight

words prior to generating the stop condition, the

address counter will roll over and the previously

received data will be o verwritten. As with the byte write

operation, once the stop condition is received an inter-

nal write cycle will begin (Figure 7-1).

Operation Control

Code Chip Select R/W

Read 1010 XXX 1

Write 1010 XXX 0

SLAVE ADDRESS

X = Don’t care

1010XXX

R/W A

START READ/WRITE

Note: Page write operations are limited to writing

bytes within a single physical page, regard-

less of the number of bytes actually being

written. Physical page boundaries start at

addresses that are integer multiples of the

page buffer size (or Ôpage sizeÕ) and end at

addresses that are integer multiples of

[page size - 1]. If a page write command

attempts to write across a physical page

boundary, the result is that the data wraps

around to the beginning of the current page

(overwriting data previously stored there),

instead of being written to the next page as

might be expected. It is therefore neces-

sary for the application software to prevent

page write operations that would attempt to

cross a page boundary.

24AA01/02

DS21052H-page 6  1998 Microchip Technology Inc.

FIGURE 4-1: BYTE WRITE

FIGURE 4-2: PAGE WRITE

S P

BUS ACTIVITY

MASTER

SDA LINE

BUS ACTIVITY

CONTROL

BYTE WORD

ADDRESS DATA

S P

BUS ACTIVITY

MASTER

SDA LINE

BUS ACTIVITY

CONTROL

BYTE WORD

ADDRESS (n) DATA n DATA n + 7 S

DATA n + 1

24AA01/02

 1998 Microchip Technology Inc. DS21052H-page 7

5.0 ACKNOWLEDGE POLLING

Since the device will not acknowledge during a write

cycle, this can be used to determine when the cycle is

complete (this feature can be used to maximize bus

throughput). Once the stop condition for a write com-

mand has been issued from the master, the device ini-

tiates the internally timed wr ite cycle. ACK polling can

be initiated immediately. This in volv es the master send-

ing a start condition followed by the control byte for a

write command (R/W = 0). If the de vice is still b usy with

the write cycle, then no ACK will be returned. If the

cycle is complete, then the device will return the ACK

and the master can then proceed with the next read or

write command. See Figure 5-1 for ﬂow diagram.

FIGURE 5-1: ACKNOWLEDGE POLLING

FLOW

6.0 WRITE PROTECTION

The 24AA01/02 can be used as a serial ROM when the

WP pin is connected to VCC. Programming will be inhib-

ited and the entire memory will be write-protected.

7.0 READ OPERATION

Read operations are initiated in the same way as write

operations with the exception that the R/W bit of the

slav e address is set to one. There are three basic types

of read operations: current address read, random

read, and sequential read.

7.1 Current Address Read

The 24AA01/02 contains an address counter that

maintains the address of the last word accessed, inter-

nally incremented by one. Therefore, if the previous

access (either a read or write operation) was to

address n, the next current address read operation

would access data from address n + 1. Upon receipt of

the slave address with R/W bit set to one , the 24AA01/

02 issues an acknowledge and transmits the eight bit

data word. The master will not acknowledge the trans-

f er but does generate a stop condition and the 24AA01/

02 discontinues transmission (Figure 7-1).

7.2 Random Read

Random read operations allow the master to access

any memory location in a random manner. To perform

this type of read operation, ﬁrst the word address m ust

be set. This is done by sending the word address to the

24AA01/02 as par t of a wr ite operation. After the word

address is sent, the master generates a start condition

following the acknowledge. This terminates the write

operation, b ut not bef ore the internal address pointer is

set. Then the master issues the control byte again but

with the R/W bit set to a one. The 24AA01/02 will then

issue an acknowledge and transmits the eight bit data

word. The master will not acknowledge the transfer but

does generate a stop condition and the 24AA01/02 dis-

continues transmission (Figure 7-2).

7.3 Sequential Read

Sequential reads are initiated in the same wa y as a ran-

dom read except that after the 24AA01/02 transmits the

ﬁrst data byte, the master issues an acknowledge as

opposed to a stop condition in a random read. This

directs the 24AA01/02 to transmit the ne xt sequentially

addressed 8-bit word (Figure 7-3).

To provide sequential reads the 24AA01/02 contains an

internal address pointer which is incremented by one at

the completion of each operation. This address pointer

allows the entire memory contents to be serially read

during one operation.

7.4 Noise Protection

The 24AA01/02 employs a VCC threshold detector cir-

cuit which disables the internal erase/write logic if the

VCC is below 1.5 volts at nominal conditions.

The SCL and SD A inputs hav e Schmitt trigger and ﬁlter

circuits which suppress noise spikes to assure proper

device operation even on a noisy bus.

Send

Write Command

Send Stop

Condition to

Initiate Write Cycle

Send Start

Send Control Byte

with R/W = 0

Did Device

Acknowledge

(ACK = 0)?

Operation

Yes

24AA01/02

DS21052H-page 8  1998 Microchip Technology Inc.

FIGURE 7-1: CURRENT ADDRESS READ

FIGURE 7-2: RANDOM READ

FIGURE 7-3: SEQUENTIAL READ

8.0 PIN DESCRIPTIONS

8.1 SDA Serial Address/Data Input/Output

This is a bi-directional pin used to transfer addresses

and data into and data out of the device. It is an open

drain terminal, therefore the SDA bus requires a pullup

resistor to VCC (typical 10KΩ for 100 kHz, 2K for 400

kHz).

F or normal data transf er SDA is allo wed to change only

during SCL low. Changes during SCL high are

reserved for indicating the START and STOP condi-

tions.

8.2 SCL Serial Clock

This input is used to synchronize the data transf er from

and to the device.

8.3 WP

This pin must be connected to either VSS or VCC.

If tied to VSS, normal memory operation is enabled

(read/write the entire memory).

If tied to VCC, WRITE operations are inhibited. The

entire memory will be write-protected. Read opera-

tions are not affected.

This f eature allows the user to use the 24AA01/02 as a

serial ROM when WP is enabled (tied to VCC).

8.4 A0, A1, A2

These pins are not used by the 24AA01/02. They may

be left ﬂoating or tied to either VSS or VCC.

BUS ACTIVITY

MASTER

SDA LINE

BUS ACTIVITY

CONTROL

BYTE DATA n

S P

BUS ACTIVITY

MASTER

SDA LINE

BUS ACTIVITY

CONTROL

BYTE

WORD

ADDRESS (n) CONTROL

BYTE

TDATA (n)

BUS ACTIVITY

MASTER

SDA LINE

BUS ACTIVITY

CONTROL

BYTE

DATA n DATA n + 1 DATA n + 2 DATA n + X

24AA01/02

 1998 Microchip Technology Inc. DS21052H-page 9

NOTES:

24AA01/02

DS21052H-page 10  1998 Microchip Technology Inc.

NOTES:

24AA01/02

 1998 Microchip Technology Inc. DS21052H-page 11

24AA01/02 PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales ofﬁce..

Sales and Support

24AA01/02 — /P

Package: P = Plastic DIP (300 mil Body), 8-lead

SN = Plastic SOIC (150 mil Body), 8-lead

SM = Plastic SOIC (207 mil Body), 8-lead

Temperature Blank = 0°C to +70°C

Range: I= -40°C to +85°C

Device:

24AA01 1.8V, 1K I2C Serial EEPROM

24AA01T 1.8V, 1K I2C Serial EEPROM (Tape and Reel)

24AA02 1.8V, 2K I2C Serial EEPROM

24AA02T 1.8V, 2K I2C Serial EEPROM (Tape and Reel)

Data Sheets

Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recom-

mended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:

1. Your local Microchip sales ofﬁce

2. The Microchip Corporate Literature Center U.S. FAX: (602) 786-7277

3. The Microchip Worldwide Site (www.microchip.com)

Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.

New Customer Notiﬁcation System

 2002 Microchip Technology Inc.

Information contained in this publication regarding device

applications and the like is intended through sug gestion only

and may be superseded by updates. It is your responsibility to

ensure that your application meets with your specifications.

No representation or warranty is given and no liability is

assumed by Microc hip Technology Inc orporated with respect

to the accuracy or use of such inf orm ation, or inf ringement of

patents or other intellectual property rights arising from such

use or otherwise. Use of Microchip’s products as critical com-

ponents in life support systems is not authorized except with

express written approval by Microchip. No licenses are con-

veyed, implicitly or otherwise, under any intellectual property

rights.

Trademarks

The Microchip name and logo, the Microchip logo, FilterLab,

KEELOQ, microID, MPLAB, PIC, PICmicro, PICMASTER,

PICSTART, PRO MATE, SEEVAL and The Embedded Control

Solutions Company are registered trademarks of Microchip T ech-

nology Incorporated in the U.S.A. and other countries.

dsPIC, ECONOMONITOR, FanSense, FlexRO M, fuzzyLAB,

In-Circuit Serial Programming, ICSP, ICEPIC, microPort,

Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM,

MXDEV, PICC, PICDEM, PICDEM.net, rfPIC, Select Mode

and Total Endurance are trademarks of Microchip Technology

Incorporated in the U.S.A.

Serialized Quick Turn Programming (SQTP) is a service mark

of Microchip Technology Incorpora ted in the U.S.A.

All other trademarks mentioned herein are property of their

respective companies.

Printed on recycled paper.

Microchip received QS-9000 quality system

certification for its worldwide headquarters,

design and wafer fabrication facilities in

Chandler and Tempe, Arizona in July 1999. The

Company’s quality system processes and

procedures are QS-9000 compliant for its

PICmicro® 8-bit MCUs, KEELOQ® code ho pp in g

devices, Serial EEPROMs and microperipheral

products. In addition, Microchip’s quality

system for the design and manufacture of

development systems is ISO 9001 certified.

Note the following details of the code protection feature on PICmicro® MCUs.

•The PICmicro family meets the specifications contained in the Microchip Data Sheet.

•Microchip believes that its family of PICmicro microcontrollers is one of the most secure products of its kind on the market today,

when used in the intended manner and under normal conditions.

•There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowl-

edge, require using the PICmicro microcontroller in a manner outside the operating specifications contained in the data sheet.

The person doing so may be engaged in theft of intellectual property.

•Microchip is willing to work with the customer who is concerned about the integrity of their code.

•Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable”.

•Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of

our product.

If you have any further questions about this matter, please contact the local sales office nearest to you.

 2002 Microchip Technology Inc.

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China - Shenzhen

Microchip Technology Consulting (Shanghai)

Co., Ltd., Shenzhen Liaison Office

Rm. 1315, 13/F, Shenzhen Kerry Centre,

Renminnan Lu

Shenzhen 518001, China

Tel: 86-755-2350361 Fax: 86-755-2366086

Hong Kong

Microchip Technology Hongkong Ltd.

Unit 901-6, Tower 2, Metroplaza

223 Hing Fong Road

Kwai Fong, N.T., Hong Kong

Tel: 852-2401-1200 Fax: 852-2401-3431

India

Microchip Technology Inc.

India Liaiso n Office

Divyasree Chambers

1 Floor, Wing A (A3/A4)

No. 11, O’Shaugnessey Road

Bangalore, 560 025, India

Tel: 91-80-2290061 Fax: 91-80-2290062

Japan

Microchip Technology Japan K.K.

Benex S-1 6F

3-18-20, Shinyokohama

Kohoku- Ku, Yokohama-shi

Kanagawa, 222-0033, Japan

Tel: 81-45-471- 6166 Fax: 81-45-471-6122

Korea

Microc hip Tech nolo gy Korea

168-1, Youngbo Bldg. 3 Floor

Samsung-Dong, Kangnam-Ku

Seoul, Ko re a 135- 88 2

Tel: 82-2-554-7200 Fax: 82-2-558-5934

Singapore

Microchip Technology Singapore Pte Ltd.

200 Midd le Ro ad

#07-02 Prime Centre

Singapore, 188980

Tel: 65-334-8870 Fax: 65 -334-8850

Taiwan

Microc hip Tech nolo gy Taiwan

11F-3, No. 207

Tung Hua North Road

Taipei, 105, Taiwan

Tel: 886-2-2717-7175 Fax: 886-2-2545-0139

EUROPE

Denmark

Microchip Technology Nordic ApS

Regus Business Centre

Lautrup hoj 1-3

Ballerup DK-2750 Denmark

Tel: 45 4420 9895 Fax: 45 4420 9910

France

Microc hip Tech nolo gy SARL

Parc d’Activite du Moulin de Massy

43 Rue du Saule T rapu

Batiment A - ler Et age

91300 Massy, France

Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79

Germany

Microc hip Tech nolo gy Gmb H

Gustav-Heinemann Ring 125

D-81739 Munich, Germany

Tel: 49-89-627-144 0 Fax: 49-89-627-144-44

Italy

Microc hip Tech nolo gy SRL

Centro Direzionale Colleoni

Palazzo Taurus 1 V. Le Colleoni 1

20041 Agrate Brianza

Milan, Italy

Tel: 39-039-65791-1 Fax: 39-039-6899883

United Kingdom

Arizona Microchip Technology Ltd.

505 Eskdale Road

Winnersh Triangle

Wokingham

Berksh ire, E ngla nd RG 41 5TU

Tel: 44 118 921 5869 Fax: 44-118 921-5820

01/18/02

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