CL
VDD = Pin 14
VSS = Pin 7
VDD
VSS
4 (10)
RESET
TG
CL
5 (9)
DATA
p
n
MASTER SECTION
CL
TG
CL
p
n
6 (8)
SET
3 (11)CL
CL CL
CL
TG
CL
p
n
CL
TG
CL
p
n
1 (13)
Q
Q
SLAVE SECTION
2 (12)
Buffered Outputs
All inputs are protected by
CMOS protection network
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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
CD4013B
SCHS023E –NOVEMBER 1998–REVISED SEPTEMBER 2016
CD4013B CMOS Dual D-Type Flip-Flop
1
1 Features
1• Asynchronous Set-Reset Capability
• Static Flip-Flop Operation
• Medium-Speed Operation: 16 MHz (Typical) Clock
Toggle Rate at 10-V Supply
• Standardized Symmetrical Output Characteristics
• Maximum Input Current Of 1-µA at 18 V Over Full
Package Temperature Range:
– 100 nA at 18 V and 25°C
• Noise Margin (Over Full Package Temperature
Range):
– 1 V at VDD =5V
– 2 V at VDD = 10 V
– 2.5 V at VDD = 15 V
2 Applications
• Power Delivery
• Grid Infrastructure
• Medical, Healthcare, and Fitness
• Body Electronics and Lighting
• Building Automation
• Telecom Infrastructure
• Test and Measurement
3 Description
The CD4013B device consists of two identical,
independent data-type flip-flops. Each flip-flop has
independent data, set, reset, and clock inputs and Q
and Q outputs. These devices can be used for shift
register applications, and, by connecting Q output to
the data input, for counter and toggle applications.
The logic level present at the D input is transferred to
the Q output during the positive-going transition of the
clock pulse. Setting or resetting is independent of the
clock and is accomplished by a high level on the set
or reset line, respectively.
The CD4013B types are supplied in 14-pin dual-in-
line plastic packages (E suffix), 14-pin small-outline
packages (M, MT, M96, and NSR suffixes), and
14-pin thin shrink small-outline packages (PW and
PWR suffixes).
Device Information(1)
PART NUMBER PACKAGE BODY SIZE (NOM)
CD4013BE PDIP (14) 19.30 mm x 6.35 mm
CD4013BF CDIP (14) 19.50 mm x 6.92 mm
CD4013BM SOIC (14) 8.65 mm x 3.90 mm
CD4013BNS SO (14) 10.20 mm x 5.30 mm
CD4013BPW TSSOP (14) 5.00 mm x 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Logic Diagram
2
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Table of Contents
1 Features.................................................................. 1
2 Applications ........................................................... 1
3 Description............................................................. 1
4 Revision History..................................................... 2
5 Pin Configuration and Functions......................... 3
6 Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 5
6.5 Electrical Characteristics: Static................................ 5
6.6 Electrical Characteristics: Dynamic........................... 7
6.7 Typical Characteristics.............................................. 8
7 Detailed Description............................................ 10
7.1 Overview ................................................................ 10
7.2 Functional Block Diagram....................................... 10
7.3 Feature Description ................................................ 10
7.4 Device Functional Modes........................................ 10
8 Application and Implementation ........................ 11
8.1 Application Information............................................ 11
8.2 Typical Application.................................................. 11
9 Power Supply Recommendations...................... 12
10 Layout................................................................... 12
10.1 Layout Guidelines ................................................ 12
10.2 Layout Example .................................................... 12
11 Device and Documentation Support................. 14
11.1 Documentation Support ........................................ 14
11.2 Receiving Notification of Documentation Updates 14
11.3 Community Resources.......................................... 14
11.4 Trademarks........................................................... 14
11.5 Electrostatic Discharge Caution............................ 14
11.6 Glossary................................................................ 14
12 Mechanical, Packaging, and Orderable
Information........................................................... 14
4 Revision History
Changes from Revision D (March 2005) to Revision E Page
• Added ESD Ratings table, Feature Description section, Device Functional Modes,Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section.................................................................................................. 1
• Added Thermal Information table........................................................................................................................................... 5
1Q1 14 VDD
2Q1 13 Q2
3CLOCK1 12 Q2
4RESET1 11 CLOCK2
5D1 10 RESET2
6SET1 9 D2
7VSS 8 SET2
Not to scale
3
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5 Pin Configuration and Functions
D, J, N, NS, PW Package
14-Pin SOIC, CDIP, PDIP, SO, TSSOP
Top View
Pin Functions
PIN I/O DESCRIPTION
NO. NAME
1 Q1 O Channel 1 output
2 Q1 O Inverted channel 1 output
3 CLOCK1 I Channel 1 clock input
4 RESET1 I Channel 1 reset
5 D1 I Channel 1 data input
6 SET1 I Channel 1 set
7 VSS — Ground
8 SET2 I Channel 2 set
9 D2 I Channel 2 data input
10 RESET2 I Channel 2 reset
11 CLOCK2 I Channel 2 clock input
12 Q2 O Inverted channel 2 output
13 Q2 O Channel 2 output
14 VDD — Power supply
4
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(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Voltages reference to VSS terminal
(3) Derate linearity at 12 mW/°C
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
DC supply voltage, VDD(2) –0.5 20 V
Input voltage, all inputs –0.5 VDD + 0.5 V
DC input current, any one input 10 mA
Power dissipation, PDTA= –55°C to 100°C 500 mW
TA= 100°C to 125°C(3) 200
Device dissipation per output transistor 100 mW
Operating temperature, TA–55 125 °C
Storage temperature, Tstg –65 150 °C
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.2 ESD Ratings VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1000
(1) If more than one unit is cascaded in a parallel clocked operation, trCL must be made less than or equal to the sum of the fixed
propagation delay time at 15 pF and the transistion time of the output driving stage for the estimated capacitive load.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) MIN TYP MAX UNIT
Supply voltage 3 18 V
tSData setup time VDD = 5 40 nsVDD = 10 20
VDD = 15 15
tWClock pulse width VDD = 5 140 nsVDD = 10 60
VDD = 15 40
fCL Clock input frequency VDD = 5 3.5 7 MHzVDD = 10 8 16
VDD = 15 12 24
trCL(1)
tfCL Clock rise or fall time VDD = 5 15 µsVDD = 10 10
VDD = 15 5
tWSet or reset pulse width VDD = 5 180 nsVDD = 10 80
VDD = 15 50
5
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(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.4 Thermal Information
THERMAL METRIC(1) CD4013B
UNITN (PDIP) D (SOIC) NS (SO) PW (TSSOP)
14 PINS 14 PINS 14 PINS 14 PINS
RθJA Junction-to-ambient thermal resistance 47.1 92.5 89.3 121 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 34.5 54 47.1 49.6 °C/W
RθJB Junction-to-board thermal resistance 27.1 46.8 48 62.7 °C/W
ψJT Junction-to-top characterization parameter 19.4 19 17 5.9 °C/W
ψJB Junction-to-board characterization parameter 27 46.5 47.7 62.1 °C/W
6.5 Electrical Characteristics: Static
over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
IDDmax Quiescent device current
VIN = 0 or 5, VDD = 5
TA= –55°C 1
µA
TA= –40°C 1
TA= 25°C 0.02 1
TA= 85°C 30
TA= 125°C 30
VIN = 0 or 10, VDD = 10
TA= –55°C 2
TA= –40°C 2
TA= 25°C 0.02 2
TA= 85°C 60
TA= 125°C 60
VIN = 0 or 15, VDD = 15
TA= –55°C 4
TA= –40°C 4
TA= 25°C 0.02 4
TA= 85°C 120
TA= 125°C 120
VIN = 0 or 20, VDD = 20
TA= –55°C 20
TA= –40°C 20
TA= 25°C 0.04 20
TA= 85°C 600
TA= 125°C 600
6
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Electrical Characteristics: Static (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
IOLmin Output low (sink) current
VO= 0.4, VIN = 0 or 5,
VDD = 5
TA= –55°C 0.64
mA
TA= –40°C 0.61
TA= 25°C 0.51 1
TA= 85°C 0.42
TA= 125°C 0.36
VO= 0.5, VIN = 0 or 10,
VDD = 10
TA= –55°C 1.6
TA= –40°C 1.5
TA= 25°C 1.3 2.6
TA= 85°C 1.1
TA= 125°C 0.9
VO= 1.5, VIN = 0 or 15,
VDD = 15
TA= –55°C 4.2
TA= –40°C 4
TA= 25°C 3.4 6.8
TA= 85°C 2.8
TA= 125°C 2.4
IOHmin Output high (source)
current
VO= 4.6, VIN = 0 or 5,
VDD = 5
TA= –55°C –0.64
mA
TA= –40°C –0.61
TA= 25°C –0.51 –1
TA= 85°C –0.42
TA= 125°C –0.36
VO= 2.5, VIN = 0 or 5,
VDD = 5
TA= –55°C –2
TA= –40°C –1.8
TA= 25°C –1.6 –3.2
TA= 85°C –1.3
TA= 125°C –1.15
VO= 9.5, VIN = 0 or 10,
VDD = 10
TA= –55°C –1.6
TA= –40°C –1.5
TA= 25°C –1.3 –2.6
TA= 85°C –1.1
TA= 125°C –0.9
VO= 13.5, VIN = 0 or 15,
VDD = 15
TA= –55°C –4.2
TA= –40°C –4
TA= 25°C –3.4 –6.8
TA= 85°C –2.8
TA= 125°C –2.4
VOLmax Low-level output voltage
VIN = 0 or 5, VDD = 5 TA= –55°C, –40°C,
25°C, 85°C, and 125°C 0 0.05
VVIN = 0 or 10, VDD = 10 TA= –55°C, –40°C,
25°C, 85°C, and 125°C 0 0.05
VIN = 0 or 15, VDD = 15 TA= –55°C, –40°C,
25°C, 85°C, and 125°C 0 0.05
VOHmin High-level output voltage
VIN = 0 or 5, VDD = 5 TA= –55°C, –40°C,
25°C, 85°C, and 125°C 4.95 5
VVIN = 0 or 10, VDD = 10 TA= –55°C, –40°C,
25°C, 85°C, and 125°C 9.95 10
VIN = 0 or 15, VDD = 15 TA= –55°C, –40°C,
25°C, 85°C, and 125°C 14.95 15
7
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Electrical Characteristics: Static (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VILmax Input low voltage
VO= 0.5 or 4.5, VDD = 5 TA= –55°C, –40°C,
25°C, 85°C, and 125°C 1.5
VVO= 1 or 9, VDD = 10 TA= –55°C, –40°C,
25°C, 85°C, and 125°C 3
VO= 1.5 or 13.5,
VDD = 15 TA= –55°C, –40°C,
25°C, 85°C, and 125°C 4
VIHmin Input high voltage
VO= 0.5 or 4.5, VDD = 5 TA= –55°C, –40°C,
25°C, 85°C, and 125°C 3.5
VVO= 1 or 9, VDD = 10 TA= –55°C, –40°C,
25°C, 85°C, and 125°C 7
VO= 1.5 or 13.5,
VDD = 15 TA= –55°C, –40°C,
25°C, 85°C, and 125°C 11
IINmax Input current VIN = 0 or 18, VDD = 18
TA= –55°C ±0.1
µA
TA= –40°C ±0.1
TA= 25°C ±10–5 ±0.1
TA= 85°C ±1
TA= 125°C ±1
(1) Input tr, tf= 5 ns
6.6 Electrical Characteristics: Dynamic
at TA= 25°C, input tr, tf= 20 ns, CL= 50 pF, RL= 20 kΩ(unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tPHL,
tPLH Propagation delay time,
clock to Q or Q outputs
VDD = 5 150 300 nsVDD = 10 65 130
VDD = 15 45 90
tPLH Set to Q or reset to Q VDD = 5 150 300 nsVDD = 10 65 130
VDD = 15 45 90
tPHL Set to Q or reset to Q VDD = 5 200 400 nsVDD = 10 85 170
VDD = 15 60 120
tTHL,
tTLH Transition time VDD = 5 100 200 nsVDD = 10 50 100
VDD = 15 40 80
fCL Maximum clock input frequency(1) VDD = 5 3.5 7 MHzVDD = 10 8 16
VDD = 15 12 24
tW
Minimum clock pulse width VDD = 5 70 140 nsVDD = 10 30 60
VDD = 15 20 40
Minimum set or reset pulse width VDD = 5 90 180 nsVDD = 10 40 80
VDD = 15 25 50
tSMinimum data setup time VDD = 5 20 40 nsVDD = 10 10 20
VDD = 15 7 15
tHMinimum data hold time VDD = 5, 10, 15 2 5 ns
Drain-to-Source Voltage (V)
Output High (Source) Current (mA)
-25 -20 -15 -10 -5 0
-40
-35
-30
-25
-20
-15
-10
-5
0
D003
Gate-to-Source Voltage = -5 V
Gate-to-Source Voltage = -10 V
Gate-to-Source Voltage = -15 V
Drain-to-Source Voltage (V)
Output High (Source) Current (mA)
-25 -20 -15 -10 -5 0
-20
-15
-10
-5
0
D004
Gate-to-Source Voltage = -5 V
Gate-to-Source Voltage = -10 V
Gate-to-Source Voltage = -15 V
Drain-to-Source Voltage (V)
Output Low (Sink) Current (mA)
0 5 10 15 20 25
0
2.5
5
7.5
10
12.5
15
17.5
20
D002
Gate-to-Source Voltage = 5 V
Gate-to-Source Voltage = 10 V
Gate-to-Source Voltage = 15 V
8
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Electrical Characteristics: Dynamic (continued)
at TA= 25°C, input tr, tf= 20 ns, CL= 50 pF, RL= 20 kΩ(unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
trCL,
tfCL Clock input rise or fall time VDD = 5 15 µsVDD = 10 10
VDD = 15 5
CIN Input capacitance Any input 5 7.5 pF
6.7 Typical Characteristics
Figure 1. Typical Output Low (Sink) Current Figure 2. Minimum Output Low (Sink) Current
Figure 3. Typical Output High (Source) Current Figure 4. Minimum Output High (Source) Current
Supply Voltage (V)
Clock Frequency (MHz)
0 5 10 15 20 25
0
5
10
15
20
25
30
35
40
D025
Input Clock Frequency (kHz)
Power Dissipation Per Device (PW)
e
100 1k 10k 100k 1M 10M
1
10
100
1k
10k
D026
Supply Voltage = 5 V
Supply Voltage = 10 V (CL = 15 pF)
Supply Voltage = 10 V (CL = 50 pF)
Supply Voltage = 15 V
Load Capacitance (pF)
Propagation Delay Time (ns)
0 20 40 60 80 100
0
50
100
150
200
250
300
D023
Supply Voltage = 5 V
Supply Voltage = 10 V
Supply Voltage = 15 V
Load Capacitance (pF)
Propagation Delay Time (ns)
0 20 40 60 80 100
0
50
100
150
200
250
300
D024
Supply Voltage = 5 V
Supply Voltage = 10 V
Supply Voltage = 15 V
9
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Typical Characteristics (continued)
CLOCK or SET to Q, CLOCK or RESET to Q
Figure 5. Typical Propagation Delay Time
vs Load Capacitance
SET to Q or RESET to Q
Figure 6. Typical Propagation Delay Time
vs Load Capacitance
Figure 7. Typical Maximum Clock Frequency
vs Supply Voltage Figure 8. Typical Power Dissipation vs Frequency
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6
5 2
3
4
1
8
9 12
11
VDD
VSS
Q1CLOCK1
RESET1
D1
SET1
Q2CLOCK2
RESET2
SET2
D2
Q1
Q2
13
10
F/F1
F/F2
10
CD4013B
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7 Detailed Description
7.1 Overview
The CD4013B device consists of two identical, independent data-type flip-flops. Each flip-flop has independent
data, set, reset, and clock inputs and Q and Q outputs. These devices are ideal for data and memory hold
functions, including shift register applications, or by connecting Q output to the data input, this device is used for
counter and toggle applications. The CD4013B is a positive-edge triggered device, meaning that the logic level
present at the D input is transferred to the Q output during the positive-going transition of the clock pulse. Setting
or resetting is independent of the clock and is accomplished by a high level on the set or reset line, respectively.
7.2 Functional Block Diagram
7.3 Feature Description
CD4013B has standardized symmetrical output characteristics and a wide operating voltage range from 3 V to
18 V with quiescent current tested at 20 V. This has a medium operation speed –tPHL, tPLH = 30 ns (typical) at 10
V. The operating temperature is from –55°C to 125°C.
7.4 Device Functional Modes
Table 1 lists the functional modes of the CD4013B.
Table 1. Function Table
INPUTS OUTPUT (Q) INVERTED OUTPUT (Q)
CLOCK SET RESET D
↑0 0 0 0 1
↑0 0 1 1 0
↓0 0 X Q0Q
X 0 1 X 0 1
X 1 0 X 1 0
X 1 1 X 1 1
NC
A
GND
VCC
Y
3V
CLK
D
Q
VCC
RESET
GND Q
SET
TO MCU
3V
3V
SN74LVC1G17
CD4013B
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11
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
A high level at the SET or RESET inputs sets or resets the outputs, regardless of the levels of the other inputs.
When SET and RESET are inactive (low), data at the data (D) input meeting the setup time requirements is
transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level
and is not related directly to the rise time of the clock pulse. Following the hold-time interval, data at the D input
can be changed without affecting the levels at the outputs. The resistor and capacitor at the RESET pin are
optional. If they are not used, the RESET and SET pin must be connected directly to ground to be inactive.
8.2 Typical Application
Figure 9. Power Button Circuit
8.2.1 Design Requirements
Input signals must be designed and implemented so that they do not exceed the voltage level of the power
supply.
8.2.2 Detailed Design Procedure
The recommended input conditions for this application example includes rise time and fall time specifications
(see Δt/ΔVinRecommended Operating Conditions) and specified high and low levels (see VIH and VIL in
Recommended Operating Conditions). Inputs are not overvoltage tolerant and must be below VCC level because
of the presence of input clamp diodes to VCC. The recommended output condition for the CD4013B application
includes specific load currents. Load currents must be limited so as to not exceed the total power (continuous
current through VCC or GND) for the device. These limits are located in Absolute Maximum Ratings. Outputs
must not be pulled above VCC.
VCC
Unused Input
Input
Output Output
Input
Unused Input
Supply Voltage (V)
Propagation Delay Time (ns)
0 5 10 15 20 25
0
20
40
60
80
100
120
140
D037
CL = 15 pF
CL = 50 pF
12
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Typical Application (continued)
8.2.3 Application Curve
Figure 10. Typical Transition Time vs Load Capacitance
9 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating located in
Recommended Operating Conditions. Each VCC pin must have a good bypass capacitor to prevent power
disturbance. For devices with a single supply, TI recommends a 0.1-μF capacitor. If there are multiple VCC pins,
then TI recommends a 0.01-μF or 0.022-μF capacitor for each power pin. It is acceptable to parallel multiple
bypass capacitors to reject different frequencies of noise. 0.1-μF and 1-μF capacitors are commonly used in
parallel. The bypass capacitor must be installed as close to the power pin as possible for best results.
10 Layout
10.1 Layout Guidelines
When using multiple bit logic devices, inputs must never float.
In many cases, digital logic device functions or parts of these functions are unused (for example, when only two
inputs of a triple-input and gate are used, or only 3 of the 4 buffer gates are used). Such input pins must not be
left unconnected because the undefined voltages at the outside connections result in undefined operational
states. This rule must be observed under all circumstances specified in the next paragraph.
All unused inputs of digital logic devices must be connected to a high or low bias to prevent them from floating.
See application note, Implications of Slow or Floating CMOS Inputs (SCBA004), for more information on the
effects of floating inputs. The logic level must apply to any particular unused input depending on the function of
the device. Generally, they are tied to GND or VCC (whichever is convenient).
10.2 Layout Example
Figure 11. Layout Example for CD4013B
13
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Layout Example (continued)
Figure 12. Dimensions and Pad Layout for CD4013B
14
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation see the following:
Implications of Slow or Floating CMOS Inputs (SCBA004)
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.6 Glossary
SLYZ022 —TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
PACKAGE OPTION ADDENDUM
www.ti.com 4-Feb-2021
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
CD4013BE ACTIVE PDIP N 14 25 RoHS & Green NIPDAU N / A for Pkg Type -55 to 125 CD4013BE
CD4013BEE4 ACTIVE PDIP N 14 25 RoHS & Green NIPDAU N / A for Pkg Type -55 to 125 CD4013BE
CD4013BF ACTIVE CDIP J 14 1 Non-RoHS
& Green SNPB N / A for Pkg Type -55 to 125 CD4013BF
CD4013BF3A ACTIVE CDIP J 14 1 Non-RoHS
& Green SNPB N / A for Pkg Type -55 to 125 CD4013BF3A
CD4013BM ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 CD4013BM
CD4013BM96 ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 CD4013BM
CD4013BM96E4 ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 CD4013BM
CD4013BM96G4 ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 CD4013BM
CD4013BME4 ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 CD4013BM
CD4013BMG4 ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 CD4013BM
CD4013BMT ACTIVE SOIC D 14 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 CD4013BM
CD4013BNSR ACTIVE SO NS 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 CD4013B
CD4013BPW ACTIVE TSSOP PW 14 90 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 CM013B
CD4013BPWR ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 CM013B
CD4013BPWRE4 ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 CM013B
CD4013BPWRG4 ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 CM013B
JM38510/05151BCA ACTIVE CDIP J 14 1 Non-RoHS
& Green SNPB N / A for Pkg Type -55 to 125 JM38510/
05151BCA
M38510/05151BCA ACTIVE CDIP J 14 1 Non-RoHS
& Green SNPB N / A for Pkg Type -55 to 125 JM38510/
05151BCA
(1) The marketing status values are defined as follows:
PACKAGE OPTION ADDENDUM
www.ti.com 4-Feb-2021
Addendum-Page 2
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF CD4013B, CD4013B-MIL :
•Catalog: CD4013B
•Military: CD4013B-MIL
NOTE: Qualified Version Definitions:
•Catalog - TI's standard catalog product
PACKAGE OPTION ADDENDUM
www.ti.com 4-Feb-2021
Addendum-Page 3
•Military - QML certified for Military and Defense Applications
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
CD4013BM96 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
CD4013BM96G4 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
CD4013BMT SOIC D 14 250 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
CD4013BNSR SO NS 14 2000 330.0 16.4 8.1 10.4 2.5 12.0 16.0 Q1
CD4013BPWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 17-Dec-2020
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
CD4013BM96 SOIC D 14 2500 853.0 449.0 35.0
CD4013BM96G4 SOIC D 14 2500 853.0 449.0 35.0
CD4013BMT SOIC D 14 250 210.0 185.0 35.0
CD4013BNSR SO NS 14 2000 853.0 449.0 35.0
CD4013BPWR TSSOP PW 14 2000 853.0 449.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 17-Dec-2020
Pack Materials-Page 2
www.ti.com
PACKAGE OUTLINE
C
14X .008-.014
[0.2-0.36]
TYP
-15
0
AT GAGE PLANE
-.314.308 -7.977.83[ ]
14X -.026.014 -0.660.36[ ]
14X -.065.045 -1.651.15[ ]
.2 MAX TYP
[5.08] .13 MIN TYP
[3.3]
TYP-.060.015 -1.520.38[ ]
4X .005 MIN
[0.13]
12X .100
[2.54]
.015 GAGE PLANE
[0.38]
A
-.785.754 -19.9419.15[ ]
B -.283.245 -7.196.22[ ]
CDIP - 5.08 mm max heightJ0014A
CERAMIC DUAL IN LINE PACKAGE
4214771/A 05/2017
NOTES:
1. All controlling linear dimensions are in inches. Dimensions in brackets are in millimeters. Any dimension in brackets or parenthesis are for
reference only. Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This package is hermitically sealed with a ceramic lid using glass frit.
4. Index point is provided on cap for terminal identification only and on press ceramic glass frit seal only.
5. Falls within MIL-STD-1835 and GDIP1-T14.
78
14
1
PIN 1 ID
(OPTIONAL)
SCALE 0.900
SEATING PLANE
.010 [0.25] C A B
www.ti.com
EXAMPLE BOARD LAYOUT
ALL AROUND
[0.05] MAX.002
.002 MAX
[0.05]
ALL AROUND
SOLDER MASK
OPENING
METAL
(.063)
[1.6]
(R.002 ) TYP
[0.05]
14X ( .039)
[1]
( .063)
[1.6]
12X (.100 )
[2.54]
(.300 ) TYP
[7.62]
CDIP - 5.08 mm max heightJ0014A
CERAMIC DUAL IN LINE PACKAGE
4214771/A 05/2017
LAND PATTERN EXAMPLE
NON-SOLDER MASK DEFINED
SCALE: 5X
SEE DETAIL A SEE DETAIL B
SYMM
SYMM
1
78
14
DETAIL A
SCALE: 15X
SOLDER MASK
OPENING
METAL
DETAIL B
13X, SCALE: 15X
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