1. General description
The 74HC259; 74HCT259 is an 8-bit addressable latch. The device features four modes
of operation. In the addressable latch mode, data on the D inpu t is written into the latch
addressed by the inputs AO to A3. The addressed latch will follow the data input,
non-addressed latches will retain their previous states. In memory mode, all latches retain
their previous states and are unaffected by the data or addre ss inputs. In the 3-to-8
decoding or demultiplexing mode, the addressed output follows the D input and all other
outputs are LOW. In the reset mode, all outputs are forced LOW and unaffected by the
data or address inputs. Inputs include clamp diodes. This enables the use of curren t
limiting resistors to interface inputs to voltages in excess of VCC.
2. Features and benefits
Combined demultiplexer and 8-bit latch
Serial-to-parallel capability
Output from each storage bit available
Random (addressable) data entry
Easily expandable
Common reset input
Useful as a 3-to-8 active HIGH decoder
Complies with JEDEC standard no. 7A
Input levels:
For 74HC259: CMOS level
For 74HCT259: TTL level
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A ex ce eds 20 0 V
CDM JESD22E exceeds 1000 V
Multiple package options
Specified from 40 C to +85 C and from 40 C to +125 C
74HC259; 74HCT259
8-bit addressable latch
Rev. 6 — 2 February 2016 Product data sheet
© Nexperia B.V. 2017. All rights reserved
74HC_HCT259 All information provided in this document is subject to legal disclaimers. .
Product data sheet Rev. 6 — 2 February 2016 2 of 21
Nexperia 74HC259; 74HCT259
8-bit addressable latch
3. Ordering information
4. Functional diagram
Table 1. Ordering information
Type number Package
Temperatu re range Name Description Version
74HC259D 40 C to +125 C SO16 plastic small outline package; 16 leads;
body widt h 3.9 mm SOT109-1
74HCT259D
74HC259DB 40 C to +125 C SSOP16 plastic shrink small outline package; 16 leads; body
width 5.3 mm SOT338-1
74HCT259DB
74HC259PW 40 C to +125 C TSSOP16 plastic thin shrink small outline package; 16 leads;
body wid t h 4.4 mm SOT403-1
74HCT259PW
74HC259BQ 40 C to +125 C DHVQFN16 plastic dual in-line compatible thermal enhanced very
thin quad flat package; no leads; 16 terminals;
body 2.5 3.5 0.85 mm
SOT763-1
74HCT259BQ
Fig 1. Logic symbol Fig 2. IEC logic symbol
PQD
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© Nexperia B.V. 2017. All rights reserved
74HC_HCT259 All information provided in this document is subject to legal disclaimers. .
Product data sheet Rev. 6 — 2 February 2016 3 of 21
Nexperia 74HC259; 74HCT259
8-bit addressable latch
5. Pinning information
5.1 Pinning
Fig 3. Functional diag ram
PQD
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(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to GND.
Fig 4. Pin configuration SO16, SSOP16 and
TSSOP16 Fig 5. Pin configuration DHVQFN16
+&
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© Nexperia B.V. 2017. All rights reserved
74HC_HCT259 All information provided in this document is subject to legal disclaimers. .
Product data sheet Rev. 6 — 2 February 2016 4 of 21
Nexperia 74HC259; 74HCT259
8-bit addressable latch
5.2 Pin description
6. Functional description
[1] H = HIGH voltage level;
L = LOW voltage level;
X = don’t care;
d = HIGH or LOW data one set-up time prior to the LOW-to-HIGH LE transition;
q = lower case letter indicates the state of the referenced input one set-up time prior to the LOW-to-HIGH transition.
Table 2. Pin description
Symbol Pin Description
A0, A1, A2 1, 2, 3 address input
Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7 4, 5, 6, 7, 9, 10, 11, 12 latch output
GND 8 ground (0 V)
D 13 data input
LE 14 latch enable input (active LOW)
MR 15 conditional reset input (active LOW)
VCC 16 supply voltage
Table 3. Function table[1]
Operating mode Input Output
MR LE DA0 A1 A2 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
Reset (clear) LHXXXXLLLLLLLL
Demultiplexer
(active HIGH 8-channel)
decoder (when D = H)
LLdLLLQ=dLLLLLLL
LLdHLLLQ=dLLLLLL
LLdLHLLLQ=dLLLLL
LLdHHLLLLQ=dLLLL
LLdLLHLLLLQ=dLLL
LLdHLHLLLLLQ=dLL
LLdLHHLLLLLLQ=dL
LLdHHHLLLLLLLQ=d
Memory (no action) H H X X X X q0q1q2q3q4q5q6q7
Addressable latch H L d L L L Q = d q1q2q3q4q5q6q7
HLdHLLq
0Q=d q
2q3q4q5q6q7
HLdLHLq
0q1Q=d q
3q4q5q6q7
HLdHHLq
0q1q2Q=d q
4q5q6q7
HLdLLHq
0q1q2q3Q=d q
5q6q7
HLdHLHq
0q1q2q3q4Q=d q
6q7
HLdLHHq
0q1q2q3q4q5Q=d q
7
HLdHHHq
0q1q2q3q4q5q6Q=d
© Nexperia B.V. 2017. All rights reserved
74HC_HCT259 All information provided in this document is subject to legal disclaimers. .
Product data sheet Rev. 6 — 2 February 2016 5 of 21
Nexperia 74HC259; 74HCT259
8-bit addressable latch
[1] H = HIGH voltage level; L = LOW voltage level.
7. Limiting values
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] Ptot derates linearly with 8 mW/K above 70 C.
[3] Ptot derates linearly with 5.5 mW/K above 60 C.
[4] Ptot derates linearly with 4.5 mW/K above 60 C.
Table 4. Operating mode select table[1]
LE MR Mode
L H Addressable latch mode
H H Memory mode
L L Demultiplexer mode
HLReset mode
Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
VCC supply voltage 0.5 +7.0 V
IIK input clamping current VI < 0.5 V or VI>V
CC +0.5 V [1] -20 mA
IOK output clamping current VO < 0.5 V or VO > VCC + 0.5 V [1] -20 mA
IOoutput current VO = 0.5 V to VCC +0.5V - 25 mA
ICC supply current - +70 mA
IGND ground current 70 - mA
Tstg storage temperature 65 +150 C
Ptot total power dissipation Tamb = 40 C to +125 C
SO16 package [2] - 500 mW
(T)SSOP16 package [3] - 500 mW
DHVQFN16 package [4] - 500 mW
© Nexperia B.V. 2017. All rights reserved
74HC_HCT259 All information provided in this document is subject to legal disclaimers. .
Product data sheet Rev. 6 — 2 February 2016 6 of 21
Nexperia 74HC259; 74HCT259
8-bit addressable latch
8. Recommended operating conditions
9. Static characteristics
Table 6. Recommended operating con ditions
Voltages are referenced to GND (ground = 0 V)
Symbol Parameter Conditions 74HC259 74HCT259 Unit
Min Typ Max Min Typ Max
VCC supply voltage 2.0 5.0 6.0 4.5 5.0 5.5 V
VIinput voltage 0 - VCC 0-V
CC V
VOoutput voltage 0 - VCC 0-V
CC V
Tamb ambient temperature 40 - +125 40 - +125 C
t/V input transition rise and fall rate VCC = 2.0 V - - 625 - - - ns/V
VCC = 4.5 V - 1.67 139 - 1.67 139 ns/V
VCC = 6.0 V - - 83 - - - ns/V
Table 7. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 25 C40 C to +85 C40 C to +125 CUnit
Min Typ Max Min Max Min Max
74HC259
VIH HIGH-level
input voltage VCC = 2.0 V 1.5 1.2 - 1.5 - 1.5 - V
VCC = 4.5 V 3.15 2.4 - 3.15 - 3.15 - V
VCC = 6.0 V 4.2 3.2 - 4.2 - 4.2 - V
VIL LOW-level
input voltage VCC = 2.0 V - 0.8 0.5 - 0.5 - 0.5 V
VCC = 4.5 V - 2.1 1.35 - 1.35 - 1 .3 5 V
VCC = 6.0 V - 2.8 1.8 - 1.8 - 1.8 V
VOH HIGH-level
output voltage VI = VIH or VIL
IO = 20 A; VCC = 2.0 V 1.9 2.0 - 1.9 - 1.9 - V
IO = 20 A; VCC = 4.5 V 4.4 4.5 - 4.4 - 4.4 - V
IO = 20 A; VCC = 6.0 V 5.9 6.0 - 5.9 - 5.9 - V
IO = 4.0 mA; VCC = 4.5 V 3.98 4.32 - 3.84 - 3.7 - V
IO = 5.2 mA; VCC = 6.0 V 5.48 5.81 - 5.34 - 5.2 - V
VOL LOW-level
output voltage VI = VIH or VIL
IO = 20 A; VCC = 2.0 V - 0 0.1 - 0.1 - 0.1 V
IO = 20 A; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V
IO = 20 A; VCC = 6.0 V - 0 0.1 - 0.1 - 0.1 V
IO = 4.0 mA; VCC = 4.5 V - 0.15 0.26 - 0.33 - 0.4 V
IO = 5.2 mA; VCC = 6.0 V - 0.16 0.26 - 0.33 - 0.4 V
IIinput leakage
current VI = VCC or GND;
VCC =6.0V --0.1 - 1-1A
ICC supply current VI = VCC or GND; IO=0A;
VCC =6.0V - - 8.0 - 80 - 160 A
© Nexperia B.V. 2017. All rights reserved
74HC_HCT259 All information provided in this document is subject to legal disclaimers. .
Product data sheet Rev. 6 — 2 February 2016 7 of 21
Nexperia 74HC259; 74HCT259
8-bit addressable latch
CIinput
capacitance -3.5- - - - -pF
74HCT259
VIH HIGH-level
input voltage VCC = 4.5 V to 5.5 V 2.0 1.6 - 2 .0 - 2.0 - V
VIL LOW-level
input voltage VCC = 4.5 V to 5.5 V - 1.2 0.8 - 0.8 - 0.8 V
VOH HIGH-level
output voltage VI = VIH or VIL; VCC = 4.5 V
IO = 20 A 4.4 4.5 - 4.4 - 4.4 - V
IO = 4.0 mA 3.98 4.32 - 3.84 - 3.7 - V
VOL LOW-level
output voltage VI = VIH or VIL; VCC = 4.5 V
IO = 20 A; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V
IO = 5.2 mA; VCC = 6.0 V - 0.15 0.26 - 0.33 - 0.4 V
IIinput leakage
current VI = VCC or GND;
VCC =5.5V --0.1 - 1-1A
ICC supply current VI = VCC or GND; IO=0A;
VCC =5.5V - - 8.0 - 80 - 160 A
ICC additional
supply current VI=V
CC 2.1 V; IO=0A;
other inputs at VCC or GND;
VCC = 4.5 V to 5.5 V
pin An, LE - 150 540 - 675 - 735 A
pin D - 120 432 - 540 - 588 A
pin MR - 75 270 - 338 - 368 A
CIinput
capacitance -3.5- - - - -pF
Table 7. Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 25 C40 C to +85 C40 C to +125 CUnit
Min Typ Max Min Max Min Max
© Nexperia B.V. 2017. All rights reserved
74HC_HCT259 All information provided in this document is subject to legal disclaimers. .
Product data sheet Rev. 6 — 2 February 2016 8 of 21
Nexperia 74HC259; 74HCT259
8-bit addressable latch
10. Dynamic characteristics
Table 8. Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 12.
Symbol Parameter Conditions 25 C40 C to +85 C40 C to +125 CUnit
Min Typ[1] Max Min Max Min Max
74HC259
tpd propagation
delay D to Qn; see Figure 6 [2]
VCC = 2.0 V - 58 185 - 230 - 280 ns
VCC = 4.5 V - 21 37 - 46 - 56 ns
VCC = 5.0 V; CL=15pF - 18 - - - - - ns
VCC = 6.0 V - 17 31 - 39 - 48 ns
An to Qn; see Figure 7 [2]
VCC = 2.0 V - 58 185 - 230 - 280 ns
VCC = 4.5 V - 21 37 - 46 - 56 ns
VCC = 5.0 V; CL=15pF - 17 - - - - - ns
VCC = 6.0 V - 17 31 - 39 - 48 ns
LE to Qn; see Figure 8 [2]
VCC = 2.0 V - 55 170 - 215 - 255 ns
VCC = 4.5 V - 20 34 - 43 - 51 ns
VCC = 5.0 V; CL=15pF - 17 - - - - - ns
VCC = 6.0 V - 16 29 - 37 - 43 ns
tPHL HIGH to LOW
propagation
delay
MR to Qn; see Figure 9
VCC = 2.0 V - 50 155 - 195 - 235 ns
VCC = 4.5 V - 18 31 - 39 - 47 ns
VCC = 5.0 V; CL=15pF - 15 - - - - - ns
VCC = 6.0 V - 14 26 - 33 - 40 ns
tttransition time see Figure 8 [3]
VCC = 2.0 V - 19 75 - 95 - 119 ns
VCC = 4.5 V - 7 15 - 19 - 22 ns
VCC = 6.0 V - 6 13 - 16 - 19 ns
tWpulse width LE HIGH or LOW;
see Figure 8
VCC = 2.0 V 70 17 - 90 - 105 - ns
VCC = 4.5 V 14 6 - 18 - 21 - ns
VCC = 6.0 V 12 5 - 15 - 18 - ns
MR LOW; see Figure 9
VCC = 2.0 V 70 17 - 90 - 105 - ns
VCC = 4.5 V 14 6 - 18 - 21 - ns
VCC = 6.0 V 12 5 - 15 - 18 - ns
© Nexperia B.V. 2017. All rights reserved
74HC_HCT259 All information provided in this document is subject to legal disclaimers. .
Product data sheet Rev. 6 — 2 February 2016 9 of 21
Nexperia 74HC259; 74HCT259
8-bit addressable latch
tsu set-up time D, An to LE;
see Figure 10 and
Figure 11
VCC = 2.0 V 80 19 - 100 - 120 - ns
VCC = 4.5 V 16 7 - 20 - 24 - ns
VCC = 6.0 V 14 6 - 17 - 20 - ns
thhold time D to LE; see Figure 10
and Figure 11
VCC = 2.0 V 0 19 - 0 - 0 - ns
VCC = 4.5 V 0 6- 0 - 0 -ns
VCC = 6.0 V 0 5- 0 - 0 -ns
An to LE; see Figure 10
and Figure 11
VCC = 2.0 V 2 11 - 2 - 2 - ns
VCC = 4.5 V 2 4- 2 - 2 -ns
VCC = 6.0 V 2 3- 2 - 2 -ns
CPD power
dissipation
capacitance
fi= 1 MHz;
VI=GNDtoV
CC
[4] -19- - - - -pF
74HCT259
tpd propagation
delay D to Qn; see Figure 6 [2]
VCC = 4.5 V - 23 39 - 49 - 59 ns
VCC = 5.0 V; CL=15pF - 20 - - - - - ns
An to Qn; see Figure 7 [2]
VCC = 4.5 V - 25 41 51 62 ns
VCC = 5.0 V; CL=15pF - 20 - - - - - ns
LE to Qn; see Figure 8 [2]
VCC = 4.5 V - 22 38 - 48 - 57 ns
VCC = 5.0 V; CL=15pF - 20 - - - - - ns
tPHL HIGH to LOW
propagation
delay
MR to Qn; see Figure 9
VCC = 4.5 V - 23 39 - 49 - 59 ns
VCC = 5.0 V; CL=15pF - 20 - - - - - ns
tttransition time see Figure 8 [3]
VCC = 4.5 V - 7 15 - 19 - 22 ns
tWpulse width LE HIGH or LOW;
see Figure 8
VCC = 4.5 V 19 11 - 24 - 29 - ns
MR LOW; see Figure 9
VCC = 4.5 V 18 10 - 23 - 27 - ns
Table 8. Dynamic characteristics …continu ed
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 12.
Symbol Parameter Conditions 25 C40 C to +85 C40 C to +125 CUnit
Min Typ[1] Max Min Max Min Max
© Nexperia B.V. 2017. All rights reserved
74HC_HCT259 All information provided in this document is subject to legal disclaimers. .
Product data sheet Rev. 6 — 2 February 2016 10 of 21
Nexperia 74HC259; 74HCT259
8-bit addressable latch
[1] Typical values are measured at nominal supply voltage (VCC = 3.3 V and VCC =5.0V).
[2] tpd is the same as tPLH and tPHL.
[3] tt is the same as tTHL and tTLH.
[4] CPD is used to determine the dynamic power dissipation (PD in W).
PD=C
PD VCC2fiN+(CLVCC2fo) where:
fi= input frequency in MHz;
fo= output frequency in MHz;
CL= output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
(CLVCC2fo) = sum of the outputs.
11. Waveforms
tsu set-up time D, An to LE;
see Figure 10 and
Figure 11
VCC = 4.5 V 17 10 - 21 - 26 - ns
thhold time D to LE; see Figure 10
and Figure 11
VCC = 4.5 V 0 8- 0 - 0 -ns
An to LE; see Figure 10
and Figure 11
VCC = 4.5 V 0 4- 0 - 0 -ns
CPD power
dissipation
capacitance
fi= 1 MHz;
VI=GNDtoV
CC 1.5 V [4] -19- - - - -pF
Table 8. Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 12.
Symbol Parameter Conditions 25 C40 C to +85 C40 C to +125 CUnit
Min Typ[1] Max Min Max Min Max
Measurement points are given in Table 9.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 6. Data input to output propagation delays
DDK
'LQSXW
4QRXWSXW
W3+/ W3/+
*1'
9&&
90
90
92+
92/
© Nexperia B.V. 2017. All rights reserved
74HC_HCT259 All information provided in this document is subject to legal disclaimers. .
Product data sheet Rev. 6 — 2 February 2016 11 of 21
Nexperia 74HC259; 74HCT259
8-bit addressable latch
Measurement points are given in Table 9.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 7. Address input to output propagation delays
DDK
$QLQSXW
4QRXWSXW
W3+/ W3/+
*1'
9&&
90
90
92+
92/
Measurement points are given in Table 9.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 8. Enable input to output propa ga tio n delays and pulse wid th
W3+/
9&&
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/(LQSXW
4QRXWSXW
W7+/ W7/+
W:
90
9<
90
9;
W3/+
9&&
*1'
92+
92/
DDM
Measurement points are given in Table 9.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 9. Master reset input to output propagation delays
DDK
05LQSXW
4QRXWSXW
W3+/
W:
90
92+
9&&
*1'
92/
90
© Nexperia B.V. 2017. All rights reserved
74HC_HCT259 All information provided in this document is subject to legal disclaimers. .
Product data sheet Rev. 6 — 2 February 2016 12 of 21
Nexperia 74HC259; 74HCT259
8-bit addressable latch
Measurement points are given in Table 9.
The shaded areas indicate when the input is permitted to change for predictable output performance.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 10. Data input to latch en a ble input set-up and hold times
DDK
*1'
*1'
WK
WVX
WK
WVX
90
90
90
9&&
92+
92/
9&&
4QRXWSXW 4 ' 4 '
/(LQSXW
'LQSXW
Measurement points are given in Table 9.
The shaded areas indicate when the input is permitted to change for predictable output performance.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 11. Address input to latch enable input set-up and hold times
DDK
9
0
$''5(6667$%/(
9
0
W
K
W
VX
9
&&
*1'
9
&&
*1'
/(LQSXW
$QLQSXW
Table 9. Measurement points
Type Input Output
VMVMVXVY
74HC259 0.5VCC 0.5VCC 0.1VCC 0.9VCC
74HCT259 1.3 V 1.3 V 0.1VCC 0.9VCC
© Nexperia B.V. 2017. All rights reserved
74HC_HCT259 All information provided in this document is subject to legal disclaimers. .
Product data sheet Rev. 6 — 2 February 2016 13 of 21
Nexperia 74HC259; 74HCT259
8-bit addressable latch
Test data is given in Table 10.
Definitions test circuit:
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
CL = Load capacitance including jig and probe capacitance.
RL = Load resistance.
S1 = Test selection switch
Fig 12. Test circuit for measuring switching times
9
0
9
0
W
:
W
:
9
9
,
9
,
QHJDWLYH
SXOVH
SRVLWLYH
SXOVH
9
9
0
9
0
W
I
W
U
W
U
W
I
DDG
'87
9
&&
9
&&
9,92
57
5/6
&/
RSHQ
*
Table 10. Test data
Type Input Load S1 position
VItr, tfCLRLtPHL, tPLH
74HC259 VCC 6ns 15pF, 50 pF 1kopen
74HCT259 3V 6ns 15pF, 50 pF 1kopen
© Nexperia B.V. 2017. All rights reserved
74HC_HCT259 All information provided in this document is subject to legal disclaimers. .
Product data sheet Rev. 6 — 2 February 2016 14 of 21
Nexperia 74HC259; 74HCT259
8-bit addressable latch
12. Package outline
Fig 13. Package outline SOT109-1 (SO16)
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© Nexperia B.V. 2017. All rights reserved
74HC_HCT259 All information provided in this document is subject to legal disclaimers. .
Product data sheet Rev. 6 — 2 February 2016 15 of 21
Nexperia 74HC259; 74HCT259
8-bit addressable latch
Fig 14. Package outline SOT338-1 (SSOP16)
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© Nexperia B.V. 2017. All rights reserved
74HC_HCT259 All information provided in this document is subject to legal disclaimers. .
Product data sheet Rev. 6 — 2 February 2016 16 of 21
Nexperia 74HC259; 74HCT259
8-bit addressable latch
Fig 15. Package outline SOT403-1 (TSSOP16)
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© Nexperia B.V. 2017. All rights reserved
74HC_HCT259 All information provided in this document is subject to legal disclaimers. .
Product data sheet Rev. 6 — 2 February 2016 17 of 21
Nexperia 74HC259; 74HCT259
8-bit addressable latch
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© Nexperia B.V. 2017. All rights reserved
74HC_HCT259 All information provided in this document is subject to legal disclaimers. .
Product data sheet Rev. 6 — 2 February 2016 18 of 21
Nexperia 74HC259; 74HCT259
8-bit addressable latch
13. Abbreviations
14. Revision history
Table 11. Abbreviations
Acronym Description
CDM Charged Device Model
CMOS Complementary Metal-Oxide Semiconductor
DUT Device Under Test
ESD ElectroStatic Discharge
HBM Human Body Model
MM Machine Model
TTL Transistor-Transistor Logic
Table 12. Revision history
Document ID Release date Data sheet status Change notice Supersedes
74HC_HCT259 v.6 20160202 Product data sheet - 74HC_HCT259 v. 5
Modifications: •Type numbers 74HC259N and 74HCT259N (SOT38-4) removed.
74HC_HCT259 v.5 20120807 Product data sheet - 74HC_HCT259 v. 4
Modifications: •The format of this data sheet has been redesigned to comply with the new identity guidelines
of NXP.
•Legal texts have been adapted to the new company name where appropriate.
74HC_HCT259 v.4 20090225 Product data sheet - 74HC_HCT259 v. 3
Modifications: •Added type number 74HC259N and 74HCT259N (DIP16 package)
•Added type number 74HC259DB and 74HCT259DB (SSOP16 package)
74HC_HCT259 v.3 20090108 Product data sheet - 74HC_HCT259_CNV v.2
74HC_HCT259_CNV v.2 19970828 Product specification - -
© Nexperia B.V. 2017. All rights reserved
74HC_HCT259 All information provided in this document is subject to legal disclaimers. .
Product data sheet Rev. 6 — 2 February 2016 19 of 21
Nexperia 74HC259; 74HCT259
8-bit addressable latch
15. Legal information
15.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of device (s) descr ibed in th is document m ay have cha nged since thi s document w as publish ed and may di ffe r in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nexperia.com.
15.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. Nexperia does not give any
representations or warrant ies as to t he accuracy or completeness of
information included herein and shall have no liab ility for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and tit le. A short data sh eet is intended
for quick reference only and shou ld not b e relied u pon to cont ain det ailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local Nexperia sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall pre va il.
Product specificat io n — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
Nexperia and its customer, unless Nexperia and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the Nexperia product is
deemed to off er functions and qualities beyond those described in the
Product data sheet.
15.3 Disclaimers
Limited warr a nty and liability — Information in this document is believed to
be accurate and reliable. However, Nexperia does not give any
representations or warrant ies, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. Nexperia takes no
responsibility for the content in this document if provided by an information
source outside of Nexperia.
In no event shall Nexperia be liable for any indirect, incidental,
punitive, special or consequ ential damages (including - wit hout limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, Nexperia's aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of Nexperia.
Right to make changes — Nexperia reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all informa tion supplied prior
to the publication hereof .
Suitability for use — Nexperia products are not designed,
authorized or warranted to be suitable for use in life support , life-critical or
safety-critical systems or equipme nt, nor in applications where failure or
malfunction of a Nexperia product can reasonably be expected
to result in perso nal injury, death or severe property or environme ntal
damage. Nexperia and its suppliers accept no liability for
inclusion and/or use of Nexperia products in such equipment or
applications and ther efore such inclu sion and/or use is at the cu stomer’s own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. Nexperia makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and ope ration of their applications
and products using Nexperia products, and Nexperia
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the Nexperia
product is suitable and fit for the customer’s applications and
products planned, as well as fo r the planned application and use of
customer’s third party customer(s). Custo mers should provide appropriate
design and operating safeguards to minimize the risks associate d with t heir
applications and products.
Nexperia does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party custo mer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using Nexperia
products in order to avoid a default of the applications and
the products or of the application or use by cust omer’s third party
customer(s). Nexperia does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress rating s only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — Nexperia
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nexperia.com/profile/terms, unless otherwise
agreed in a valid written individua l agreement. In case an individual
agreement is concluded only the ter m s and conditions of the respective
agreement shall apply. Nexperia hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of Nexperia products by customer.
No offer to sell or license — Nothing i n this document may be interpreted or
construed as an of fer t o sell product s that is open for accept ance or the gr ant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specification.
Product [short] data sheet Production This document contains the product specification.
© Nexperia B.V. 2017. All rights reserved
74HC_HCT259 All information provided in this document is subject to legal disclaimers. .
Product data sheet Rev. 6 — 2 February 2016 20 of 21
Nexperia 74HC259; 74HCT259
8-bit addressable latch
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific Nexperia product is automotive qualified,
the product is not suitable for aut omo tive use. It i s neither qua lif ied nor test ed
in accordance with automotive testing or application requirements. Nexperia
accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automot ive specifications and standards, custome r
(a) shall use the product without Nexperia's warranty of the
product for such au tomotive applications, use and specifi ca tions, and (b)
whenever customer uses the product for automotive applications beyond
Nexperia's specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies Nexperia for any
liability, damages or failed product claims resulting f rom customer design an d
use of the product for automotive applications beyond Nexperia's
standard warranty and Nexperia's product specifications.
Translations — A non-English (translated) versio n of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
15.4 Trademarks
Notice: All referenced b rands, produc t names, service names and trademarks
are the property of their respective ow ners.
16. Contact information
For more information, please visit: http://www.nexperia.com
For sales office addresses, please send an email to: salesaddresses@nexperia.com
Nexperia 74HC259; 74HCT259
8-bit addressable latch
17. Contents
1 General description. . . . . . . . . . . . . . . . . . . . . . 1
2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1
3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2
4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
5 Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
6 Functional description . . . . . . . . . . . . . . . . . . . 4
7 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5
8 Recommended operating conditions. . . . . . . . 6
9 Static characteristics. . . . . . . . . . . . . . . . . . . . . 6
10 Dynamic characteristics . . . . . . . . . . . . . . . . . . 8
11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 14
13 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 18
14 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 18
15 Legal information. . . . . . . . . . . . . . . . . . . . . . . 19
15.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 19
15.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
15.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 19
15.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 20
16 Contact information. . . . . . . . . . . . . . . . . . . . . 20
17 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
© Nexperia B.V. 2017. All rights reserved
For more information, please visit: http://www.nexperia.com
For sales office addresses, please send an email to: salesaddresses@nexperia.com
Date of release:
02 February 2016
