General Description
The MAXQ7670 is a highly integrated solution for mea-
suring multiple analog signals and outputting the results
on a control area network (CAN) bus. The device oper-
ates from a single 5V supply and incorporates a high-
performance, 16-bit reduced instruction set computing
(RISC) core, a SAR ADC, and a CAN 2.0B controller,
supporting transfer rates up to 1Mbps. The 10-bit SAR
ADC includes an amplifier with programmable gains of
1V/V or 16V/V, 8 input channels, and conversion rates up
to 250ksps. The eight single-ended ADC inputs can be
configured as four unipolar or bipolar, fully differential
inputs. For single-supply operation, the external 5V sup-
ply powers the digital I/Os and two separate integrated
linear regulators that supply the 2.5V digital core and the
3.3V analog circuitry. Each supply rail has a dedicated
power-supply supervisor that provides brownout detec-
tion and power-on reset (POR) functions. The 16-bit RISC
microcontroller (µC) includes 64KB (32K x 16) of non-
volatile program/data flash and 2KB (1K x 16) of data
RAM. Other features of the MAXQ7670 include a 4-wire
SPI™ interface, a JTAG interface for in-system program-
ming and debugging, an integrated 15MHz RC oscilla-
tor, external crystal oscillator support, a timer/counter
with pulse-width modulation (PWM) capability, and seven
GPIO pins with interrupt and wake-up capability.
The system-on-a-chip (SoC) MAXQ7670 is a µC-based,
smart data acquisition system. As a member of the
MAXQ®family of 16-bit, RISC µCs, the MAXQ7670 is
ideal for low-cost, low-power, embedded-applications
such as automotive, industrial controls, and building
automation. The flexible, modular architecture used in
the MAXQ µCs allows development of targeted prod-
ucts for specific applications with minimal effort.
The MAXQ7670 is available in a 40-pin, 5mm x 5mm
TQFN package, and is specified to operate over the -40°C
to +125°C automotive temperature range.
Applications
Automotive Steering Angle and Torque Sensors
CAN-Based Automotive Sensor Applications
Industrial Control
Building Automation
Features
oHigh-Performance, Low-Power, 16-Bit RISC Core
0.166MHz to 16MHz Operation, Approaching
1MIPs/MHz
Low Power (< 1mA/MIPS, VDVDD = +2.5V)
16-Bit Instruction Word, 16-Bit Data Bus
33 Instructions, Most Require Only One Clock
Cycle
16-Level Hardware Stack
16 x 16-Bit, General-Purpose Working Registers
Three Independent Data Pointers with Auto-
Increment/Decrement
Low-Power, Divide-by-256, Power-Management
Modes (PMM) and Stop Mode
oProgram and Data Memory
64KB Internal Nonvolatile Program/Data Flash
2KB Internal Data RAM
oSAR ADC
8 Single-Ended/4 Differential Channels,
10-Bit Resolution with No Missing Codes
PGA Gain = 1V/V or 16V/V
250ksps (150.9ksps with PGA Gain = 16V/V)
oTimer/Digital I/O Peripherals
CAN 2.0B Controller (15 Message Centers)
Serial Peripheral Interface (SPI)
JTAG Interface (Extensive Debug and Emulation
Support)
Single 16-Bit/Dual 8-Bit Timer/PWM
Seven General-Purpose, Digital I/O Pins with
External Interrupt/Wake-Up Features
oOscillator/Clock Module
Internal Oscillator Supports External Crystal
(8MHz or 16MHz)
Integrated 15MHz RC Oscillator
External Clock Source Operation
Programmable Watchdog Timer
oPower-Management Module
Power-On Reset
Power-Supply Supervisor/Brownout Detection
Integrated +2.5V and +3.3V Linear Regulators
MAXQ7670
Microcontroller with 10-Bit ADC,
PGA, 64KB Flash, and CAN Interface
________________________________________________________________
Maxim Integrated Products
1
19-4384; Rev 1; 7/09
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
Typical Application Circuit and Pin Configuration appear at
end of data sheet.
SPI is a trademark of Motorola, Inc.
MAXQ is a registered trademark of Maxim Integrated Products, Inc.
Ordering Information
PART TEMP RANGE PIN-PACKAGE
MAXQ7670ATL/V+
-40°C to +125°C
40 TQFN-EP*
/V denotes an automotive qualified part.
+
Denotes a lead-free/RoHS-compliant package.
*
EP = Exposed pad.
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of
any device may be simultaneously available through various sales channels. For information about device errata, go to:
http://www.maxim-ic.com/errata.
MAXQ7670
Microcontroller with 10-Bit ADC,
PGA, 64KB Flash, and CAN Interface
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(VDVDDIO = +5.0V, VAVDD = +3.3V, VDVDD = +2.5V, VREFADC = +3.3V, system clock = 16MHz. TA= TMIN to TMAX, unless otherwise
noted. Typical values are at TA= +25°C.) (Note 1)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
DVDD to DGND ........................................................-0.3V to +3V
DVDDIO to GNDIO ................................................-0.3V to +5.5V
AVDD to AGND ........................................................-0.3V to +4V
DGND to GNDIO. ..................................................-0.3V to +0.3V
GNDIO to AGND. ..................................................-0.3V to +0.3V
AGND to DGND.....................................................-0.3V to +0.3V
Analog Inputs to AGND..........................-0.3V to (VAVDD + 0.3V)
RESET, Digital Inputs/Outputs to
GNDIO ............................................-0.3V to (VDVDDIO + 0.3V)
XIN, XOUT to DGND ..............................-0.3V to (VDVDD + 0.3V)
Continuous Power Dissipation (TA= +70°C)
40-Pin TQFN (derate 36mW/°C above +70°C) ..........2857mW
Continuous Current into Any Pin.......................................±50mA
Operating Temperature Range .........................-40°C to +125°C
Junction Temperature......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) ................................+300°C
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
POWER REQUIREMENTS
DVDD REGEN2 = DVDDIO, DVDD ≤ AVDD,
DVDD ≤ DVDDIO 2.25 2.5 2.75
AVDD LRAPD = 1, AVDD ≤ DVDDIO 3.0 3.3 3.6
Supply Voltage Ranges
DVDDIO 4.5 5.0 5.25
V
Shutdown (Note 2) 3 10 µA
AVDD Supply Current IAVDD All analog functions enabled 6 7 mA
ADC, 50ksps, 4MHz ADCCLK 5200
ADC, 250ksps, 4MHz ADCCLK 5600
AVDD brownout interrupt monitor 3
Analog Module Incremental
Subfunction Supply Current ∆IAVDD
PGA enabled 5500
µA
CPU in stop mode, all peripherals
disabled 25 200 µA
High speed/2MHz mode (Note 3) 2.0 2.5
High speed/16MHz mode (Note 4) 11.3
Low speed/625kHz mode (Note 5) 0.95
DVDD Supply Current IDVDD
Program flash erase or write 14 23
mA
DVDDIO brownout reset monitor 1
HF crystal oscillator 60
Digital Peripheral Incremental
Subfunction Supply Current ∆IDVDD
Internal fixed-frequency oscillator 50
µA
All digital I/Os static at GNDIO or
DVDDIO 220µA
DVDDIO Supply Current IDVDDIO CAN transmitting, timer output
switching (Note 6) 0.2 0.3 mA
MAXQ7670
Microcontroller with 10-Bit ADC,
PGA, 64KB Flash, and CAN Interface
_______________________________________________________________________________________ 3
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
MEMORY SECTION
Flash Memory Size Program or data storage 64 KB
Flash Page Size 16-bit word size 256 Words
Flash Erase/Write Endurance Program or data (Note 7) 10,000 Cycles
All flash, TA = +25°C 100
Flash Data Retention (Note 7) All flash, TA = +85°C 15 Years
Flash page erase 20 50
Flash Erase Time Entire flash mass erase 200 500 ms
Flash single word programming 20 40 µs
Flash Programming Time Entire flash programming 0.66 1.31 s
RAM Memory Size 2KB
Utility ROM Size 16-bit word size 4 KWords
ANALOG SENSE PATH (Includes PGA and ADC)
Resolution NADC No missing codes 10 Bits
PGA gain = 16V/V, bipolar mode,
VIN = ±100mV, 150.9ksps ±0.5 ±1
Integral Nonlinearity INLADC PGA gain = 1V/V, unipolar mode,
VIN = +1.0V, 250ksps ±0.4 ±1
LSB10
Differential Nonlinearity DNLADC PGA gain = 1V/V or 16V/V ±0.4 ±1 LSB10
Input-Referred Offset Error Test at TA = +25°C,
PGA gain = 1V/V or 16V/V ±1 ±10 mV
Offset-Error Temperature
Coefficient PGA gain = 16V/V, bipolar mode ±2 µV/°C
Gain Error
PGA gain = 16V/V, bipolar mode,
excludes offset and reference error,
test at TA = +25°C
-2 +2 %
Gain-Error Temperature
Coefficient PGA gain = 16V/V, bipolar mode ±5 ppm/°C
Conversion Clock Frequency fADCCLK fSYSCLK = 8MHz or 16MHz 0.5 4.0 MHz
PGA gain = 16V/V, fADCCLK = 4MHz 150.9
Sample Rate fSAMPLE PGA gain = 1V/V, fADCCLK = 4MHz 250 ksps
PGA gain = 16V/V,
13.5 ADCCLK cycles at 4MHz 3.375
Channel Select, Track-and-
Hold Acquisition Time tACQ PGA gain = 1V/V,
three ADCCLK cycles at 4MHz 0.75
µs
Conversion Time tCONV 13 ADCCLK cycles at 4MHz 3.25 µs
ELECTRICAL CHARACTERISTICS (continued)
(VDVDDIO = +5.0V, VAVDD = +3.3V, VDVDD = +2.5V, VREFADC = +3.3V, system clock = 16MHz. TA= TMIN to TMAX, unless otherwise
noted. Typical values are at TA= +25°C.) (Note 1)
MAXQ7670
Microcontroller with 10-Bit ADC,
PGA, 64KB Flash, and CAN Interface
4 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(VDVDDIO = +5.0V, VAVDD = +3.3V, VDVDD = +2.5V, VREFADC = +3.3V, system clock = 16MHz. TA= TMIN to TMAX, unless otherwise
noted. Typical values are at TA= +25°C.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
PGA gain = 16V/V,
26.5 ADCCLK cycles at 4MHz 6.625
Channel Select Plus
Conversion Time
tACQ +
tCONV PGA gain = 1V/V,
16 ADCCLK cycles at 4MHz 4
µs
Turn-On Time tRECOV 10 µs
Aperture Delay 60 ns
Aperture Jitter 100 psP-P
At AIN0–AIN7, unipolar mode,
PGA gain = 1V/V 0V
REFADC
At AIN0–AIN7, unipolar mode,
PGA gain = 16V/V 0 0.125
At AIN0–AIN7, bipolar mode,
PGA gain = 1V/V
-VREFADC
/2
+VREFADC
/2
Differential Input Voltage
Range
At AIN0–AIN7, bipolar mode,
PGA gain = 16V/V
-VREFADC
/32
+VREFADC
/32
V
Absolute Input Voltage Range At AIN0–AIN7 0 VAVDD V
Input Leakage Current At AIN0–AIN7 ±0.1 µA
At AIN0–AIN7, PGA gain = 16V/V 50
Input-Referred Noise At AIN0–AIN7, PGA gain = 1V/V 400 µVRMS
VIN = 12mVP-P, PGA gain = 16V/V 33
Small-Signal Bandwidth (-3dB) VIN = 200mVP-P, PGA gain = 1V/V 23 MHz
VIN = 150mVP-P, PGA gain =16V/V 33
Large-Signal Bandwidth (-3dB) VIN = 2.5VP-P, PGA gain = 1V/V 19 MHz
Single-ended, any AIN0–AIN7,
PGA gain = 16V/V 16
Input Capacitance (Note 8)
Single-ended, any AIN0–AIN7,
PGA gain = 1V/V 13
pF
Input Common-Mode Rejection
Ratio CMRR AIN0–AIN7,
VCM = differential input range 75 dB
Power-Supply Rejection Ratio PSRR AVDD = 3.0V to 3.6V 90 dB
EXTERNAL REFERENCE INPUTS
REFADC Input Voltage Range 1.0 3.3 VAVDD V
REFADC Leakage Current ADC disabled 1 µA
Input Capacitance (Note 9) 20 pF
+3.3V (AVDD) LINEAR REGULATOR
AVDD Output Voltage LRAPD = 0 3.15 3.3 3.45 V
No-Load Quiescent Current LRAPD = 0, all internal analog
peripherals disabled 10 µA
MAXQ7670
ELECTRICAL CHARACTERISTICS (continued)
(VDVDDIO = +5.0V, VAVDD = +3.3V, VDVDD = +2.5V, VREFADC = +3.3V, system clock = 16MHz. TA= TMIN to TMAX, unless otherwise
noted. Typical values are at TA= +25°C.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Output Current Capability LRAPD = 0 50 mA
Output Short-Circuit Current LRAPD = 0, AVDD shorted to AGND 100 mA
Maximum AVDD Bypass
Capacitor to AGND LRAPD = 0 0.47 µF
+2.5V (DVDD) LINEAR REGULATOR
DVDD Output Voltage REGEN2 = GNDIO 2.38 2.5 2.62 V
No-Load Quiescent Current REGEN2 = GNDIO, all internal digital
peripherals disabled 15 µA
Output Current Capability REGEN2 = GNDIO 50 mA
Output Short-Circuit Current REGEN2 = GNDIO, DVDD shorted to
DGND 100 mA
Maximum DVDD Bypass
Capacitor to DGND REGEN2 = GNDIO 0.47 µF
SUPPLY-VOLTAGE SUPERVISORS AND BROWNOUT DETECTION
DVDD Reset Threshold Asserts RESET if VDVDD is below this
threshold 2.1 2.25 V
DVDD Interrupt Threshold Generates an interrupt if VDVDD falls
below this threshold 2.25 2.38 V
Minimum DVDD Interrupt and
Reset Threshold Difference 0.14 V
AVDD Interrupt Threshold Generates an interrupt if VAVDD falls
below this threshold 3.0 3.15 V
DVDDIO Interrupt Threshold Generates an interrupt if VDVDDIO
falls below this threshold 4.5 4.75 V
DVDD 1 2.75
AVDD 1 3.6
Operational Range
DVDDIO 1 5.25
V
Supervisor Hysteresis ±0.7 %
CAN INTERFACE
CAN Baud Rate fCANCLK = 8MHz 1 Mbps
CANCLK Mean Frequency
Error
8MHz or 16MHz, 50ppm external
crystal 60 ppm
CANCLK Total Frequency Error
8MHz or 16MHz, 50ppm external
crystal; measured over a 12ms
interval; mean plus peak cycle jitter
< 0.5 %
Microcontroller with 10-Bit ADC,
PGA, 64KB Flash, and CAN Interface
_______________________________________________________________________________________ 5
MAXQ7670
Microcontroller with 10-Bit ADC,
PGA, 64KB Flash, and CAN Interface
6 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(VDVDDIO = +5.0V, VAVDD = +3.3V, VDVDD = +2.5V, VREFADC = +3.3V, system clock = 16MHz. TA= TMIN to TMAX, unless otherwise
noted. Typical values are at TA= +25°C.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
HIGH-FREQUENCY CRYSTAL OSCILLATOR
Using external crystal 8 or 16 16
Clock Frequency External input (Note 10) 0.166 16.67 MHz
Stability Excluding crystal drift 25 ppm
Startup Time fSYSCLK cycles 65,535 Cycles
XIN Input Low Voltage Driven with external clock source 0.3 x
VDVDD V
XIN Input High Voltage Driven with external clock source 0.7 x
VDVDD V
INTERNAL FIXED-FREQUENCY OSCILLATOR
Frequency fIFFCLK TA = TMIN to TMAX 13.8 15 16.35 MHz
Tolerance TA = +25°C ±0.4 %
Temperature Drift TA = TMIN to TMAX 5%
Power-Supply Rejection TA = +25°C, DVDD = 2.25V to 2.75V ±1.5 %
RESET (RESET)
RESET Internal Pullup
Resistance Pulled up to DVDDIO 55 kΩ
RESET Output Low Voltage RESET asserted, no external load 0.4 V
RESET Output High Voltage RESET deasserted, no external load 0.9 x
VDVDDIO V
RESET Input Low Voltage Driven with external clock source 0.3 x
VDVDD V
RESET Input High Voltage Driven with external clock source 0.7 x
VDVDDIO V
DIGITAL INPUTS (P0._, CANRXD, MISO, MOSI, SS, SCLK, TCK, TDI, TMS)
Input Low Voltage 0.8 V
Input High Voltage 2.1 V
Input Hysteresis 500 mV
Input Leakage Current VIN = GNDIO or VDVDDIO,
pullup disabled -10 ±0.01 +10 µA
Input Pullup Resistance 55 kΩ
Input Pulldown Resistance 55 kΩ
Input Capacitance 15 pF
DIGITAL OUTPUTS (P0._, CANTXD, MOSI, SCLK, SS, TDO)
Output Low Voltage ISINK = 0.5mA 0.4 V
Output High Voltage ISOURCE = 0.5mA VDVDDIO
- 0.5 V
MAXQ7670
Microcontroller with 10-Bit ADC,
PGA, 64KB Flash, and CAN Interface
_______________________________________________________________________________________ 7
ELECTRICAL CHARACTERISTICS (continued)
(VDVDDIO = +5.0V, VAVDD = +3.3V, VDVDD = +2.5V, VREFADC = +3.3V, system clock = 16MHz. TA= TMIN to TMAX, unless otherwise
noted. Typical values are at TA= +25°C.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Output Capacitance I/O pins three-state 15 pF
PD0._ = 0 880
Maximum Output Impedance PD0._ = 1 450
Ω
SYSTEM CLOCK
System Clock Frequency fSYSCLK From any clock source 0 16.67 MHz
SPI INTERFACE TIMING
SPI Master Operating
Frequency fMCLK 0.5 x fSYSCLK 8 MHz
SPI Slave Mode Operating
Frequency fSCLK fSYSCLK/8 MHz
SCLK Output Pulse-Width
High/Low
tMCH,
tMCL
tSYSCLK
- 25 ns
SCLK Input Pulse-Width
High/Low tSCH, tSCL tSYSCLK ns
MOSI Output Hold Time
After SCLK Sample Edge tMOH tSYSCLK
- 25 ns
MOSI Output Setup Time to
SCLK Sample Edge tMOS tSYSCLK
- 25 ns
MISO Input Setup Time to
SCLK Sample Edge tMIS 30 ns
MISO Input Hold Time After
SCLK Sample Edge tMIH 0ns
SCLK Inactive to MOSI
Inactive tMLH tSYSCLK
- 25 ns
MOSI Input Setup Time to
SCLK Sample Edge tSIS 30 ns
MOSI Input Hold Time After
SCLK Sample Edge tSIH tSYSCLK
+ 25 ns
MISO Output Valid After
SCLK Shift Edge Transition tSOV 3 tSYSCLK
+ 25 ns
MISO Output Disabled After
SS Edge Rise tSLH 2 tSYSCLK
+ 50 ns
SS Falling Edge to MISO Active tSOE 2 tSYSCLK
+ 2.5 ns
MAXQ7670
Microcontroller with 10-Bit ADC,
PGA, 64KB Flash, and CAN Interface
8 _______________________________________________________________________________________
Note 1: All devices are 100% production tested at TA= +25°C and +125°C. Temperature limits to TA= -40°C are guaranteed by
design.
Note 2: All analog functions disabled and all digital inputs connected to supply or ground.
Note 3: High-speed/8 mode without CAN; VDVDD = +2.5V, CPU and 16-bit timer running at 2MHz from an external, 16MHz crystal
oscillator; all other peripherals disabled; all digital I/Os static at VDVDDIO or GNDIO; TA= TMIN to TMAX.
Note 4: High-speed/1 mode with CAN; VDVDD = +2.5V, CPU and 16-bit timer running at 16MHz from an external, 16MHz crystal
oscillator; CAN enabled and communicating at 500kbps; all other peripherals disabled, all digital I/Os (except CANTXD
and CANRXD) static at VDVDDIO or GNDIO, TA= TMIN to TMAX.
Note 5: Low speed, PMM1 mode without CAN; VDVDD = +2.5V, CPU and one timer running from an external, 16MHz crystal oscilla-
tor in PMM1 mode; all other peripherals disabled; all digital I/Os static at VDVDDIO or GNDIO, TA= TMIN to TMAX.
Note 6: CAN transmitting at 500kbps; 16-bit timer output switching at 500kHz; all active I/Os are loaded with a 20pF capacitor; all
remaining digital I/Os are static at VDVDDIO or GNDIO, TA= TMIN to TMAX.
Note 7: Guaranteed by design and characterization.
Note 8: This is not a static capacitance. It is the capacitance presented to the analog input when the T/H amplifier is in sample mode.
Note 9: The switched capacitor on the REFADC input can disturb the reference voltage. To reduce this disturbance, place a 0.1µF
capacitor from REFADC to AGND as close as possible to REFADC.
Note 10: The digital design is fully static. However, the lower clock limit is set by a clock detect circuit. The MAXQ7670 switches to
the internal RC clock if the external input goes below 166kHz. This clock detect circuit also acts to detect a crystal failure
when a crystal is used.
ELECTRICAL CHARACTERISTICS (continued)
(VDVDDIO = +5.0V, VAVDD = +3.3V, VDVDD = +2.5V, VREFADC = +3.3V, system clock = 16MHz. TA= TMIN to TMAX, unless otherwise
noted. Typical values are at TA= +25°C.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
SS Falling Edge to First SCLK
Sample Edge tSSE 2 tSYSCLK
+ 5 ns
SCLK Inactive to SS Rising
Edge tSD tSYSCLK
+ 10 ns
Minimum CS Pulse Width tSCW tSYSCLK
+ 10 ns
MAXQ7670
Microcontroller with 10-Bit ADC,
PGA, 64KB Flash, and CAN Interface
_______________________________________________________________________________________ 9
MISO
MOSI
SCLK
(CKPOL/CKPHA =
0/1 OR 1/0 MODE)
SCLK
(CKPOL/CKPHA =
0/0 OR 1/1 MODE)
SAMPLE EDGE
SHIFT EDGE
tMLH
tMOH
tMOS
tMIH
tMIS
tMCL
tMCH
tMCH tMCLK
tMCL
HIGH IMPEDANCE
Figure 1. SPI Timing Diagram in Master Mode
tSLH
tSOV
tSOE
MISO
MOSI
tSIS
tSCH tSCL
tSCL
tSCW
tSSE tSCH
tSCLK
tSIH
tSD
SAMPLE EDGE
HIGH
IMPEDANCE
HIGH
IMPEDANCE
SHIFT EDGE
SCLK
(CKPOL/CKPHA =
0/1 OR 1/0 MODE)
SS
SCLK
(CKPOL/CKPHA =
0/0 OR 1/1 MODE)
Figure 2. SPI Timing Diagram in Slave Mode
MAXQ7670
Microcontroller with 10-Bit ADC,
PGA, 64KB Flash, and CAN Interface
10 ______________________________________________________________________________________
GPO._ OUTPUT HIGH VOLTAGE
vs. SOURCE CURRENT
IOH (mA)
VOH (V)
MAXQ7670 toc01
0 0.5 1.0 1.5 2.0 2.5
0
1
2
3
4
5
TA = -40°C
TA = -40°C
TA = +85°C
TA = +85°C
TA = +25°CTA = +25°C
PS0._ = 1
TA = +105°CTA = +105°C
PS0._ = 0
GPO._ OUTPUT LOW VOLTAGE
vs. SINK CURRENT
IOL (mA)
VOL (V)
MAXQ7670 toc02
0 0.5 1.0 1.5 2.0 2.5
0
1
2
3
4
5
TA = -40°C
TA = +85°C
TA = +25°C
TA = +105°C
TA = -40°C
TA = +85°C
TA = +25°C
TA = +105°C
PS0._ = 1
PS0._ = 0
ADC INL vs. CODE
(REF ADC = +3.3V, 150.9ksps, PGA GAIN = 16V/V)
DIGITAL OUTPUT CODE
ADC INL (LSB)
MAXQ7670 toc03
-512 -256 0 256 512
-1.5
-0.5
-1.0
0
0.5
1.0
1.5
BIPOLAR MODE
VIN = -100mV TO +100mV
ADC DNL vs. CODE
(REFADC = +3.3V, 150.9ksps,
PGA GAIN = 16V/V)
DIGITAL OUTPUT CODE
ADC DNL (LSB)
MAXQ7670 toc04
-512 -256 0 256 512
-1.0
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1.0
BIPOLAR MODE
VIN = -100mV to +100mV
ADC OFFSET ERROR vs. TEMPERATURE
TEMPERATURE (°C)
OFFSET ERROR (mV)
MAXQ7670 toc05
-40 -25 -10 5 20 35 50 65 80 95 110 125
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
BIPOLAR MODE
PGA GAIN = 16V/V
VIN-DIFF = 0
VIN-CM = +1.65V
ADC GAIN ERROR vs. TEMPERATURE
TEMPERATURE (°C)
GAIN ERROR (%)
MAXQ7670 toc06
-40 -25 -10 5 20 35 50 65 80 95 110 125
-1.0
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1.0
BIPOLAR MODE
PGA GAIN = 16V/V
VIN-DIFF = 200mV
VIN-CM = +1.65V
10ms/div
DVDD, RESET POWER-UP
CHARACTERISTICS
DVDDIO
2V/div
DVDD
1V/div
MAXQ7670 toc07
RESET
2V/div
REGEN2 = GNDIO
20ms/div
DVDD, RESET POWER-DOWN
CHARACTERISTICS
DVDDIO
2V/div
DVDD
1V/div
MAXQ7670 toc08
RESET
2V/div
REGEN2 = GNDIO
MAXIMUM DVDD TRANSIENT DURATION
vs. BOI THRESHOLD OVERDRIVE
DVDD BOI THRESHOLD OVERDRIVE (mV)
MAXIMUM TRANSIENT DURATION (µs)
MAXQ7670 toc09
0
20
40
60
80
100
120
140
160
180
200
1 10 100 1000
BOI ASSERTED ABOVE THIS LINE
Typical Operating Characteristics
(VDVDDIO = 5.0V, VAVDD = 3.3V, VDVDD = 2.5V, fSYSCLK = 16MHz, ADC resolution = 10 bits, VREFDAC = 3.3V, TA = +25°C, unless
otherwise noted.)
MAXQ7670
Microcontroller with 10-Bit ADC,
PGA, 64KB Flash, and CAN Interface
______________________________________________________________________________________
11
MAXIMUM DVDDIO TRANSIENT DURATION
vs. BOI THRESHOLD OVERDRIVE
DVDDIO BOI THRESHOLD OVERDRIVE (mV)
MAXIMUM TRANSIENT DURATION (µs)
MAXQ7670 toc10
0
20
40
60
80
100
120
140
160
180
200
1 10 100 1000
BOI ASSERTED ABOVE THIS LINE
MAXIMUM AVDD TRANSIENT DURATION
vs. BOI THRESHOLD OVERDRIVE
AVDD BOI THRESHOLD OVERDRIVE (mV)
MAXIMUM TRANSIENT DURATION (µs)
MAXQ7670 toc11
0
20
40
60
80
100
120
140
160
180
200
1 10 100 1000
BOI ASSERTED ABOVE THIS LINE
AVDD LINEAR REGULATOR OUTPUT VOLTAGE
vs. DVDDIO SUPPLY VOLTAGE
DVDDIO (V)
AVDD (V)
MAXQ7670 toc12
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
LRAPD = 0
IOUT = 10mA
AVDD LINEAR REGULATOR OUTPUT VOLTAGE
vs. TEMPERATURE
TEMPERATURE (°C)
AVDD (V)
MAXQ7670 toc13
-40 -25 -10 5 20 35 50 65 80 95 110 125
3.20
3.25
3.30
3.35
3.40
LRAPD = 0
IOUT = 10mA
AVDD LINEAR REGULATOR OUTPUT VOLTAGE
vs. LOAD CURRENT
LOAD CURRENT (mA)
AVDD (V)
MAXQ7670 toc14
0 5 10 15 20 25 30 35 40 45 50
3.20
3.25
3.30
3.35
3.40
LRAPD = 0
DVDD LINEAR REGULATOR OUTPUT VOLTAGE
vs. DVDDIO SUPPLY VOLTAGE
DVDDIO (V)
DVDD (V)
MAXQ7670 toc15
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
0
0.5
1.0
1.5
2.0
2.5
3.0
REGEN2 = DVDDIO
IOUT = 10mA
DVDD LINEAR REGULATOR OUTPUT VOLTAG
E
vs. TEMPERATURE
TEMPERATURE (°C)
DVDD (V)
MAXQ7670 toc16
-40 -25 -10 5 20 35 50 65 80 95 110 125
2.40
2.45
2.50
2.55
2.60
REGEN2 = DVDDIO
IOUT = 10mA
DVDD LINEAR REGULATOR OUTPUT VOLTAGE
vs. LOAD CURRENT
LOAD CURRENT (mA)
DVDD (V)
MAXQ7670 toc17
0 5 10 15 20 25 30 35 40 45 50
2.40
2.45
2.50
2.55
2.60
REGEN2 = DVDDIO
RC OSCILLATOR OUTPUT FREQUENCY
vs. TEMPERATURE
TEMPERATURE (°C)
FREQUENCY (MHz)
MAXQ7670 toc18
-40 -25 -10 5 20 35 50 65 80 95 110 125
14.0
14.5
15.0
15.5
16.0
16.5
17.0
Typical Operating Characteristics (continued)
(VDVDDIO = 5.0V, VAVDD = 3.3V, VDVDD = 2.5V, fSYSCLK = 16MHz, ADC resolution = 10 bits, VREFDAC = 3.3V, TA = +25°C, unless
otherwise noted.)
MAXQ7670
Microcontroller with 10-Bit ADC,
PGA, 64KB Flash, and CAN Interface
12 ______________________________________________________________________________________
RC OSCILLATOR OUTPUT FREQUENCY
vs. DVDD
DVDD (V)
FREQUENCY (MHz)
MAXQ7670 toc19
2.25 2.35 2.45 2.55 2.65 2.75
14.0
14.5
15.0
15.5
16.0
DVDD SUPPLY CURRENT
vs. DVDD SUPPLY VOLTAGE
MAXQ7670 toc020
DVDD SUPPLY VOLTAGE (V)
DVDD SUPPLY CURRENT (mA)
2.6252.5002.375
2
4
6
8
10
12
14
16
18
20
0
2.250 2.750
FLASH ERASE
NOTE 4 IN EC CHARACTERISTICS
NOTE 3 IN EC CHARACTERISTICS
NOTE 5 IN EC CHARACTERISTICS
DVDD SUPPLY CURRENT
vs. TEMPERATURE
MAXQ7670 toc21
TEMPERATURE (°C)
DVDD SUPPLY CURRENT (mA)
1109565 80-10 520 35 50-25
2
4
6
8
10
12
14
16
18
20
0
-40 125
FLASH ERASE
NOTE 3 IN EC CHARACTERISTICS
NOTE 5 IN EC CHARACTERISTICS
NOTE 4 IN EC CHARACTERISTICS
DVDD SUPPLY CURRENT
vs. DVDD SUPPLY VOLTAGE
MAXQ7670 toc22
DVDD SUPPLY VOLTAGE (V)
DVDD SUPPLY CURRENT (µA)
2.6252.5002.375
24.0
24.5
25.0
25.5
26.0
26.5
23.5
2.250 2.750
STOP MODE
DVDD SUPPLY CURRENT
vs. TEMPERATURE
MAXQ7670 toc23
TEMPERATURE (°C)
DVDD SUPPLY CURRENT (µA)
1109580655035205-10-25
23
24
25
26
27
28
22
-40 125
STOP MODE
AVDD SUPPLY CURRENT
vs. AVDD SUPPLY VOLTAGE
MAXQ7670 toc24
AVDD SUPPLY VOLTAGE (V)
AVDD SUPPLY CURRENT (nA)
3.453.303.15
20
40
60
80
100
120
140
0
3.00 3.60
SHUTDOWN (NOTE 2)
IN EC CHARACTERISTICS
AVDD SUPPLY CURRENT
vs. TEMPERATURE
MAXQ7670 toc25
TEMPERATURE (°C)
AVDD SUPPLY CURRENT (nA)
1109565 80-10 5 20 35 50-25
20
40
60
80
100
120
140
0
-40 125
SHUTDOWN (NOTE 2)
IN EC CHARACTERISTICS
AVDD SUPPLY CURRENT
vs. AVDD SUPPLY VOLTAGE
MAXQ7670 toc26
AVDD SUPPLY VOLTAGE (V)
AVDD SUPPLY CURRENT (mA)
3.453.303.15
5.7
5.8
5.9
6.0
5.6
3.00 3.60
ALL ANALOG FUNCTIONS ENABLED
AVDD SUPPLY CURRENT
vs. TEMPERATURE
MAXQ7670 toc27
TEMPERATURE (°C)
AVDD SUPPLY CURRENT (mA)
1109580655035205-10-25
5.4
5.6
5.8
6.0
6.2
5.2
-40 125
ALL ANALOG FUNCTIONS ENABLED
Typical Operating Characteristics (continued)
(VDVDDIO = 5.0V, VAVDD = 3.3V, VDVDD = 2.5V, fSYSCLK = 16MHz, ADC resolution = 10 bits, VREFDAC = 3.3V, TA = +25°C, unless
otherwise noted.)
MAXQ7670
Microcontroller with 10-Bit ADC,
PGA, 64KB Flash, and CAN Interface
______________________________________________________________________________________
13
AVDD SUPPLY CURRENT
vs. ADC SAMPLING RATE
MAXQ7670 toc28
ADC SAMPLING RATE (ksps)
AVDD SUPPLY CURRENT (mA)
10 100
5.5
5.6
5.7
5.4
1 1000
PGA GAIN = 16V/V
DVDDIO DYNAMIC SUPPLY CURRENT
vs. DVDDIO SUPPLY VOLTAGE
MAXQ7670 toc29
DVDDIO SUPPLY VOLTAGE (V)
DVDDIO SUPPLY CURRENT (µA)
2.6252.5002.375
120
140
160
180
200
220
240
260
100
2.250 2.750
NOTE 6 IN EC CHARACTERISTICS
DVDDIO DYNAMIC SUPPLY CURRENT
vs. TEMPERATURE
MAXQ7670 toc30
TEMPERATURE (°C)
DVDDIO SUPPLY CURRENT (µA)
1109580655035205-10-25
210
220
230
240
250
200
-40 125
NOTE 6 IN EC CHARACTERISTICS
DVDDIO STATIC SUPPLY CURRENT
vs. DVDDIO SUPPLY VOLTAGE
MAXQ7670 toc31
DVDDIO SUPPLY VOLTAGE (V)
DVDDIO SUPPLY CURRENT (µA)
5.1255.004.875
60
80
100
120
140
160
40
4.750 5.250
DVDDIO STATIC SUPPLY CURRENT
vs. TEMPERATURE
MAXQ7670 toc32
TEMPERATURE (°C)
DVDDIO SUPPLY CURRENT (µA)
1109580655035205-10-25
60
80
100
120
140
160
40
-40 125
Typical Operating Characteristics (continued)
(VDVDDIO = 5.0V, VAVDD = 3.3V, VDVDD = 2.5V, fSYSCLK = 16MHz, ADC resolution = 10 bits, VREFDAC = 3.3V, TA = +25°C, unless
otherwise noted.)
DVDDIO INCREMENTAL SUPPLY CURRENT
vs. DVDDIO SUPPLY VOLTAGE
MAXQ7670 toc33
DVDDIO SUPPLY VOLTAGE (V)
DVDDIO SUPPLY CURRENT (µA)
5.1255.0004.875
1
2
3
4
5
0
4.750 5.250
BOI ENABLED
DVDDIO INCREMENTAL SUPPLY CURRENT
vs. TEMPERATURE
MAXQ7670 toc34
TEMPERATURE (°C)
DVDDIO SUPPLY CURRENT (µA)
5-10-25 503520 110958065
1
2
3
4
5
0
-40 125
BOI ENABLED
ADC SAMPLING ERROR
vs. INPUT SOURCE IMPEDANCE
SOURCE IMPEDANCE (Ω)
SAMPLING ERROR (LSB)
MAXQ7670 toc35
-5
-4
-3
-2
-1
0
1
1 10 100 1000 10,000 100,000
PGA GAIN = 16V/V
fS = 150.9ksps
SNR
FREQUENCY (kHz)
MAGNITUDE (dB)
MAXQ7670 toc36
0 5 10 15 20 25 30 35
-140
-120
-100
-80
-60
-40
-20
0
fIN = 10kHz
fS = 62.5ksps
MAXQ7670
Microcontroller with 10-Bit ADC,
PGA, 64KB Flash, and CAN Interface
14 ______________________________________________________________________________________
Pin Description
PIN NAME FUNCTION
1 AIN7 Analog Input Channel 7. AIN7 is multiplexed to the PGA or ADC as single-ended analog input 7 or as a
differential input with AIN6. As a differential input, the polarity of AIN7 is negative.
2 AIN6 Analog Input Channel 6. AIN6 is multiplexed to the PGA or ADC as a single-ended analog input 6 or as a
differential input with AIN7. As a differential input, the polarity of AIN6 is positive.
3 AIN5 Analog Input Channel 5. AIN5 is multiplexed to the PGA or ADC as single-ended analog input 5 or as a
differential input with AIN4. As a differential input, the polarity of AIN5 is negative.
4 AIN4 Analog Input Channel 4. AIN4 is multiplexed to the PGA or ADC as single-ended analog input 4 or as a
differential input with AIN5. As a differential input, the polarity of AIN4 is positive.
5 REFADC ADC External Reference Input. Connect an external reference between 1V and VAVDD.
6 AGND Analog Ground
7 AIN3 Analog Input Channel 3. AIN3 is multiplexed to the PGA or ADC as single-ended analog input 3 or as a
differential input with AIN2. As a differential input, the polarity of AIN3 is negative.
8 AIN2 Analog Input Channel 2. AIN2 is multiplexed to the PGA or ADC as single-ended analog input 2 or as a
differential input with AIN3. As a differential input, the polarity of AIN2 is positive.
9 AIN1 Analog Input Channel 1. AIN1 is multiplexed to the PGA or ADC as single-ended analog input 1 or as a
differential input with AIN0. As a differential input, the polarity of AIN1 is negative.
10 AIN0 Analog Input Channel 0. AIN0 is multiplexed to the PGA or ADC as single-ended analog input 0 or as a
differential input with AIN1. As a differential input, the polarity of AIN0 is positive.
11 I.C. Internally Connected. Connect to GNDIO for proper operation.
12 P0.0 Port 0 Bit 0. P0.0 is a general-purpose digital I/O with interrupt/wake-up capability.
13 P0.1 Port 0 Bit 1. P0.1 is a general-purpose digital I/O with interrupt/wake-up capability.
14 P0.2 Port 0 Bit 2. P0.2 is a general-purpose digital I/O with interrupt/wake-up capability.
15, 22, 38 GNDIO Digital I/O Ground and Regulator Ground
16 CANRXD CAN Bus Receiver Input. CAN receiver input.
17 CANTXD CAN Bus Transmitter Output. CAN transmitter output.
18 SS
Active-Low, SPI Port Slave Select Input. In SPI slave mode, this is the slave select input. In SPI master
mode, this is an input and connection is optional (connect if mode fault enable is required, refer to the
MAXQ7670 User’s Guide for a description of the SPICN register). In master mode, use an available GPIO
as a slave selector and pull SS high to DVDDIO through a pullup resistor.
19 P0.6/T0
Port 0 Bit 6/Timer 0 I/O. P0.6 is a general-purpose digital I/O with interrupt/wake-up input capability. T0 is a
primary timer/PWM input or output. The alternative function, T0, is selected using the T2CNA0 register.
When this function is selected, it overrides the GPIO functionality.
20 P0.7/T0B
Port 0 Bit 7/Timer 0 Output. P0.7 is a general-purpose digital I/O with interrupt/wake-up input capability.
T0B is a secondary timer/PWM output. The alternative function, T0B, is selected using the T2CNB0 register.
When this function is selected, it overrides the GPIO functionality.
21, 39 DVDDIO
Digital I/O Supply Voltage and Regulator Supply Input. DVDDIO supplies all digital I/O except for XIN and
XOUT, and supplies power to the two internal linear regulators, AVDD and DVDD. Bypass DVDDIO to
GNDIO with a 0.1µF capacitor as close as possible to the device.
MAXQ7670
Microcontroller with 10-Bit ADC,
PGA, 64KB Flash, and CAN Interface
______________________________________________________________________________________ 15
Pin Description (continued)
PIN NAME FUNCTION
23 SCLK SPI Serial Clock. SCLK is the SPI interface serial clock I/O. In SPI master mode, SCLK is an output. While in
SPI slave mode, SCLK is an input.
24 MOSI SPI Serial Data I/O. MOSI is the SPI interface serial data output in master mode or serial data input in slave
mode.
25 MISO SPI Serial Data I/O. MISO is the SPI interface serial data input in master mode or serial data output in slave
mode.
26 REGEN2 Active-Low +2.5V Linear Regulator Enable Input. Connect REGEN2 to GNDIO to enable the +2.5V linear
regulator. Connect to DVDDIO to disable the +2.5V linear regulator.
27 TDO JTAG Serial Test Data Output. TDO is the JTAG serial test, data output.
28 TMS JTAG Test Mode Select. TMS is the JTAG test mode, select input.
29 TDI JTAG Serial Test Data Input. TDI is the JTAG serial test, data input.
30 TCK JTAG Serial Test Clock Input. TCK is the JTAG serial test, clock input.
31 P0.4/
ADCCNV
Port 0 Bit 4/ADC Start Conversion Control. P0.4 is a general-purpose digital I/O with interrupt/wake-up
capability. ADCCNV is a firmware-configurable, rising or falling edge, start/convert signal used to trigger
ADC conversions. The alternative function, ADCCNV, is selected using the register bits ACNT[2:0]. When
using ADCCNV as a trigger for ADC conversion, set P0.4/ADCCNV as an input using the PD0 register. This
action prevents any unintentional interference in the SARADC operation.
32 P0.5 Port 0 Bit 5. P0.5 is a general-purpose digital I/O with interrupt/wake-up capability.
33 RESET Reset Input/Output. Active-low input/output with internal 55kΩ pullup to DVDDIO. Drive low to reset the
MAXQ7670. The MAXQ20 µC core holds RESET low during POR and during DVDD brownout conditions.
34 DGND Digital Ground
35 XOUT
High-Frequency Crystal Output. Connect an external crystal to XIN and XOUT for normal operation, or leave
unconnected if XIN is driven with an external clock source. Leave unconnected if an external clock source
is not used.
36 XIN H i g h- Fr eq uency C r ystal Inp ut. C onnect an exter nal cr ystal or r esonator to X IN and X OU T for nor m al op er ati on,
or d r i ve X IN w i th an exter nal cl ock sour ce. Leave unconnected i f an exter nal cl ock sour ce i s not used .
37 DVDD
D i g i tal S up p l y V ol tag e. D V D D sup p l i es i nter nal d i g i tal cor e and fl ash m em or y. D V D D i s d i r ectl y connected to
the outp ut of the i nter nal + 2.5V l i near r eg ul ator . D i sab l e the i nter nal r eg ul ator ( thr oug h REG EN 2) to connect an
exter nal sup p l y. Byp ass D V D D to D GN D w i th a 0.1µF cap aci tor as cl ose as p ossi b
l e to the d evi ce.
40 AVDD
Analog Supply Voltage. AVDD supplies PGA and ADC. AVDD is directly connected to the output of the
internal +3.3V linear regulator. Disable the internal regulator (via software) to connect an external supply.
Bypass AVDD to AGND with a 0.1µF capacitor as close as possible to the device.
— EP Exposed Pad. Connect EP to the ground plane.
MAXQ7670
Microcontroller with 10-Bit ADC,
PGA, 64KB Flash, and CAN Interface
16 ______________________________________________________________________________________
REFADC
10:1
MUX 10-BIT ADC
SOFTWARE-
INTERRUPT
CONTROLLER
DVDDIO BROWNOUT
MONITOR
I/O
BUFFERS
6:1
MUX
AIN0
AIN1
AIN7
AIN6
AIN1
AIN3
AIN5
AIN7
AIN9
AGND
ADCMX[3:0]
HFFINT
EIFO
SPI
T0I
CANSTI
CANERI VIBE
VIOBI
ADCCLK
ADCE
ADCRY
GNDIO
DVDDIO
P0.7/T0B
P0.6/T0
MOSI
MISO
SERIAL PERIPHERAL
INTERFACE (SPI)
PORT 0
I/O REGISTERS
16-BIT TIMER0
T0CLK
T0I
SPI
WATCHDOG
TIMER
IFFCLK
EWT
4K x 16
UTILITY ROM
16-BIT
MAXQ20 CORE
RISC CPU
64KB (32K x 16)
PROGRAM/DATA
FLASH
2KB (1K x 16)
DATA RAM
+2.5V
LINEAR
REGAULATOR
DVDD
POWER-ON
RESET
MONITOR
HF CLOCK
PRESCALER
ADC CLOCK
PRESCALER
CAN CLOCK
PRESCALER
JTAG INTERFACE
PORT 0
I/O REGISTERS
I/O
BUFFERS
M
U
XM
U
X
GNDIO
HF
XTAL
OSC.
IFFCLK
TIMER CLOCK
PRESCALER
HFE
IFE
INT
FIXED
FREQ
OSC.
SYSCLK
SYSCLK
XHFRY
HFFINT
2:1
DGND
CAN 2.0B
INTERFACE
I/O
BUFFERS
CANSTI
CANERI
GNDIO
CANCLK
CANTXD
CANRXD
GNDIO
DVDDIO
DGND
TCK
TMS
TDI
TDO
REGEN2
DVDD
XOUT
DGND
GNDIO
DGND
GNDIO
XIN
WDI
VDPE
DVDD
RESET
DVDDIO
DVDD
WTR
CANCLK
ADCCLK
T0CLK
AIN2
AIN3
AIN4
AIN5
DGND
GAIN = 1x, 16x
PGA
PGAE
PD0
PO0
PI0
EIF0
HFCLK
DVDDIO
ADCREF
MAXQ7670
GNDIO
DGND
SS
SCLK
P0.5
P0.4/ADCCNV
P0.2
P0.1
P0.0
AVDD BROWNOUT
MONITOR
VABE
VABI
AGND
ADCCNV ADCBY
DVDD
DVDDIO
DVDDIO
DVDDIO
+3.3V
LINEAR
REGAULATOR
GNDIO
LRAPD
AVDD
AVDD
DVDDIO
Block Diagram
MAXQ7670
Microcontroller with 10-Bit ADC,
PGA, 64KB Flash, and CAN Interface
______________________________________________________________________________________ 17
Detailed Description
The MAXQ7670 incorporates a 16-bit RISC arithmetic
logic unit (ALU) with a Harvard memory architecture
that addresses 64KB (32K x 16) of flash and 2048
bytes (1024 x 16) of RAM memory. This core combined
with digital and analog peripherals provide versatile
data-acquisition functions. The peripherals include up to
seven digital I/Os, a 4-wire SPI interface, a CAN 2.0B
bus, a JTAG interface, a timer, an integrated RC oscilla-
tor, two linear regulators, a watchdog timer, three
power-supply supervisors, a 10-bit 250ksps SAR ADC
with programmable-gain amplifier (PGA) and eight sin-
gle-ended or four differential multiplexed inputs. The
power-efficient MAXQ20 µC core consumes less than
1mA/MIPS. Refer to the
MAXQ7670 User’s Guide
for
more detailed information on configuring and program-
ming the MAXQ7670.
Analog Input Peripheral
The integrated 10-bit ADC employs an ultra-low-power
SAR-based conversion method and operates up to
250ksps with PGA = 1V/V (150.9ksps with PGA =
16V/V). The integrated 8-channel multiplexer (mux) and
PGA allow the ADC to measure eight single-ended (rel-
ative to AGND) or four fully differential analog inputs
with software-selectable input ranges through the PGA.
See Figures 3 and 4.
10-BIT ADC
250ksps
DATA
BUS
PGA
1V/V OR
16V/V
PGG
ADCE
1 0
ADCASD
ADCBY
ACTL
TIMER 0
ADCDUL
ADCRDY
ADCBIP
CONVERSION
CONTROL
ADC
CLOCK
DIV
8:1
MUX
ADCCD
1 032
ADCMX
120
10
ADCCLK
SOURCE
REFADC
P0.4/ADCCNV
AGND
AIN4
AIN3
AIN2
AIN7
AIN6
AIN5
AIN1
AIN0
MAXQ7670
Figure 3. Simplified Analog Input Diagram (Eight Single-Ended Inputs)
MAXQ7670
Microcontroller with 10-Bit ADC,
PGA, 64KB Flash, and CAN Interface
18 ______________________________________________________________________________________
10-BIT ADC
250ksps
DATA
BUS
PGG
ADCE
1 0
ADCASD
ADCBY
TIMER 0
ADCDUL
ADCRDY
ADCBIP
CONVERSION
CONTROL
ADC
CLOCK
DIV
4:1
MUX
4:1
MUX
ADCCD
1 032
ADCMX
120
10
ADCCLK
SOURCE
REFADC
P0.4/ADCCNV
AIN1
AIN6
AIN4
AIN7
AIN5
AIN3
AIN2
AIN0
PGA
1V/V OR
16V/V
ACTL
MAXQ7670
Figure 4. Simplified Analog Input Diagram (Four Fully Differential Inputs)
MAXQ7670
Microcontroller with 10-Bit ADC,
PGA, 64KB Flash, and CAN Interface
______________________________________________________________________________________ 19
The MAXQ7670 ADC uses a fully differential SAR con-
version technique and an integrated T/H (track and
hold) block to convert voltage signals into a 10-bit digi-
tal result. Both single-ended and differential configura-
tions are implemented using an analog input channel
multiplexer that supports 8 single-ended or 4 differen-
tial channels.
In single-ended mode, the mux selects from either of
the ground-referenced analog inputs AIN0–AIN7. In dif-
ferential input configuration, analog inputs are selected
from the following pairs: AIN0/AIN1, AIN2/AIN3,
AIN4/AIN5, and AIN6/AIN7. Table 1 shows the single-
ended and differential input configurations possible for
the ADC mux.
Analog Input Track and Hold
A SAR conversion in the MAXQ7670 has different T/H
cycles depending on whether a gain of 1 (bypass) or a
gain of 16 (PGA enabled) is selected.
Gain = 1V/V
In gain = 1V/V, the conversion has a two-stage T/H
cycle. In track mode, a positive input capacitor con-
nects to the signal channel. A negative input capacitor
connects to the reference channel. After the T/H enters
hold mode, the difference between the signal and the
reference channel is converted to a 10-bit value. This
two-stage cycle takes 16 SARCLKs to complete.
Gain = 16V/V
In gain = 16V/V, the conversion has a three-stage T/H
cycle: amplification, ADC track, and ADC hold. First,
the PGA tracks the selected input and reference sig-
nals. The PGA amplifies the difference between the two
signals and holds the result for the next stage, ADC
track. The ADC tracks and converts the PGA result into
a 10-bit value. The SAR operation itself does not
change irrespective of the chosen gain. This three-
stage cycle takes 26.5 SARCLKs to complete. Figure 5
shows the conversion timing differences between gain
= 1V/V and gain = 16V/V.
SAR CHANNEL
SELECT
(REGISTER
ACNT[14:11])
SIGNAL CHANNEL
INTO ADC
REFERENCE
CHANNEL INTO
ADC
MEASUREMENT TYPE
0000 AIN0 AGND Single-ended measurement on AIN0
0001 AIN1 AGND Single-ended measurement on AIN1
0010 AIN2 AGND Single-ended measurement on AIN2
0011 AIN3 AGND Single-ended measurement on AIN3
0100 AIN4 AGND Single-ended measurement on AIN4
0101 AIN5 AGND Single-ended measurement on AIN5
0110 AIN6 AGND Single-ended measurement on AIN6
0111 AIN7 AGND Single-ended measurement on AIN7
1000 — — Reserved
1001 — — Reserved
1010 AIN0 AIN1 AIN0/AIN1
1011 AIN2 AIN3 AIN2/AIN3
1100 AIN4 AIN5 AIN4/AIN5
1101 AIN6 AIN7 AIN6/AIN7
1110 — — Reserved
1111 — — VCIM differential zero offset trim
Table 1. ADC Mux Input Configurations
MAXQ7670
Microcontroller with 10-Bit ADC,
PGA, 64KB Flash, and CAN Interface
20 ______________________________________________________________________________________
Input Impedance
The input-capacitance charging rate determines the
time required for the T/H to acquire an input signal. The
required acquisition time lengthens with the increase of
the input signals source resistance. Any source below
5kΩdoes not significantly affect the ADC’s perfor-
mance. A high-impedance source can be accommo-
dated by placing a 1µF capacitor between the input
channel and AGND. The combination of analog-input
source impedance and the capacitance at the analog
input creates an RC filter that limits the analog-input
bandwidth.
Controlling ADC Conversions
Use the following methods to control the ADC conver-
sion timing:
1) Software register bit control
2) Continuous conversion
3) Internal timer (T0)
4) External input through ADCCNV
Refer to the
MAXQ7670 User’s Guide
for more detailed
information on the ADC and mux.
POR and Brownout
The MAXQ7670 operates from a single, external +5V
supply connected to the DVDDIO. DVDDIO is the sup-
ply rail for the digital I/O and the supply input for both
integrated linear regulators. The +3.3V linear regulator
powers AVDD, while the +2.5V linear regulator powers
DVDD. Alternatively, connect REGEN2 to DVDDIO and
apply external power supplies to AVDD and DVDD.
Power supplies DVDDIO, DVDD, and AVDD each
include a brownout monitor that alerts the µC through
an interrupt when the corresponding supply voltages
drop below a defined threshold. This condition is gen-
erally referred to as brownout interrupt (BOI). Enable
BOI by setting the VABE, VDBE, and VIBE bits in the
APE register. By continually checking for low supply
voltages, appropriate action can be taken for brownout
conditions.
Startup Using Internal Regulators
Once the +5V DVDDIO supply reaches approximately
1.25V, the +2.5V linear regulator turns on and DVDD
begins ramping. Between the DVDD levels of 1V and
the reset threshold, the DVDD monitor holds RESET
low. DVDD releases RESET after reaching the reset
threshold. The MAXQ7670 jumps to the reset vector
location (8000h in the utility ROM). During this time,
DVDD finishes ramping to its nominal voltage of +2.5V.
During this POR time, the software-enabled +3.3V lin-
ear regulator remains off. Turn on the +3.3V linear regu-
lator after the MAXQ7670 has completed its bootup
routines and is running application code. To turn on the
+3.3V regulator, set the LRAPD bit in the APE register
to 0. The AVDD supply begins ramping to its nominal
voltage of +3.3V.
Brownout Detectors
The MAXQ7670 features brownout monitors for the +5V
DVDDIO, +3.3V AVDD, and +2.5V DVDD power sup-
plies. When enabled, these monitors generate interrupts
when DVDDIO, AVDD, or DVDD fall below their respec-
tive brownout thresholds. Monitoring the supply rails
alerts the µC to brownout conditions so appropriate
action can be taken. Under normal conditions the DVDDIO
brownout monitor signals a falling +5V supply before
the DVDD or AVDD brownout monitors indicate that the
+2.5V or +3.3V are falling. The exceptions to this condi-
tion are:
•If either DVDD or AVDD are externally powered and
the source of power is removed
•If there is some type of device failure that pulls the reg-
ulator outputs low without affecting the +5V DVDDIO
supply
SAR CYCLE
PGA = 1V/V
SAR CYCLE
PGA = 16V/V
SAR TRACK HOLD AND SAR CONVERT
PGA TRACK PGA HOLD, SAR TRACK HOLD AND SAR CONVERT
3 SCLK
13 SCLK
7.5 SCLK 6 SCLK 13 SCLK
Figure 5. Conversion Timing Differences Between Gain = 1V/V and Gain = 16V/V
MAXQ7670
Microcontroller with 10-Bit ADC,
PGA, 64KB Flash, and CAN Interface
______________________________________________________________________________________ 21
The DVDD reset supervisor resets the MAXQ7670 when
the +2.5V DVDD falls below the reset threshold. The
processor remains in reset until DVDD returns above
the reset threshold. The µC does not execute com-
mands in reset mode. See Figure 6 for the µC response
to DVDD brownout and reset.
Refer to the
MAXQ7670 User’s Guide
for detailed pro-
gramming information, and a more thorough descrip-
tion of POR and brownout behavior.
Internal 3.3V Linear Regulator
The integrated 3.3V 50mA linear regulator or an exter-
nal 3.3V supply powers AVDD. The integrated 3.3V reg-
ulator is inactive upon power-up. Enable the integrated
regulator with software programming after power-up.
When using an external supply, connect a regulated
3.3V supply to AVDD after applying DVDDIO.
Internal 2.5V Linear Regulator
The integrated 2.5V 50mA linear regulator or an exter-
nal 2.5V supply applied at DVDD powers DVDD.
Connect REGEN2 to GNDIO to enable the integrated
regulator. Connect REGEN2 to DVDDIO to use an
external supply. When using an external supply, con-
nect a regulated 2.5V supply to DVDD after applying
DVDDIO.
DVDDIO Current Requirements
Both internal linear regulators are capable of supplying
up to 50mA each. When using the regulators to power
AVDD and DVDD and to provide power to external
devices, make sure DVDDIO’s power input can source
a current greater than the sum of the MAXQ7670 sup-
ply current and the load currents of the two regulators.
DGND
NOMINAL
DVDD (+2.5V)
BROWNOUT
RESET
(BOR)
+2.38V
INTERNAL RESET BOR STATE
RESET OUTPUT
+2.25V
BROWNOUT
INTERRUPT
(BOI)
DVLVL FLAG
(ASR[14])
DVBI FLAG
(ASR[4])
FLAG ARBITRARILY
CLEARED BY
µ
C
VDBE BIT SET BY µC
DVDD BROWNOUT
INTERRUPT
THRESHOLD RANGE
Figure 6. DVDD Brownout and Reset Behavior
MAXQ7670
Microcontroller with 10-Bit ADC,
PGA, 64KB Flash, and CAN Interface
22 ______________________________________________________________________________________
System Clock Generator
The MAXQ7670 oscillator module provides the master
clock generator that supplies the system clock for the
µC core and all of the peripheral modules. The high-fre-
quency oscillator operates with an 8MHz or 16MHz
crystal. Alternatively, use the integrated RC oscillator in
applications that do not require precise timing. The
MAXQ7670 executes most instructions in a single
SYSCLK period. The oscillator module contains all of
the primary clock generation circuitry. Figure 7 shows a
block diagram of the system clock module.
The MAXQ7670 contains the following features for gen-
erating its master clock signal timing source:
•Internal, fast-starting, 15MHz RC oscillator eliminates
external crystal
•Internal high-frequency oscillator that can drive an
external 8MHz or 16MHz crystal
•External high-frequency 0.166MHz to 16MHz clock input
•Power-up timer
•Power-saving management modes
•Fail-safe modes
Watchdog Timer
The primary function of the watchdog timer is to super-
vise software execution, watching for stalled or stuck
software. The watchdog timer performs a controlled
system restart when the µC fails to write to the watch-
dog timer register before a selectable timeout interval
expires. A watchdog timer typically has four objectives:
1) To detect if a system is operating normally
2) To detect an infinite loop in any of the tasks
3) To detect an arbitration deadlock involving two or
more tasks
4) To detect if some lower priority tasks are not getting
to run because of higher priority tasks
As illustrated in Figure 8, the internal RC oscillator
(CLK_RC) drives the watchdog timer through a series
of dividers. The programmable divider output deter-
mines the timeout interval. When enabled, the interrupt
flag WDIF sets. A system reset occurs after a time
delay (based on the divider ratio) unless an interrupt
service routine clears the watchdog interrupt.
The watchdog timer functions as the source of both the
watchdog interrupt and the watchdog reset. The inter-
rupt timeout has a default divide ratio of 212 of the
CLK_RC, with the watchdog reset set to timeout 29
clock cycles later. With the nominal RC oscillator value
of 15MHz, an interrupt timeout occurs every 0.273ms,
followed by a watchdog reset 34µs later. The watchdog
timer resets to the default divide ratio following any
reset event. Use the WD0 and WD1 bits in the WDCN
register to increase the watchdog interrupt period.
Changing the WD[1:0] bits before a watchdog interrupt
timeout occurs (i.e. before the watchdog reset counter
begins) resets the watchdog timer count. The watch-
dog reset timeout occurs 512 RC oscillator cycles after
the watchdog interrupt timeout. For more information on
the MAXQ7670 watchdog timer, refer to the
MAXQ7670
User’s Guide.
CD1 CD0 PMME
SYSCLK
MUX
CLK_RC
CLOCK
DIVIDE
HF
XTAL
OSC
RC
OSC
XIN
XOUT
XT EXTHF
RCE
HFE
Figure 7. High-Frequency and RC Oscillator Functional
Diagram
EWDI
WD0
RWT
WD1
CLK_RC
(15MHz)
INTERRUPT
WTRF
RESET
WDIF
TIMEOUT
TIME
212
DIV 212 DIV 23DIV 23DIV 23
215 218 221
EWT
RESET
Figure 8. Watchdog Functional Diagram
MAXQ7670
Microcontroller with 10-Bit ADC,
PGA, 64KB Flash, and CAN Interface
______________________________________________________________________________________ 23
Timer and PWM
The MAXQ7670 includes a 16-bit timer channel. The
timer offers two ports, T0 and T0B, to facilitate PWM
outputs, and capture timing events. The autoreload 16-
bit timer/counter offers the following functions:
•8-/16-bit timer/counter
•Up/down autoreload
•Counter function of external pulse
•Capture
•Compare
•PWM output
•Event timer
•System supervisor
Refer to the
MAXQ7670 User’s Guide
and Application
Note 3205:
Using Timers in the MAXQ Family of
Microcontrollers
for more information about the timer
module.
CAN Interface Bus
The MAXQ7670 incorporates a fully compliant CAN
2.0B controller.
Two groups of registers provide the µC interface to the
CAN controller. To simplify the software associated with
the operation of the CAN controllers, most of the global
CAN status and controls as well as the individual mes-
sage center control/status registers are located in the
peripheral register map. The remaining registers asso-
ciated with the data identification, identification masks,
format, and data are located in a dual port memory to
allow the CAN controller and the processor access to
the required functions. The CAN controller can directly
access the dual port memory. The processor accesses
the dual port memory through a dedicated interface
that consists of the CAN 0 data pointer (C0DP) and the
CAN 0 data buffer (C0DB) special function registers.
See Figure 9 for CAN controller details.
CAN Functional Description
The CAN module stores up to 15 messages. Each mes-
sage consists of an acceptance identifier and 8 bytes
of data. The MAXQ7670 supports both the standard 11-
bit and extended 29-bit identification modes.
Configure each of the first 14 message centers either to
transmit or receive. Message center 15 is a receive-
only center, storing any message that centers 1–14 do
not accept.
A message center only accepts an incoming message
if the following conditions are satisfied:
•The incoming message’s arbitration value matches
the message center’s acceptance identifier
•The first 2 data bytes of the incoming message match
the bytes in the media arbitration registers (C0MA0
and C0MA1)
Use the global mask registers to mask out bits in the
incoming message that do not require a comparison.
A message center, configured to transmit, meets these
conditions: T/R = 1, TIH = 0, DTUP = 1, MSRDY = 1,
and MTRQ = 1. The message center transmits its con-
tents when it receives an incoming request message
containing the same identifier (i.e., a remote frame).
Global control and status registers in the CAN unit
enable the µC to evaluate error messages, validate and
locate new data, establish the bus timing for the CAN
bus, establish the identification mask bits, and verify the
source of individual messages. In addition, each mes-
sage center is individually equipped with the necessary
status and controls to establish directions, interrupt gen-
eration, identification mode (standard or extended), data
field size, data status, automatic remote frame request
and acknowledgment, and masked or nonmasked identi-
fication acceptance testing.
JTAG Interface Bus
The joint test action group (JTAG) IEEE®1149.1 stan-
dard defines a unique method for in-circuit testing and
programming. The MAXQ7670 conforms to this stan-
dard, implementing an external test access port (TAP)
and internal TAP controller for communication with a
JTAG bus master, such as an automatic test equipment
(ATE). For detailed information on the TAP and TAP con-
troller, refer to IEEE Standard 1149.1 on the IEEE website
at www.standards.ieee.org. The JTAG on the MAXQ7670
does not support boundary scan test capability.
IEEE is a registered service mark of the Institute of Electrical and Electronics Engineers.
MAXQ7670
Microcontroller with 10-Bit ADC,
PGA, 64KB Flash, and CAN Interface
24 ______________________________________________________________________________________
The TAP controller communicates synchronously with
the host system (bus master) through four digital I/Os:
test mode select (TMS), test clock (TCK), test data
input (TDI), and test data output (TDO). The internal
TAP module consists of several shift registers and a
TAP controller (see Figure 11). The shift registers serve
as transmit-and-receive data buffers for a debugger.
4-Wire SPI Bus
The MAXQ7670 includes a powerful hardware SPI mod-
ule, providing serial communication with a wide variety
of external devices. The SPI port on the MAXQ7670 is a
fully independent module that is accessed through soft-
ware. This full 4-wire, full-duplex serial bus module sup-
ports master and slave modes. The SPI clock
CAN 0 CONTROLLER BLOCK DIAGRAM
DUAL PORT MEMORY CAN PROCESSOR
CAN 0 PERIPHERAL REGISTERS
MESSAGE CENTERS 1–15 BUS ACTIVITY WAKE-UP
8-BIT
Rx
CRC
CHECK
BIT
DESTUFF
Rx
SHIFT
BIT
TIMING CANRXD
CANTXD
MESSAGE CENTER 2
ARBITRATION 0–3
FORMAT
DATA 0–7
MESSAGE CENTER 1
ARBITRATION 0–3
FORMAT
DATA 0–7
MESSAGE CENTER 15
CONTROL/STATUS/MASK REGISTERS
ARBITRATION 0–3
MEDIA ARBITRATION 0–1 EXT GLOBAL MASK 0–3
MEDIA ID MASK 0–1 STD GLOBAL MASK 0–1
BUS TIMING 0–1 MSG15 MASK 0–3
FORMAT
DATA 0–7
MESSAGE CENTER 14
ARBITRATION 0–3
FORMAT
DATA 0–7
CAN 0 TRANSMIT MSG ACK
CAN 0 INTERRUPT REGISTER
CAN 0 STATUS REGISTER
CAN 0 RECEIVE MSG ACK
CAN 0 OPERATION CONTROL
CAN 0 CONTROL REGISTER
CAN 0 DATA POINTER
CAN 0 MESSAGE 1–15
CONTROL REGISTERS
CAN 0 DATA BUFFER
CAN 0 TRANSMIT ERROR
COUNTER
CAN 0 RECEIVE ERROR
COUNTER
CAN INTERRUPT
SOURCES
8-BIT
Tx
CRC
GENERATE
CAN
PROTOCOL
FSM
BIT
STUFF
Tx
SHIFT
MAXQ7670
Figure 9. CAN 0 Controller Block Diagram
MAXQ7670
Microcontroller with 10-Bit ADC,
PGA, 64KB Flash, and CAN Interface
______________________________________________________________________________________ 25
frequency is limited to SYSCLK/2 in master mode and
SYSCLK/8 in slave mode. Figure 10 shows the function-
al diagram of the SPI port. Figures 1 and 2 illustrate the
timing parameters listed in the
Electrical Characteristics
table.
General-Purpose Digital I/Os
The MAXQ7670 provides seven general-purpose digital
I/Os (GPIOs). Some of the GPIOs include an additional
special function (SF), such as a timer input/output. For
example, the state of P0.6/T0 is programmable to
depend on timer channel 0 logic. When used as a port,
each I/O is configurable for high-impedance, weak
pullup to DVDDIO or pulldown to GNDIO. At power-up,
each GPIO is configured as an input with a pullup to
DVDDIO. In addition, each GPIO can be programmed
to cause an interrupt (on falling or rising edges). In stop
mode, use any interrupt to wake-up the device.
The port direction (PD) register determines the
input/output direction of each I/O. The port output (PO)
register contains the current state of the logic output
buffers. When an I/O is configured as an output, writing
to the PO register controls the output logic state.
Reading the PO register shows the current state of the
output buffers, independent of the data direction. The
port input (PI) register is a read-only register that
always reflects the logic state of the I/Os.
SFR DATA BUS
READ BUFFER
SHIFT REGISTER
LSB(0)
MSB (15)
MISO
MASTER
SLAVE
SLAVE
SPI CONTROL UNIT
SYSCLK
SPI INTERRUPT
/2 MASTER (MAX)
/8 SLAVE (MAX)
SHIFT CLK
07
SPI CONTRL REG (SPICN)
SPI CONTRL REG (SPICF)
SPI CONTRL REG (SPICK)
MASTER/SLAVE SELECT
SCLK OUT
SCLK IN
SPI ENABLE
MASTER
MOSI
SCLK
DVDDIO
DVDDIO
SLAVE
MASTER
MAXQ7670
SS
Figure 10. SPI Functional Diagram
MAXQ7670
Microcontroller with 10-Bit ADC,
PGA, 64KB Flash, and CAN Interface
26 ______________________________________________________________________________________
The drive capability of the I/O, when configured for out-
put, depends on the value in the PS0 (pad drive
strength) register and can be set for either 1mA or
2mA. When an I/O is configured as an input, writing to
the PO register enables/disables the pullup/pulldown
resistor. The value in the PRO (pad resistive pull direc-
tion) register sets the enabled resistor at the I/O as
either a pullup to DVDDIO or pulldown to GNDIO.
Refer to the
MAXQ7670 User’s Guide
for more detailed
information.
Port Characteristics
The MAXQ7670 includes a bidirectional 7-bit I/O port
(P0) whose features include:
•Schmitt trigger input circuitry with software-selectable
high-impedance or weak pullup to DVDDIO or pull-
down to GNDIO
•Software-selectable push-pull CMOS output drivers
capable of sinking and sourcing 0.5mA
•Falling or rising edge interrupt capability
•P0.4, P0.6, and P0.7 I/Os contain an additional special
function, such as a logic input/output for a timer channel
•Selectable pad drive strength and resistive pull direction
Refer to the
MAXQ7670 User’s Guide
for more details.
Figure 11 illustrates the functional blocks of an I/O.
MAXQ20 Core Architecture
The MAXQ7670’s core is a member of the low-cost,
high-performance, CMOS, fully static, 16-bit MAXQ20
core µCs. The MAXQ7670 is structured on a highly
advanced, accumulator-based, 16-bit RISC architec-
ture. Fetch and execution operations complete in one
cycle without pipelining because the instruction con-
tains both the op code and data. The result is a stream-
lined 1 million instructions-per-second-per-megahertz
(MIPS/MHz) µC.
The highly efficient core is supported by a 16-level
hardware stack, enabling fast subroutine calling and
task switching. The internal data pointers manipulate
data quickly and efficiently. Multiple data pointers allow
more than one function to access data memory without
having to save and restore data pointers each time. The
data pointers can automatically increment or decre-
ment following an operation, eliminating the need for
software intervention and increasing application speed.
Instruction Set
The instruction set is composed of fixed-length, 16-bit
instructions that operate on registers and memory loca-
tions. The highly orthogonal instruction set allows arith-
metic and logical operations to use any register along
with the accumulator. Special-function registers (also
called peripheral registers) control the peripherals and
are subdivided into register modules. The modular fam-
ily architecture allows new devices and modules to
reuse code developed for existing products. The archi-
tecture is transport-triggered. This means that writes or
reads from certain register locations can also cause
side effects to occur. These side effects form the basis
for the higher-level op codes defined by the assembler,
such as ADDC, OR, JUMP, etc.
Memory Organization
The MAXQ7670 incorporates the following memory
areas (see Figure 12):
•8KB (4K x 16) utility ROM
•64KB (32K x 16) of flash memory for program storage
•2048 bytes (1024 x 16) of SRAM for storage of tempo-
rary variables
•16-level stack memory for storage of program return
addresses and general-purpose use
A 16-bit-wide x 16 deep internal hardware stack pro-
vides storage for program return addresses and gener-
al-purpose use. The MAXQ7670 core implicitly uses the
stack when executing an interrupt service routine (ISR)
and also when running CALL, RET, and RETI instruc-
tions. The stack can also be explicitly used by the
MAXQ7670
VDVDDIO
P
N
PI0._
PO0._
PS0._
PD0._
PULLUP/
PULLDOWN
LOGIC
PR0._
PD0._
PO0._
P0._
Figure 11. Digital I/O Circuitry
MAXQ7670
Microcontroller with 10-Bit ADC,
PGA, 64KB Flash, and CAN Interface
______________________________________________________________________________________ 27
application code to store data when context switching
(e.g., during a call or an interrupt). Storing and retriev-
ing data is executed through the PUSH, POP, and POPI
instructions.
The incorporation of flash memory allows device repro-
gramming, eliminating the expense of discarding one-
time programmable devices during development and
field upgrades (see Figure 13 for the flash memory sec-
tor maps).
A 16-word key protects the flash memory from access
by unauthorized individuals. Without supplying the 16-
word key, the password lock (PWL) bit in the SC regis-
ter remains set, and the utility ROM is inaccessible.
Supplying the 16-word key makes the utility ROM trans-
parent. The password-unlock command is issued
through the TAP interface. The 16-word password is
compared to the password in the program space to
determine its validity.
Enabling a pseudo-Von Neumann memory map places
the utility ROM, code, and data memory into a single
contiguous memory map. Use this mapping scheme for
applications that require dynamic program modification
or unique memory configurations.
EXECUTING
FROM
PROGRAM
SPACE
DATA SPACE
(WORD MODE)
1024 x 16
DATA RAM
4K x 16
UTILITY ROM
32K x 16
PROGRAM
FLASH
FFFFh
A3FFh
7FFFh
0000h
A400h
A000h
8FFFh
8000h
8FFFh
8000h
03FFh
0000h
FFFFh
7FFFh
0400h
9000h
DATA SPACE
(BYTE MODE)
8K x 8
UTILITY ROM
2048 x 8
DATA RAM
FFFFh
7FFFh
0400h
03FFh
0000h
9000h
8FFFh
8000h
1024 x 16
DATA RAM
4K x 16
UTILITY ROM
Figure 12. MAXQ7670 Memory Map
32K x 16
PROGRAM
FLASH
7FFFh
0000h
1 PAGE = 256 WORDS
PAGE 127
PAGE 126
PAGE 125
PAGE 2
PAGE 1
PAGE 0
Figure 13. Flash Memory Sector Maps
MAXQ7670
Microcontroller with 10-Bit ADC,
PGA, 64KB Flash, and CAN Interface
28 ______________________________________________________________________________________
Stack Memory
A 16-bit-wide x 16 deep internal hardware stack pro-
vides storage for program return addresses and gener-
al-purpose use. The processor uses the stack
automatically when executing the CALL, RET, and RETI
instructions and when servicing interrupts. The stack
stores and retrieves data through the PUSH, POP, and
POPI instructions.
On reset, the stack pointer, SP, initializes to the top of
the stack (0Fh). The CALL, PUSH, and interrupt-vector-
ing operations increment SP, then store a value at the
location pointed to by SP. The RET, RETI, POP, and
POPI operations retrieve the value at SP and then
decrement SP.
Utility ROM
The utility ROM is a 8KB (4K x 16) block of internal
ROM memory that defaults to a starting address of
8000h. The utility ROM consists of subroutines
accessed from application software. These include:
•In-system programming (bootstrap loader) over JTAG
and CAN
•In-circuit debug routines
•Routines for in-application flash programming and
fast table lookup
Following any reset, execution begins in the utility ROM.
The ROM software determines whether the program exe-
cution should immediately jump to location 0000h, the
start of user-application code, or to one of the above rou-
tines. Utility ROM routines are accessible in the applica-
tion software. For more information on the utility ROM
contents, refer to the
MAXQ7670 User’s Guide
.
Programming Flash Memory
The MAXQ7670 allows the user to program its flash
through the JTAG or the CAN port by allowing access
to the ROM-based bootloader through these ports. The
bootloader is entered in one of three ways: by a JTAG
request during the power-up sequence, through a CAN
request immediately after power-up when no password
has been set, and by jumping to the bootloader from
the application code. After a reset, the MAXQ7670
instruction pointer jumps to the beginning of ROM code
(0x8000). The ROM code does some initial housekeep-
ing and then looks for a request from the JTAG port. If
there is a valid request (i.e., SPE = 1, PSS = 00), the
processor establishes communication between the
ROM bootloader and the JTAG port. If there is no JTAG
request and the password has been set (0x0010 to
0x001F is not all 0s or all Fs), then program execution
jumps to the application code at address 0x0000. If the
password has not been set (0x0010 to 0x001F is all 0s
or all Fs), the ROM code monitors the CAN port for 5s
waiting to receive 0x3E. If this character is not detected
within 5s, program execution jumps to the application
code at address 0x000. If 0x3E is detected during the
five-second window, the CAN port is established as the
bootloader communication port and the MAXQ7670
responds with 0x3E, verifying that it is in the loader
mode. CAN bootloader communication speed is set to
500kbaud when using a 16MHz crystal and 250kbaud
when using an 8MHz crystal.
Once communication has been established with the
loader, the host has access to all the family 0 com-
mands regardless of the state of the PWL bit. If PWL =
0, all the loader commands are accessible. Family 0
commands all start with a 0 and provide basic function-
ality, but do not allow access to information in either
program memory or data memory. This prevents unau-
thorized access of proprietary information. A mass
erase of the flash sets all flash memory including the
password to 0xFFFF. With this condition, it is as if no
password has been set and the PWL bit is set to 0,
which allows access to all loader commands. For more
information on password protection and loader com-
mands, refer to the
MAXQ7670 User’s Guide
.
In-Application Programming
The in-application programming feature allows the µC
to modify its own flash program memory while simulta-
neously executing its application software. This allows
on-the-fly software updates in mission-critical applica-
tions that cannot afford downtime. In-application pro-
gramming also allows the application to develop
custom loader software that can operate under the con-
trol of the application software. The utility ROM contains
user-accessible flash programming functions that erase
and program flash memory. These functions are
described in detail in the
MAXQ7670 User’s Guide
.
Register Set
Register sets control the MAXQ7670 functions. These
registers provide a working space for memory opera-
tions as well as configuring and addressing peripheral
registers on the device. Registers are divided into two
major types: system registers and peripheral registers.
The common register set, also known as the system
registers, includes the ALU, accumulator registers, data
pointers, interrupt vectors and control, and stack point-
er. Tables 2–5 show the MAXQ7670 register set.
MAXQ7670
Microcontroller with 10-Bit ADC,
PGA, 64KB Flash, and CAN Interface
______________________________________________________________________________________ 29
Power Management
Advanced power-management features minimize
power consumption by dynamically matching the pro-
cessing speed of the device to the required perfor-
mance level. During periods of reduced activity, lower
the system clock speed to reduce power consumption.
Use the source-clock-divide feature to reduce the sys-
tem clock speed to 1/2, 1/4, and 1/8 of the source
clock’s speed. A lower power state is thus achievable
without additional hardware. For extremely power-sen-
sitive applications, two additional low-power modes are
available:
•PMM: divide-by-256 power-management mode
(PMME = 1)
•Stop mode (STOP = 1)
Enabling PMM reduces the system clock speed to
1/256 of the source clock speed, and significantly
reduces power consumption. The optional switchback
feature allows enabled interrupt sources including
external, CAN, and SPI interrupts to bring the µC out of
the power-management mode and to run at a faster
system clock speed.
Power consumption is minimal in stop mode. In this
mode, the external oscillator, internal RC oscillator, sys-
tem clock, and all processing activity stop. Triggering
an enabled external interrupt or applying an external
reset signal to RESET brings the µC out of stop mode.
Upon exiting stop mode, the µC can either wait for the
external crystal to warm up, or execute immediately by
using the internal RC oscillator as the crystal warms up.
Interrupts
Multiple interrupt sources are available for quick
response to internal and external events. Examples of
events that can trigger an interrupt are:
•Watchdog interrupt
•GPIO0–GPIO7 interrupts
•SPI mode fault, write collision, receive overrun, and
transfer complete interrupts
•Timer 0 low compare, low overflow, capture/compare,
and overflow interrupts
•CAN0 receive and transmit interrupts and a change in
CAN0 status register interrupt
•ADC data ready interrupt
•Voltage brownout interrupts
•Crystal oscillator failure interrupt
Each interrupt has flag and enable bits. The flag indi-
cates whether an interrupt event has occurred. Enable
the µC to generate an interrupt by setting the enable
bit. Interrupts are organized into modules. Enable the
interrupt individually, by module, and globally.
The µC jumps to an ISR after an enabled interrupt event
occurs. Use the interrupt identification register (IIR) to
determine whether the interrupt is a system or peripher-
al interrupt. In the ISR, clear the interrupt flag to elimi-
nate repeated interrupts from the same event. After
clearing the interrupt, allow a delay before issuing the
return from interrupt (RETI) instruction. Asynchronous
interrupt flags require a one-instruction delay and syn-
chronous interrupt flags require a two-instruction delay.
The MAXQ architecture uses a single interrupt vector
(IV) and single ISR design. The IV register holds the
address of the ISR. In the application code, assign a
unique address to each ISR. Otherwise, the IV automat-
ically jumps to 0000h, the beginning of application
code, after an enabled interrupt occurs.
Reset Sources
Reset sources are provided for µC control. Although
code execution stops in the reset state, the internal RC
oscillator continues to oscillate. Internal resets, such as
the power-on and watchdog resets, pull RESET low.
Power-On Reset (POR)
An internal POR circuit enhances system reliability. The
POR circuit forces the device to perform a POR when-
ever a rising voltage on DVDD climbs above the POR
threshold. At this point the following events occur:
•All registers and circuits enter the default state
•The POR flag (WDCN.7) sets to indicate if the source
of the reset was a loss of power
•The internal 15MHz RC oscillator becomes the clock
source
•Code execution begins at location 8000h
Refer to the
MAXQ7670 User’s Guide
for more information.
Watchdog Timer Reset
The watchdog timer functions are described in the
MAXQ7670 User’s Guide
. Execution resumes at loca-
tion 8000h following a watchdog timer reset.
External System Reset
Pulling RESET low externally causes the device to enter
the reset state. The external reset functions as
described in the
MAXQ7670 User’s Guide
. Execution
resumes at location 8000h after RESET is released.
MAXQ7670
Microcontroller with 10-Bit ADC,
PGA, 64KB Flash, and CAN Interface
30 ______________________________________________________________________________________
Crystal Selection
The MAXQ7670 uses an 8MHz or 16MHz Jauch
JXG53P2 (or similar specification):
Frequency: 8MHz or 16MHz ±0.25%.
CLOAD: 12pF.
CO: < 7pF max.
Series resonance resistance: max 50Ω/300Ωfor
16MHz/8MHz, respectively.
Note: Series resonance resistance is the resistance
observed when the resonator is in the series resonant
condition. This is a parameter often stated by quartz
crystal vendors and is called R1. When a resonator is
used in the parallel resonant mode with an external
load capacitance, as is the case with the MAXQ7670
oscillator circuit, the effective resistance is sometimes
stated. This effective resistance at the loaded frequen-
cy of oscillation is:
R1 x (1 + (CO/CLOAD))2
For typical COand CLOAD values, the effective resis-
tance can be greater than R1 by a factor of two.
Development and Technical Support
Highly versatile, affordably priced development tools
for this µC are available from Maxim and third-party
suppliers. Tools for the MAXQ7670 include:
•Compilers
•Evaluation kits
•JTAG-to-serial converters for programming and
debugging
A list of development tool vendors can be found at
www.maxim-ic.com/microcontrollers. For technical
support, go to www.maxim-ic.com/support.
MODULE NAME (BASE SPECIFIER)
REGISTER
INDEX AP (8h) A (9h) PFX (Bh) IP (Ch) SP (Dh) DPC (Eh) DP (Fh)
0h AP A[0] PFX[0] IP ———
1h APC A[1] PFX[1] —SP ——
2h — A[2] PFX[2] —IV ——
3h — A[3] PFX[3] — — OFFS DP0
4h PSF A[4] PFX[4] ——DPC —
5h IC A[5] PFX[5] ——GR —
6h IMR A[6] PFX[6] —LC0 GRL —
7h — A[7] PFX[7] —LC1 BP DP1
8h SC A[8] ——GRS —
9h — A[9] — — — GRH —
Ah — A[10] ———GRXL —
Bh IIR A[11] ———FP —
Ch — A[12] —————
Dh — A[13] —————
Eh CKCN A[14] —————
Fh WDCN A[15] —————
Table 2. System Register Map
MAXQ7670
Microcontroller with 10-Bit ADC,
PGA, 64KB Flash, and CAN Interface
______________________________________________________________________________________ 31
REGISTER BIT
REGISTER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
— — — — AP (4 Bits)
AP 00000000
CLR IDS — — — MOD2 MOD1 MOD0
APC 00000000
Z S — GPF1 GPF0 OV C E
PSF 10000000
— — CGDS — — — INS IGE
IC 00000000
IMS — IM5 IM4 IM3 IM2 IM1 IM0
IMR 00000000
TAP — CDA1 CDA0 UPA ROD PWL —
SC 100000s*0
IIS — II5 II4 II3 II2 II1 II0
IIR 00000000
XT — RGMD STOP SWB PMME CD1 CD0
CKCN s* 0 s* 0 0 0 0 1
POR EWDI WD1 WD0 WDIF WTRF EWT RWT
WDCN s* s* 0 0 0 s* s* 0
A[n] (16 Bits)
A[n] (0..15) 0000000000 0 00 0 0 0
PFX[n] (16 Bits)
PFX[n] (0..15) 0000000000 0 00 0 0 0
IP (16 Bits)
IP 1000000000 0 00 0 0 0
—————————— — — SP (4 Bits)
SP 0000000000 0 01 1 1 1
IV (16 Bits)
IV 0000000000 0 00 0 0 0
LC[0] (16 Bits)
LC[0] 0000000000 0 00 0 0 0
LC[1] (16 Bits)
LC[1] 0000000000 0 00 0 0 0
OFFS (8 Bits)
OFFS 00000000
—————————— —WBS2 WBS1 WBS0 SDPS1 SDPS0
DPC 0000000000 0 11 1 0 0
GR.15 GR.14 GR.13 GR.12 GR.11 GR.10 GR.9 GR.8 GR.7 GR.6 GR.5 GR.4 GR.3 GR.2 GR.1 GR.0
GR 0000000000 0 00 0 0 0
GR.7 GR.6 GR.5 GR.4 GR.3 GR.2 GR.1 GR.0
GRL 00000000
BP (16 Bits)
BP 0000000000 0 00 0 0 0
GR.7 GR.6 GR.5 GR.4 GR.3 GR.2 GR.1 GR.0 GR.15 GR.14 GR.13 GR.12 GR.11 GR.10 GR.9 GR.8
GRS 0000000000 0 00 0 0 0
GR.15 GR.14 GR.13 GR.12 GR.11 GR.10 GR.9 GR.8
GRH 00000000
GR.7 GR.7 GR.7 GR.7 GR.7 GR.7 GR.7 GR.7 GR.7 GR.6 GR.5 GR.4 GR.3 GR.2 GR.1 GR.0
GRXL 0000000000 0 00 0 0 0
FP (16 Bits)
FP 0000000000 0 00 0 0 0
DP[0] (16 Bits)
DP[0] 0000000000 0 00 0 0 0
DP[1] (16 Bits)
DP[1] 0000000000 0 00 0 0 0
Table 3. System Register Bit and Reset Values
*Bits indicated by an "s" are only affected by a POR and not by other forms of reset. These bits are set to 0 after a POR. Refer to the
MAXQ7670 User’s Guide
for more information.
MAXQ7670
Microcontroller with 10-Bit ADC,
PGA, 64KB Flash, and CAN Interface
32 ______________________________________________________________________________________
REGISTER
INDEX M0 (0h) M1 (1h) M2 (2h) M3 (3h) M4 (4h) M5 (5h)
0h PO0 — T2CNA0 — C0C —
1h — — T2HO — C0S APE
2h — — T2RHO — COIR ACNTL
3h EIFO — T2CHO — C0TE —
4h————C0RE —
5h————C0R—
6h — SPIB — — C0DP —
7h — SPICN — — C0DB —
8h PI0 SPICF T2CNBO — C0RMS ADCD
9h — SPICK T2VO — C0TMA —
Ah — FCNTL T2RO — — AIE
Bh EIEO — T2CO — — ASR
Ch—————OSCC
Dh——————
Eh——————
Fh——————
10h PD0 — T2CFG0 — — —
11h — FPCTL — — C0M1C —
12h————C0M2C —
13h EIESO — — — C0M3C —
14h————C0M4C —
15h————C0M5C —
16h————C0M6C —
17h————C0M7C —
18h PS0 — ICDT0 — C0M8C —
19h — — ICDT1 — C0M9C —
1Ah — — ICDC — C0M10C —
1Bh PRO — ICDF — C0M11C —
1Ch — ID0 ICDB — C0M12C —
1Dh — — ICDA — C0M13C —
1Eh — — ICDD — C0M14C —
1Fh — — TM — C0M15C —
Table 4. Peripheral Register Map
MAXQ7670
Microcontroller with 10-Bit ADC,
PGA, 64KB Flash, and CAN Interface
______________________________________________________________________________________ 33
REGISTER BIT
REGISTER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
— — — — — — — — PO0.7 PO0.6 PO0.5 PO0.4 — PO0.2 PO0.1 PO0.0
PO0 0000000011 1 101 1 1
— — — — — — — — IE7 IE6 IE5 IE4 — IE2 IE1 IE0
EIF0 0000000000 0 000 0 0
— — — — — — — — PI0.7 PI0.6 PI0.5 PI0.4 — PI0.2 PI0.1 PI0.0
PI0 0 0 0 0 0 0 0 0 ST ST ST ST 0 ST ST ST
———————— EX7 EX6 EX5 EX4 — EX2 EX1 EX0
EIE0 0 0 0 0 0 0 0 0 00 0 000 0 0
———————— PD0.7 PD0.6 PD0.5 PD0.4 — PD0.2 PDO.1 PD0.0
PD0 0 0 0 0 0 0 0 0 00 0 000 0 0
— — — — — — — — IT7 IT6 IT5 IT4 — IT2 IT1 IT0
EIES0 0000000000 0 000 0 0
— — — — — — — — PS7 PS6 PS5 PS4 — PS2 PS1 PS0
PS0 0000000000 0 000 0 0
— — — — — — — — PR7 PR6 PR5 PR4 — PR2 PR1 PR0
PR0 0000000000 0 000 0 0
SPIB.15 SPIB.14 SPIB.13 SPIB.12 SPIB.11 SPIB.10 SPIB.9 SPIB.8 SPIB.7 SPIB.6 SPIB.5 SPIB.4 SPIB.3 SPIB.2 SPIB.1 SPIB.0
SPIB 0 0 0 0 0 0 0 0 00 0 000 0 0
———————— STBY SPIC ROVR WCOL MODF MODFE MSTM SPIEN
SPICN 0 0 0 0 0 0 0 0 00 0 000 0 0
———————— ESPII — — — — CHR CKPHA CKPOL
SPICF 0 0 0 0 0 0 0 0 00 0 000 0 0
— — — — — — — — SPICK7 SPICK6 SPICK5 SPICK4 SPICK3 SPICK2 SPICK1 SPICK0
SPICK 0000000000 0 000 0 0
— — — — — — — — FBUSY — — — — FC2 FC1 FC0
FCNTL 0000000010 0 000 0 0
— — — — — — — — — — — — — — — DPMG
FPCTL 0000000000 0 000 0 0
— — — — — — — — ID0.7 ID0.6 ID0.5 ID0.4 ID0.3 ID0.2 ID0.1 ID0.0
ID0 0 0 0 0 0 0 0 0 00 0 000 0 0
———————— ET2 T2OE0 T2POL0 TR2L TR2 CPRL2 SS2 G2EN
T2CNA0 0 0 0 0 0 0 0 0 00 0 000 0 0
———————— T2H0.7 T2H0.6 T2H0.5 T2H0.4 T2H0.3 T2H0.2 T2H0.1 T2H0.0
T2H0 0 0 0 0 0 0 0 0 00 0 000 0 0
— — — — — — — — T2RH0.7 T2RH0.6 T2RH0.5 T2RH0.4 T2RH0.3 T2RH0.2 T2RH0.1 T2RH0.0
T2RH0 0000000000 0 000 0 0
— — — — — — — — T2CH0.7 T2CH0.6 T2CH0.5 T2CH0.4 T2CH0.3 T2CH0.2 T2CH0.1 T2CH0.0
T2CH0 0000000000 0 000 0 0
— — — — — — — — ET2L T2OE1 T2POL1 —TF2 TF2L TCC2 TC2L
T2CNB0 0000000000 0 000 0 0
T2V0.15 T2V0.14 T2V0.13 T2V0.12 T2V0.11 T2V0.10 T2V0.9 T2V0.8 T2V0.7 T2V0.6 T2V0.5 T2V0.4 T2V0.3 T2V0.2 T2V0.1 T2V0.0
T2V0 0 0 0 0 0 0 0 0 00 0 000 0 0
T2R0.15 T2R0.14 T2R0.13 T2R0.12 T2R0.11 T2R0.10 T2R0.9 T2R0.8 T2R0.7 T2R0.6 T2R0.5 T2R0.4 T2R0.3 T2R0.2 T2R0.1 T2R0.0
T2R0 0 0 0 0 0 0 0 0 00 0 000 0 0
T2C0.15 T2C0.14 T2C0.13 T2C0.12 T2C0.11 T2C0.10 T2C0.9 T2C0.8 T2C0.7 T2C0.6 T2C0.5 T2C0.4 T2C0.3 T2C0.2 T2C0.1 T2C0.0
T2C0 0 0 0 0 0 0 0 0 00 0 000 0 0
————————T2C1 T2DIV2 T2DIV1 T2DIV0 T2MD CCF1 CCF0 C/T2
T2CFG0 00000000000000 0 0
ICDT0.15 ICDT0.14 ICDT0.13 ICDT0.12 ICDT0.11 ICDT0.10 ICDT0.9 ICDT0.8 ICDT0.7 ICDT0.6 ICDT0.5 ICDT0.4 ICDT0.3 ICDT0.2 ICDT0.1 ICDT0.0
ICDT0 DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB
ICDT1.15 ICDT1.14 ICDT1.13 ICDT1.12 ICDT1.11 ICDT1.10 ICDT1.9 ICDT1.8 ICDT1.7 ICDT1.6 ICDT1.5 ICDT1.4 ICDT1.3 ICDT1.2 ICDT1.1 ICDT1.0
ICDT1 DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB
— — — — — — — — DME — REGE — CMD3 CMD2 CMD1 CMD0
ICDC 0 0 0 0 0 0 0 0 DW 0 DW 0 DW DW DW DW
————————————PSS1 PSS0 SPE TXC
ICDF 00000000000000 0 0
————————ICDB.7ICDB.6ICDB.5ICDB.4ICDB.3ICDB.2ICDB.1 ICDB.0
ICDB 00000000000000 0 0
ICDA.15 ICDA.14 ICDA.13 ICDA.12 ICDA.11 ICDA.10 ICDA.9 ICDA.8 ICDA.7 ICDA.6 ICDA.5 ICDA.4 ICDA.3 ICDA.2 ICDA.1 ICDA.0
ICDA 00000000000000 0 0
ICDD.15 ICDD.14 ICDD.13 ICDD.12 ICDD.11 ICDD.10 ICDD.9 ICDD.8 ICDD.7 ICDD.6 ICDD.5 ICDD.4 ICDD.3 ICDD.2 ICDD.1 ICDD.0
ICDD 00000000000000 0 0
Table 5. Peripheral Register Bit Functions and Reset Values
MAXQ7670
Microcontroller with 10-Bit ADC,
PGA, 64KB Flash, and CAN Interface
34 ______________________________________________________________________________________
REGISTER BIT
REGISTER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
— — — — CRTMS CRTM TESTCAN — DCW FTEST DOFF — SRT — SCANMODE TME
TM 00000000000000 0 0
————————ERIE STIE PDE SIESTA CRST AUTOB ERCS SWINT
C0C 00000000000010 0 1
————————BSSEC96/128 WKS RXS TXS ER2 ER1 ER0
C0S 00000000000000 0 0
————————INTIN7INTIN6 INTIN5 INTIN4 INTIN3 INTIN2 INTIN1 INTIN0
C0IR 00000000000000 0 0
————————C0TE.7 C0TE.6 C0TE.5 C0TE.4 C0TE.3 C0TE.2 C0TE.1 C0TE.0
C0TE 00000000000000 0 0
————————C0RE.7 C0RE.6 C0RE.5 C0RE.4 C0RE.3 C0RE.2 C0RE.1 C0RE.0
C0RE 00000000000000 0 0
————————CAN0BA INCDEC AID C0BPR7 C0BPR6 — C0BIE C0IE
COR 00000000000000 0 0
C0DP.15 C0DP.14 C0DP.13 C0DP.12 C0DP.11 C0DP.10 C0DP.9 C0DP.8 C0DP.7 C0DP.6 C0DP.5 C0DP.4 C0DP.3 C0DP.2 C0DP.1 C0DP.0
C0DP 00000000000000 0 0
C0DB.15 C0DB.14 C0DB.13 C0DB.12 C0DB.11 C0DB.10 C0DB.9 C0DB.8 C0DB.7 C0DB.6 C0DB.5 C0DB.4 C0DB.3 C0DB.2 C0DB.1 C0DB.0
C0DB 00000000000000 0 0
— C0RMS.15 C0RMS.14 C0RMS.13 C0RMS.12 C0RMS.11 C0RMS.10 C0RMS.9 C0RMS.8 C0RMS.7 C0RMS.6 C0RMS.5 C0RMS.4 C0RMS.3 C0RMS.2 C0RMS.1
C0RMS 00000000000000 0 0
— C0TMA.15 C0TMA.14 C0TMA.13 C0TMA.12 C0TMA.11 C0TMA.10 C0TMA.9 C0TMA.8 C0TMA.7 C0TMA.6 C0TMA.5 C0TMA.4 C0TMA.3 C0TMA.2 C0TMA.1
C0TMA 00000000000000 0 0
————————MSRDY ETI ERI INTRQ EXTRQ MTRQ ROW/TIH DTUP
C0M1C 00000000000000 0 0
————————MSRDY ETI ERI INTRQ EXTRQ MTRQ ROW/TIH DTUP
C0M2C 00000000000000 0 0
————————MSRDY ETI ERI INTRQ EXTRQ MTRQ ROW/TIH DTUP
C0M3C 00000000000000 0 0
————————MSRDY ETI ERI INTRQ EXTRQ MTRQ ROW/TIH DTUP
C0M4C 00000000000000 0 0
————————MSRDY ETI ERI INTRQ EXTRQ MTRQ ROW/TIH DTUP
C0M5C 00000000000000 0 0
————————MSRDY ETI ERI INTRQ EXTRQ MTRQ ROW/TIH DTUP
C0M6C 00000000000000 0 0
————————MSRDY ETI ERI INTRQ EXTRQ MTRQ ROW/TIH DTUP
C0M7C 00000000000000 0 0
————————MSRDY ETI ERI INTRQ EXTRQ MTRQ ROW/TIH DTUP
C0M8C 00000000000000 0 0
————————MSRDY ETI ERI INTRQ EXTRQ MTRQ ROW/TIH DTUP
C0M9C 00000000000000 0 0
————————MSRDY ETI ERI INTRQ EXTRQ MTRQ ROW/TIH DTUP
C0M10C 00000000000000 0 0
————————MSRDY ETI ERI INTRQ EXTRQ MTRQ ROW/TIH DTUP
C0M11C 00000000000000 0 0
————————MSRDY ETI ERI INTRQ EXTRQ MTRQ ROW/TIH DTUP
C0M12C 00000000000000 0 0
Table 5. Peripheral Register Bit Functions and Reset Values (continued)
MAXQ7670
Microcontroller with 10-Bit ADC,
PGA, 64KB Flash, and CAN Interface
______________________________________________________________________________________ 35
Bits indicated by “—“ are unused.
Bits indicated by “DB” have read/write access only in background or debug mode. These bits are cleared after a POR.
Bits indicated by “DW” are only written to in debug mode. These bits are cleared after a POR.
The OSCC register is cleared to 0002h after a POR and is not affected by other forms of reset.
REGISTER BIT
REGISTER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
————————MSRDY ETI ERI INTRQ EXTRQ MTRQ ROW/TIH DTUP
C0M13C 00000000000000 0 0
————————MSRDY ETI ERI INTRQ EXTRQ MTRQ ROW/TIH DTUP
C0M14C 00000000000000 0 0
————————MSRDY ETI ERI INTRQ EXTRQ MTRQ ROW/TIH DTUP
C0M15C 00000000000000 0 0
— — LRAPD VIBE VDBE VDPE VABE — — — PGG0 — — BIASE — ADCE
APE 00100100000000 0 0
— ADCMX3 ADCMX2 ADCMX1 ADCMX0 — ADCBIP — — ADCDUL ADCRSEF ADCASD ADCBY ADCS2 ADCS1 ADCS0
ACNT —0000000000000 0 0
— — — — — — ADCD.9 ADCD.8 ADCD.7 ADCD.6 ADCD.5 ADCD.4 ADCD.3 ADCD.2 ADCD.1 ADCD.0
ADCD 00000000000000 0 0
—————————HFFIE VIOBIE DVBIE AVBIE — ADCIE —
AIE 00000000000000 0 0
VIOLVL DVLVL AVLVL — XHFRY — — — — HFFINT VIOBI DVBI AVBI — ADCRY —
ASR 00000000000000 0 0
—————————ADCCD1 ADCCD0 — — XTE RCE —
OSCC 00000000000000 0 0
Table 5. Peripheral Register Bit Functions and Reset Values (continued)
MAXQ7670
Microcontroller with 10-Bit ADC,
PGA, 64KB Flash, and CAN Interface
36 ______________________________________________________________________________________
MAXQ7670
10-BIT
ADC
PGA
x16
MUX
MUX
-2nF
-2nF
R+dr
R-dr
R-dr
R+dr
VBRIDGEA
GNDA
OUTA+
OUTA-
-2nF
-2nF
R+dr
R-dr
R-dr
R+dr
VBRIDGEB
GNDB
OUTB+
OUTB-
DUAL-BRIDGE SENSOR
-2nF
-2nF
R+dr
R-dr
R-dr
R+dr
VBRIDGEA
GNDA
OUTA+
OUTA-
-2nF
-2nF
0.47µF
R+dr
R-dr
R-dr
R+dr
VBRIDGEB
GNDB
OUTB+
OUTB-
DUAL-BRIDGE SENSOR
AIN0
AIN2
AIN4
AIN6
AIN1
AIN3
AIN5
AIN7
GPIO
16-BIT TIMER
SPI
JTAG
CAN 2.0B
64KB
PROGRAM/DATA
FLASH
2KB DATA RAM
MAXQ20 CORE
16-BIT RISC
MICRO
0.47µF
+3.3V
16MHz
AVDD
DIGITAL I/O
SPI
REFADC
I.C.
0.1µF
0.1µF
0.1µF15µF
DVDDIO
P0.7/T0B
P0.6/T0
P0.5
P0.4/ADCCNV
SCLK
MISO
MOSI
SS
P0.2
P0.1
P0.0
JTAG
CAN
TCK
TDI
TMS
CANTXD
CANRXD
TDO
DVDD
AGND
GNDIO
DGND
EN
HOLD
10µF
MAX5024LASA
OUT+12V
RESET
RESET
SET
REGEN2
EXTERNAL RESET IS OPTIONAL
IN
GND
VDD (+5V)
XIN
XOUT
TXD
VCC
RXD
MAX13053ASA/AUT
S
REF
GND
VDD
+2.5V
CANH
CANL
TO CAN BUS
TO CAN BUS
60Ω
60Ω
4.7nF
Typical Application Circuit
MAXQ7670
Microcontroller with 10-Bit ADC,
PGA, 64KB Flash, and CAN Interface
______________________________________________________________________________________ 37
MAXQ7670
TOP VIEW
5
6
4
3
22
21
23
P0.0
P0.2
GNDIO
CANRXD
CANTXD
24
I.C.
DVDD
XOUT
DGND
GNDIO
DVDDIO
AVDD
RESET
P0.5
11 12
AIN4
14 15 16 17
37383940 36 34 33 32
REFADC
AGND
TMS
TDO
REGEN2
MISO
P0.1
XIN
13
35
7
AIN3 MOSI
8
9
10
AIN2
AIN1
AIN0
SCLK
GNDIO
*EP
DVDDIO
AIN5
2
25
TDI
AIN6
1
26
27
28
29
30 TCK
SS
P0.6/TO
P0.7/TOB P0.4/ADCCNV
18 19 20
31
AIN7 +
Pin Configuration
Package Information
For the latest package outline information and land patterns, go
to www.maxim-ic.com/packages.
PACKAGE TYPE PACKAGE CODE DOCUMENT NO.
40 TQFN-EP T4055+1 21-0140
Chip Information
PROCESS: CMOS
MAXQ7670
Microcontroller with 10-Bit ADC,
PGA, 64KB Flash, and CAN Interface
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
38
____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2009 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.
Revision History
REVISION
NUMBER
REVISION
DATE DESCRIPTION PAGES CHANGED
0 11/08 Initial release —
1 7/09 Updated Ordering Information to indicate automotive qualified part 1
